From a0d970b6a973b542f950e6758d1843fff3a4ba83 Mon Sep 17 00:00:00 2001 From: Rafaël Carré Date: Tue, 13 Apr 2010 14:05:55 +0000 Subject: s5l8700 : remove some CRLF line endings git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25623 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/s5l8700/crt0.S | 108 ++++++++++++++++++------------------- 1 file changed, 54 insertions(+), 54 deletions(-) (limited to 'firmware/target/arm/s5l8700/crt0.S') diff --git a/firmware/target/arm/s5l8700/crt0.S b/firmware/target/arm/s5l8700/crt0.S index bb6d910e22..583b762505 100644 --- a/firmware/target/arm/s5l8700/crt0.S +++ b/firmware/target/arm/s5l8700/crt0.S @@ -260,64 +260,64 @@ start_loc: #if defined(MEIZU_M6SP) || defined(MEIZU_M3) /* setup SDRAM for Meizu M6SP */ - ldr r1, =0x38200000 - // configure SDR drive strength and pad settings - mov r0, #SDR_DSS_SEL_B - str r0, [r1, #0x4C] // MIU_DSS_SEL_B - mov r0, #SDR_DSS_SEL_O - str r0, [r1, #0x50] // MIU_DSS_SEL_O - mov r0, #SDR_DSS_SEL_C - str r0, [r1, #0x54] // MIU_DSS_SEL_C - mov r0, #2 - str r0, [r1, #0x60] // SSTL2_PAD_ON - // select SDR mode + ldr r1, =0x38200000 + // configure SDR drive strength and pad settings + mov r0, #SDR_DSS_SEL_B + str r0, [r1, #0x4C] // MIU_DSS_SEL_B + mov r0, #SDR_DSS_SEL_O + str r0, [r1, #0x50] // MIU_DSS_SEL_O + mov r0, #SDR_DSS_SEL_C + str r0, [r1, #0x54] // MIU_DSS_SEL_C + mov r0, #2 + str r0, [r1, #0x60] // SSTL2_PAD_ON + // select SDR mode ldr r0, [r1, #0x40] - mov r2, #0xFFFDFFFF - and r0, r0, r2 - orr r0, r0, #1 - str r0, [r1, #0x40] // MIUORG + mov r2, #0xFFFDFFFF + and r0, r0, r2 + orr r0, r0, #1 + str r0, [r1, #0x40] // MIUORG // set controller configuration mov r0, #SDR_CONFIG str r0, [r1] // MIUCON - // set SDRAM timing - ldr r0, =SDR_TIMING - str r0, [r1, #0x10] // MIUSDPARA - // set refresh rate - mov r0, #0x1080 - str r0, [r1, #0x08] // MIUAREF - // initialise SDRAM - mov r0, #0x003 - str r0, [r1, #0x04] // MIUCOM = nop - ldr r0, =0x203 - str r0, [r1, #0x04] // MIUCOM = precharge all banks - nop - nop - nop - ldr r0, =0x303 - str r0, [r1, #0x04] // MIUCOM = auto-refresh - nop - nop - nop - nop - str r0, [r1, #0x04] // MIUCOM = auto-refresh - nop - nop - nop - nop - str r0, [r1, #0x04] // MIUCOM = auto-refresh - nop - nop - nop - nop - // set mode register - mov r0, #SDR_MRS - str r0, [r1, #0x0C] // MIUMRS - ldr r0, =0x103 - str r0, [r1, #0x04] // MIUCOM = mode register set - ldr r0, =SDR_EMRS - str r0, [r1, #0x0C] // MIUMRS - ldr r0, =0x103 - str r0, [r1, #0x04] // MIUCOM = mode register set + // set SDRAM timing + ldr r0, =SDR_TIMING + str r0, [r1, #0x10] // MIUSDPARA + // set refresh rate + mov r0, #0x1080 + str r0, [r1, #0x08] // MIUAREF + // initialise SDRAM + mov r0, #0x003 + str r0, [r1, #0x04] // MIUCOM = nop + ldr r0, =0x203 + str r0, [r1, #0x04] // MIUCOM = precharge all banks + nop + nop + nop + ldr r0, =0x303 + str r0, [r1, #0x04] // MIUCOM = auto-refresh + nop + nop + nop + nop + str r0, [r1, #0x04] // MIUCOM = auto-refresh + nop + nop + nop + nop + str r0, [r1, #0x04] // MIUCOM = auto-refresh + nop + nop + nop + nop + // set mode register + mov r0, #SDR_MRS + str r0, [r1, #0x0C] // MIUMRS + ldr r0, =0x103 + str r0, [r1, #0x04] // MIUCOM = mode register set + ldr r0, =SDR_EMRS + str r0, [r1, #0x0C] // MIUMRS + ldr r0, =0x103 + str r0, [r1, #0x04] // MIUCOM = mode register set #endif /* MEIZU_M6SP */ mov r1, #0x1 -- cgit v1.2.3