From 05099149f193cac0c81b0129c17feb78b1a9681a Mon Sep 17 00:00:00 2001 From: Michael Sevakis Date: Sun, 6 Apr 2008 04:34:57 +0000 Subject: Enable nocache sections using the linker. PP5022/4 must use SW_CORELOCK now with shared variables in DRAM (it seems swp(b) is at least partially broken on all PP or I'm doing something very wrong here :\). For core-shared data use SHAREDBSS/DATA_ATTR. NOCACHEBSS/DATA_ATTR is available whether or not single core is forced for static peripheral-DMA buffer allocation without use of the UNCACHED_ADDR macro in code and is likely useful on a non-PP target with a data cache (although not actually enabled in config.h and the .lds's in this commit). git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16981 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/iriver/boot.lds | 2 ++ 1 file changed, 2 insertions(+) (limited to 'firmware/target/arm/iriver/boot.lds') diff --git a/firmware/target/arm/iriver/boot.lds b/firmware/target/arm/iriver/boot.lds index 5fbe999333..971ec6627b 100644 --- a/firmware/target/arm/iriver/boot.lds +++ b/firmware/target/arm/iriver/boot.lds @@ -27,6 +27,7 @@ SECTIONS *(.irodata) *(.idata) *(.data*) + *(.ncdata*); _dataend = . ; } @@ -48,6 +49,7 @@ SECTIONS _edata = .; *(.bss*); *(.ibss); + *(.ncbss*); _end = .; } } -- cgit v1.2.3