From 79d90b9e763ab50b900b35bc6746fea9bbaacb53 Mon Sep 17 00:00:00 2001 From: Michael Sevakis Date: Sat, 10 Apr 2010 09:24:06 +0000 Subject: Gigabeat S/i.MX31: Continue, and most likely complete, the platform/player-specific code/data shuffling begun in r25547. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25564 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/imx31/mc13783-imx31.c | 17 +---------------- 1 file changed, 1 insertion(+), 16 deletions(-) (limited to 'firmware/target/arm/imx31/mc13783-imx31.c') diff --git a/firmware/target/arm/imx31/mc13783-imx31.c b/firmware/target/arm/imx31/mc13783-imx31.c index 9b7248dc45..1c43b3b6fa 100644 --- a/firmware/target/arm/imx31/mc13783-imx31.c +++ b/firmware/target/arm/imx31/mc13783-imx31.c @@ -30,23 +30,8 @@ #define PMIC_DRIVER_CLOSE #endif -/* This is all based on communicating with the MC13783 PMU which is on - * CSPI2 with the chip select at 0. The LCD controller resides on - * CSPI3 cs1, but we have no idea how to communicate to it */ -static struct spi_node mc13783_spi = -{ - CSPI2_NUM, /* CSPI module 2 */ - CSPI_CONREG_CHIP_SELECT_SS0 | /* Chip select 0 */ - CSPI_CONREG_DRCTL_DONT_CARE | /* Don't care about CSPI_RDY */ - CSPI_CONREG_DATA_RATE_DIV_32 | /* Clock = IPG_CLK/32 = 2,062,500Hz. */ - CSPI_BITCOUNT(32-1) | /* All 32 bits are to be transferred */ - CSPI_CONREG_SSPOL | /* SS active high */ - CSPI_CONREG_SSCTL | /* Negate SS between SPI bursts */ - CSPI_CONREG_MODE, /* Master mode */ - 0, /* SPI clock - no wait states */ -}; - extern const struct mc13783_event_list mc13783_event_list; +extern struct spi_node mc13783_spi; static int mc13783_thread_stack[DEFAULT_STACK_SIZE/sizeof(int)]; static const char *mc13783_thread_name = "pmic"; -- cgit v1.2.3