From 85c32dbd12108fc570afdec450b7d73684f37a2d Mon Sep 17 00:00:00 2001 From: Amaury Pouly Date: Fri, 22 Jul 2011 15:45:50 +0000 Subject: imx233/fuze+: add pin irq support git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30195 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/imx233/pinctrl-imx233.c | 77 +++++++++++++++++++++++++++++ firmware/target/arm/imx233/pinctrl-imx233.h | 7 +++ 2 files changed, 84 insertions(+) create mode 100644 firmware/target/arm/imx233/pinctrl-imx233.c (limited to 'firmware/target/arm/imx233') diff --git a/firmware/target/arm/imx233/pinctrl-imx233.c b/firmware/target/arm/imx233/pinctrl-imx233.c new file mode 100644 index 0000000000..7997292fcb --- /dev/null +++ b/firmware/target/arm/imx233/pinctrl-imx233.c @@ -0,0 +1,77 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2011 by Amaury Pouly + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#include "system.h" +#include "system-target.h" +#include "cpu.h" +#include "pinctrl-imx233.h" + +static pin_irq_cb_t pin_cb[3][32]; /* 3 banks, 32 pins/bank */ + +static void INT_GPIO(int bank) +{ + uint32_t fire = HW_PINCTRL_IRQSTAT(bank) & HW_PINCTRL_IRQEN(bank); + for(int pin = 0; pin < 32; pin++) + if(fire & (1 << pin)) + { + pin_irq_cb_t cb = pin_cb[bank][pin]; + imx233_setup_pin_irq(bank, pin, false, false, false, NULL); + if(cb) + cb(bank, pin); + } +} + +void INT_GPIO0(void) +{ + INT_GPIO(0); +} + +void INT_GPIO1(void) +{ + INT_GPIO(1); +} + +void INT_GPIO2(void) +{ + INT_GPIO(2); +} + +void imx233_setup_pin_irq(int bank, int pin, bool enable_int, + bool level, bool polarity, pin_irq_cb_t cb) +{ + __REG_CLR(HW_PINCTRL_PIN2IRQ(bank)) = 1 << pin; + __REG_CLR(HW_PINCTRL_IRQEN(bank)) = 1 << pin; + __REG_CLR(HW_PINCTRL_IRQSTAT(bank))= 1 << pin; + pin_cb[bank][pin] = cb; + if(enable_int) + { + if(level) + __REG_SET(HW_PINCTRL_IRQLEVEL(bank)) = 1 << pin; + else + __REG_CLR(HW_PINCTRL_IRQLEVEL(bank)) = 1 << pin; + if(polarity) + __REG_SET(HW_PINCTRL_IRQPOL(bank)) = 1 << pin; + else + __REG_CLR(HW_PINCTRL_IRQPOL(bank)) = 1 << pin; + __REG_SET(HW_PINCTRL_PIN2IRQ(bank)) = 1 << pin; + __REG_SET(HW_PINCTRL_IRQEN(bank)) = 1 << pin; + imx233_enable_interrupt(INT_SRC_GPIO(bank), true); + } +} diff --git a/firmware/target/arm/imx233/pinctrl-imx233.h b/firmware/target/arm/imx233/pinctrl-imx233.h index a2e02adec4..ec23410442 100644 --- a/firmware/target/arm/imx233/pinctrl-imx233.h +++ b/firmware/target/arm/imx233/pinctrl-imx233.h @@ -51,6 +51,8 @@ #define PINCTRL_DRIVE_12mA 2 #define PINCTRL_DRIVE_16mA 3 /* not available on all pins */ +typedef void (*pin_irq_cb_t)(int bank, int pin); + static inline void imx233_pinctrl_init(void) { __REG_CLR(HW_PINCTRL_CTRL) = __BLOCK_CLKGATE | __BLOCK_SFTRST; @@ -121,4 +123,9 @@ static inline void imx233_enable_pin_pullup_mask(unsigned bank, uint32_t pin_msk __REG_CLR(HW_PINCTRL_PULL(bank)) = pin_msk; } +/** On irq, the pin irq interrupt is disable and then cb is called; + * the setup_pin_irq function needs to be called again to enable it again */ +void imx233_setup_pin_irq(int bank, int pin, bool enable_int, + bool level, bool polarity, pin_irq_cb_t cb); + #endif /* __PINCTRL_IMX233_H__ */ -- cgit v1.2.3