From 017667c2dc9843eb5082e991f421c773636dcf36 Mon Sep 17 00:00:00 2001 From: Amaury Pouly Date: Thu, 13 Jun 2013 19:03:33 +0200 Subject: imx233: generate register headers for stmp3600, stmp3700 and imx233 Change-Id: Ia87086f4f4f4ecbb844ffd869407b14ea2509934 --- .../target/arm/imx233/regs/stmp3700/regs-saif.h | 154 +++++++++++++++++++++ 1 file changed, 154 insertions(+) create mode 100644 firmware/target/arm/imx233/regs/stmp3700/regs-saif.h (limited to 'firmware/target/arm/imx233/regs/stmp3700/regs-saif.h') diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-saif.h b/firmware/target/arm/imx233/regs/stmp3700/regs-saif.h new file mode 100644 index 0000000000..01faeabc62 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-saif.h @@ -0,0 +1,154 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 2.1.7 + * XML versions: stmp3700:3.2.0 + * + * Copyright (C) 2013 by Amaury Pouly + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN__STMP3700__SAIF__H__ +#define __HEADERGEN__STMP3700__SAIF__H__ + +#define REGS_SAIF_BASE(i) ((i) == 1 ? 0x80042000 : 0x80046000) + +#define REGS_SAIF_VERSION "3.2.0" + +/** + * Register: HW_SAIF_CTRL + * Address: 0 + * SCT: yes +*/ +#define HW_SAIF_CTRL(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x0)) +#define HW_SAIF_CTRL_SET(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x4)) +#define HW_SAIF_CTRL_CLR(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x8)) +#define HW_SAIF_CTRL_TOG(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0xc)) +#define BP_SAIF_CTRL_SFTRST 31 +#define BM_SAIF_CTRL_SFTRST 0x80000000 +#define BF_SAIF_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) +#define BP_SAIF_CTRL_CLKGATE 30 +#define BM_SAIF_CTRL_CLKGATE 0x40000000 +#define BF_SAIF_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) +#define BP_SAIF_CTRL_BITCLK_MULT_RATE 27 +#define BM_SAIF_CTRL_BITCLK_MULT_RATE 0x38000000 +#define BF_SAIF_CTRL_BITCLK_MULT_RATE(v) (((v) << 27) & 0x38000000) +#define BP_SAIF_CTRL_BITCLK_BASE_RATE 26 +#define BM_SAIF_CTRL_BITCLK_BASE_RATE 0x4000000 +#define BF_SAIF_CTRL_BITCLK_BASE_RATE(v) (((v) << 26) & 0x4000000) +#define BP_SAIF_CTRL_FIFO_ERROR_IRQ_EN 25 +#define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN 0x2000000 +#define BF_SAIF_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) << 25) & 0x2000000) +#define BP_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 24 +#define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 0x1000000 +#define BF_SAIF_CTRL_FIFO_SERVICE_IRQ_EN(v) (((v) << 24) & 0x1000000) +#define BP_SAIF_CTRL_DMAWAIT_COUNT 16 +#define BM_SAIF_CTRL_DMAWAIT_COUNT 0x1f0000 +#define BF_SAIF_CTRL_DMAWAIT_COUNT(v) (((v) << 16) & 0x1f0000) +#define BP_SAIF_CTRL_CHANNEL_NUM_SELECT 14 +#define BM_SAIF_CTRL_CHANNEL_NUM_SELECT 0xc000 +#define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v) (((v) << 14) & 0xc000) +#define BP_SAIF_CTRL_BIT_ORDER 12 +#define BM_SAIF_CTRL_BIT_ORDER 0x1000 +#define BF_SAIF_CTRL_BIT_ORDER(v) (((v) << 12) & 0x1000) +#define BP_SAIF_CTRL_DELAY 11 +#define BM_SAIF_CTRL_DELAY 0x800 +#define BF_SAIF_CTRL_DELAY(v) (((v) << 11) & 0x800) +#define BP_SAIF_CTRL_JUSTIFY 10 +#define BM_SAIF_CTRL_JUSTIFY 0x400 +#define BF_SAIF_CTRL_JUSTIFY(v) (((v) << 10) & 0x400) +#define BP_SAIF_CTRL_LRCLK_POLARITY 9 +#define BM_SAIF_CTRL_LRCLK_POLARITY 0x200 +#define BF_SAIF_CTRL_LRCLK_POLARITY(v) (((v) << 9) & 0x200) +#define BP_SAIF_CTRL_BITCLK_EDGE 8 +#define BM_SAIF_CTRL_BITCLK_EDGE 0x100 +#define BF_SAIF_CTRL_BITCLK_EDGE(v) (((v) << 8) & 0x100) +#define BP_SAIF_CTRL_WORD_LENGTH 4 +#define BM_SAIF_CTRL_WORD_LENGTH 0xf0 +#define BF_SAIF_CTRL_WORD_LENGTH(v) (((v) << 4) & 0xf0) +#define BP_SAIF_CTRL_BITCLK_48XFS_ENABLE 3 +#define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE 0x8 +#define BF_SAIF_CTRL_BITCLK_48XFS_ENABLE(v) (((v) << 3) & 0x8) +#define BP_SAIF_CTRL_SLAVE_MODE 2 +#define BM_SAIF_CTRL_SLAVE_MODE 0x4 +#define BF_SAIF_CTRL_SLAVE_MODE(v) (((v) << 2) & 0x4) +#define BP_SAIF_CTRL_READ_MODE 1 +#define BM_SAIF_CTRL_READ_MODE 0x2 +#define BF_SAIF_CTRL_READ_MODE(v) (((v) << 1) & 0x2) +#define BP_SAIF_CTRL_RUN 0 +#define BM_SAIF_CTRL_RUN 0x1 +#define BF_SAIF_CTRL_RUN(v) (((v) << 0) & 0x1) + +/** + * Register: HW_SAIF_STAT + * Address: 0x10 + * SCT: yes +*/ +#define HW_SAIF_STAT(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x0)) +#define HW_SAIF_STAT_SET(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x4)) +#define HW_SAIF_STAT_CLR(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x8)) +#define HW_SAIF_STAT_TOG(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0xc)) +#define BP_SAIF_STAT_PRESENT 31 +#define BM_SAIF_STAT_PRESENT 0x80000000 +#define BF_SAIF_STAT_PRESENT(v) (((v) << 31) & 0x80000000) +#define BP_SAIF_STAT_DMA_PREQ 16 +#define BM_SAIF_STAT_DMA_PREQ 0x10000 +#define BF_SAIF_STAT_DMA_PREQ(v) (((v) << 16) & 0x10000) +#define BP_SAIF_STAT_FIFO_UNDERFLOW_IRQ 6 +#define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ 0x40 +#define BF_SAIF_STAT_FIFO_UNDERFLOW_IRQ(v) (((v) << 6) & 0x40) +#define BP_SAIF_STAT_FIFO_OVERFLOW_IRQ 5 +#define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ 0x20 +#define BF_SAIF_STAT_FIFO_OVERFLOW_IRQ(v) (((v) << 5) & 0x20) +#define BP_SAIF_STAT_FIFO_SERVICE_IRQ 4 +#define BM_SAIF_STAT_FIFO_SERVICE_IRQ 0x10 +#define BF_SAIF_STAT_FIFO_SERVICE_IRQ(v) (((v) << 4) & 0x10) +#define BP_SAIF_STAT_BUSY 0 +#define BM_SAIF_STAT_BUSY 0x1 +#define BF_SAIF_STAT_BUSY(v) (((v) << 0) & 0x1) + +/** + * Register: HW_SAIF_DATA + * Address: 0x20 + * SCT: yes +*/ +#define HW_SAIF_DATA(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x0)) +#define HW_SAIF_DATA_SET(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x4)) +#define HW_SAIF_DATA_CLR(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x8)) +#define HW_SAIF_DATA_TOG(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0xc)) +#define BP_SAIF_DATA_PCM_RIGHT 16 +#define BM_SAIF_DATA_PCM_RIGHT 0xffff0000 +#define BF_SAIF_DATA_PCM_RIGHT(v) (((v) << 16) & 0xffff0000) +#define BP_SAIF_DATA_PCM_LEFT 0 +#define BM_SAIF_DATA_PCM_LEFT 0xffff +#define BF_SAIF_DATA_PCM_LEFT(v) (((v) << 0) & 0xffff) + +/** + * Register: HW_SAIF_VERSION + * Address: 0x30 + * SCT: no +*/ +#define HW_SAIF_VERSION(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x30)) +#define BP_SAIF_VERSION_MAJOR 24 +#define BM_SAIF_VERSION_MAJOR 0xff000000 +#define BF_SAIF_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) +#define BP_SAIF_VERSION_MINOR 16 +#define BM_SAIF_VERSION_MINOR 0xff0000 +#define BF_SAIF_VERSION_MINOR(v) (((v) << 16) & 0xff0000) +#define BP_SAIF_VERSION_STEP 0 +#define BM_SAIF_VERSION_STEP 0xffff +#define BF_SAIF_VERSION_STEP(v) (((v) << 0) & 0xffff) + +#endif /* __HEADERGEN__STMP3700__SAIF__H__ */ -- cgit v1.2.3