From 017667c2dc9843eb5082e991f421c773636dcf36 Mon Sep 17 00:00:00 2001 From: Amaury Pouly Date: Thu, 13 Jun 2013 19:03:33 +0200 Subject: imx233: generate register headers for stmp3600, stmp3700 and imx233 Change-Id: Ia87086f4f4f4ecbb844ffd869407b14ea2509934 --- .../target/arm/imx233/regs/stmp3700/regs-power.h | 581 +++++++++++++++++++++ 1 file changed, 581 insertions(+) create mode 100644 firmware/target/arm/imx233/regs/stmp3700/regs-power.h (limited to 'firmware/target/arm/imx233/regs/stmp3700/regs-power.h') diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-power.h b/firmware/target/arm/imx233/regs/stmp3700/regs-power.h new file mode 100644 index 0000000000..85116c79cb --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-power.h @@ -0,0 +1,581 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 2.1.7 + * XML versions: stmp3700:3.2.0 + * + * Copyright (C) 2013 by Amaury Pouly + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN__STMP3700__POWER__H__ +#define __HEADERGEN__STMP3700__POWER__H__ + +#define REGS_POWER_BASE (0x80044000) + +#define REGS_POWER_VERSION "3.2.0" + +/** + * Register: HW_POWER_CTRL + * Address: 0 + * SCT: yes +*/ +#define HW_POWER_CTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x0)) +#define HW_POWER_CTRL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x4)) +#define HW_POWER_CTRL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x8)) +#define HW_POWER_CTRL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0xc)) +#define BP_POWER_CTRL_CLKGATE 30 +#define BM_POWER_CTRL_CLKGATE 0x40000000 +#define BF_POWER_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) +#define BP_POWER_CTRL_PSWITCH_IRQ 22 +#define BM_POWER_CTRL_PSWITCH_IRQ 0x400000 +#define BF_POWER_CTRL_PSWITCH_IRQ(v) (((v) << 22) & 0x400000) +#define BP_POWER_CTRL_PSWITCH_IRQ_SRC 21 +#define BM_POWER_CTRL_PSWITCH_IRQ_SRC 0x200000 +#define BF_POWER_CTRL_PSWITCH_IRQ_SRC(v) (((v) << 21) & 0x200000) +#define BP_POWER_CTRL_POLARITY_PSWITCH 20 +#define BM_POWER_CTRL_POLARITY_PSWITCH 0x100000 +#define BF_POWER_CTRL_POLARITY_PSWITCH(v) (((v) << 20) & 0x100000) +#define BP_POWER_CTRL_ENIRQ_PSWITCH 19 +#define BM_POWER_CTRL_ENIRQ_PSWITCH 0x80000 +#define BF_POWER_CTRL_ENIRQ_PSWITCH(v) (((v) << 19) & 0x80000) +#define BP_POWER_CTRL_POLARITY_LINREG_OK 18 +#define BM_POWER_CTRL_POLARITY_LINREG_OK 0x40000 +#define BF_POWER_CTRL_POLARITY_LINREG_OK(v) (((v) << 18) & 0x40000) +#define BP_POWER_CTRL_LINREG_OK_IRQ 17 +#define BM_POWER_CTRL_LINREG_OK_IRQ 0x20000 +#define BF_POWER_CTRL_LINREG_OK_IRQ(v) (((v) << 17) & 0x20000) +#define BP_POWER_CTRL_ENIRQ_LINREG_OK 16 +#define BM_POWER_CTRL_ENIRQ_LINREG_OK 0x10000 +#define BF_POWER_CTRL_ENIRQ_LINREG_OK(v) (((v) << 16) & 0x10000) +#define BP_POWER_CTRL_DC_OK_IRQ 15 +#define BM_POWER_CTRL_DC_OK_IRQ 0x8000 +#define BF_POWER_CTRL_DC_OK_IRQ(v) (((v) << 15) & 0x8000) +#define BP_POWER_CTRL_ENIRQ_DC_OK 14 +#define BM_POWER_CTRL_ENIRQ_DC_OK 0x4000 +#define BF_POWER_CTRL_ENIRQ_DC_OK(v) (((v) << 14) & 0x4000) +#define BP_POWER_CTRL_BATT_BO_IRQ 13 +#define BM_POWER_CTRL_BATT_BO_IRQ 0x2000 +#define BF_POWER_CTRL_BATT_BO_IRQ(v) (((v) << 13) & 0x2000) +#define BP_POWER_CTRL_ENIRQBATT_BO 12 +#define BM_POWER_CTRL_ENIRQBATT_BO 0x1000 +#define BF_POWER_CTRL_ENIRQBATT_BO(v) (((v) << 12) & 0x1000) +#define BP_POWER_CTRL_VDDIO_BO_IRQ 11 +#define BM_POWER_CTRL_VDDIO_BO_IRQ 0x800 +#define BF_POWER_CTRL_VDDIO_BO_IRQ(v) (((v) << 11) & 0x800) +#define BP_POWER_CTRL_ENIRQ_VDDIO_BO 10 +#define BM_POWER_CTRL_ENIRQ_VDDIO_BO 0x400 +#define BF_POWER_CTRL_ENIRQ_VDDIO_BO(v) (((v) << 10) & 0x400) +#define BP_POWER_CTRL_VDDA_BO_IRQ 9 +#define BM_POWER_CTRL_VDDA_BO_IRQ 0x200 +#define BF_POWER_CTRL_VDDA_BO_IRQ(v) (((v) << 9) & 0x200) +#define BP_POWER_CTRL_ENIRQ_VDDA_BO 8 +#define BM_POWER_CTRL_ENIRQ_VDDA_BO 0x100 +#define BF_POWER_CTRL_ENIRQ_VDDA_BO(v) (((v) << 8) & 0x100) +#define BP_POWER_CTRL_VDDD_BO_IRQ 7 +#define BM_POWER_CTRL_VDDD_BO_IRQ 0x80 +#define BF_POWER_CTRL_VDDD_BO_IRQ(v) (((v) << 7) & 0x80) +#define BP_POWER_CTRL_ENIRQ_VDDD_BO 6 +#define BM_POWER_CTRL_ENIRQ_VDDD_BO 0x40 +#define BF_POWER_CTRL_ENIRQ_VDDD_BO(v) (((v) << 6) & 0x40) +#define BP_POWER_CTRL_POLARITY_VBUSVALID 5 +#define BM_POWER_CTRL_POLARITY_VBUSVALID 0x20 +#define BF_POWER_CTRL_POLARITY_VBUSVALID(v) (((v) << 5) & 0x20) +#define BP_POWER_CTRL_VBUSVALID_IRQ 4 +#define BM_POWER_CTRL_VBUSVALID_IRQ 0x10 +#define BF_POWER_CTRL_VBUSVALID_IRQ(v) (((v) << 4) & 0x10) +#define BP_POWER_CTRL_ENIRQ_VBUS_VALID 3 +#define BM_POWER_CTRL_ENIRQ_VBUS_VALID 0x8 +#define BF_POWER_CTRL_ENIRQ_VBUS_VALID(v) (((v) << 3) & 0x8) +#define BP_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO 2 +#define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO 0x4 +#define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v) (((v) << 2) & 0x4) +#define BP_POWER_CTRL_VDD5V_GT_VDDIO_IRQ 1 +#define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ 0x2 +#define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v) (((v) << 1) & 0x2) +#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0 +#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x1 +#define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v) (((v) << 0) & 0x1) + +/** + * Register: HW_POWER_5VCTRL + * Address: 0x10 + * SCT: yes +*/ +#define HW_POWER_5VCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x0)) +#define HW_POWER_5VCTRL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x4)) +#define HW_POWER_5VCTRL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x8)) +#define HW_POWER_5VCTRL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0xc)) +#define BP_POWER_5VCTRL_VBUSVALID_TRSH 10 +#define BM_POWER_5VCTRL_VBUSVALID_TRSH 0xc00 +#define BF_POWER_5VCTRL_VBUSVALID_TRSH(v) (((v) << 10) & 0xc00) +#define BP_POWER_5VCTRL_PWDN_5VBRNOUT 8 +#define BM_POWER_5VCTRL_PWDN_5VBRNOUT 0x100 +#define BF_POWER_5VCTRL_PWDN_5VBRNOUT(v) (((v) << 8) & 0x100) +#define BP_POWER_5VCTRL_ENABLE_ILIMIT 7 +#define BM_POWER_5VCTRL_ENABLE_ILIMIT 0x80 +#define BF_POWER_5VCTRL_ENABLE_ILIMIT(v) (((v) << 7) & 0x80) +#define BP_POWER_5VCTRL_DCDC_XFER 6 +#define BM_POWER_5VCTRL_DCDC_XFER 0x40 +#define BF_POWER_5VCTRL_DCDC_XFER(v) (((v) << 6) & 0x40) +#define BP_POWER_5VCTRL_EN_BATT_PULLDN 5 +#define BM_POWER_5VCTRL_EN_BATT_PULLDN 0x20 +#define BF_POWER_5VCTRL_EN_BATT_PULLDN(v) (((v) << 5) & 0x20) +#define BP_POWER_5VCTRL_VBUSVALID_5VDETECT 4 +#define BM_POWER_5VCTRL_VBUSVALID_5VDETECT 0x10 +#define BF_POWER_5VCTRL_VBUSVALID_5VDETECT(v) (((v) << 4) & 0x10) +#define BP_POWER_5VCTRL_VBUSVALID_TO_B 3 +#define BM_POWER_5VCTRL_VBUSVALID_TO_B 0x8 +#define BF_POWER_5VCTRL_VBUSVALID_TO_B(v) (((v) << 3) & 0x8) +#define BP_POWER_5VCTRL_ILIMIT_EQ_ZERO 2 +#define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO 0x4 +#define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(v) (((v) << 2) & 0x4) +#define BP_POWER_5VCTRL_OTG_PWRUP_CMPS 1 +#define BM_POWER_5VCTRL_OTG_PWRUP_CMPS 0x2 +#define BF_POWER_5VCTRL_OTG_PWRUP_CMPS(v) (((v) << 1) & 0x2) +#define BP_POWER_5VCTRL_ENABLE_DCDC 0 +#define BM_POWER_5VCTRL_ENABLE_DCDC 0x1 +#define BF_POWER_5VCTRL_ENABLE_DCDC(v) (((v) << 0) & 0x1) + +/** + * Register: HW_POWER_MINPWR + * Address: 0x20 + * SCT: yes +*/ +#define HW_POWER_MINPWR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x0)) +#define HW_POWER_MINPWR_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x4)) +#define HW_POWER_MINPWR_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x8)) +#define HW_POWER_MINPWR_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0xc)) +#define BP_POWER_MINPWR_PWD_BO 11 +#define BM_POWER_MINPWR_PWD_BO 0x800 +#define BF_POWER_MINPWR_PWD_BO(v) (((v) << 11) & 0x800) +#define BP_POWER_MINPWR_USB_I_SUSPEND 10 +#define BM_POWER_MINPWR_USB_I_SUSPEND 0x400 +#define BF_POWER_MINPWR_USB_I_SUSPEND(v) (((v) << 10) & 0x400) +#define BP_POWER_MINPWR_ENABLE_OSC 9 +#define BM_POWER_MINPWR_ENABLE_OSC 0x200 +#define BF_POWER_MINPWR_ENABLE_OSC(v) (((v) << 9) & 0x200) +#define BP_POWER_MINPWR_SELECT_OSC 8 +#define BM_POWER_MINPWR_SELECT_OSC 0x100 +#define BF_POWER_MINPWR_SELECT_OSC(v) (((v) << 8) & 0x100) +#define BP_POWER_MINPWR_VBG_OFF 7 +#define BM_POWER_MINPWR_VBG_OFF 0x80 +#define BF_POWER_MINPWR_VBG_OFF(v) (((v) << 7) & 0x80) +#define BP_POWER_MINPWR_DOUBLE_FETS 6 +#define BM_POWER_MINPWR_DOUBLE_FETS 0x40 +#define BF_POWER_MINPWR_DOUBLE_FETS(v) (((v) << 6) & 0x40) +#define BP_POWER_MINPWR_HALF_FETS 5 +#define BM_POWER_MINPWR_HALF_FETS 0x20 +#define BF_POWER_MINPWR_HALF_FETS(v) (((v) << 5) & 0x20) +#define BP_POWER_MINPWR_LESSANA_I 4 +#define BM_POWER_MINPWR_LESSANA_I 0x10 +#define BF_POWER_MINPWR_LESSANA_I(v) (((v) << 4) & 0x10) +#define BP_POWER_MINPWR_PWD_XTAL24 3 +#define BM_POWER_MINPWR_PWD_XTAL24 0x8 +#define BF_POWER_MINPWR_PWD_XTAL24(v) (((v) << 3) & 0x8) +#define BP_POWER_MINPWR_DC_STOPCLK 2 +#define BM_POWER_MINPWR_DC_STOPCLK 0x4 +#define BF_POWER_MINPWR_DC_STOPCLK(v) (((v) << 2) & 0x4) +#define BP_POWER_MINPWR_EN_DC_PFM 1 +#define BM_POWER_MINPWR_EN_DC_PFM 0x2 +#define BF_POWER_MINPWR_EN_DC_PFM(v) (((v) << 1) & 0x2) +#define BP_POWER_MINPWR_DC_HALFCLK 0 +#define BM_POWER_MINPWR_DC_HALFCLK 0x1 +#define BF_POWER_MINPWR_DC_HALFCLK(v) (((v) << 0) & 0x1) + +/** + * Register: HW_POWER_CHARGE + * Address: 0x30 + * SCT: yes +*/ +#define HW_POWER_CHARGE (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x0)) +#define HW_POWER_CHARGE_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x4)) +#define HW_POWER_CHARGE_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x8)) +#define HW_POWER_CHARGE_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0xc)) +#define BP_POWER_CHARGE_ENABLE_FAULT_DETECT 20 +#define BM_POWER_CHARGE_ENABLE_FAULT_DETECT 0x100000 +#define BF_POWER_CHARGE_ENABLE_FAULT_DETECT(v) (((v) << 20) & 0x100000) +#define BP_POWER_CHARGE_CHRG_STS_OFF 19 +#define BM_POWER_CHARGE_CHRG_STS_OFF 0x80000 +#define BF_POWER_CHARGE_CHRG_STS_OFF(v) (((v) << 19) & 0x80000) +#define BP_POWER_CHARGE_USE_EXTERN_R 17 +#define BM_POWER_CHARGE_USE_EXTERN_R 0x20000 +#define BF_POWER_CHARGE_USE_EXTERN_R(v) (((v) << 17) & 0x20000) +#define BP_POWER_CHARGE_PWD_BATTCHRG 16 +#define BM_POWER_CHARGE_PWD_BATTCHRG 0x10000 +#define BF_POWER_CHARGE_PWD_BATTCHRG(v) (((v) << 16) & 0x10000) +#define BP_POWER_CHARGE_STOP_ILIMIT 8 +#define BM_POWER_CHARGE_STOP_ILIMIT 0xf00 +#define BF_POWER_CHARGE_STOP_ILIMIT(v) (((v) << 8) & 0xf00) +#define BP_POWER_CHARGE_BATTCHRG_I 0 +#define BM_POWER_CHARGE_BATTCHRG_I 0x3f +#define BF_POWER_CHARGE_BATTCHRG_I(v) (((v) << 0) & 0x3f) + +/** + * Register: HW_POWER_VDDDCTRL + * Address: 0x40 + * SCT: no +*/ +#define HW_POWER_VDDDCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x40)) +#define BP_POWER_VDDDCTRL_ADJTN 28 +#define BM_POWER_VDDDCTRL_ADJTN 0xf0000000 +#define BF_POWER_VDDDCTRL_ADJTN(v) (((v) << 28) & 0xf0000000) +#define BP_POWER_VDDDCTRL_ALKALINE_CHARGE 24 +#define BM_POWER_VDDDCTRL_ALKALINE_CHARGE 0x1000000 +#define BF_POWER_VDDDCTRL_ALKALINE_CHARGE(v) (((v) << 24) & 0x1000000) +#define BP_POWER_VDDDCTRL_DISABLE_STEPPING 23 +#define BM_POWER_VDDDCTRL_DISABLE_STEPPING 0x800000 +#define BF_POWER_VDDDCTRL_DISABLE_STEPPING(v) (((v) << 23) & 0x800000) +#define BP_POWER_VDDDCTRL_LINREG_FROM_BATT 22 +#define BM_POWER_VDDDCTRL_LINREG_FROM_BATT 0x400000 +#define BF_POWER_VDDDCTRL_LINREG_FROM_BATT(v) (((v) << 22) & 0x400000) +#define BP_POWER_VDDDCTRL_ENABLE_LINREG 21 +#define BM_POWER_VDDDCTRL_ENABLE_LINREG 0x200000 +#define BF_POWER_VDDDCTRL_ENABLE_LINREG(v) (((v) << 21) & 0x200000) +#define BP_POWER_VDDDCTRL_DISABLE_FET 20 +#define BM_POWER_VDDDCTRL_DISABLE_FET 0x100000 +#define BF_POWER_VDDDCTRL_DISABLE_FET(v) (((v) << 20) & 0x100000) +#define BP_POWER_VDDDCTRL_LINREG_OFFSET 16 +#define BM_POWER_VDDDCTRL_LINREG_OFFSET 0x30000 +#define BF_POWER_VDDDCTRL_LINREG_OFFSET(v) (((v) << 16) & 0x30000) +#define BP_POWER_VDDDCTRL_BO_OFFSET 8 +#define BM_POWER_VDDDCTRL_BO_OFFSET 0x700 +#define BF_POWER_VDDDCTRL_BO_OFFSET(v) (((v) << 8) & 0x700) +#define BP_POWER_VDDDCTRL_TRG 0 +#define BM_POWER_VDDDCTRL_TRG 0x1f +#define BF_POWER_VDDDCTRL_TRG(v) (((v) << 0) & 0x1f) + +/** + * Register: HW_POWER_VDDACTRL + * Address: 0x50 + * SCT: no +*/ +#define HW_POWER_VDDACTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x50)) +#define BP_POWER_VDDACTRL_DISABLE_STEPPING 18 +#define BM_POWER_VDDACTRL_DISABLE_STEPPING 0x40000 +#define BF_POWER_VDDACTRL_DISABLE_STEPPING(v) (((v) << 18) & 0x40000) +#define BP_POWER_VDDACTRL_ENABLE_LINREG 17 +#define BM_POWER_VDDACTRL_ENABLE_LINREG 0x20000 +#define BF_POWER_VDDACTRL_ENABLE_LINREG(v) (((v) << 17) & 0x20000) +#define BP_POWER_VDDACTRL_DISABLE_FET 16 +#define BM_POWER_VDDACTRL_DISABLE_FET 0x10000 +#define BF_POWER_VDDACTRL_DISABLE_FET(v) (((v) << 16) & 0x10000) +#define BP_POWER_VDDACTRL_LINREG_OFFSET 12 +#define BM_POWER_VDDACTRL_LINREG_OFFSET 0x3000 +#define BF_POWER_VDDACTRL_LINREG_OFFSET(v) (((v) << 12) & 0x3000) +#define BP_POWER_VDDACTRL_BO_OFFSET 8 +#define BM_POWER_VDDACTRL_BO_OFFSET 0x700 +#define BF_POWER_VDDACTRL_BO_OFFSET(v) (((v) << 8) & 0x700) +#define BP_POWER_VDDACTRL_TRG 0 +#define BM_POWER_VDDACTRL_TRG 0x1f +#define BF_POWER_VDDACTRL_TRG(v) (((v) << 0) & 0x1f) + +/** + * Register: HW_POWER_VDDIOCTRL + * Address: 0x60 + * SCT: no +*/ +#define HW_POWER_VDDIOCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x60)) +#define BP_POWER_VDDIOCTRL_ADJTN 16 +#define BM_POWER_VDDIOCTRL_ADJTN 0xf0000 +#define BF_POWER_VDDIOCTRL_ADJTN(v) (((v) << 16) & 0xf0000) +#define BP_POWER_VDDIOCTRL_DISABLE_STEPPING 15 +#define BM_POWER_VDDIOCTRL_DISABLE_STEPPING 0x8000 +#define BF_POWER_VDDIOCTRL_DISABLE_STEPPING(v) (((v) << 15) & 0x8000) +#define BP_POWER_VDDIOCTRL_DISABLE_FET 14 +#define BM_POWER_VDDIOCTRL_DISABLE_FET 0x4000 +#define BF_POWER_VDDIOCTRL_DISABLE_FET(v) (((v) << 14) & 0x4000) +#define BP_POWER_VDDIOCTRL_LINREG_OFFSET 12 +#define BM_POWER_VDDIOCTRL_LINREG_OFFSET 0x3000 +#define BF_POWER_VDDIOCTRL_LINREG_OFFSET(v) (((v) << 12) & 0x3000) +#define BP_POWER_VDDIOCTRL_BO_OFFSET 8 +#define BM_POWER_VDDIOCTRL_BO_OFFSET 0x700 +#define BF_POWER_VDDIOCTRL_BO_OFFSET(v) (((v) << 8) & 0x700) +#define BP_POWER_VDDIOCTRL_TRG 0 +#define BM_POWER_VDDIOCTRL_TRG 0x1f +#define BF_POWER_VDDIOCTRL_TRG(v) (((v) << 0) & 0x1f) + +/** + * Register: HW_POWER_DCFUNCV + * Address: 0x70 + * SCT: no +*/ +#define HW_POWER_DCFUNCV (*(volatile unsigned long *)(REGS_POWER_BASE + 0x70)) +#define BP_POWER_DCFUNCV_VDDD 16 +#define BM_POWER_DCFUNCV_VDDD 0x3ff0000 +#define BF_POWER_DCFUNCV_VDDD(v) (((v) << 16) & 0x3ff0000) +#define BP_POWER_DCFUNCV_VDDIO 0 +#define BM_POWER_DCFUNCV_VDDIO 0x3ff +#define BF_POWER_DCFUNCV_VDDIO(v) (((v) << 0) & 0x3ff) + +/** + * Register: HW_POWER_MISC + * Address: 0x80 + * SCT: no +*/ +#define HW_POWER_MISC (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80)) +#define BP_POWER_MISC_FREQSEL 4 +#define BM_POWER_MISC_FREQSEL 0x30 +#define BF_POWER_MISC_FREQSEL(v) (((v) << 4) & 0x30) +#define BP_POWER_MISC_DELAY_TIMING 3 +#define BM_POWER_MISC_DELAY_TIMING 0x8 +#define BF_POWER_MISC_DELAY_TIMING(v) (((v) << 3) & 0x8) +#define BP_POWER_MISC_TEST 2 +#define BM_POWER_MISC_TEST 0x4 +#define BF_POWER_MISC_TEST(v) (((v) << 2) & 0x4) +#define BP_POWER_MISC_SEL_PLLCLK 1 +#define BM_POWER_MISC_SEL_PLLCLK 0x2 +#define BF_POWER_MISC_SEL_PLLCLK(v) (((v) << 1) & 0x2) +#define BP_POWER_MISC_PERIPHERALSWOFF 0 +#define BM_POWER_MISC_PERIPHERALSWOFF 0x1 +#define BF_POWER_MISC_PERIPHERALSWOFF(v) (((v) << 0) & 0x1) + +/** + * Register: HW_POWER_DCLIMITS + * Address: 0x90 + * SCT: no +*/ +#define HW_POWER_DCLIMITS (*(volatile unsigned long *)(REGS_POWER_BASE + 0x90)) +#define BP_POWER_DCLIMITS_POSLIMIT_BOOST 16 +#define BM_POWER_DCLIMITS_POSLIMIT_BOOST 0x7f0000 +#define BF_POWER_DCLIMITS_POSLIMIT_BOOST(v) (((v) << 16) & 0x7f0000) +#define BP_POWER_DCLIMITS_POSLIMIT_BUCK 8 +#define BM_POWER_DCLIMITS_POSLIMIT_BUCK 0x7f00 +#define BF_POWER_DCLIMITS_POSLIMIT_BUCK(v) (((v) << 8) & 0x7f00) +#define BP_POWER_DCLIMITS_NEGLIMIT 0 +#define BM_POWER_DCLIMITS_NEGLIMIT 0x7f +#define BF_POWER_DCLIMITS_NEGLIMIT(v) (((v) << 0) & 0x7f) + +/** + * Register: HW_POWER_LOOPCTRL + * Address: 0xa0 + * SCT: yes +*/ +#define HW_POWER_LOOPCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x0)) +#define HW_POWER_LOOPCTRL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x4)) +#define HW_POWER_LOOPCTRL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x8)) +#define HW_POWER_LOOPCTRL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0xc)) +#define BP_POWER_LOOPCTRL_TOGGLE_DIF 20 +#define BM_POWER_LOOPCTRL_TOGGLE_DIF 0x100000 +#define BF_POWER_LOOPCTRL_TOGGLE_DIF(v) (((v) << 20) & 0x100000) +#define BP_POWER_LOOPCTRL_HYST_SIGN 19 +#define BM_POWER_LOOPCTRL_HYST_SIGN 0x80000 +#define BF_POWER_LOOPCTRL_HYST_SIGN(v) (((v) << 19) & 0x80000) +#define BP_POWER_LOOPCTRL_EN_CM_HYST 18 +#define BM_POWER_LOOPCTRL_EN_CM_HYST 0x40000 +#define BF_POWER_LOOPCTRL_EN_CM_HYST(v) (((v) << 18) & 0x40000) +#define BP_POWER_LOOPCTRL_EN_DF_HYST 17 +#define BM_POWER_LOOPCTRL_EN_DF_HYST 0x20000 +#define BF_POWER_LOOPCTRL_EN_DF_HYST(v) (((v) << 17) & 0x20000) +#define BP_POWER_LOOPCTRL_CM_HYST_THRESH 16 +#define BM_POWER_LOOPCTRL_CM_HYST_THRESH 0x10000 +#define BF_POWER_LOOPCTRL_CM_HYST_THRESH(v) (((v) << 16) & 0x10000) +#define BP_POWER_LOOPCTRL_DF_HYST_THRESH 15 +#define BM_POWER_LOOPCTRL_DF_HYST_THRESH 0x8000 +#define BF_POWER_LOOPCTRL_DF_HYST_THRESH(v) (((v) << 15) & 0x8000) +#define BP_POWER_LOOPCTRL_RCSCALE_THRESH 14 +#define BM_POWER_LOOPCTRL_RCSCALE_THRESH 0x4000 +#define BF_POWER_LOOPCTRL_RCSCALE_THRESH(v) (((v) << 14) & 0x4000) +#define BP_POWER_LOOPCTRL_EN_RCSCALE 12 +#define BM_POWER_LOOPCTRL_EN_RCSCALE 0x3000 +#define BF_POWER_LOOPCTRL_EN_RCSCALE(v) (((v) << 12) & 0x3000) +#define BP_POWER_LOOPCTRL_DC_FF 8 +#define BM_POWER_LOOPCTRL_DC_FF 0x700 +#define BF_POWER_LOOPCTRL_DC_FF(v) (((v) << 8) & 0x700) +#define BP_POWER_LOOPCTRL_DC_R 4 +#define BM_POWER_LOOPCTRL_DC_R 0xf0 +#define BF_POWER_LOOPCTRL_DC_R(v) (((v) << 4) & 0xf0) +#define BP_POWER_LOOPCTRL_DC_C 0 +#define BM_POWER_LOOPCTRL_DC_C 0x3 +#define BF_POWER_LOOPCTRL_DC_C(v) (((v) << 0) & 0x3) + +/** + * Register: HW_POWER_STS + * Address: 0xb0 + * SCT: no +*/ +#define HW_POWER_STS (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0)) +#define BP_POWER_STS_BATT_CHRG_PRESENT 31 +#define BM_POWER_STS_BATT_CHRG_PRESENT 0x80000000 +#define BF_POWER_STS_BATT_CHRG_PRESENT(v) (((v) << 31) & 0x80000000) +#define BP_POWER_STS_PSWITCH 18 +#define BM_POWER_STS_PSWITCH 0xc0000 +#define BF_POWER_STS_PSWITCH(v) (((v) << 18) & 0xc0000) +#define BP_POWER_STS_AVALID_STATUS 17 +#define BM_POWER_STS_AVALID_STATUS 0x20000 +#define BF_POWER_STS_AVALID_STATUS(v) (((v) << 17) & 0x20000) +#define BP_POWER_STS_BVALID_STATUS 16 +#define BM_POWER_STS_BVALID_STATUS 0x10000 +#define BF_POWER_STS_BVALID_STATUS(v) (((v) << 16) & 0x10000) +#define BP_POWER_STS_VBUSVALID_STATUS 15 +#define BM_POWER_STS_VBUSVALID_STATUS 0x8000 +#define BF_POWER_STS_VBUSVALID_STATUS(v) (((v) << 15) & 0x8000) +#define BP_POWER_STS_SESSEND_STATUS 14 +#define BM_POWER_STS_SESSEND_STATUS 0x4000 +#define BF_POWER_STS_SESSEND_STATUS(v) (((v) << 14) & 0x4000) +#define BP_POWER_STS_MODE 13 +#define BM_POWER_STS_MODE 0x2000 +#define BF_POWER_STS_MODE(v) (((v) << 13) & 0x2000) +#define BP_POWER_STS_BATT_BO 12 +#define BM_POWER_STS_BATT_BO 0x1000 +#define BF_POWER_STS_BATT_BO(v) (((v) << 12) & 0x1000) +#define BP_POWER_STS_VDD5V_FAULT 11 +#define BM_POWER_STS_VDD5V_FAULT 0x800 +#define BF_POWER_STS_VDD5V_FAULT(v) (((v) << 11) & 0x800) +#define BP_POWER_STS_CHRGSTS 10 +#define BM_POWER_STS_CHRGSTS 0x400 +#define BF_POWER_STS_CHRGSTS(v) (((v) << 10) & 0x400) +#define BP_POWER_STS_LINREG_OK 9 +#define BM_POWER_STS_LINREG_OK 0x200 +#define BF_POWER_STS_LINREG_OK(v) (((v) << 9) & 0x200) +#define BP_POWER_STS_DC_OK 8 +#define BM_POWER_STS_DC_OK 0x100 +#define BF_POWER_STS_DC_OK(v) (((v) << 8) & 0x100) +#define BP_POWER_STS_VDDIO_BO 7 +#define BM_POWER_STS_VDDIO_BO 0x80 +#define BF_POWER_STS_VDDIO_BO(v) (((v) << 7) & 0x80) +#define BP_POWER_STS_VDDA_BO 6 +#define BM_POWER_STS_VDDA_BO 0x40 +#define BF_POWER_STS_VDDA_BO(v) (((v) << 6) & 0x40) +#define BP_POWER_STS_VDDD_BO 5 +#define BM_POWER_STS_VDDD_BO 0x20 +#define BF_POWER_STS_VDDD_BO(v) (((v) << 5) & 0x20) +#define BP_POWER_STS_VDD5V_GT_VDDIO 4 +#define BM_POWER_STS_VDD5V_GT_VDDIO 0x10 +#define BF_POWER_STS_VDD5V_GT_VDDIO(v) (((v) << 4) & 0x10) +#define BP_POWER_STS_AVALID 3 +#define BM_POWER_STS_AVALID 0x8 +#define BF_POWER_STS_AVALID(v) (((v) << 3) & 0x8) +#define BP_POWER_STS_BVALID 2 +#define BM_POWER_STS_BVALID 0x4 +#define BF_POWER_STS_BVALID(v) (((v) << 2) & 0x4) +#define BP_POWER_STS_VBUSVALID 1 +#define BM_POWER_STS_VBUSVALID 0x2 +#define BF_POWER_STS_VBUSVALID(v) (((v) << 1) & 0x2) +#define BP_POWER_STS_SESSEND 0 +#define BM_POWER_STS_SESSEND 0x1 +#define BF_POWER_STS_SESSEND(v) (((v) << 0) & 0x1) + +/** + * Register: HW_POWER_SPEED + * Address: 0xc0 + * SCT: yes +*/ +#define HW_POWER_SPEED (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x0)) +#define HW_POWER_SPEED_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x4)) +#define HW_POWER_SPEED_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x8)) +#define HW_POWER_SPEED_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0xc)) +#define BP_POWER_SPEED_STATUS 16 +#define BM_POWER_SPEED_STATUS 0xff0000 +#define BF_POWER_SPEED_STATUS(v) (((v) << 16) & 0xff0000) +#define BP_POWER_SPEED_CTRL 0 +#define BM_POWER_SPEED_CTRL 0x3 +#define BF_POWER_SPEED_CTRL(v) (((v) << 0) & 0x3) + +/** + * Register: HW_POWER_BATTMONITOR + * Address: 0xd0 + * SCT: no +*/ +#define HW_POWER_BATTMONITOR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0)) +#define BP_POWER_BATTMONITOR_BATT_VAL 16 +#define BM_POWER_BATTMONITOR_BATT_VAL 0x3ff0000 +#define BF_POWER_BATTMONITOR_BATT_VAL(v) (((v) << 16) & 0x3ff0000) +#define BP_POWER_BATTMONITOR_EN_BATADJ 6 +#define BM_POWER_BATTMONITOR_EN_BATADJ 0x40 +#define BF_POWER_BATTMONITOR_EN_BATADJ(v) (((v) << 6) & 0x40) +#define BP_POWER_BATTMONITOR_PWDN_BATTBRNOUT 5 +#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT 0x20 +#define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v) (((v) << 5) & 0x20) +#define BP_POWER_BATTMONITOR_BRWNOUT_PWD 4 +#define BM_POWER_BATTMONITOR_BRWNOUT_PWD 0x10 +#define BF_POWER_BATTMONITOR_BRWNOUT_PWD(v) (((v) << 4) & 0x10) +#define BP_POWER_BATTMONITOR_BRWNOUT_LVL 0 +#define BM_POWER_BATTMONITOR_BRWNOUT_LVL 0xf +#define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v) (((v) << 0) & 0xf) + +/** + * Register: HW_POWER_RESET + * Address: 0xe0 + * SCT: yes +*/ +#define HW_POWER_RESET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0x0)) +#define HW_POWER_RESET_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0x4)) +#define HW_POWER_RESET_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0x8)) +#define HW_POWER_RESET_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0xc)) +#define BP_POWER_RESET_UNLOCK 16 +#define BM_POWER_RESET_UNLOCK 0xffff0000 +#define BV_POWER_RESET_UNLOCK__KEY 0x3e77 +#define BF_POWER_RESET_UNLOCK(v) (((v) << 16) & 0xffff0000) +#define BF_POWER_RESET_UNLOCK_V(v) ((BV_POWER_RESET_UNLOCK__##v << 16) & 0xffff0000) +#define BP_POWER_RESET_PWD_OFF 1 +#define BM_POWER_RESET_PWD_OFF 0x2 +#define BF_POWER_RESET_PWD_OFF(v) (((v) << 1) & 0x2) +#define BP_POWER_RESET_PWD 0 +#define BM_POWER_RESET_PWD 0x1 +#define BF_POWER_RESET_PWD(v) (((v) << 0) & 0x1) + +/** + * Register: HW_POWER_DEBUG + * Address: 0xf0 + * SCT: yes +*/ +#define HW_POWER_DEBUG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0x0)) +#define HW_POWER_DEBUG_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0x4)) +#define HW_POWER_DEBUG_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0x8)) +#define HW_POWER_DEBUG_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0xc)) +#define BP_POWER_DEBUG_VBUSVALIDPIOLOCK 3 +#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x8 +#define BF_POWER_DEBUG_VBUSVALIDPIOLOCK(v) (((v) << 3) & 0x8) +#define BP_POWER_DEBUG_AVALIDPIOLOCK 2 +#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x4 +#define BF_POWER_DEBUG_AVALIDPIOLOCK(v) (((v) << 2) & 0x4) +#define BP_POWER_DEBUG_BVALIDPIOLOCK 1 +#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x2 +#define BF_POWER_DEBUG_BVALIDPIOLOCK(v) (((v) << 1) & 0x2) +#define BP_POWER_DEBUG_SESSENDPIOLOCK 0 +#define BM_POWER_DEBUG_SESSENDPIOLOCK 0x1 +#define BF_POWER_DEBUG_SESSENDPIOLOCK(v) (((v) << 0) & 0x1) + +/** + * Register: HW_POWER_SPECIAL + * Address: 0x100 + * SCT: yes +*/ +#define HW_POWER_SPECIAL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x0)) +#define HW_POWER_SPECIAL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x4)) +#define HW_POWER_SPECIAL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x8)) +#define HW_POWER_SPECIAL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0xc)) +#define BP_POWER_SPECIAL_TEST 0 +#define BM_POWER_SPECIAL_TEST 0xffffffff +#define BF_POWER_SPECIAL_TEST(v) (((v) << 0) & 0xffffffff) + +/** + * Register: HW_POWER_VERSION + * Address: 0x110 + * SCT: no +*/ +#define HW_POWER_VERSION (*(volatile unsigned long *)(REGS_POWER_BASE + 0x110)) +#define BP_POWER_VERSION_MAJOR 24 +#define BM_POWER_VERSION_MAJOR 0xff000000 +#define BF_POWER_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) +#define BP_POWER_VERSION_MINOR 16 +#define BM_POWER_VERSION_MINOR 0xff0000 +#define BF_POWER_VERSION_MINOR(v) (((v) << 16) & 0xff0000) +#define BP_POWER_VERSION_STEP 0 +#define BM_POWER_VERSION_STEP 0xffff +#define BF_POWER_VERSION_STEP(v) (((v) << 0) & 0xffff) + +#endif /* __HEADERGEN__STMP3700__POWER__H__ */ -- cgit v1.2.3