From 017667c2dc9843eb5082e991f421c773636dcf36 Mon Sep 17 00:00:00 2001 From: Amaury Pouly Date: Thu, 13 Jun 2013 19:03:33 +0200 Subject: imx233: generate register headers for stmp3600, stmp3700 and imx233 Change-Id: Ia87086f4f4f4ecbb844ffd869407b14ea2509934 --- .../target/arm/imx233/regs/stmp3700/regs-lradc.h | 708 +++++++++++++++++++++ 1 file changed, 708 insertions(+) create mode 100644 firmware/target/arm/imx233/regs/stmp3700/regs-lradc.h (limited to 'firmware/target/arm/imx233/regs/stmp3700/regs-lradc.h') diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-lradc.h b/firmware/target/arm/imx233/regs/stmp3700/regs-lradc.h new file mode 100644 index 0000000000..ad0beecbae --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-lradc.h @@ -0,0 +1,708 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 2.1.7 + * XML versions: stmp3700:3.2.0 + * + * Copyright (C) 2013 by Amaury Pouly + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN__STMP3700__LRADC__H__ +#define __HEADERGEN__STMP3700__LRADC__H__ + +#define REGS_LRADC_BASE (0x80050000) + +#define REGS_LRADC_VERSION "3.2.0" + +/** + * Register: HW_LRADC_CTRL0 + * Address: 0 + * SCT: yes +*/ +#define HW_LRADC_CTRL0 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x0)) +#define HW_LRADC_CTRL0_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x4)) +#define HW_LRADC_CTRL0_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x8)) +#define HW_LRADC_CTRL0_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0xc)) +#define BP_LRADC_CTRL0_SFTRST 31 +#define BM_LRADC_CTRL0_SFTRST 0x80000000 +#define BF_LRADC_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) +#define BP_LRADC_CTRL0_CLKGATE 30 +#define BM_LRADC_CTRL0_CLKGATE 0x40000000 +#define BF_LRADC_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) +#define BP_LRADC_CTRL0_ONCHIP_GROUNDREF 21 +#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x200000 +#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF 0x0 +#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON 0x1 +#define BF_LRADC_CTRL0_ONCHIP_GROUNDREF(v) (((v) << 21) & 0x200000) +#define BF_LRADC_CTRL0_ONCHIP_GROUNDREF_V(v) ((BV_LRADC_CTRL0_ONCHIP_GROUNDREF__##v << 21) & 0x200000) +#define BP_LRADC_CTRL0_TOUCH_DETECT_ENABLE 20 +#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x100000 +#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON 0x1 +#define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE(v) (((v) << 20) & 0x100000) +#define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE_V(v) ((BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__##v << 20) & 0x100000) +#define BP_LRADC_CTRL0_YMINUS_ENABLE 19 +#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x80000 +#define BV_LRADC_CTRL0_YMINUS_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_YMINUS_ENABLE__ON 0x1 +#define BF_LRADC_CTRL0_YMINUS_ENABLE(v) (((v) << 19) & 0x80000) +#define BF_LRADC_CTRL0_YMINUS_ENABLE_V(v) ((BV_LRADC_CTRL0_YMINUS_ENABLE__##v << 19) & 0x80000) +#define BP_LRADC_CTRL0_XMINUS_ENABLE 18 +#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x40000 +#define BV_LRADC_CTRL0_XMINUS_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_XMINUS_ENABLE__ON 0x1 +#define BF_LRADC_CTRL0_XMINUS_ENABLE(v) (((v) << 18) & 0x40000) +#define BF_LRADC_CTRL0_XMINUS_ENABLE_V(v) ((BV_LRADC_CTRL0_XMINUS_ENABLE__##v << 18) & 0x40000) +#define BP_LRADC_CTRL0_YPLUS_ENABLE 17 +#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x20000 +#define BV_LRADC_CTRL0_YPLUS_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_YPLUS_ENABLE__ON 0x1 +#define BF_LRADC_CTRL0_YPLUS_ENABLE(v) (((v) << 17) & 0x20000) +#define BF_LRADC_CTRL0_YPLUS_ENABLE_V(v) ((BV_LRADC_CTRL0_YPLUS_ENABLE__##v << 17) & 0x20000) +#define BP_LRADC_CTRL0_XPLUS_ENABLE 16 +#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x10000 +#define BV_LRADC_CTRL0_XPLUS_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_XPLUS_ENABLE__ON 0x1 +#define BF_LRADC_CTRL0_XPLUS_ENABLE(v) (((v) << 16) & 0x10000) +#define BF_LRADC_CTRL0_XPLUS_ENABLE_V(v) ((BV_LRADC_CTRL0_XPLUS_ENABLE__##v << 16) & 0x10000) +#define BP_LRADC_CTRL0_SCHEDULE 0 +#define BM_LRADC_CTRL0_SCHEDULE 0xff +#define BF_LRADC_CTRL0_SCHEDULE(v) (((v) << 0) & 0xff) + +/** + * Register: HW_LRADC_CTRL1 + * Address: 0x10 + * SCT: yes +*/ +#define HW_LRADC_CTRL1 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x0)) +#define HW_LRADC_CTRL1_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x4)) +#define HW_LRADC_CTRL1_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x8)) +#define HW_LRADC_CTRL1_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0xc)) +#define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 24 +#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x1000000 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE 0x1 +#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(v) (((v) << 24) & 0x1000000) +#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN_V(v) ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__##v << 24) & 0x1000000) +#define BP_LRADC_CTRL1_LRADC7_IRQ_EN 23 +#define BM_LRADC_CTRL1_LRADC7_IRQ_EN 0x800000 +#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE 0x1 +#define BF_LRADC_CTRL1_LRADC7_IRQ_EN(v) (((v) << 23) & 0x800000) +#define BF_LRADC_CTRL1_LRADC7_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC7_IRQ_EN__##v << 23) & 0x800000) +#define BP_LRADC_CTRL1_LRADC6_IRQ_EN 22 +#define BM_LRADC_CTRL1_LRADC6_IRQ_EN 0x400000 +#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE 0x1 +#define BF_LRADC_CTRL1_LRADC6_IRQ_EN(v) (((v) << 22) & 0x400000) +#define BF_LRADC_CTRL1_LRADC6_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC6_IRQ_EN__##v << 22) & 0x400000) +#define BP_LRADC_CTRL1_LRADC5_IRQ_EN 21 +#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x200000 +#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE 0x1 +#define BF_LRADC_CTRL1_LRADC5_IRQ_EN(v) (((v) << 21) & 0x200000) +#define BF_LRADC_CTRL1_LRADC5_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC5_IRQ_EN__##v << 21) & 0x200000) +#define BP_LRADC_CTRL1_LRADC4_IRQ_EN 20 +#define BM_LRADC_CTRL1_LRADC4_IRQ_EN 0x100000 +#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE 0x1 +#define BF_LRADC_CTRL1_LRADC4_IRQ_EN(v) (((v) << 20) & 0x100000) +#define BF_LRADC_CTRL1_LRADC4_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC4_IRQ_EN__##v << 20) & 0x100000) +#define BP_LRADC_CTRL1_LRADC3_IRQ_EN 19 +#define BM_LRADC_CTRL1_LRADC3_IRQ_EN 0x80000 +#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE 0x1 +#define BF_LRADC_CTRL1_LRADC3_IRQ_EN(v) (((v) << 19) & 0x80000) +#define BF_LRADC_CTRL1_LRADC3_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC3_IRQ_EN__##v << 19) & 0x80000) +#define BP_LRADC_CTRL1_LRADC2_IRQ_EN 18 +#define BM_LRADC_CTRL1_LRADC2_IRQ_EN 0x40000 +#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE 0x1 +#define BF_LRADC_CTRL1_LRADC2_IRQ_EN(v) (((v) << 18) & 0x40000) +#define BF_LRADC_CTRL1_LRADC2_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC2_IRQ_EN__##v << 18) & 0x40000) +#define BP_LRADC_CTRL1_LRADC1_IRQ_EN 17 +#define BM_LRADC_CTRL1_LRADC1_IRQ_EN 0x20000 +#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE 0x1 +#define BF_LRADC_CTRL1_LRADC1_IRQ_EN(v) (((v) << 17) & 0x20000) +#define BF_LRADC_CTRL1_LRADC1_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC1_IRQ_EN__##v << 17) & 0x20000) +#define BP_LRADC_CTRL1_LRADC0_IRQ_EN 16 +#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x10000 +#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE 0x1 +#define BF_LRADC_CTRL1_LRADC0_IRQ_EN(v) (((v) << 16) & 0x10000) +#define BF_LRADC_CTRL1_LRADC0_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC0_IRQ_EN__##v << 16) & 0x10000) +#define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ 8 +#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x100 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING 0x1 +#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ(v) (((v) << 8) & 0x100) +#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_V(v) ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__##v << 8) & 0x100) +#define BP_LRADC_CTRL1_LRADC7_IRQ 7 +#define BM_LRADC_CTRL1_LRADC7_IRQ 0x80 +#define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING 0x1 +#define BF_LRADC_CTRL1_LRADC7_IRQ(v) (((v) << 7) & 0x80) +#define BF_LRADC_CTRL1_LRADC7_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC7_IRQ__##v << 7) & 0x80) +#define BP_LRADC_CTRL1_LRADC6_IRQ 6 +#define BM_LRADC_CTRL1_LRADC6_IRQ 0x40 +#define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING 0x1 +#define BF_LRADC_CTRL1_LRADC6_IRQ(v) (((v) << 6) & 0x40) +#define BF_LRADC_CTRL1_LRADC6_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC6_IRQ__##v << 6) & 0x40) +#define BP_LRADC_CTRL1_LRADC5_IRQ 5 +#define BM_LRADC_CTRL1_LRADC5_IRQ 0x20 +#define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING 0x1 +#define BF_LRADC_CTRL1_LRADC5_IRQ(v) (((v) << 5) & 0x20) +#define BF_LRADC_CTRL1_LRADC5_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC5_IRQ__##v << 5) & 0x20) +#define BP_LRADC_CTRL1_LRADC4_IRQ 4 +#define BM_LRADC_CTRL1_LRADC4_IRQ 0x10 +#define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING 0x1 +#define BF_LRADC_CTRL1_LRADC4_IRQ(v) (((v) << 4) & 0x10) +#define BF_LRADC_CTRL1_LRADC4_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC4_IRQ__##v << 4) & 0x10) +#define BP_LRADC_CTRL1_LRADC3_IRQ 3 +#define BM_LRADC_CTRL1_LRADC3_IRQ 0x8 +#define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING 0x1 +#define BF_LRADC_CTRL1_LRADC3_IRQ(v) (((v) << 3) & 0x8) +#define BF_LRADC_CTRL1_LRADC3_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC3_IRQ__##v << 3) & 0x8) +#define BP_LRADC_CTRL1_LRADC2_IRQ 2 +#define BM_LRADC_CTRL1_LRADC2_IRQ 0x4 +#define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING 0x1 +#define BF_LRADC_CTRL1_LRADC2_IRQ(v) (((v) << 2) & 0x4) +#define BF_LRADC_CTRL1_LRADC2_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC2_IRQ__##v << 2) & 0x4) +#define BP_LRADC_CTRL1_LRADC1_IRQ 1 +#define BM_LRADC_CTRL1_LRADC1_IRQ 0x2 +#define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING 0x1 +#define BF_LRADC_CTRL1_LRADC1_IRQ(v) (((v) << 1) & 0x2) +#define BF_LRADC_CTRL1_LRADC1_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC1_IRQ__##v << 1) & 0x2) +#define BP_LRADC_CTRL1_LRADC0_IRQ 0 +#define BM_LRADC_CTRL1_LRADC0_IRQ 0x1 +#define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING 0x1 +#define BF_LRADC_CTRL1_LRADC0_IRQ(v) (((v) << 0) & 0x1) +#define BF_LRADC_CTRL1_LRADC0_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC0_IRQ__##v << 0) & 0x1) + +/** + * Register: HW_LRADC_CTRL2 + * Address: 0x20 + * SCT: yes +*/ +#define HW_LRADC_CTRL2 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x0)) +#define HW_LRADC_CTRL2_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x4)) +#define HW_LRADC_CTRL2_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x8)) +#define HW_LRADC_CTRL2_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0xc)) +#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24 +#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xff000000 +#define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v) (((v) << 24) & 0xff000000) +#define BP_LRADC_CTRL2_BL_AMP_BYPASS 23 +#define BM_LRADC_CTRL2_BL_AMP_BYPASS 0x800000 +#define BV_LRADC_CTRL2_BL_AMP_BYPASS__DISABLE 0x0 +#define BV_LRADC_CTRL2_BL_AMP_BYPASS__ENABLE 0x1 +#define BF_LRADC_CTRL2_BL_AMP_BYPASS(v) (((v) << 23) & 0x800000) +#define BF_LRADC_CTRL2_BL_AMP_BYPASS_V(v) ((BV_LRADC_CTRL2_BL_AMP_BYPASS__##v << 23) & 0x800000) +#define BP_LRADC_CTRL2_BL_ENABLE 22 +#define BM_LRADC_CTRL2_BL_ENABLE 0x400000 +#define BF_LRADC_CTRL2_BL_ENABLE(v) (((v) << 22) & 0x400000) +#define BP_LRADC_CTRL2_BL_MUX_SELECT 21 +#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x200000 +#define BF_LRADC_CTRL2_BL_MUX_SELECT(v) (((v) << 21) & 0x200000) +#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16 +#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x1f0000 +#define BF_LRADC_CTRL2_BL_BRIGHTNESS(v) (((v) << 16) & 0x1f0000) +#define BP_LRADC_CTRL2_TEMPSENSE_PWD 15 +#define BM_LRADC_CTRL2_TEMPSENSE_PWD 0x8000 +#define BV_LRADC_CTRL2_TEMPSENSE_PWD__DISABLE 0x0 +#define BV_LRADC_CTRL2_TEMPSENSE_PWD__ENABLE 0x1 +#define BF_LRADC_CTRL2_TEMPSENSE_PWD(v) (((v) << 15) & 0x8000) +#define BF_LRADC_CTRL2_TEMPSENSE_PWD_V(v) ((BV_LRADC_CTRL2_TEMPSENSE_PWD__##v << 15) & 0x8000) +#define BP_LRADC_CTRL2_EXT_EN1 13 +#define BM_LRADC_CTRL2_EXT_EN1 0x2000 +#define BV_LRADC_CTRL2_EXT_EN1__DISABLE 0x0 +#define BV_LRADC_CTRL2_EXT_EN1__ENABLE 0x1 +#define BF_LRADC_CTRL2_EXT_EN1(v) (((v) << 13) & 0x2000) +#define BF_LRADC_CTRL2_EXT_EN1_V(v) ((BV_LRADC_CTRL2_EXT_EN1__##v << 13) & 0x2000) +#define BP_LRADC_CTRL2_EXT_EN0 12 +#define BM_LRADC_CTRL2_EXT_EN0 0x1000 +#define BF_LRADC_CTRL2_EXT_EN0(v) (((v) << 12) & 0x1000) +#define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 9 +#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 0x200 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE 0x0 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE 0x1 +#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(v) (((v) << 9) & 0x200) +#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1_V(v) ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__##v << 9) & 0x200) +#define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 8 +#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 0x100 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE 0x0 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE 0x1 +#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(v) (((v) << 8) & 0x100) +#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0_V(v) ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__##v << 8) & 0x100) +#define BP_LRADC_CTRL2_TEMP_ISRC1 4 +#define BM_LRADC_CTRL2_TEMP_ISRC1 0xf0 +#define BV_LRADC_CTRL2_TEMP_ISRC1__300 0xf +#define BV_LRADC_CTRL2_TEMP_ISRC1__280 0xe +#define BV_LRADC_CTRL2_TEMP_ISRC1__260 0xd +#define BV_LRADC_CTRL2_TEMP_ISRC1__240 0xc +#define BV_LRADC_CTRL2_TEMP_ISRC1__220 0xb +#define BV_LRADC_CTRL2_TEMP_ISRC1__200 0xa +#define BV_LRADC_CTRL2_TEMP_ISRC1__180 0x9 +#define BV_LRADC_CTRL2_TEMP_ISRC1__160 0x8 +#define BV_LRADC_CTRL2_TEMP_ISRC1__140 0x7 +#define BV_LRADC_CTRL2_TEMP_ISRC1__120 0x6 +#define BV_LRADC_CTRL2_TEMP_ISRC1__100 0x5 +#define BV_LRADC_CTRL2_TEMP_ISRC1__80 0x4 +#define BV_LRADC_CTRL2_TEMP_ISRC1__60 0x3 +#define BV_LRADC_CTRL2_TEMP_ISRC1__40 0x2 +#define BV_LRADC_CTRL2_TEMP_ISRC1__20 0x1 +#define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO 0x0 +#define BF_LRADC_CTRL2_TEMP_ISRC1(v) (((v) << 4) & 0xf0) +#define BF_LRADC_CTRL2_TEMP_ISRC1_V(v) ((BV_LRADC_CTRL2_TEMP_ISRC1__##v << 4) & 0xf0) +#define BP_LRADC_CTRL2_TEMP_ISRC0 0 +#define BM_LRADC_CTRL2_TEMP_ISRC0 0xf +#define BV_LRADC_CTRL2_TEMP_ISRC0__300 0xf +#define BV_LRADC_CTRL2_TEMP_ISRC0__280 0xe +#define BV_LRADC_CTRL2_TEMP_ISRC0__260 0xd +#define BV_LRADC_CTRL2_TEMP_ISRC0__240 0xc +#define BV_LRADC_CTRL2_TEMP_ISRC0__220 0xb +#define BV_LRADC_CTRL2_TEMP_ISRC0__200 0xa +#define BV_LRADC_CTRL2_TEMP_ISRC0__180 0x9 +#define BV_LRADC_CTRL2_TEMP_ISRC0__160 0x8 +#define BV_LRADC_CTRL2_TEMP_ISRC0__140 0x7 +#define BV_LRADC_CTRL2_TEMP_ISRC0__120 0x6 +#define BV_LRADC_CTRL2_TEMP_ISRC0__100 0x5 +#define BV_LRADC_CTRL2_TEMP_ISRC0__80 0x4 +#define BV_LRADC_CTRL2_TEMP_ISRC0__60 0x3 +#define BV_LRADC_CTRL2_TEMP_ISRC0__40 0x2 +#define BV_LRADC_CTRL2_TEMP_ISRC0__20 0x1 +#define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO 0x0 +#define BF_LRADC_CTRL2_TEMP_ISRC0(v) (((v) << 0) & 0xf) +#define BF_LRADC_CTRL2_TEMP_ISRC0_V(v) ((BV_LRADC_CTRL2_TEMP_ISRC0__##v << 0) & 0xf) + +/** + * Register: HW_LRADC_CTRL3 + * Address: 0x30 + * SCT: yes +*/ +#define HW_LRADC_CTRL3 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x0)) +#define HW_LRADC_CTRL3_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x4)) +#define HW_LRADC_CTRL3_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x8)) +#define HW_LRADC_CTRL3_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0xc)) +#define BP_LRADC_CTRL3_DISCARD 24 +#define BM_LRADC_CTRL3_DISCARD 0x3000000 +#define BV_LRADC_CTRL3_DISCARD__1_SAMPLE 0x1 +#define BV_LRADC_CTRL3_DISCARD__2_SAMPLES 0x2 +#define BV_LRADC_CTRL3_DISCARD__3_SAMPLES 0x3 +#define BF_LRADC_CTRL3_DISCARD(v) (((v) << 24) & 0x3000000) +#define BF_LRADC_CTRL3_DISCARD_V(v) ((BV_LRADC_CTRL3_DISCARD__##v << 24) & 0x3000000) +#define BP_LRADC_CTRL3_FORCE_ANALOG_PWUP 23 +#define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP 0x800000 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF 0x0 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON 0x1 +#define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP(v) (((v) << 23) & 0x800000) +#define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP_V(v) ((BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__##v << 23) & 0x800000) +#define BP_LRADC_CTRL3_FORCE_ANALOG_PWDN 22 +#define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN 0x400000 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON 0x0 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF 0x1 +#define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN(v) (((v) << 22) & 0x400000) +#define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN_V(v) ((BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__##v << 22) & 0x400000) +#define BP_LRADC_CTRL3_CYCLE_TIME 8 +#define BM_LRADC_CTRL3_CYCLE_TIME 0x300 +#define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ 0x0 +#define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ 0x1 +#define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ 0x2 +#define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ 0x3 +#define BF_LRADC_CTRL3_CYCLE_TIME(v) (((v) << 8) & 0x300) +#define BF_LRADC_CTRL3_CYCLE_TIME_V(v) ((BV_LRADC_CTRL3_CYCLE_TIME__##v << 8) & 0x300) +#define BP_LRADC_CTRL3_HIGH_TIME 4 +#define BM_LRADC_CTRL3_HIGH_TIME 0x30 +#define BV_LRADC_CTRL3_HIGH_TIME__42NS 0x0 +#define BV_LRADC_CTRL3_HIGH_TIME__83NS 0x1 +#define BV_LRADC_CTRL3_HIGH_TIME__125NS 0x2 +#define BV_LRADC_CTRL3_HIGH_TIME__250NS 0x3 +#define BF_LRADC_CTRL3_HIGH_TIME(v) (((v) << 4) & 0x30) +#define BF_LRADC_CTRL3_HIGH_TIME_V(v) ((BV_LRADC_CTRL3_HIGH_TIME__##v << 4) & 0x30) +#define BP_LRADC_CTRL3_DELAY_CLOCK 1 +#define BM_LRADC_CTRL3_DELAY_CLOCK 0x2 +#define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL 0x0 +#define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED 0x1 +#define BF_LRADC_CTRL3_DELAY_CLOCK(v) (((v) << 1) & 0x2) +#define BF_LRADC_CTRL3_DELAY_CLOCK_V(v) ((BV_LRADC_CTRL3_DELAY_CLOCK__##v << 1) & 0x2) +#define BP_LRADC_CTRL3_INVERT_CLOCK 0 +#define BM_LRADC_CTRL3_INVERT_CLOCK 0x1 +#define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL 0x0 +#define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT 0x1 +#define BF_LRADC_CTRL3_INVERT_CLOCK(v) (((v) << 0) & 0x1) +#define BF_LRADC_CTRL3_INVERT_CLOCK_V(v) ((BV_LRADC_CTRL3_INVERT_CLOCK__##v << 0) & 0x1) + +/** + * Register: HW_LRADC_STATUS + * Address: 0x40 + * SCT: no +*/ +#define HW_LRADC_STATUS (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x40)) +#define BP_LRADC_STATUS_TEMP1_PRESENT 26 +#define BM_LRADC_STATUS_TEMP1_PRESENT 0x4000000 +#define BF_LRADC_STATUS_TEMP1_PRESENT(v) (((v) << 26) & 0x4000000) +#define BP_LRADC_STATUS_TEMP0_PRESENT 25 +#define BM_LRADC_STATUS_TEMP0_PRESENT 0x2000000 +#define BF_LRADC_STATUS_TEMP0_PRESENT(v) (((v) << 25) & 0x2000000) +#define BP_LRADC_STATUS_TOUCH_PANEL_PRESENT 24 +#define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT 0x1000000 +#define BF_LRADC_STATUS_TOUCH_PANEL_PRESENT(v) (((v) << 24) & 0x1000000) +#define BP_LRADC_STATUS_CHANNEL7_PRESENT 23 +#define BM_LRADC_STATUS_CHANNEL7_PRESENT 0x800000 +#define BF_LRADC_STATUS_CHANNEL7_PRESENT(v) (((v) << 23) & 0x800000) +#define BP_LRADC_STATUS_CHANNEL6_PRESENT 22 +#define BM_LRADC_STATUS_CHANNEL6_PRESENT 0x400000 +#define BF_LRADC_STATUS_CHANNEL6_PRESENT(v) (((v) << 22) & 0x400000) +#define BP_LRADC_STATUS_CHANNEL5_PRESENT 21 +#define BM_LRADC_STATUS_CHANNEL5_PRESENT 0x200000 +#define BF_LRADC_STATUS_CHANNEL5_PRESENT(v) (((v) << 21) & 0x200000) +#define BP_LRADC_STATUS_CHANNEL4_PRESENT 20 +#define BM_LRADC_STATUS_CHANNEL4_PRESENT 0x100000 +#define BF_LRADC_STATUS_CHANNEL4_PRESENT(v) (((v) << 20) & 0x100000) +#define BP_LRADC_STATUS_CHANNEL3_PRESENT 19 +#define BM_LRADC_STATUS_CHANNEL3_PRESENT 0x80000 +#define BF_LRADC_STATUS_CHANNEL3_PRESENT(v) (((v) << 19) & 0x80000) +#define BP_LRADC_STATUS_CHANNEL2_PRESENT 18 +#define BM_LRADC_STATUS_CHANNEL2_PRESENT 0x40000 +#define BF_LRADC_STATUS_CHANNEL2_PRESENT(v) (((v) << 18) & 0x40000) +#define BP_LRADC_STATUS_CHANNEL1_PRESENT 17 +#define BM_LRADC_STATUS_CHANNEL1_PRESENT 0x20000 +#define BF_LRADC_STATUS_CHANNEL1_PRESENT(v) (((v) << 17) & 0x20000) +#define BP_LRADC_STATUS_CHANNEL0_PRESENT 16 +#define BM_LRADC_STATUS_CHANNEL0_PRESENT 0x10000 +#define BF_LRADC_STATUS_CHANNEL0_PRESENT(v) (((v) << 16) & 0x10000) +#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0 +#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x1 +#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN 0x0 +#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT 0x1 +#define BF_LRADC_STATUS_TOUCH_DETECT_RAW(v) (((v) << 0) & 0x1) +#define BF_LRADC_STATUS_TOUCH_DETECT_RAW_V(v) ((BV_LRADC_STATUS_TOUCH_DETECT_RAW__##v << 0) & 0x1) + +/** + * Register: HW_LRADC_CHn + * Address: 0x50+n*0x10 + * SCT: yes +*/ +#define HW_LRADC_CHn(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x0)) +#define HW_LRADC_CHn_SET(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x4)) +#define HW_LRADC_CHn_CLR(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x8)) +#define HW_LRADC_CHn_TOG(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0xc)) +#define BP_LRADC_CHn_TOGGLE 31 +#define BM_LRADC_CHn_TOGGLE 0x80000000 +#define BF_LRADC_CHn_TOGGLE(v) (((v) << 31) & 0x80000000) +#define BP_LRADC_CHn_ACCUMULATE 29 +#define BM_LRADC_CHn_ACCUMULATE 0x20000000 +#define BF_LRADC_CHn_ACCUMULATE(v) (((v) << 29) & 0x20000000) +#define BP_LRADC_CHn_NUM_SAMPLES 24 +#define BM_LRADC_CHn_NUM_SAMPLES 0x1f000000 +#define BF_LRADC_CHn_NUM_SAMPLES(v) (((v) << 24) & 0x1f000000) +#define BP_LRADC_CHn_VALUE 0 +#define BM_LRADC_CHn_VALUE 0x3ffff +#define BF_LRADC_CHn_VALUE(v) (((v) << 0) & 0x3ffff) + +/** + * Register: HW_LRADC_DELAYn + * Address: 0xd0+n*0x10 + * SCT: yes +*/ +#define HW_LRADC_DELAYn(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x0)) +#define HW_LRADC_DELAYn_SET(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x4)) +#define HW_LRADC_DELAYn_CLR(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x8)) +#define HW_LRADC_DELAYn_TOG(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0xc)) +#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24 +#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xff000000 +#define BF_LRADC_DELAYn_TRIGGER_LRADCS(v) (((v) << 24) & 0xff000000) +#define BP_LRADC_DELAYn_KICK 20 +#define BM_LRADC_DELAYn_KICK 0x100000 +#define BF_LRADC_DELAYn_KICK(v) (((v) << 20) & 0x100000) +#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16 +#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0xf0000 +#define BF_LRADC_DELAYn_TRIGGER_DELAYS(v) (((v) << 16) & 0xf0000) +#define BP_LRADC_DELAYn_LOOP_COUNT 11 +#define BM_LRADC_DELAYn_LOOP_COUNT 0xf800 +#define BF_LRADC_DELAYn_LOOP_COUNT(v) (((v) << 11) & 0xf800) +#define BP_LRADC_DELAYn_DELAY 0 +#define BM_LRADC_DELAYn_DELAY 0x7ff +#define BF_LRADC_DELAYn_DELAY(v) (((v) << 0) & 0x7ff) + +/** + * Register: HW_LRADC_DEBUG0 + * Address: 0x110 + * SCT: no +*/ +#define HW_LRADC_DEBUG0 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x110)) +#define BP_LRADC_DEBUG0_READONLY 16 +#define BM_LRADC_DEBUG0_READONLY 0xffff0000 +#define BF_LRADC_DEBUG0_READONLY(v) (((v) << 16) & 0xffff0000) +#define BP_LRADC_DEBUG0_STATE 0 +#define BM_LRADC_DEBUG0_STATE 0xfff +#define BF_LRADC_DEBUG0_STATE(v) (((v) << 0) & 0xfff) + +/** + * Register: HW_LRADC_DEBUG1 + * Address: 0x120 + * SCT: yes +*/ +#define HW_LRADC_DEBUG1 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x0)) +#define HW_LRADC_DEBUG1_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x4)) +#define HW_LRADC_DEBUG1_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x8)) +#define HW_LRADC_DEBUG1_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0xc)) +#define BP_LRADC_DEBUG1_REQUEST 16 +#define BM_LRADC_DEBUG1_REQUEST 0xff0000 +#define BF_LRADC_DEBUG1_REQUEST(v) (((v) << 16) & 0xff0000) +#define BP_LRADC_DEBUG1_TESTMODE_COUNT 8 +#define BM_LRADC_DEBUG1_TESTMODE_COUNT 0x1f00 +#define BF_LRADC_DEBUG1_TESTMODE_COUNT(v) (((v) << 8) & 0x1f00) +#define BP_LRADC_DEBUG1_TESTMODE6 2 +#define BM_LRADC_DEBUG1_TESTMODE6 0x4 +#define BV_LRADC_DEBUG1_TESTMODE6__NORMAL 0x0 +#define BV_LRADC_DEBUG1_TESTMODE6__TEST 0x1 +#define BF_LRADC_DEBUG1_TESTMODE6(v) (((v) << 2) & 0x4) +#define BF_LRADC_DEBUG1_TESTMODE6_V(v) ((BV_LRADC_DEBUG1_TESTMODE6__##v << 2) & 0x4) +#define BP_LRADC_DEBUG1_TESTMODE5 1 +#define BM_LRADC_DEBUG1_TESTMODE5 0x2 +#define BV_LRADC_DEBUG1_TESTMODE5__NORMAL 0x0 +#define BV_LRADC_DEBUG1_TESTMODE5__TEST 0x1 +#define BF_LRADC_DEBUG1_TESTMODE5(v) (((v) << 1) & 0x2) +#define BF_LRADC_DEBUG1_TESTMODE5_V(v) ((BV_LRADC_DEBUG1_TESTMODE5__##v << 1) & 0x2) +#define BP_LRADC_DEBUG1_TESTMODE 0 +#define BM_LRADC_DEBUG1_TESTMODE 0x1 +#define BV_LRADC_DEBUG1_TESTMODE__NORMAL 0x0 +#define BV_LRADC_DEBUG1_TESTMODE__TEST 0x1 +#define BF_LRADC_DEBUG1_TESTMODE(v) (((v) << 0) & 0x1) +#define BF_LRADC_DEBUG1_TESTMODE_V(v) ((BV_LRADC_DEBUG1_TESTMODE__##v << 0) & 0x1) + +/** + * Register: HW_LRADC_CONVERSION + * Address: 0x130 + * SCT: yes +*/ +#define HW_LRADC_CONVERSION (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x0)) +#define HW_LRADC_CONVERSION_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x4)) +#define HW_LRADC_CONVERSION_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x8)) +#define HW_LRADC_CONVERSION_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0xc)) +#define BP_LRADC_CONVERSION_AUTOMATIC 20 +#define BM_LRADC_CONVERSION_AUTOMATIC 0x100000 +#define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE 0x0 +#define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE 0x1 +#define BF_LRADC_CONVERSION_AUTOMATIC(v) (((v) << 20) & 0x100000) +#define BF_LRADC_CONVERSION_AUTOMATIC_V(v) ((BV_LRADC_CONVERSION_AUTOMATIC__##v << 20) & 0x100000) +#define BP_LRADC_CONVERSION_SCALE_FACTOR 16 +#define BM_LRADC_CONVERSION_SCALE_FACTOR 0x30000 +#define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH 0x0 +#define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH 0x1 +#define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION 0x2 +#define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION 0x3 +#define BF_LRADC_CONVERSION_SCALE_FACTOR(v) (((v) << 16) & 0x30000) +#define BF_LRADC_CONVERSION_SCALE_FACTOR_V(v) ((BV_LRADC_CONVERSION_SCALE_FACTOR__##v << 16) & 0x30000) +#define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0 +#define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0x3ff +#define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v) (((v) << 0) & 0x3ff) + +/** + * Register: HW_LRADC_CTRL4 + * Address: 0x140 + * SCT: yes +*/ +#define HW_LRADC_CTRL4 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x0)) +#define HW_LRADC_CTRL4_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x4)) +#define HW_LRADC_CTRL4_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x8)) +#define HW_LRADC_CTRL4_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0xc)) +#define BP_LRADC_CTRL4_LRADC7SELECT 28 +#define BM_LRADC_CTRL4_LRADC7SELECT 0xf0000000 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL10 0xa +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL11 0xb +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL12 0xc +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL13 0xd +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL14 0xe +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL15 0xf +#define BF_LRADC_CTRL4_LRADC7SELECT(v) (((v) << 28) & 0xf0000000) +#define BF_LRADC_CTRL4_LRADC7SELECT_V(v) ((BV_LRADC_CTRL4_LRADC7SELECT__##v << 28) & 0xf0000000) +#define BP_LRADC_CTRL4_LRADC6SELECT 24 +#define BM_LRADC_CTRL4_LRADC6SELECT 0xf000000 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL10 0xa +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL11 0xb +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL12 0xc +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL13 0xd +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL14 0xe +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL15 0xf +#define BF_LRADC_CTRL4_LRADC6SELECT(v) (((v) << 24) & 0xf000000) +#define BF_LRADC_CTRL4_LRADC6SELECT_V(v) ((BV_LRADC_CTRL4_LRADC6SELECT__##v << 24) & 0xf000000) +#define BP_LRADC_CTRL4_LRADC5SELECT 20 +#define BM_LRADC_CTRL4_LRADC5SELECT 0xf00000 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL10 0xa +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL11 0xb +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL12 0xc +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL13 0xd +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL14 0xe +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL15 0xf +#define BF_LRADC_CTRL4_LRADC5SELECT(v) (((v) << 20) & 0xf00000) +#define BF_LRADC_CTRL4_LRADC5SELECT_V(v) ((BV_LRADC_CTRL4_LRADC5SELECT__##v << 20) & 0xf00000) +#define BP_LRADC_CTRL4_LRADC4SELECT 16 +#define BM_LRADC_CTRL4_LRADC4SELECT 0xf0000 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL10 0xa +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL11 0xb +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL12 0xc +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL13 0xd +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL14 0xe +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL15 0xf +#define BF_LRADC_CTRL4_LRADC4SELECT(v) (((v) << 16) & 0xf0000) +#define BF_LRADC_CTRL4_LRADC4SELECT_V(v) ((BV_LRADC_CTRL4_LRADC4SELECT__##v << 16) & 0xf0000) +#define BP_LRADC_CTRL4_LRADC3SELECT 12 +#define BM_LRADC_CTRL4_LRADC3SELECT 0xf000 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL10 0xa +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL11 0xb +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL12 0xc +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL13 0xd +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL14 0xe +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL15 0xf +#define BF_LRADC_CTRL4_LRADC3SELECT(v) (((v) << 12) & 0xf000) +#define BF_LRADC_CTRL4_LRADC3SELECT_V(v) ((BV_LRADC_CTRL4_LRADC3SELECT__##v << 12) & 0xf000) +#define BP_LRADC_CTRL4_LRADC2SELECT 8 +#define BM_LRADC_CTRL4_LRADC2SELECT 0xf00 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL10 0xa +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL11 0xb +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL12 0xc +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL13 0xd +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL14 0xe +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL15 0xf +#define BF_LRADC_CTRL4_LRADC2SELECT(v) (((v) << 8) & 0xf00) +#define BF_LRADC_CTRL4_LRADC2SELECT_V(v) ((BV_LRADC_CTRL4_LRADC2SELECT__##v << 8) & 0xf00) +#define BP_LRADC_CTRL4_LRADC1SELECT 4 +#define BM_LRADC_CTRL4_LRADC1SELECT 0xf0 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL10 0xa +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL11 0xb +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL12 0xc +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL13 0xd +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL14 0xe +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL15 0xf +#define BF_LRADC_CTRL4_LRADC1SELECT(v) (((v) << 4) & 0xf0) +#define BF_LRADC_CTRL4_LRADC1SELECT_V(v) ((BV_LRADC_CTRL4_LRADC1SELECT__##v << 4) & 0xf0) +#define BP_LRADC_CTRL4_LRADC0SELECT 0 +#define BM_LRADC_CTRL4_LRADC0SELECT 0xf +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL10 0xa +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL11 0xb +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL12 0xc +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL13 0xd +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL14 0xe +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL15 0xf +#define BF_LRADC_CTRL4_LRADC0SELECT(v) (((v) << 0) & 0xf) +#define BF_LRADC_CTRL4_LRADC0SELECT_V(v) ((BV_LRADC_CTRL4_LRADC0SELECT__##v << 0) & 0xf) + +/** + * Register: HW_LRADC_VERSION + * Address: 0x150 + * SCT: no +*/ +#define HW_LRADC_VERSION (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x150)) +#define BP_LRADC_VERSION_MAJOR 24 +#define BM_LRADC_VERSION_MAJOR 0xff000000 +#define BF_LRADC_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) +#define BP_LRADC_VERSION_MINOR 16 +#define BM_LRADC_VERSION_MINOR 0xff0000 +#define BF_LRADC_VERSION_MINOR(v) (((v) << 16) & 0xff0000) +#define BP_LRADC_VERSION_STEP 0 +#define BM_LRADC_VERSION_STEP 0xffff +#define BF_LRADC_VERSION_STEP(v) (((v) << 0) & 0xffff) + +#endif /* __HEADERGEN__STMP3700__LRADC__H__ */ -- cgit v1.2.3