From 2cf33133820ee17e4b5d2d622db15dedff1a1f6e Mon Sep 17 00:00:00 2001 From: Amaury Pouly Date: Fri, 17 Jun 2011 22:30:58 +0000 Subject: fuze+: add more clocking code, add dma code, add ssp code, add stub usb code, update storage to SD + MMC, beginning of the driver git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30010 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/imx233/clkctrl-imx233.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'firmware/target/arm/imx233/clkctrl-imx233.c') diff --git a/firmware/target/arm/imx233/clkctrl-imx233.c b/firmware/target/arm/imx233/clkctrl-imx233.c index 0b46a0e8db..7701b84c41 100644 --- a/firmware/target/arm/imx233/clkctrl-imx233.c +++ b/firmware/target/arm/imx233/clkctrl-imx233.c @@ -37,6 +37,7 @@ void imx233_enable_clock(enum imx233_clock_t clk, bool enable) switch(clk) { case CLK_PIX: REG = &HW_CLKCTRL_PIX; break; + case CLK_SSP: REG = &HW_CLKCTRL_SSP; break; default: return; } @@ -63,8 +64,30 @@ void imx233_set_clock_divisor(enum imx233_clock_t clk, int div) __REG_SET(HW_CLKCTRL_PIX) = div; while(HW_CLKCTRL_PIX & __CLK_BUSY); break; + case CLK_SSP: + __REG_CLR(HW_CLKCTRL_SSP) = (1 << 9) - 1; + __REG_SET(HW_CLKCTRL_SSP) = div; + while(HW_CLKCTRL_SSP & __CLK_BUSY); + break; + default: return; + } +} + +void imx233_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv) +{ + /* NOTE: HW_CLKCTRL_FRAC only support byte access ! */ + volatile uint8_t *REG; + switch(clk) + { + case CLK_PIX: REG = &HW_CLKCTRL_FRAC_PIX; break; + case CLK_IO: REG = &HW_CLKCTRL_FRAC_IO; break; default: return; } + + if(fracdiv != 0) + *REG = fracdiv; + else + *REG = HW_CLKCTRL_FRAC_XX__CLKGATEXX;; } void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass) @@ -73,6 +96,7 @@ void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass) switch(clk) { case CLK_PIX: msk = HW_CLKCTRL_CLKSEQ__BYPASS_PIX; break; + case CLK_SSP: msk = HW_CLKCTRL_CLKSEQ__BYPASS_SSP; break; default: return; } -- cgit v1.2.3