From 15e40dd3a6ac8e9df88b77c0dbd9a90870ad91e6 Mon Sep 17 00:00:00 2001
From: Rafaël Carré <rafael.carre@gmail.com>
Date: Mon, 29 Jun 2009 14:28:49 +0000
Subject: Move Sansa AMS timer code in the target tree

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21552 a1c6a512-1295-4272-9138-f99709370657
---
 firmware/target/arm/as3525/timer-as3525.c | 68 +++++++++++++++++++++++++++++++
 1 file changed, 68 insertions(+)
 create mode 100644 firmware/target/arm/as3525/timer-as3525.c

(limited to 'firmware/target/arm/as3525')

diff --git a/firmware/target/arm/as3525/timer-as3525.c b/firmware/target/arm/as3525/timer-as3525.c
new file mode 100644
index 0000000000..755438a1f8
--- /dev/null
+++ b/firmware/target/arm/as3525/timer-as3525.c
@@ -0,0 +1,68 @@
+/***************************************************************************
+*             __________               __   ___.
+*   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+*   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+*   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+*   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+*                     \/            \/     \/    \/            \/
+* $Id$
+*
+* Copyright (C) 2008 Rafaël Carré
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License
+* as published by the Free Software Foundation; either version 2
+* of the License, or (at your option) any later version.
+*
+* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+* KIND, either express or implied.
+*
+****************************************************************************/
+
+#include "as3525.h"
+#include "timer.h"
+#include "stdlib.h"
+
+void INT_TIMER1(void)
+{
+    if (pfn_timer != NULL)
+        pfn_timer();
+
+    TIMER1_INTCLR = 0; /* clear interrupt */
+}
+
+bool __timer_set(long cycles, bool start)
+{
+    if (start)
+    {
+        if (pfn_unregister != NULL)
+        {
+            pfn_unregister();
+            pfn_unregister = NULL;
+        }
+    }
+
+    TIMER1_LOAD = TIMER1_BGLOAD = cycles;
+    /* /!\ bit 4 (reserved) must not be modified
+     * periodic mode, interrupt enabled, no prescale, 32 bits counter */
+    TIMER1_CONTROL = (TIMER1_CONTROL & (1<<4)) |
+                     TIMER_ENABLE |
+                     TIMER_PERIODIC |
+                     TIMER_INT_ENABLE |
+                     TIMER_32_BIT;
+    return true;
+}
+
+bool __timer_register(void)
+{
+    CGU_PERI |= CGU_TIMER1_CLOCK_ENABLE;    /* enable peripheral */
+    VIC_INT_ENABLE |= INTERRUPT_TIMER1;
+    return true;
+}
+
+void __timer_unregister(void)
+{
+    TIMER1_CONTROL &= 0x10; /* disable timer 1 (don't modify bit 4) */
+    VIC_INT_EN_CLEAR = INTERRUPT_TIMER1;  /* disable interrupt */
+    CGU_PERI &= ~CGU_TIMER1_CLOCK_ENABLE;   /* disable peripheral */
+}
-- 
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