From 04ae1db3318e5538a28ee2b5ff7429622524231b Mon Sep 17 00:00:00 2001 From: Amaury Pouly Date: Sat, 19 Jun 2010 20:40:07 +0000 Subject: as3525v2-usb: end of massive renaming git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26972 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/as3525/usb-drv-as3525v2.h | 292 ++++++++++++++------------ 1 file changed, 162 insertions(+), 130 deletions(-) (limited to 'firmware/target/arm/as3525/usb-drv-as3525v2.h') diff --git a/firmware/target/arm/as3525/usb-drv-as3525v2.h b/firmware/target/arm/as3525/usb-drv-as3525v2.h index 96b13f2028..0f5714eadd 100644 --- a/firmware/target/arm/as3525/usb-drv-as3525v2.h +++ b/firmware/target/arm/as3525/usb-drv-as3525v2.h @@ -24,15 +24,26 @@ #include "as3525v2.h" /* All multi-bit fields in the driver use the following convention. - * If the register name is NAME, then there is one define NAME_bit_pos + * If the register name is NAME, then there is one define NAME_bitp * which holds the bit position and one define NAME_bits which holds - * a mask of the bits within the register. + * a mask of the bits within the register (after shift). * These macros allow easy access and construction of such fields */ /* Usage: * - extract(reg_name,field_name) - note: the field_name must not be prefix with the reg name */ + * extract a field of the register + * - bitm(reg_name,field_name) + * build a bitmask for the field + * - make(reg_name,field_name,value) + * build the value of the field (doesn't mask) + */ #define extract(reg_name, field_name) \ - ((reg_name & reg_name##_##field_name##_bits) >> reg_name##_##field_name##_bit_pos) + ((reg_name >> reg_name##_##field_name##_bitp) & reg_name##_##field_name##_bits) + +#define bitm(reg_name, field_name) \ + (reg_name##_##field_name##_bits << reg_name##_##field_name##_bitp) + +#define make(reg_name, field_name, value) \ + ((value) << reg_name##_##field_name##_bitp) #define USB_DEVICE (USB_BASE + 0x0800) /** USB Device base address */ @@ -50,7 +61,7 @@ /** Core AHB Configuration Register */ #define GAHBCFG BASE_REG(0x008) #define GAHBCFG_glblintrmsk (1 << 0) /** Global interrupt mask */ -#define GAHBCFG_hburstlen_bit_pos 1 +#define GAHBCFG_hburstlen_bitp 1 #define GAHBCFG_INT_DMA_BURST_SINGLE 0 #define GAHBCFG_INT_DMA_BURST_INCR 1 /** note: the linux patch has several other value, this is one picked for internal dma */ #define GAHBCFG_INT_DMA_BURST_INCR4 3 @@ -60,8 +71,8 @@ /** Core USB Configuration Register */ #define GUSBCFG BASE_REG(0x00C) -#define GUSBCFG_toutcal_bit_pos 0 -#define GUSBCFG_toutcal_bits (0x7 << GUSBCFG_toutcal_bit_pos) +#define GUSBCFG_toutcal_bitp 0 +#define GUSBCFG_toutcal_bits 0x7 #define GUSBCFG_phy_if (1 << 3) /** select utmi bus width ? */ #define GUSBCFG_ulpi_utmi_sel (1 << 4) /** select ulpi:1 or utmi:0 */ #define GUSBCFG_fsintf (1 << 5) @@ -69,8 +80,8 @@ #define GUSBCFG_ddrsel (1 << 7) #define GUSBCFG_srpcap (1 << 8) #define GUSBCFG_hnpcapp (1 << 9) -#define GUSBCFG_usbtrdtim_bit_pos 10 -#define GUSBCFG_usbtrdtim_bits (0xf << GUSBCFG_usbtrdtim_bit_pos) +#define GUSBCFG_usbtrdtim_bitp 10 +#define GUSBCFG_usbtrdtim_bits 0xf #define GUSBCFG_nptxfrwnden (1 << 14) #define GUSBCFG_phylpwrclksel (1 << 15) #define GUSBCFG_otgutmifssel (1 << 16) @@ -91,8 +102,8 @@ #define GRSTCTL_intknqflsh (1 << 3) /** In Token Sequence Learning Queue Flush */ #define GRSTCTL_rxfflsh_flush (1 << 4) /** RxFIFO Flush */ #define GRSTCTL_txfflsh_flush (1 << 5) /** TxFIFO Flush */ -#define GRSTCTL_txfnum_bit_pos 6 /** TxFIFO Number */ -#define GRSTCTL_txfnum_bits (0x1f << 6) +#define GRSTCTL_txfnum_bitp 6 /** TxFIFO Number */ +#define GRSTCTL_txfnum_bits 0x1f #define GRSTCTL_ahbidle (1 << 31) /** AHB idle state*/ /** Core Interrupt Register */ @@ -166,25 +177,32 @@ /** User HW Config2 Register */ #define GHWCFG2 BASE_REG(0x048) -#define GHWCFG2_ARCH_bit_pos 3 /** Architecture */ -#define GHWCFG2_ARCH_bits (0x3 << GHWCFG2_ARCH_bit_pos) -#define GHWCFG2_HS_PHY_TYPE_bit_pos 6 /** High speed PHY type */ -#define GHWCFG2_HS_PHY_TYPE_bits (0x3 << GHWCFG2_HS_PHY_TYPE_bit_pos) -#define GHWCFG2_FS_PHY_TYPE_bit_pos 8 /** Full speed PHY type */ -#define GHWCFG2_FS_PHY_TYPE_bits (0x3 << GHWCFG2_FS_PHY_TYPE_bit_pos) -#define GHWCFG2_NUM_EP_bit_pos 10 /** Number of endpoints */ -#define GHWCFG2_NUM_EP_bits (0xf << GHWCFG2_NUM_EP_bit_pos) -#define GHWCFG2_DYN_FIFO (1 << 19) /** Dynamic FIFO */ -/* For GHWCFG2_HS_PHY_TYPE and GHWCFG2_SS_PHY_TYPE */ -#define PHY_TYPE_UNSUPPORTED 0 -#define PHY_TYPE_UTMI 1 -#define INT_DMA_ARCH 2 +#define GHWCFG2_arch_bitp 3 /** Architecture */ +#define GHWCFG2_arch_bits 0x3 +#define GHWCFG2_hs_phy_type_bitp 6 /** High speed PHY type */ +#define GHWCFG2_hs_phy_type_bits 0x3 +#define GHWCFG2_fs_phy_type_bitp 8 /** Full speed PHY type */ +#define GHWCFG2_fs_phy_type_bits 0x3 +#define GHWCFG2_num_ep_bitp 10 /** Number of endpoints */ +#define GHWCFG2_num_ep_bits 0xf +#define GHWCFG2_dyn_fifo (1 << 19) /** Dynamic FIFO */ +/* For GHWCFG2_HS_PHY_TYPE and GHWCFG2_FS_PHY_TYPE */ +#define GHWCFG2_PHY_TYPE_UNSUPPORTED 0 +#define GHWCFG2_PHY_TYPE_UTMI 1 +#define GHWCFG2_ARCH_INTERNAL_DMA 2 /** User HW Config3 Register */ -#define GHWCFG3 BASE_REG(0x04C) +#define GHWCFG3 BASE_REG(0x04C) +#define GHWCFG3_dfifo_len_bitp 16 /** Total fifo size */ +#define GHWCFG3_dfifo_len_bits 0xffff /** User HW Config4 Register */ -#define GHWCFG4 BASE_REG(0x050) +#define GHWCFG4 BASE_REG(0x050) +#define GHWCFG4_utmi_phy_data_width_bitp 14 /** UTMI+ data bus width */ +#define GHWCFG4_utmi_phy_data_width_bits 0x3 +#define GHWCFG4_ded_fifo_en (1 << 25) /** Dedicated Tx FIFOs */ +#define GHWCFG4_num_in_ep_bitp 26 /** Number of IN endpoints */ +#define GHWCFG4_num_in_ep_bits 0xf /* 1<=ep<=15, don't use ep=0 !!! */ /** Device IN Endpoint Transmit FIFO (ep) Size Register */ @@ -200,100 +218,58 @@ #define GET_FIFOSIZE_START_ADR(data) \ ((data) & 0xffff) - - - - -#define GHWCFG3_DFIFO_LEN (GHWCFG3 >> 16) /** Total fifo size */ - -#define GHWCFG4_UTMI_PHY_DATA_WIDTH ((GHWCFG4 >> 14) & 0x3) /** UTMI+ data bus width (format is unsure) */ -#define GHWCFG4_DED_FIFO_EN ((GHWCFG4 >> 25) & 0x1) /** Dedicated Tx FIFOs */ -#define GHWCFG4_NUM_IN_EP ((GHWCFG4 >> 26) & 0xf) /** Number of IN endpoints */ - - - /** * Device Registers Base Addresses */ #define DEV_REG(offset) (*(volatile unsigned long *)(USB_DEVICE + offset)) -#define DCFG DEV_REG(0x00) /** Device Configuration Register */ -#define DCTL DEV_REG(0x04) /** Device Control Register */ -#define DSTS DEV_REG(0x08) /** Device Status Register */ -#define DIEPMSK DEV_REG(0x10) /** Device IN Endpoint Common Interrupt Mask Register */ -#define DOEPMSK DEV_REG(0x14) /** Device OUT Endpoint Common Interrupt Mask Register */ -#define DAINT DEV_REG(0x18) /** Device All Endpoints Interrupt Register */ -#define DAINTMSK DEV_REG(0x1C) /** Device Endpoints Interrupt Mask Register */ -#define DTKNQR1 DEV_REG(0x20) /** Device IN Token Sequence Learning Queue Read Register 1 */ -#define DTKNQR2 DEV_REG(0x24) /** Device IN Token Sequence Learning Queue Register 2 */ -#define DTKNQP DEV_REG(0x28) /** Device IN Token Queue Pop register */ -/* fixme: those registers are not present in registers.h but are in dwc_otgh_regs.h. - * the previous registers exists but has a different name :( */ -#define DVBUSDIS DEV_REG(0x28) /** Device VBUS discharge register*/ -#define DVBUSPULSE DEV_REG(0x2C) /** Device VBUS pulse register */ -#define DTKNQR3 DEV_REG(0x30) /** Device IN Token Queue Read Register 3 (RO) */ -#define DTHRCTL DEV_REG(0x30) /** Device Thresholding control register */ -#define DTKNQR4 DEV_REG(0x34) /** Device IN Token Queue Read Register 4 (RO) */ -#define FFEMPTYMSK DEV_REG(0x34) /** Device IN EPs empty Inr. Mask Register */ - -#define DCTL_rmtwkupsig (1 << 0) /** Remote Wakeup */ -#define DCTL_sftdiscon (1 << 1) /** Soft Disconnect */ -#define DCTL_gnpinnaksts (1 << 2) /** Global Non-Periodic IN NAK Status */ -#define DCTL_goutnaksts (1 << 3) /** Global OUT NAK Status */ -#define DCTL_tstctl_bit_pos 4 /** Test Control */ -#define DCTL_tstctl_bits (0x7 << DCTL_tstctl_bit_pos) -#define DCTL_sgnpinnak (1 << 7) /** Set Global Non-Periodic IN NAK */ -#define DCTL_cgnpinnak (1 << 8) /** Clear Global Non-Periodic IN NAK */ -#define DCTL_sgoutnak (1 << 9) /** Set Global OUT NAK */ -#define DCTL_cgoutnak (1 << 10) /** Clear Global OUT NAK */ +/** Device Configuration Register */ +#define DCFG DEV_REG(0x00) +#define DCFG_devspd_bitp 0 /** Device Speed */ +#define DCFG_devspd_bits 0x3 +#define DCFG_devspd_hs_phy_hs 0 /** High speed PHY running at high speed */ +#define DCFG_devspd_hs_phy_fs 1 /** High speed PHY running at full speed */ +#define DCFG_nzstsouthshk (1 << 2) /** Non Zero Length Status OUT Handshake */ +#define DCFG_devadr_bitp 4 /** Device Address */ +#define DCFG_devadr_bits 0x7f +#define DCFG_perfrint_bitp 11 /** Periodic Frame Interval */ +#define DCFG_perfrint_bits 0x3 +#define DCFG_FRAME_INTERVAL_80 0 +#define DCFG_FRAME_INTERVAL_85 1 +#define DCFG_FRAME_INTERVAL_90 2 +#define DCFG_FRAME_INTERVAL_95 3 + +/** Device Control Register */ +#define DCTL DEV_REG(0x04) +#define DCTL_rmtwkupsig (1 << 0) /** Remote Wakeup */ +#define DCTL_sftdiscon (1 << 1) /** Soft Disconnect */ +#define DCTL_gnpinnaksts (1 << 2) /** Global Non-Periodic IN NAK Status */ +#define DCTL_goutnaksts (1 << 3) /** Global OUT NAK Status */ +#define DCTL_tstctl_bitp 4 /** Test Control */ +#define DCTL_tstctl_bits 0x7 +#define DCTL_sgnpinnak (1 << 7) /** Set Global Non-Periodic IN NAK */ +#define DCTL_cgnpinnak (1 << 8) /** Clear Global Non-Periodic IN NAK */ +#define DCTL_sgoutnak (1 << 9) /** Set Global OUT NAK */ +#define DCTL_cgoutnak (1 << 10) /** Clear Global OUT NAK */ /* "documented" in constants.h only */ -#define DCTL_pwronprgdone (1 << 11) /** Power on Program Done ? */ - -#define DCFG_devspd_bits 0x3 /** Device Speed */ -#define DCFG_devspd_hs_phy_hs 0 /** High speed PHY running at high speed */ -#define DCFG_devspd_hs_phy_fs 1 /** High speed PHY running at full speed */ -#define DCFG_nzstsouthshk (1 << 2) /** Non Zero Length Status OUT Handshake */ -#define DCFG_devadr_bit_pos 4 /** Device Address */ -#define DCFG_devadr_bits (0x7f << DCFG_devadr_bit_pos) -#define DCFG_perfrint_bit_pos 11 /** Periodic Frame Interval */ -#define DCFG_perfrint_bits (0x3 << DCFG_perfrint_bit_pos) -#define DCFG_FRAME_INTERVAL_80 0 -#define DCFG_FRAME_INTERVAL_85 1 -#define DCFG_FRAME_INTERVAL_90 2 -#define DCFG_FRAME_INTERVAL_95 3 - -#define DSTS_suspsts (1 << 0) /** Suspend status */ -#define DSTS_enumspd_bit_pos 1 /** Enumerated speed */ -#define DSTS_enumspd_bits (0x3 << DSTS_enumspd_bit_pos) +#define DCTL_pwronprgdone (1 << 11) /** Power on Program Done ? */ + +/** Device Status Register */ +#define DSTS DEV_REG(0x08) +#define DSTS_suspsts (1 << 0) /** Suspend status */ +#define DSTS_enumspd_bitp 1 /** Enumerated speed */ +#define DSTS_enumspd_bits 0x3 #define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 #define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 #define DSTS_ENUMSPD_LS_PHY_6MHZ 2 #define DSTS_ENUMSPD_FS_PHY_48MHZ 3 -#define DSTS_errticerr (1 << 3) /** Erratic errors ? */ -#define DSTS_soffn_bit_pos 7 /** Frame or Microframe Number of the received SOF */ -#define DSTS_soffn_bits (0x3fff << DSTS_soffn_bit_pos) - -#define DTHRCTL_non_iso_thr_en (1 << 0) -#define DTHRCTL_iso_thr_en (1 << 1) -#define DTHRCTL_tx_thr_len_bit_pos 2 -#define DTHRCTL_tx_thr_len_bits (0x1FF << DTHRCTL_tx_thr_len_bit_pos) -#define DTHRCTL_rx_thr_en (1 << 16) -#define DTHRCTL_rx_thr_len_bit_pos 17 -#define DTHRCTL_rx_thr_len_bits (0x1FF << DTHRCTL_rx_thr_len_bit_pos) - -/* 0<=ep<=15, you can use ep=0 */ -/** Device IN Endpoint (ep) Control Register */ -#define DIEPCTL(ep) DEV_REG(0x100 + (ep) * 0x20) -/** Device IN Endpoint (ep) Interrupt Register */ -#define DIEPINT(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x8) -/** Device IN Endpoint (ep) Transfer Size Register */ -#define DIEPTSIZ(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x10) -/** Device IN Endpoint (ep) DMA Address Register */ -#define DIEPDMA(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x14) -/** Device IN Endpoint (ep) Transmit FIFO Status Register */ -#define DTXFSTS(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x18) +#define DSTS_errticerr (1 << 3) /** Erratic errors ? */ +#define DSTS_soffn_bitp 7 /** Frame or Microframe Number of the received SOF */ +#define DSTS_soffn_bits 0x3fff -/* the following also apply to DIEPMSK */ +/** Device IN Endpoint Common Interrupt Mask Register */ +#define DIEPMSK DEV_REG(0x10) +/* the following apply to DIEPMSK and DIEPINT */ #define DIEPINT_xfercompl (1 << 0) /** Transfer complete */ #define DIEPINT_epdisabled (1 << 1) /** Endpoint disabled */ #define DIEPINT_ahberr (1 << 2) /** AHB error */ @@ -304,12 +280,72 @@ #define DIEPINT_emptyintr (1 << 7) /** linux doc broken on this, empty fifo ? */ #define DIEPINT_txfifoundrn (1 << 8) /** linux doc void on this, tx fifo underrun ? */ -/* the following also apply to DOEPMSK */ +/** Device OUT Endpoint Common Interrupt Mask Register */ +#define DOEPMSK DEV_REG(0x14) +/* the following apply to DOEPMSK and DOEPINT */ #define DOEPINT_xfercompl (1 << 0) /** Transfer complete */ #define DOEPINT_epdisabled (1 << 1) /** Endpoint disabled */ #define DOEPINT_ahberr (1 << 2) /** AHB error */ #define DOEPINT_setup (1 << 3) /** Setup Phase Done (control EPs)*/ +/** Device All Endpoints Interrupt Register */ +#define DAINT DEV_REG(0x18) +/* valid for DAINT and DAINTMSK, for 0<=ep<=15 */ +#define DAINT_IN_EP(i) (1 << (i)) +#define DAINT_OUT_EP(i) (1 << ((i) + 16)) + +/** Device Endpoints Interrupt Mask Register */ +#define DAINTMSK DEV_REG(0x1C) + +/** Device IN Token Sequence Learning Queue Read Register 1 */ +#define DTKNQR1 DEV_REG(0x20) + +/** Device IN Token Sequence Learning Queue Register 2 */ +#define DTKNQR2 DEV_REG(0x24) + +/** Device IN Token Queue Pop register */ +#define DTKNQP DEV_REG(0x28) + +/* fixme: those registers are not present in registers.h but are in dwc_otgh_regs.h. + * the previous registers exists but has a different name :( */ +/** Device VBUS discharge register*/ +#define DVBUSDIS DEV_REG(0x28) + +/** Device VBUS pulse register */ +#define DVBUSPULSE DEV_REG(0x2C) + +/** Device IN Token Queue Read Register 3 (RO) */ +#define DTKNQR3 DEV_REG(0x30) + +/** Device Thresholding control register */ +#define DTHRCTL DEV_REG(0x30) +#define DTHRCTL_non_iso_thr_en (1 << 0) +#define DTHRCTL_iso_thr_en (1 << 1) +#define DTHRCTL_tx_thr_len_bitp 2 +#define DTHRCTL_tx_thr_len_bits 0x1FF +#define DTHRCTL_rx_thr_en (1 << 16) +#define DTHRCTL_rx_thr_len_bitp 17 +#define DTHRCTL_rx_thr_len_bits 0x1FF + +/** Device IN Token Queue Read Register 4 (RO) */ +#define DTKNQR4 DEV_REG(0x34) + +/** Device IN EPs empty Inr. Mask Register */ +#define FFEMPTYMSK DEV_REG(0x34) + + +/* 0<=ep<=15, you can use ep=0 */ +/** Device IN Endpoint (ep) Control Register */ +#define DIEPCTL(ep) DEV_REG(0x100 + (ep) * 0x20) +/** Device IN Endpoint (ep) Interrupt Register */ +#define DIEPINT(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x8) +/** Device IN Endpoint (ep) Transfer Size Register */ +#define DIEPTSIZ(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x10) +/** Device IN Endpoint (ep) DMA Address Register */ +#define DIEPDMA(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x14) +/** Device IN Endpoint (ep) Transmit FIFO Status Register */ +#define DTXFSTS(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x18) + /* 0<=ep<=15, you can use ep=0 */ /** Device OUT Endpoint (ep) Control Register */ #define DOEPCTL(ep) DEV_REG(0x300 + (ep) * 0x20) @@ -332,8 +368,8 @@ * 2'b01: 32 * 2'b10: 16 * 2'b11: 8 */ +#define DEPCTL_mps_bitp 0 #define DEPCTL_mps_bits 0x7ff -#define DEPCTL_mps_bit_pos 0 #define DEPCTL_MPS_64 0 #define DEPCTL_MPS_32 1 #define DEPCTL_MPS_16 2 @@ -341,8 +377,8 @@ /** Next Endpoint * IN EPn/IN EP0 * OUT EPn/OUT EP0 - reserved */ -#define DEPCTL_nextep_bit_pos 11 -#define DEPCTL_nextep_bits (0xf << DEPCTL_nextep_bit_pos) +#define DEPCTL_nextep_bitp 11 +#define DEPCTL_nextep_bits 0xf #define DEPCTL_usbactep (1 << 15) /** USB Active Endpoint */ /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) * This field contains the PID of the packet going to @@ -365,8 +401,8 @@ * 2'b01: Isochronous * 2'b10: Bulk * 2'b11: Interrupt */ -#define DEPCTL_eptype_bit_pos 18 -#define DEPCTL_eptype_bits (0x3 << DEPCTL_eptype_bit_pos) +#define DEPCTL_eptype_bitp 18 +#define DEPCTL_eptype_bits 0x3 /** Snoop Mode * OUT EPn/OUT EP0 * IN EPn/IN EP0 - reserved */ @@ -375,8 +411,8 @@ /** Tx Fifo Number * IN EPn/IN EP0 * OUT EPn/OUT EP0 - reserved */ -#define DEPCTL_txfnum_bit_pos 22 -#define DEPCTL_txfnum_bits (0xf << DEPCTL_txfnum_bit_pos) +#define DEPCTL_txfnum_bitp 22 +#define DEPCTL_txfnum_bits 0xf #define DEPCTL_cnak (1 << 26) /** Clear NAK */ #define DEPCTL_snak (1 << 27) /** Set NAK */ @@ -403,21 +439,17 @@ /* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */ #define DEPTSIZ_xfersize_bits 0x7ffff /** Transfer Size */ -#define DEPTSIZ_pkcnt_bit_pos 19 /** Packet Count */ -#define DEPTSIZ_pkcnt_bits (0x3ff << DEPTSIZ_pkcnt_bit_pos) -#define DEPTSIZ_mc_bit_pos 29 /** Multi Count - Periodic IN endpoints */ -#define DEPTSIZ_mc_bits (0x3 << DEPTSIZ_mc_bit_pos) +#define DEPTSIZ_pkcnt_bitp 19 /** Packet Count */ +#define DEPTSIZ_pkcnt_bits 0x3ff +#define DEPTSIZ_mc_bitp 29 /** Multi Count - Periodic IN endpoints */ +#define DEPTSIZ_mc_bits 0x3 /* idem but for i=0 */ -#define DEPTSIZ0_xfersize_bits 0x7f /** Transfer Size */ -#define DEPTSIZ0_pkcnt_bit_pos 19 /** Packet Count */ -#define DEPTSIZ0_pkcnt_bits (0x1 << DEPTSIZ0_pkcnt_bit_pos) -#define DEPTSIZ0_supcnt_bit_pos 29 /** Setup Packet Count (DOEPTSIZ0 Only) */ -#define DEPTSIZ0_supcnt_bits (0x3 << DEPTSIZ0_supcnt_bit_pos) - -/* valid for DAINT and DAINTMSK, for 0<=ep<=15 */ -#define DAINT_IN_EP(i) (1 << (i)) -#define DAINT_OUT_EP(i) (1 << ((i) + 16)) +#define DEPTSIZ0_xfersize_bits 0x7f /** Transfer Size */ +#define DEPTSIZ0_pkcnt_bitp 19 /** Packet Count */ +#define DEPTSIZ0_pkcnt_bits 0x1 +#define DEPTSIZ0_supcnt_bitp 29 /** Setup Packet Count (DOEPTSIZ0 Only) */ +#define DEPTSIZ0_supcnt_bits 0x3 /** * Parameters -- cgit v1.2.3