From 562e41bae5b76abd49eceebf8324a445a4b82450 Mon Sep 17 00:00:00 2001 From: Jack Halpin Date: Thu, 15 Oct 2009 19:48:26 +0000 Subject: AMS Sansa: FS#10669 Reimplement Voltage scaling. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reimplement voltage scaling on AMS Sansas at 1.10v during unboosted operation to improve runtimes. The voltage is now also boosted during disk access if a µSD is present. This prevents the µSD problems we saw on the last implementation. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23193 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/as3525/system-as3525.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'firmware/target/arm/as3525/system-as3525.c') diff --git a/firmware/target/arm/as3525/system-as3525.c b/firmware/target/arm/as3525/system-as3525.c index d68f2c4f00..ba817b4ad3 100644 --- a/firmware/target/arm/as3525/system-as3525.c +++ b/firmware/target/arm/as3525/system-as3525.c @@ -335,14 +335,13 @@ void set_cpu_frequency(long frequency) { if(frequency == CPUFREQ_MAX) { -#ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE /* Increasing frequency so boost voltage before change */ ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_20)); /* Wait for voltage to be at least 1.20v before making fclk > 200 MHz */ while(adc_read(ADC_CVDD) < 480) /* 480 * .0025 = 1.20V */ ; -#endif + asm volatile( "mrc p15, 0, r0, c1, c0 \n" @@ -365,10 +364,10 @@ void set_cpu_frequency(long frequency) "bic r0, r0, #3<<30 \n" /* fastbus clocking */ "mcr p15, 0, r0, c1, c0 \n" : : : "r0" ); -#ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE + /* Decreasing frequency so reduce voltage after change */ ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_10)); -#endif + cpu_frequency = CPUFREQ_NORMAL; } } -- cgit v1.2.3