From 6f0320a9535bc1aa81d83fa879ac14d5ee603658 Mon Sep 17 00:00:00 2001 From: William Wilgus Date: Fri, 27 Jul 2018 23:56:32 +0200 Subject: As3525 v1/v2 Add power savings menu Allow user to select cpu undervolt There have been quite a few issues across the SANSA AMS line related to CPU undervolting while most players show greatly increased runtime some crash. Rather than constanly upping the voltage we now have a setting with a safe value for all players and the option for lower voltages I plan to add a few other options here later such as disk timings and maybe some other clocks/experimental settings Added: Disk Low speed option for AS3525v2 devices cuts frequency to 12 MHz from 24 MHz Added: Disk Low speed option for AS3525v1 devices cuts frequency to 15.5 MHz from 31 MHz Added: I2c Low Speed AS3525 devices, should be bigger improvement for v1 devices Fixed: Debug menu for AS3525v2 No SDSLOT frequency, Showed IDE freq though it is unused Added: DBOP and SSP underclocking affects display on v1/v2 respectively Fixed: debug menu now has SSP frequency, and SSP_CPSR Update: made settings menu more generic Update: cleaned up code Added: Clip v1 & Fuze v1 didn't have HAVE_ADJUSTABLE_CPU_VOLTAGE. not sure why but, waiting on testing to confirm Added: C200v2 and E200v2 devices and HAVE_ADJUSTABLE_CPU_VOLTAGE. Fixed: v1 devices don't like display timing set lower (dbop) v1 devices don't have a divider set for ssp (causes divide by 0) Fixed: ClipZip display lags with Max SSP divider changed from 0xFE to 0x32 Fixed: v1 devices didn't work properly with highspeed sd cards Added code from http://gerrit.rockbox.org/r/#/c/1704/ Added powersave and IDE interface enable/disable Added: V2 devices now have powersave enabled on sd interface Update: cleaned up code, lang defines, added manual entries Update ssp clock mechanism added calculated ssp divider to clipzip Update turn display clock off when clip+ turns off display Fixed: clipzip wrong register for SSP clock Change-Id: I04137682243be92f0f8d8bf1cfa54fbb1965559b TODO: add other players? --- firmware/target/arm/as3525/sd-as3525.c | 138 ++++++++++++++++++++++++--------- 1 file changed, 103 insertions(+), 35 deletions(-) (limited to 'firmware/target/arm/as3525/sd-as3525.c') diff --git a/firmware/target/arm/as3525/sd-as3525.c b/firmware/target/arm/as3525/sd-as3525.c index 494a76a782..9e4a86acbe 100644 --- a/firmware/target/arm/as3525/sd-as3525.c +++ b/firmware/target/arm/as3525/sd-as3525.c @@ -89,6 +89,8 @@ | MCI_CMD_CRC_FAIL) #define MCI_FIFO(i) ((unsigned long *) (pl180_base[i]+0x80)) + +#define IDE_INTERFACE_CLK (1<<6) /* non AHB interface */ /* volumes */ #define INTERNAL_AS3525 0 /* embedded SD card */ #define SD_SLOT_AS3525 1 /* SD slot if present */ @@ -109,7 +111,8 @@ static void init_pl180_controller(const int drive); static tCardInfo card_info[NUM_DRIVES]; -/* maximum timeouts recommanded in the SD Specification v2.00 */ +/* maximum timeouts recommended in the SD Specification v2.00 */ +/* MCI_DATA_TIMER register data timeout in card bus clock periods */ #define SD_MAX_READ_TIMEOUT ((AS3525_PCLK_FREQ) / 1000 * 100) /* 100 ms */ #define SD_MAX_WRITE_TIMEOUT ((AS3525_PCLK_FREQ) / 1000 * 250) /* 250 ms */ @@ -143,7 +146,17 @@ static unsigned char *uncached_buffer = AS3525_UNCACHED_ADDR(&aligned_buffer[0]) static inline void mci_delay(void) { udelay(1000) ; } -static void enable_controller(bool on) +static inline bool card_detect_target(void) +{ +#if defined(HAVE_MULTIDRIVE) + return !(GPIOA_PIN(2)); +#else + return false; +#endif +} + +#if defined(HAVE_MULTIDRIVE) || defined(HAVE_HOTSWAP) +static void enable_controller_mci(bool on) { #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE) @@ -197,17 +210,33 @@ static void enable_controller(bool on) #endif } } +#endif /* defined(HAVE_MULTIDRIVE) || defined(HAVE_HOTSWAP) */ -static inline bool card_detect_target(void) +/* AMS v1 have two different drive interfaces MCI_SD(XPD) and GGU_IDE */ +static void enable_controller(bool on, const int drive) { -#if defined(HAVE_MULTIDRIVE) - return !(GPIOA_PIN(2)); -#else - return false; + + if (drive == INTERNAL_AS3525) + { +#ifndef BOOTLOADER + if (on) + { + bitset32(&CGU_PERI, CGU_NAF_CLOCK_ENABLE); + CGU_IDE |= IDE_INTERFACE_CLK; /* interface enable */ + } + else + { + CGU_IDE &= ~(IDE_INTERFACE_CLK); /* interface disable */ + bitclr32(&CGU_PERI, CGU_NAF_CLOCK_ENABLE); + } +#endif + } +#if defined(HAVE_MULTIDRIVE) || defined(HAVE_HOTSWAP) + else + enable_controller_mci(on); #endif } - #ifdef HAVE_HOTSWAP static int sd1_oneshot_callback(struct timeout *tmo) { @@ -326,6 +355,7 @@ static bool send_cmd(const int drive, const int cmd, const int arg, return false; } +/* MCI_CLOCK = MCLK / 2x(ClkDiv[bits 7:0]+1) */ #define MCI_FULLSPEED (MCI_CLOCK_ENABLE | MCI_CLOCK_BYPASS) /* MCLK */ #define MCI_HALFSPEED (MCI_CLOCK_ENABLE) /* MCLK/2 */ #define MCI_QUARTERSPEED (MCI_CLOCK_ENABLE | 1) /* MCLK/4 */ @@ -345,7 +375,7 @@ static int sd_init_card(const int drive) /* 100 - 400kHz clock required for Identification Mode */ /* Start of Card Identification Mode ************************************/ - /* CMD0 Go Idle */ + /* CMD0 Go Idle -- all card functions switch back to default */ if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL)) return -1; mci_delay(); @@ -393,10 +423,10 @@ static int sd_init_card(const int drive) if(sd_wait_for_tran_state(drive)) return -6; - /* CMD6 */ + /* CMD6 0xf indicates no influence, [3:0],0x1 - HS Access*/ if(!send_cmd(drive, SD_SWITCH_FUNC, 0x80fffff1, MCI_NO_RESP, NULL)) return -7; - sleep(HZ/10); + sleep(HZ/10);/* need to wait at least 8 clock periods */ /* go back to STBY state so we can read csd */ /* CMD7 w/rca=0: Deselect card to put it in STBY state */ @@ -517,7 +547,7 @@ static void init_pl180_controller(const int drive) int sd_init(void) { int ret; - CGU_IDE = (1<<6) /* enable non AHB interface*/ + CGU_IDE = IDE_INTERFACE_CLK /* enable interface */ | (AS3525_IDE_DIV << 2) | AS3525_CLK_PLLA; /* clock source = PLLA */ @@ -540,7 +570,9 @@ int sd_init(void) /* init mutex */ mutex_init(&sd_mtx); - enable_controller(false); + for (int i = 0; i < NUM_DRIVES ; i++) + enable_controller(false, i); + return 0; } @@ -656,7 +688,7 @@ static int sd_transfer_sectors(IF_MD(int drive,) unsigned long start, unsigned long response; bool aligned = !((uintptr_t)buf & (CACHEALIGN_SIZE - 1)); - enable_controller(true); + enable_controller(true, drive); led(true); if (card_info[drive].initialized <= 0) @@ -692,27 +724,21 @@ static int sd_transfer_sectors(IF_MD(int drive,) unsigned long start, else discard_dcache_range(buf, count * SECTOR_SIZE); } - - while(count) + const int cmd = write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK; + while(count > 0) { /* 128 * 512 = 2^16, and doesn't fit in the 16 bits of DATA_LENGTH * register, so we have to transfer maximum 127 sectors at a time. */ unsigned int transfer = (count >= 128) ? 127 : count; /* sectors */ void *dma_buf; - const int cmd = - write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK; + unsigned long bank_start = start; - unsigned long status; /* Only switch banks for internal storage */ if(drive == INTERNAL_AS3525) { - unsigned int bank = 0; - while(bank_start >= BLOCKS_PER_BANK) - { - bank_start -= BLOCKS_PER_BANK; - bank++; - } + unsigned int bank = bank_start / BLOCKS_PER_BANK; + bank_start -= bank * BLOCKS_PER_BANK; /* Switch bank if needed */ if(card_info[INTERNAL_AS3525].current_bank != bank) @@ -770,10 +796,7 @@ static int sd_transfer_sectors(IF_MD(int drive,) unsigned long start, /*Small delay for writes prevents data crc failures at lower freqs*/ #ifdef HAVE_MULTIDRIVE if((drive == SD_SLOT_AS3525) && !hs_card) - { - int write_delay = 125; - while(write_delay--); - } + udelay(4); #endif } else @@ -804,7 +827,7 @@ static int sd_transfer_sectors(IF_MD(int drive,) unsigned long start, last_disk_activity = current_tick; - if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_RESP, &status)) + if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_RESP, &response)) { ret = -4*20; goto sd_transfer_error; @@ -831,7 +854,7 @@ sd_transfer_error: sd_transfer_error_nodma: led(false); - enable_controller(false); + enable_controller(false, drive); if (ret) /* error */ card_info[drive].initialized = 0; @@ -922,12 +945,18 @@ void ams_sd_get_debug_info(struct ams_sd_debug_info *info) #define MCI_SD *((volatile unsigned long *)(SD_MCI_BASE + 0x04)) mutex_lock(&sd_mtx); - enable_controller(true); /* must be on to read regs */ + + for (int i = 0; i < NUM_DRIVES ; i++) + enable_controller(true, i); /* must be on to read regs */ + info->mci_nand = MCI_NAND; #ifdef HAVE_MULTIDRIVE info->mci_sd = MCI_SD; #endif - enable_controller(false); + + for (int i = 0; i < NUM_DRIVES ; i++) + enable_controller(false, i); + mutex_unlock(&sd_mtx); } @@ -948,10 +977,10 @@ int sd_event(long id, intptr_t data) if (id == SYS_HOTSWAP_INSERTED) { - enable_controller(true); + enable_controller(true, data); init_pl180_controller(data); rc = sd_init_card(data); - enable_controller(false); + enable_controller(false, data); } mutex_unlock(&sd_mtx); @@ -968,3 +997,42 @@ int sd_event(long id, intptr_t data) return rc; } + +#if defined(CONFIG_POWER_SAVING) && (CONFIG_POWER_SAVING & POWERSV_DISK) +/* declared in system-as3525.c */ +void ams_sd_set_low_speed(bool slow) +{ + /* block access while speed is changed */ + mutex_lock(&sd_mtx); + enable_controller(true, INTERNAL_AS3525); + + /* After a data write, data cannot be written to MCI_CLOCK + for 3 MCLK periods + 2 PCLK periods. ~10us worst case + */ + udelay(100); + if (slow) + { + /* only affects internal drive clock speed*/ + CGU_IDE = (CGU_IDE & ~(0xF << 2)) | (AS3525_IDE_DIV_MAX << 2); + /* power save is enabled for the sd card(s) */ + for (int i = 0; i < NUM_DRIVES ; i++) + { + if (i != INTERNAL_AS3525 && (MCI_CLOCK(i) & MCI_CLOCK_POWERSAVE) == 0) + MCI_CLOCK(i) |= MCI_CLOCK_POWERSAVE; + } + } + else + { + /* Full Speed */ + CGU_IDE = (CGU_IDE & ~(0xF << 2)) | (AS3525_IDE_DIV << 2); + for (int i = 0; i < NUM_DRIVES ; i++) + { + if (i != INTERNAL_AS3525 && (MCI_CLOCK(i) & MCI_CLOCK_POWERSAVE) != 0) + MCI_CLOCK(i) = (MCI_CLOCK(i) & ~MCI_CLOCK_POWERSAVE); + } + } + enable_controller(false, INTERNAL_AS3525); + mutex_unlock(&sd_mtx); +} +#endif + -- cgit v1.2.3