From b714ace1634cd6da7f21fca10ac2e8981da7fc88 Mon Sep 17 00:00:00 2001 From: Jack Halpin Date: Fri, 29 May 2009 06:43:37 +0000 Subject: AMSSansa: clock-target.h and debug-as3525 now use AS3525_FCLK_PREDIV correctly. Default frequency scheme remains 248/62/62. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21125 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/as3525/clock-target.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'firmware/target/arm/as3525/clock-target.h') diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index c9b2ceb9a4..923f4e7c43 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h @@ -89,8 +89,8 @@ /* FCLK */ #define AS3525_FCLK_SEL AS3525_CLK_PLLA -#define AS3525_FCLK_PREDIV 0 /* div = (8-n)/8 acts strange when used!*/ -#define AS3525_FCLK_POSTDIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/ +#define AS3525_FCLK_PREDIV 0 /* div = (8-n)/8 Enter manually & postdiv will be calculated*/ +#define AS3525_FCLK_POSTDIV (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/ /* PCLK */ #ifdef ASYNCHRONOUS_BUS -- cgit v1.2.3