From ae64b59afad9e186340b4cfe27f8fa78157c80b1 Mon Sep 17 00:00:00 2001 From: Bertrik Sikken Date: Fri, 18 Jun 2010 18:32:38 +0000 Subject: as3525v2: document PLL bits and show current PLL frequency in the debug menu git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26930 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/as3525/clock-target.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'firmware/target/arm/as3525/clock-target.h') diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 96c2c264fe..1689c59448 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h @@ -62,10 +62,20 @@ #if CONFIG_CPU == AS3525v2 /* PLLA & PLLB registers differ from AS3525(v1) - * so we use a setting with a known frequency */ + * PLL bits: + * - bit 0-6 = F-1 (F=multiplier) + * - bit 7-9 = R-1 (R=divisor) + * - bit 10 = OD (output divider)? Divides by 2 if set. + * - bit 11 = unknown (no effect) + * - bit 12 = unknown (always set to 1) + * Fpll = Fin * F / (R * OD), where Fin = 12 MHz + */ #define AS3525_PLLA_FREQ 240000000 #define AS3525_PLLA_SETTING 0x113B +#define AS3525_PLLB_FREQ 192000000 +#define AS3525_PLLB_SETTING 0x155F + #define AS3525_FCLK_PREDIV 0 #define AS3525_FCLK_FREQ AS3525_PLLA_FREQ -- cgit v1.2.3