From 19fc7297bae8225bfaab51bd8b1f2f8c3aa67858 Mon Sep 17 00:00:00 2001 From: Jack Halpin Date: Tue, 23 Mar 2010 17:00:59 +0000 Subject: SansaAMSv2: Give register CGU_BASE + 0x3C the name CGU_SDSLOT. Move CLKDIV macros into clock-target.h. Only enable the necessary interfaces for the 3 clock registers used for SD. Add MEMSTICK and SDSLOT registers to bottom of register display in View HW info debug page. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25309 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/as3525/clock-target.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'firmware/target/arm/as3525/clock-target.h') diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index dceefb7284..65fc681d24 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h @@ -156,7 +156,10 @@ #define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/ #if CONFIG_CPU == AS3525v2 -#define AS3525_MS_FREQ 120000000 +#define AS3525_MS_FREQ 120000000 +#define AS3525_MS_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_MS_FREQ) -1) +#define AS3525_SDSLOT_FREQ 24000000 +#define AS3525_SDSLOT_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_SDSLOT_FREQ) -1) #define AS3525_IDE_FREQ 80000000 #else #define AS3525_IDE_FREQ 50000000 /* The OF uses 66MHz maximal freq */ -- cgit v1.2.3