From 05099149f193cac0c81b0129c17feb78b1a9681a Mon Sep 17 00:00:00 2001 From: Michael Sevakis Date: Sun, 6 Apr 2008 04:34:57 +0000 Subject: Enable nocache sections using the linker. PP5022/4 must use SW_CORELOCK now with shared variables in DRAM (it seems swp(b) is at least partially broken on all PP or I'm doing something very wrong here :\). For core-shared data use SHAREDBSS/DATA_ATTR. NOCACHEBSS/DATA_ATTR is available whether or not single core is forced for static peripheral-DMA buffer allocation without use of the UNCACHED_ADDR macro in code and is likely useful on a non-PP target with a data cache (although not actually enabled in config.h and the .lds's in this commit). git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16981 a1c6a512-1295-4272-9138-f99709370657 --- firmware/system.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'firmware/system.c') diff --git a/firmware/system.c b/firmware/system.c index 65478e724b..15eb77eada 100644 --- a/firmware/system.c +++ b/firmware/system.c @@ -29,14 +29,14 @@ #include "string.h" #ifndef SIMULATOR -long cpu_frequency NOCACHEBSS_ATTR = CPU_FREQ; +long cpu_frequency SHAREDBSS_ATTR = CPU_FREQ; #endif #ifdef HAVE_ADJUSTABLE_CPU_FREQ -static int boost_counter NOCACHEBSS_ATTR = 0; -static bool cpu_idle NOCACHEBSS_ATTR = false; +static int boost_counter SHAREDBSS_ATTR = 0; +static bool cpu_idle SHAREDBSS_ATTR = false; #if NUM_CORES > 1 -struct spinlock boostctrl_spin NOCACHEBSS_ATTR; +struct spinlock boostctrl_spin SHAREDBSS_ATTR; void cpu_boost_init(void) { spinlock_init(&boostctrl_spin); -- cgit v1.2.3