From bc943a06ba06e7f23837a122ef760c6f660c26d3 Mon Sep 17 00:00:00 2001 From: Rafaël Carré Date: Tue, 13 Dec 2011 04:21:06 +0000 Subject: Move usb-s3c6400 register comments to usb-s3c6400.h Use common defines in usb-s3c6400.c and usb-drv-as3525v2.c No functional changes git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31220 a1c6a512-1295-4272-9138-f99709370657 --- firmware/export/as3525.h | 1 + firmware/export/usb-s3c6400x.h | 453 +++++++++++++++++++++++++++-------------- 2 files changed, 304 insertions(+), 150 deletions(-) (limited to 'firmware/export') diff --git a/firmware/export/as3525.h b/firmware/export/as3525.h index bad88a20e3..0d3923ce75 100644 --- a/firmware/export/as3525.h +++ b/firmware/export/as3525.h @@ -61,6 +61,7 @@ /* AHB */ #define USB_BASE 0xC6000000 +#define OTGBASE USB_BASE #define VIC_BASE 0xC6010000 #define DMAC_BASE 0xC6020000 #define MPMC_BASE 0xC6030000 diff --git a/firmware/export/usb-s3c6400x.h b/firmware/export/usb-s3c6400x.h index eeac9d038e..e8fb4b10a4 100644 --- a/firmware/export/usb-s3c6400x.h +++ b/firmware/export/usb-s3c6400x.h @@ -22,6 +22,22 @@ #define USB_S3C6400X_H +/* All multi-bit fields in the driver use the following convention. + * If the register name is NAME, then there is one define NAME_bitp + * which holds the bit position and one define NAME_bits which holds + * a mask of the bits within the register (after shift). + * These macros allow easy access and construction of such fields */ +/* Usage: + * - extract(reg_name,field_name) + * extract a field of the register + * - bitm(reg_name,field_name) + * build a bitmask for the field + */ +#define extract(reg_name, field_name) \ + ((reg_name >> reg_name##_##field_name##_bitp) & reg_name##_##field_name##_bits) + +#define bitm(reg_name, field_name) \ + (reg_name##_##field_name##_bits << reg_name##_##field_name##_bitp) /*** OTG PHY CONTROL REGISTERS ***/ @@ -34,35 +50,117 @@ /*** OTG LINK CORE REGISTERS ***/ /* Core Global Registers */ + +/** OTG Control and Status Register */ #define GOTGCTL (*((uint32_t volatile*)(OTGBASE + 0x000))) + +/** OTG Interrupt Register */ #define GOTGINT (*((uint32_t volatile*)(OTGBASE + 0x004))) + +/** Core AHB Configuration Register */ #define GAHBCFG (*((uint32_t volatile*)(OTGBASE + 0x008))) +#define GAHBCFG_glblintrmsk (1 << 0) /** Global interrupt mask */ +#define GAHBCFG_hburstlen_bitp 1 +#define GAHBCFG_hburstlen_bits 0xf +#define GAHBCFG_INT_DMA_BURST_SINGLE 0 +#define GAHBCFG_INT_DMA_BURST_INCR 1 /** note: the linux patch has several other value, this is one picked for internal dma */ +#define GAHBCFG_INT_DMA_BURST_INCR4 3 +#define GAHBCFG_INT_DMA_BURST_INCR8 5 +#define GAHBCFG_INT_DMA_BURST_INCR16 7 +#define GAHBCFG_dma_enable (1 << 5) /** Enable DMA */ + +/** Core USB Configuration Register */ #define GUSBCFG (*((uint32_t volatile*)(OTGBASE + 0x00C))) +#define GUSBCFG_toutcal_bitp 0 +#define GUSBCFG_toutcal_bits 0x7 +#define GUSBCFG_phy_if (1 << 3) /** select utmi bus width ? */ +#define GUSBCFG_ulpi_utmi_sel (1 << 4) /** select ulpi:1 or utmi:0 */ +#define GUSBCFG_fsintf (1 << 5) +#define GUSBCFG_physel (1 << 6) +#define GUSBCFG_ddrsel (1 << 7) +#define GUSBCFG_srpcap (1 << 8) +#define GUSBCFG_hnpcapp (1 << 9) +#define GUSBCFG_usbtrdtim_bitp 10 +#define GUSBCFG_usbtrdtim_bits 0xf +#define GUSBCFG_nptxfrwnden (1 << 14) +#define GUSBCFG_phylpwrclksel (1 << 15) +#define GUSBCFG_otgutmifssel (1 << 16) +#define GUSBCFG_ulpi_fsls (1 << 17) +#define GUSBCFG_ulpi_auto_res (1 << 18) +#define GUSBCFG_ulpi_clk_sus_m (1 << 19) +#define GUSBCFG_ulpi_ext_vbus_drv (1 << 20) +#define GUSBCFG_ulpi_int_vbus_indicator (1 << 21) +#define GUSBCFG_term_sel_dl_pulse (1 << 22) +#define GUSBCFG_force_host_mode (1 << 29) +#define GUSBCFG_force_device_mode (1 << 30) +#define GUSBCFG_corrupt_tx_packet (1 << 31) + + +/** Core Reset Register */ #define GRSTCTL (*((uint32_t volatile*)(OTGBASE + 0x010))) +#define GRSTCTL_csftrst (1 << 0) /** Core soft reset */ +#define GRSTCTL_hsftrst (1 << 1) /** Hclk soft reset */ +#define GRSTCTL_intknqflsh (1 << 3) /** In Token Sequence Learning Queue Flush */ +#define GRSTCTL_rxfflsh_flush (1 << 4) /** RxFIFO Flush */ +#define GRSTCTL_txfflsh_flush (1 << 5) /** TxFIFO Flush */ +#define GRSTCTL_txfnum_bitp 6 /** TxFIFO Number */ +#define GRSTCTL_txfnum_bits 0x1f +#define GRSTCTL_ahbidle (1 << 31) /** AHB idle state*/ + +/** Core Interrupt Register */ #define GINTSTS (*((uint32_t volatile*)(OTGBASE + 0x014))) +/* NOTE: GINTSTS bits are the same as in GINTMSK plus this one */ +#define GINTSTS_curmode (1 << 0) /** Current mode, 0 for device */ + +/** Core Interrupt Mask Register */ #define GINTMSK (*((uint32_t volatile*)(OTGBASE + 0x018))) +#define GINTMSK_modemismatch (1 << 1) /** mode mismatch ? */ +#define GINTMSK_otgintr (1 << 2) +#define GINTMSK_sofintr (1 << 3) +#define GINTMSK_rxstsqlvl (1 << 4) +#define GINTMSK_nptxfempty (1 << 5) /** Non-periodic TX fifo empty ? */ +#define GINTMSK_ginnakeff (1 << 6) +#define GINTMSK_goutnakeff (1 << 7) +#define GINTMSK_i2cintr (1 << 9) +#define GINTMSK_erlysuspend (1 << 10) +#define GINTMSK_usbsuspend (1 << 11) /** USB suspend */ +#define GINTMSK_usbreset (1 << 12) /** USB reset */ +#define GINTMSK_enumdone (1 << 13) /** Enumeration done */ +#define GINTMSK_isooutdrop (1 << 14) +#define GINTMSK_eopframe (1 << 15) +#define GINTMSK_epmismatch (1 << 17) /** endpoint mismatch ? */ +#define GINTMSK_inepintr (1 << 18) /** in pending ? */ +#define GINTMSK_outepintr (1 << 19) /** out pending ? */ +#define GINTMSK_incomplisoin (1 << 20) /** ISP in complete ? */ +#define GINTMSK_incomplisoout (1 << 21) /** ISO out complete ? */ +#define GINTMSK_portintr (1 << 24) /** Port status change ? */ +#define GINTMSK_hcintr (1 << 25) +#define GINTMSK_ptxfempty (1 << 26) /** Periodic TX fifof empty ? */ +#define GINTMSK_conidstschng (1 << 28) +#define GINTMSK_disconnect (1 << 29) /** Disconnect */ +#define GINTMSK_sessreqintr (1 << 30) /** Session request */ +#define GINTMSK_wkupintr (1 << 31) /** Wake up */ + +/** Receive Status Debug Read Register (Read Only) */ #define GRXSTSR (*((uint32_t volatile*)(OTGBASE + 0x01C))) + +/** Receive Status Read /Pop Register (Read Only) */ #define GRXSTSP (*((uint32_t volatile*)(OTGBASE + 0x020))) + +/** Receive FIFO Size Register */ #define GRXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x024))) + +/** Periodic Transmit FIFO Size Register */ #define GNPTXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x028))) +#define MAKE_FIFOSIZE_DATA(depth) ((depth) | ((depth) << 16)) + +/** Non-Periodic Transmit FIFO/Queue Status Register */ #define GNPTXSTS (*((uint32_t volatile*)(OTGBASE + 0x02C))) + +/** Device IN Endpoint Transmit FIFO (ep) Size Register */ +/* 1<=ep<=15, don't use ep=0 !!! */ #define HPTXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x100))) #define DPTXFSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x100 + 4 * (x)))) -#define DPTXFSIZ1 (*((uint32_t volatile*)(OTGBASE + 0x104))) -#define DPTXFSIZ2 (*((uint32_t volatile*)(OTGBASE + 0x108))) -#define DPTXFSIZ3 (*((uint32_t volatile*)(OTGBASE + 0x10C))) -#define DPTXFSIZ4 (*((uint32_t volatile*)(OTGBASE + 0x110))) -#define DPTXFSIZ5 (*((uint32_t volatile*)(OTGBASE + 0x114))) -#define DPTXFSIZ6 (*((uint32_t volatile*)(OTGBASE + 0x118))) -#define DPTXFSIZ7 (*((uint32_t volatile*)(OTGBASE + 0x11C))) -#define DPTXFSIZ8 (*((uint32_t volatile*)(OTGBASE + 0x120))) -#define DPTXFSIZ9 (*((uint32_t volatile*)(OTGBASE + 0x124))) -#define DPTXFSIZ10 (*((uint32_t volatile*)(OTGBASE + 0x128))) -#define DPTXFSIZ11 (*((uint32_t volatile*)(OTGBASE + 0x12C))) -#define DPTXFSIZ12 (*((uint32_t volatile*)(OTGBASE + 0x130))) -#define DPTXFSIZ13 (*((uint32_t volatile*)(OTGBASE + 0x134))) -#define DPTXFSIZ14 (*((uint32_t volatile*)(OTGBASE + 0x138))) -#define DPTXFSIZ15 (*((uint32_t volatile*)(OTGBASE + 0x13C))) /*** HOST MODE REGISTERS ***/ /* Host Global Registers */ @@ -182,162 +280,217 @@ /*** DEVICE MODE REGISTERS ***/ /* Device Global Registers */ + +/** Device Configuration Register */ #define DCFG (*((uint32_t volatile*)(OTGBASE + 0x800))) +#define DCFG_devspd_bitp 0 /** Device Speed */ +#define DCFG_devspd_bits 0x3 +#define DCFG_devspd_hs_phy_hs 0 /** High speed PHY running at high speed */ +#define DCFG_devspd_hs_phy_fs 1 /** High speed PHY running at full speed */ +#define DCFG_nzstsouthshk (1 << 2) /** Non Zero Length Status OUT Handshake */ +#define DCFG_devadr_bitp 4 /** Device Address */ +#define DCFG_devadr_bits 0x7f +#define DCFG_perfrint_bitp 11 /** Periodic Frame Interval */ +#define DCFG_perfrint_bits 0x3 +#define DCFG_FRAME_INTERVAL_80 0 +#define DCFG_FRAME_INTERVAL_85 1 +#define DCFG_FRAME_INTERVAL_90 2 +#define DCFG_FRAME_INTERVAL_95 3 + +/** Device Control Register */ #define DCTL (*((uint32_t volatile*)(OTGBASE + 0x804))) +#define DCTL_rmtwkupsig (1 << 0) /** Remote Wakeup */ +#define DCTL_sftdiscon (1 << 1) /** Soft Disconnect */ +#define DCTL_gnpinnaksts (1 << 2) /** Global Non-Periodic IN NAK Status */ +#define DCTL_goutnaksts (1 << 3) /** Global OUT NAK Status */ +#define DCTL_tstctl_bitp 4 /** Test Control */ +#define DCTL_tstctl_bits 0x7 +#define DCTL_sgnpinnak (1 << 7) /** Set Global Non-Periodic IN NAK */ +#define DCTL_cgnpinnak (1 << 8) /** Clear Global Non-Periodic IN NAK */ +#define DCTL_sgoutnak (1 << 9) /** Set Global OUT NAK */ +#define DCTL_cgoutnak (1 << 10) /** Clear Global OUT NAK */ +#define DCTL_pwronprgdone (1 << 11) /** Power on Program Done ? */ + +/** Device Status Register */ #define DSTS (*((uint32_t volatile*)(OTGBASE + 0x808))) +#define DSTS_suspsts (1 << 0) /** Suspend status */ +#define DSTS_enumspd_bitp 1 /** Enumerated speed */ +#define DSTS_enumspd_bits 0x3 +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 +#define DSTS_ENUMSPD_LS_PHY_6MHZ 2 +#define DSTS_ENUMSPD_FS_PHY_48MHZ 3 +#define DSTS_errticerr (1 << 3) /** Erratic errors ? */ +#define DSTS_soffn_bitp 8 /** Frame or Microframe Number of the received SOF */ +#define DSTS_soffn_bits 0x3fff + +/** Device IN Endpoint Common Interrupt Mask Register */ #define DIEPMSK (*((uint32_t volatile*)(OTGBASE + 0x810))) +/* the following apply to DIEPMSK and DIEPINT */ +#define DIEPINT_xfercompl (1 << 0) /** Transfer complete */ +#define DIEPINT_epdisabled (1 << 1) /** Endpoint disabled */ +#define DIEPINT_ahberr (1 << 2) /** AHB error */ +#define DIEPINT_timeout (1 << 3) /** Timeout handshake (non-iso TX) */ +#define DIEPINT_intktxfemp (1 << 4) /** IN token received with tx fifo empty */ +#define DIEPINT_intknepmis (1 << 5) /** IN token received with ep mismatch */ +#define DIEPINT_inepnakeff (1 << 6) /** IN endpoint NAK effective */ +#define DIEPINT_emptyintr (1 << 7) /** linux doc broken on this, empty fifo ? */ +#define DIEPINT_txfifoundrn (1 << 8) /** linux doc void on this, tx fifo underrun ? */ + +/** Device OUT Endpoint Common Interrupt Mask Register */ #define DOEPMSK (*((uint32_t volatile*)(OTGBASE + 0x814))) +/* the following apply to DOEPMSK and DOEPINT */ +#define DOEPINT_xfercompl (1 << 0) /** Transfer complete */ +#define DOEPINT_epdisabled (1 << 1) /** Endpoint disabled */ +#define DOEPINT_ahberr (1 << 2) /** AHB error */ +#define DOEPINT_setup (1 << 3) /** Setup Phase Done (control EPs)*/ + +/** Device All Endpoints Interrupt Register */ #define DAINT (*((uint32_t volatile*)(OTGBASE + 0x818))) +/* valid for DAINT and DAINTMSK, for 0<=ep<=15 */ +#define DAINT_IN_EP(i) (1 << (i)) +#define DAINT_OUT_EP(i) (1 << ((i) + 16)) + +/** Device Endpoints Interrupt Mask Register */ #define DAINTMSK (*((uint32_t volatile*)(OTGBASE + 0x81C))) + +/** Device IN Token Sequence Learning Queue Read Register 1 */ #define DTKNQR1 (*((uint32_t volatile*)(OTGBASE + 0x820))) + +/** Device IN Token Sequence Learning Queue Register 2 */ #define DTKNQR2 (*((uint32_t volatile*)(OTGBASE + 0x824))) + +/* fixme: those registers are not present in registers.h but are in dwc_otgh_regs.h. + * the previous registers exists but has a different name :( */ +/** Device VBUS discharge register*/ #define DVBUSDIS (*((uint32_t volatile*)(OTGBASE + 0x828))) + +/** Device VBUS pulse register */ #define DVBUSPULSE (*((uint32_t volatile*)(OTGBASE + 0x82C))) + +// FIXME : 2 names for the same reg? +/** Device IN Token Queue Read Register 3 (RO) */ +/** Device Thresholding control register */ #define DTKNQR3 (*((uint32_t volatile*)(OTGBASE + 0x830))) +#define DTHRCTL (*((uint32_t volatile*)(OTGBASE + 0x830))) +#define DTHRCTL_non_iso_thr_en (1 << 0) +#define DTHRCTL_iso_thr_en (1 << 1) +#define DTHRCTL_tx_thr_len_bitp 2 +#define DTHRCTL_tx_thr_len_bits 0x1FF +#define DTHRCTL_rx_thr_en (1 << 16) +#define DTHRCTL_rx_thr_len_bitp 17 +#define DTHRCTL_rx_thr_len_bits 0x1FF + +/** Device IN Token Queue Read Register 4 (RO) */ #define DTKNQR4 (*((uint32_t volatile*)(OTGBASE + 0x834))) /* Device Logical IN Endpoint-Specific Registers */ #define DIEPCTL(x) (*((uint32_t volatile*)(OTGBASE + 0x900 + 0x20 * (x)))) -#define DIEPINT(x) (*((uint32_t volatile*)(OTGBASE + 0x908 + 0x20 * (x)))) -#define DIEPTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x910 + 0x20 * (x)))) -#define DIEPDMA(x) (*((const void* volatile*)(OTGBASE + 0x914 + 0x20 * (x)))) -#define DIEPCTL0 (*((uint32_t volatile*)(OTGBASE + 0x900))) -#define DIEPINT0 (*((uint32_t volatile*)(OTGBASE + 0x908))) -#define DIEPTSIZ0 (*((uint32_t volatile*)(OTGBASE + 0x910))) -#define DIEPDMA0 (*((const void* volatile*)(OTGBASE + 0x914))) -#define DIEPCTL1 (*((uint32_t volatile*)(OTGBASE + 0x920))) -#define DIEPINT1 (*((uint32_t volatile*)(OTGBASE + 0x928))) -#define DIEPTSIZ1 (*((uint32_t volatile*)(OTGBASE + 0x930))) -#define DIEPDMA1 (*((const void* volatile*)(OTGBASE + 0x934))) -#define DIEPCTL2 (*((uint32_t volatile*)(OTGBASE + 0x940))) -#define DIEPINT2 (*((uint32_t volatile*)(OTGBASE + 0x948))) -#define DIEPTSIZ2 (*((uint32_t volatile*)(OTGBASE + 0x950))) -#define DIEPDMA2 (*((const void* volatile*)(OTGBASE + 0x954))) -#define DIEPCTL3 (*((uint32_t volatile*)(OTGBASE + 0x960))) -#define DIEPINT3 (*((uint32_t volatile*)(OTGBASE + 0x968))) -#define DIEPTSIZ3 (*((uint32_t volatile*)(OTGBASE + 0x970))) -#define DIEPDMA3 (*((const void* volatile*)(OTGBASE + 0x974))) -#define DIEPCTL4 (*((uint32_t volatile*)(OTGBASE + 0x980))) -#define DIEPINT4 (*((uint32_t volatile*)(OTGBASE + 0x988))) -#define DIEPTSIZ4 (*((uint32_t volatile*)(OTGBASE + 0x990))) -#define DIEPDMA4 (*((const void* volatile*)(OTGBASE + 0x994))) -#define DIEPCTL5 (*((uint32_t volatile*)(OTGBASE + 0x9A0))) -#define DIEPINT5 (*((uint32_t volatile*)(OTGBASE + 0x9A8))) -#define DIEPTSIZ5 (*((uint32_t volatile*)(OTGBASE + 0x9B0))) -#define DIEPDMA5 (*((const void* volatile*)(OTGBASE + 0x9B4))) -#define DIEPCTL6 (*((uint32_t volatile*)(OTGBASE + 0x9C0))) -#define DIEPINT6 (*((uint32_t volatile*)(OTGBASE + 0x9C8))) -#define DIEPTSIZ6 (*((uint32_t volatile*)(OTGBASE + 0x9D0))) -#define DIEPDMA6 (*((const void* volatile*)(OTGBASE + 0x9D4))) -#define DIEPCTL7 (*((uint32_t volatile*)(OTGBASE + 0x9E0))) -#define DIEPINT7 (*((uint32_t volatile*)(OTGBASE + 0x9E8))) -#define DIEPTSIZ7 (*((uint32_t volatile*)(OTGBASE + 0x9F0))) -#define DIEPDMA7 (*((const void* volatile*)(OTGBASE + 0x9F4))) -#define DIEPCTL8 (*((uint32_t volatile*)(OTGBASE + 0xA00))) -#define DIEPINT8 (*((uint32_t volatile*)(OTGBASE + 0xA08))) -#define DIEPTSIZ8 (*((uint32_t volatile*)(OTGBASE + 0xA10))) -#define DIEPDMA8 (*((const void* volatile*)(OTGBASE + 0xA14))) -#define DIEPCTL9 (*((uint32_t volatile*)(OTGBASE + 0xA20))) -#define DIEPINT9 (*((uint32_t volatile*)(OTGBASE + 0xA28))) -#define DIEPTSIZ9 (*((uint32_t volatile*)(OTGBASE + 0xA30))) -#define DIEPDMA9 (*((const void* volatile*)(OTGBASE + 0xA34))) -#define DIEPCTL10 (*((uint32_t volatile*)(OTGBASE + 0xA40))) -#define DIEPINT10 (*((uint32_t volatile*)(OTGBASE + 0xA48))) -#define DIEPTSIZ10 (*((uint32_t volatile*)(OTGBASE + 0xA50))) -#define DIEPDMA10 (*((const void* volatile*)(OTGBASE + 0xA54))) -#define DIEPCTL11 (*((uint32_t volatile*)(OTGBASE + 0xA60))) -#define DIEPINT11 (*((uint32_t volatile*)(OTGBASE + 0xA68))) -#define DIEPTSIZ11 (*((uint32_t volatile*)(OTGBASE + 0xA70))) -#define DIEPDMA11 (*((const void* volatile*)(OTGBASE + 0xA74))) -#define DIEPCTL12 (*((uint32_t volatile*)(OTGBASE + 0xA80))) -#define DIEPINT12 (*((uint32_t volatile*)(OTGBASE + 0xA88))) -#define DIEPTSIZ12 (*((uint32_t volatile*)(OTGBASE + 0xA90))) -#define DIEPDMA12 (*((const void* volatile*)(OTGBASE + 0xA94))) -#define DIEPCTL13 (*((uint32_t volatile*)(OTGBASE + 0xAA0))) -#define DIEPINT13 (*((uint32_t volatile*)(OTGBASE + 0xAA8))) -#define DIEPTSIZ13 (*((uint32_t volatile*)(OTGBASE + 0xAB0))) -#define DIEPDMA13 (*((const void* volatile*)(OTGBASE + 0xAB4))) -#define DIEPCTL14 (*((uint32_t volatile*)(OTGBASE + 0xAC0))) -#define DIEPINT14 (*((uint32_t volatile*)(OTGBASE + 0xAC8))) -#define DIEPTSIZ14 (*((uint32_t volatile*)(OTGBASE + 0xAD0))) -#define DIEPDMA14 (*((const void* volatile*)(OTGBASE + 0xAD4))) -#define DIEPCTL15 (*((uint32_t volatile*)(OTGBASE + 0xAE0))) -#define DIEPINT15 (*((uint32_t volatile*)(OTGBASE + 0xAE8))) -#define DIEPTSIZ15 (*((uint32_t volatile*)(OTGBASE + 0xAF0))) -#define DIEPDMA15 (*((const void* volatile*)(OTGBASE + 0xAF4))) - /* Device Logical OUT Endpoint-Specific Registers */ #define DOEPCTL(x) (*((uint32_t volatile*)(OTGBASE + 0xB00 + 0x20 * (x)))) -#define DOEPINT(x) (*((uint32_t volatile*)(OTGBASE + 0xB08 + 0x20 * (x)))) +/** Maximum Packet Size + * IN/OUT EPn + * IN/OUT EP0 - 2 bits + * 2'b00: 64 Bytes + * 2'b01: 32 + * 2'b10: 16 + * 2'b11: 8 */ +#define DEPCTL_mps_bitp 0 +#define DEPCTL_mps_bits 0x7ff +#define DEPCTL_MPS_64 0 +#define DEPCTL_MPS_32 1 +#define DEPCTL_MPS_16 2 +#define DEPCTL_MPS_8 3 +/** Next Endpoint + * IN EPn/IN EP0 + * OUT EPn/OUT EP0 - reserved */ +#define DEPCTL_nextep_bitp 11 +#define DEPCTL_nextep_bits 0xf +#define DEPCTL_usbactep (1 << 15) /** USB Active Endpoint */ +/** Endpoint DPID (INTR/Bulk IN and OUT endpoints) + * This field contains the PID of the packet going to + * be received or transmitted on this endpoint. The + * application should program the PID of the first + * packet going to be received or transmitted on this + * endpoint , after the endpoint is + * activated. Application use the SetD1PID and + * SetD0PID fields of this register to program either + * D0 or D1 PID. + * + * The encoding for this field is + * - 0: D0 + * - 1: D1 + */ +#define DEPCTL_dpid (1 << 16) +#define DEPCTL_naksts (1 << 17) /** NAK Status */ +/** Endpoint Type + * 2'b00: Control + * 2'b01: Isochronous + * 2'b10: Bulk + * 2'b11: Interrupt */ +#define DEPCTL_eptype_bitp 18 +#define DEPCTL_eptype_bits 0x3 +/** Snoop Mode + * OUT EPn/OUT EP0 + * IN EPn/IN EP0 - reserved */ +#define DEPCTL_snp (1 << 20) +#define DEPCTL_stall (1 << 21) /** Stall Handshake */ +/** Tx Fifo Number + * IN EPn/IN EP0 + * OUT EPn/OUT EP0 - reserved */ +#define DEPCTL_txfnum_bitp 22 +#define DEPCTL_txfnum_bits 0xf +#define DEPCTL_cnak (1 << 26) /** Clear NAK */ +#define DEPCTL_snak (1 << 27) /** Set NAK */ +/** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) + * Writing to this field sets the Endpoint DPID (DPID) + * field in this register to DATA0. Set Even + * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) + * Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) + * frame. + */ +#define DEPCTL_setd0pid (1 << 28) +/** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) + * Writing to this field sets the Endpoint DPID (DPID) + * field in this register to DATA1 Set Odd + * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) + * Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to odd (micro) frame. + */ +#define DEPCTL_setd1pid (1 << 29) +#define DEPCTL_epdis (1 << 30) /** Endpoint disable */ +#define DEPCTL_epena (1 << 31) /** Endpoint enable */ + +/** Device IN Endpoint (ep) Transfer Size Register */ +#define DIEPTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x910 + 0x20 * (x)))) +/** Device OUT Endpoint (ep) Transfer Size Register */ #define DOEPTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0xB10 + 0x20 * (x)))) -#define DOEPDMA(x) (*((void* volatile*)(OTGBASE + 0xB14 + 0x20 * (x)))) -#define DOEPCTL0 (*((uint32_t volatile*)(OTGBASE + 0xB00))) -#define DOEPINT0 (*((uint32_t volatile*)(OTGBASE + 0xB08))) -#define DOEPTSIZ0 (*((uint32_t volatile*)(OTGBASE + 0xB10))) -#define DOEPDMA0 (*((void* volatile*)(OTGBASE + 0xB14))) -#define DOEPCTL1 (*((uint32_t volatile*)(OTGBASE + 0xB20))) -#define DOEPINT1 (*((uint32_t volatile*)(OTGBASE + 0xB28))) -#define DOEPTSIZ1 (*((uint32_t volatile*)(OTGBASE + 0xB30))) -#define DOEPDMA1 (*((void* volatile*)(OTGBASE + 0xB34))) -#define DOEPCTL2 (*((uint32_t volatile*)(OTGBASE + 0xB40))) -#define DOEPINT2 (*((uint32_t volatile*)(OTGBASE + 0xB48))) -#define DOEPTSIZ2 (*((uint32_t volatile*)(OTGBASE + 0xB50))) -#define DOEPDMA2 (*((void* volatile*)(OTGBASE + 0xB54))) -#define DOEPCTL3 (*((uint32_t volatile*)(OTGBASE + 0xB60))) -#define DOEPINT3 (*((uint32_t volatile*)(OTGBASE + 0xB68))) -#define DOEPTSIZ3 (*((uint32_t volatile*)(OTGBASE + 0xB70))) -#define DOEPDMA3 (*((void* volatile*)(OTGBASE + 0xB74))) -#define DOEPCTL4 (*((uint32_t volatile*)(OTGBASE + 0xB80))) -#define DOEPINT4 (*((uint32_t volatile*)(OTGBASE + 0xB88))) -#define DOEPTSIZ4 (*((uint32_t volatile*)(OTGBASE + 0xB90))) -#define DOEPDMA4 (*((void* volatile*)(OTGBASE + 0xB94))) -#define DOEPCTL5 (*((uint32_t volatile*)(OTGBASE + 0xBA0))) -#define DOEPINT5 (*((uint32_t volatile*)(OTGBASE + 0xBA8))) -#define DOEPTSIZ5 (*((uint32_t volatile*)(OTGBASE + 0xBB0))) -#define DOEPDMA5 (*((void* volatile*)(OTGBASE + 0xBB4))) -#define DOEPCTL6 (*((uint32_t volatile*)(OTGBASE + 0xBC0))) -#define DOEPINT6 (*((uint32_t volatile*)(OTGBASE + 0xBC8))) -#define DOEPTSIZ6 (*((uint32_t volatile*)(OTGBASE + 0xBD0))) -#define DOEPDMA6 (*((void* volatile*)(OTGBASE + 0xBD4))) -#define DOEPCTL7 (*((uint32_t volatile*)(OTGBASE + 0xBE0))) -#define DOEPINT7 (*((uint32_t volatile*)(OTGBASE + 0xBE8))) -#define DOEPTSIZ7 (*((uint32_t volatile*)(OTGBASE + 0xBF0))) -#define DOEPDMA7 (*((void* volatile*)(OTGBASE + 0xBF4))) -#define DOEPCTL8 (*((uint32_t volatile*)(OTGBASE + 0xC00))) -#define DOEPINT8 (*((uint32_t volatile*)(OTGBASE + 0xC08))) -#define DOEPTSIZ8 (*((uint32_t volatile*)(OTGBASE + 0xC10))) -#define DOEPDMA8 (*((void* volatile*)(OTGBASE + 0xC14))) -#define DOEPCTL9 (*((uint32_t volatile*)(OTGBASE + 0xC20))) -#define DOEPINT9 (*((uint32_t volatile*)(OTGBASE + 0xC28))) -#define DOEPTSIZ9 (*((uint32_t volatile*)(OTGBASE + 0xC30))) -#define DOEPDMA9 (*((void* volatile*)(OTGBASE + 0xC34))) -#define DOEPCTL10 (*((uint32_t volatile*)(OTGBASE + 0xC40))) -#define DOEPINT10 (*((uint32_t volatile*)(OTGBASE + 0xC48))) -#define DOEPTSIZ10 (*((uint32_t volatile*)(OTGBASE + 0xC50))) -#define DOEPDMA10 (*((void* volatile*)(OTGBASE + 0xC54))) -#define DOEPCTL11 (*((uint32_t volatile*)(OTGBASE + 0xC60))) -#define DOEPINT11 (*((uint32_t volatile*)(OTGBASE + 0xC68))) -#define DOEPTSIZ11 (*((uint32_t volatile*)(OTGBASE + 0xC70))) -#define DOEPDMA11 (*((void* volatile*)(OTGBASE + 0xC74))) -#define DOEPCTL12 (*((uint32_t volatile*)(OTGBASE + 0xC80))) -#define DOEPINT12 (*((uint32_t volatile*)(OTGBASE + 0xC88))) -#define DOEPTSIZ12 (*((uint32_t volatile*)(OTGBASE + 0xC90))) -#define DOEPDMA12 (*((void* volatile*)(OTGBASE + 0xC94))) -#define DOEPCTL13 (*((uint32_t volatile*)(OTGBASE + 0xCA0))) -#define DOEPINT13 (*((uint32_t volatile*)(OTGBASE + 0xCA8))) -#define DOEPTSIZ13 (*((uint32_t volatile*)(OTGBASE + 0xCB0))) -#define DOEPDMA13 (*((void* volatile*)(OTGBASE + 0xCB4))) -#define DOEPCTL14 (*((uint32_t volatile*)(OTGBASE + 0xCC0))) -#define DOEPINT14 (*((uint32_t volatile*)(OTGBASE + 0xCC8))) -#define DOEPTSIZ14 (*((uint32_t volatile*)(OTGBASE + 0xCD0))) -#define DOEPDMA14 (*((void* volatile*)(OTGBASE + 0xCD4))) -#define DOEPCTL15 (*((uint32_t volatile*)(OTGBASE + 0xCE0))) -#define DOEPINT15 (*((uint32_t volatile*)(OTGBASE + 0xCE8))) -#define DOEPTSIZ15 (*((uint32_t volatile*)(OTGBASE + 0xCF0))) -#define DOEPDMA15 (*((void* volatile*)(OTGBASE + 0xCF4))) +/* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */ +#define DEPTSIZ_xfersize_bitp 0 /** Transfer Size */ +#define DEPTSIZ_xfersize_bits 0x7ffff +#define DEPTSIZ_pkcnt_bitp 19 /** Packet Count */ +#define DEPTSIZ_pkcnt_bits 0x3ff +#define DEPTSIZ_mc_bitp 29 /** Multi Count - Periodic IN endpoints */ +#define DEPTSIZ_mc_bits 0x3 +/* idem but for i=0 */ +#define DEPTSIZ0_xfersize_bitp 0 /** Transfer Size */ +#define DEPTSIZ0_xfersize_bits 0x7f +#define DEPTSIZ0_pkcnt_bitp 19 /** Packet Count */ +#define DEPTSIZ0_pkcnt_bits 0x3 +#define DEPTSIZ0_supcnt_bitp 29 /** Setup Packet Count (DOEPTSIZ0 Only) */ +#define DEPTSIZ0_supcnt_bits 0x3 + + +/** Device Endpoint (ep) Control Register */ +#define DIEPINT(x) (*((uint32_t volatile*)(OTGBASE + 0x908 + 0x20 * (x)))) +#define DOEPINT(x) (*((uint32_t volatile*)(OTGBASE + 0xB08 + 0x20 * (x)))) + +/** Device Endpoint (ep) DMA Address Register */ +#define DIEPDMA(x) (*((const void* volatile*)(OTGBASE + 0x914 + 0x20 * (x)))) +#define DOEPDMA(x) (*((const void* volatile*)(OTGBASE + 0xB14 + 0x20 * (x)))) /* Power and Clock Gating Register */ #define PCGCCTL (*((uint32_t volatile*)(OTGBASE + 0xE00))) - #endif /* USB_S3C6400X_H */ -- cgit v1.2.3