From 4a483bb1bf69a0f0a1bf99aaa9bb47c6f79ab990 Mon Sep 17 00:00:00 2001 From: Karl Kurbjun Date: Mon, 8 Jun 2009 00:19:16 +0000 Subject: M:Robe 500: Mostly complete USB driver, supports BULK mode currently and gets about 2 MB/s writes vs 1.1 MB/s on the OF. Mostly tested against Linux, preliminary testing in Windows appears to work. There is currently a bug in the attach process where it only works once per boot that needs to be fixed. There are a few other minor M:Robe 500 changes as well. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21208 a1c6a512-1295-4272-9138-f99709370657 --- firmware/export/config-mrobe500.h | 16 ++++++ firmware/export/config.h | 3 +- firmware/export/m66591.h | 102 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 120 insertions(+), 1 deletion(-) create mode 100644 firmware/export/m66591.h (limited to 'firmware/export') diff --git a/firmware/export/config-mrobe500.h b/firmware/export/config-mrobe500.h index f9e8d9ebf6..619e3fe8e7 100644 --- a/firmware/export/config-mrobe500.h +++ b/firmware/export/config-mrobe500.h @@ -35,6 +35,9 @@ /* define this if you use an ATA controller */ #define CONFIG_STORAGE STORAGE_ATA +/* Define this to add support for ATA DMA */ +//#define HAVE_ATA_DMA + /* define this if you have a bitmap LCD display */ #define HAVE_LCD_BITMAP @@ -114,6 +117,19 @@ #define HAVE_TOUCHSCREEN #define HAVE_BUTTON_DATA +/* M66591 register base */ +#define M66591_BASE 0x60000000 + +/* enable these for the usb stack */ +#define CONFIG_USBOTG USBOTG_M66591 +#define USE_ROCKBOX_USB +#define HAVE_USBSTACK +#define USB_STORAGE +/* usb stack and driver settings */ +#define USB_NUM_ENDPOINTS 7 +#define USB_VENDOR_ID 0x07b4 +#define USB_PRODUCT_ID 0x0281 + /* define this if the target has volume keys which can be used in the lists */ #define HAVE_VOLUME_IN_LIST diff --git a/firmware/export/config.h b/firmware/export/config.h index 5cdf46dcfd..696c923bb6 100644 --- a/firmware/export/config.h +++ b/firmware/export/config.h @@ -250,6 +250,7 @@ Lyre prototype 1*/ #define RTC_JZ47XX 16 /* Ingenic Jz47XX */ /* USB On-the-go */ +#define USBOTG_M66591 6591 /* M:Robe 500 */ #define USBOTG_ISP1362 1362 /* iriver H300 */ #define USBOTG_ISP1583 1583 /* Creative Zen Vision:M */ #define USBOTG_M5636 5636 /* iAudio X5 */ @@ -775,7 +776,7 @@ Lyre prototype 1*/ #elif CONFIG_USBOTG == USBOTG_JZ4740 #define USB_HAS_BULK #define USB_HAS_INTERRUPT -#elif defined(CPU_TCC780X) || defined(CPU_TCC77X) +#elif defined(CPU_TCC780X) || defined(CPU_TCC77X) || defined(MROBE_500) #define USB_HAS_BULK #endif /* CONFIG_USBOTG */ diff --git a/firmware/export/m66591.h b/firmware/export/m66591.h new file mode 100644 index 0000000000..db7776e45f --- /dev/null +++ b/firmware/export/m66591.h @@ -0,0 +1,102 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id: $ + * + * Copyright (C) 2009 by Karl Kurbjun + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +#include "config.h" + +#define M66591_REG(addr) (*(volatile unsigned short *) \ + ((unsigned char *) M66591_BASE + (addr)) ) + +/* Interrupt handler routine, visible for target handler */ +void USB_DEVICE(void); + +/* Register offsets */ +#define M66591_TRN_CTRL M66591_REG(0x00) /* pg 14 */ +#define M66591_TRN_LNSTAT M66591_REG(0x02) /* pg 16 */ + +#define M66591_HSFS M66591_REG(0x04) /* pg 17 */ +#define M66591_TESTMODE M66591_REG(0x06) /* pg 18 */ + +#define M66591_PIN_CFG0 M66591_REG(0x08) /* pg 19 */ +#define M66591_PIN_CFG1 M66591_REG(0x0A) /* pg 20 */ +#define M66591_PIN_CFG2 M66591_REG(0x0C) /* pg 21 */ + +#define M66591_CPORT M66591_REG(0x14) /* pg 23 */ +#define M66591_DPORT M66591_REG(0x18) /* pg 24 */ + +#define M66591_DCP_CTRLEN M66591_REG(0x26) /* pg 25 */ + +#define M66591_CPORT_CTRL0 M66591_REG(0x28) /* pg 26 */ +#define M66591_CPORT_CTRL1 M66591_REG(0x2C) /* pg 28 */ +#define M66591_CPORT_CTRL2 M66591_REG(0x2E) /* pg 30 */ + +#define M66591_DPORT_CTRL0 M66591_REG(0x30) /* pg 31 */ +#define M66591_DPORT_CTRL1 M66591_REG(0x34) /* pg 34 */ +#define M66591_DPORT_CTRL2 M66591_REG(0x36) /* pg 36 */ + +#define M66591_INTCFG_MAIN M66591_REG(0x40) /* pg 37 */ +#define M66591_INTCFG_OUT M66591_REG(0x42) /* pg 40 */ +#define M66591_INTCFG_RDY M66591_REG(0x44) /* pg 41 */ +#define M66591_INTCFG_NRDY M66591_REG(0x48) /* pg 42 */ +#define M66591_INTCFG_EMP M66591_REG(0x4C) /* pg 43 */ + +#define M66591_INTSTAT_MAIN M66591_REG(0x60) /* pg 44 */ +#define M66591_INTSTAT_RDY M66591_REG(0x64) /* pg 48 */ +#define M66591_INTSTAT_NRDY M66591_REG(0x68) /* pg 50 */ +#define M66591_INTSTAT_EMP M66591_REG(0x6C) /* pg 53 */ + +#define M66591_USB_ADDRESS M66591_REG(0x74) /* pg 56 */ + +#define M66591_USB_REQ0 M66591_REG(0x78) /* pg 57 */ +#define M66591_USB_REQ1 M66591_REG(0x7A) /* pg 58 */ +#define M66591_USB_REQ2 M66591_REG(0x7C) /* pg 59 */ +#define M66591_USB_REQ3 M66591_REG(0x7E) /* pg 60 */ + +#define M66591_DCP_CNTMD M66591_REG(0x82) /* pg 61 */ +#define M66591_DCP_MXPKSZ M66591_REG(0x84) /* pg 62 */ +#define M66591_DCPCTRL M66591_REG(0x88) /* pg 63 */ + +#define M66591_PIPE_CFGSEL M66591_REG(0x8C) /* pg 65 */ +#define M66591_PIPE_CFGWND M66591_REG(0x90) /* pg 66 */ + +#define M66591_PIPECTRL1 M66591_REG(0xA0) /* pg 69 */ +#define M66591_PIPECTRL2 M66591_REG(0xA2) /* pg 69 */ +#define M66591_PIPECTRL3 M66591_REG(0xA4) /* pg 69 */ +#define M66591_PIPECTRL4 M66591_REG(0xA6) /* pg 69 */ +#define M66591_PIPECTRL5 M66591_REG(0xA8) /* pg 71 */ +#define M66591_PIPECTRL6 M66591_REG(0xAA) /* pg 71 */ + +/* These defines are used for CTRL register handshake setup + * They are used on the following registers: + * DCPCTRL and PIPECTRL(1-6) + */ +#define PIPE_SHAKE_NAK 0x00 +#define PIPE_SHAKE_BUF 0x01 +#define PIPE_SHAKE_STALL 0x02 + +/* These defines are used for the control transfer stage status */ +#define CTRL_IDLE 0x00 /* Idle Stage */ +#define CTRL_RTDS 0x01 /* Read transfer data stage */ +#define CTRL_RTSS 0x02 /* Read transfer status stage */ +#define CTRL_WTDS 0x03 /* Write transfer data stage */ +#define CTRL_WTSS 0x04 /* Write transfer status stage */ +#define CTRL_WTND 0x05 /* Write transfer no data stage */ +#define CTRL_TRER 0x06 /* Transmit error stage */ + -- cgit v1.2.3