From 18bee1bafb7ce4cb7610a491c12c2d41939a2c2f Mon Sep 17 00:00:00 2001 From: Rafaël Carré Date: Sat, 31 Dec 2011 21:15:10 +0000 Subject: usb-drv-as3525v2.h: remove git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31507 a1c6a512-1295-4272-9138-f99709370657 --- firmware/export/as3525v2.h | 39 +++++++++++++++++++++++++++++++++++++++ firmware/export/usb-s3c6400x.h | 8 ++++++++ 2 files changed, 47 insertions(+) (limited to 'firmware/export') diff --git a/firmware/export/as3525v2.h b/firmware/export/as3525v2.h index 4c571f2a22..3778ff7785 100644 --- a/firmware/export/as3525v2.h +++ b/firmware/export/as3525v2.h @@ -45,4 +45,43 @@ #undef USB_DEVBSS_ATTR #define USB_DEVBSS_ATTR __attribute__((aligned(32))) +#define USBPHY_REG(offset) (*(volatile uint32_t*)(OTGBASE + offset)) + +/** User HW Config1 Register */ +#define GHWCFG1 USBPHY_REG(0x044) +#define GHWCFG1_epdir_bitp(ep) (2 * (ep)) +#define GHWCFG1_epdir_bits 0x3 +#define GHWCFG1_EPDIR_BIDIR 0 +#define GHWCFG1_EPDIR_IN 1 +#define GHWCFG1_EPDIR_OUT 2 + +/** User HW Config2 Register */ +#define GHWCFG2 USBPHY_REG(0x048) +#define GHWCFG2_arch_bitp 3 /** Architecture */ +#define GHWCFG2_arch_bits 0x3 +#define GHWCFG2_hs_phy_type_bitp 6 /** High speed PHY type */ +#define GHWCFG2_hs_phy_type_bits 0x3 +#define GHWCFG2_fs_phy_type_bitp 8 /** Full speed PHY type */ +#define GHWCFG2_fs_phy_type_bits 0x3 +#define GHWCFG2_num_ep_bitp 10 /** Number of endpoints */ +#define GHWCFG2_num_ep_bits 0xf +#define GHWCFG2_dyn_fifo (1 << 19) /** Dynamic FIFO */ +/* For GHWCFG2_HS_PHY_TYPE and GHWCFG2_FS_PHY_TYPE */ +#define GHWCFG2_PHY_TYPE_UNSUPPORTED 0 +#define GHWCFG2_PHY_TYPE_UTMI 1 +#define GHWCFG2_ARCH_INTERNAL_DMA 2 + +/** User HW Config3 Register */ +#define GHWCFG3 USBPHY_REG(0x04C) +#define GHWCFG3_dfifo_len_bitp 16 /** Total fifo size */ +#define GHWCFG3_dfifo_len_bits 0xffff + +/** User HW Config4 Register */ +#define GHWCFG4 USBPHY_REG(0x050) +#define GHWCFG4_utmi_phy_data_width_bitp 14 /** UTMI+ data bus width */ +#define GHWCFG4_utmi_phy_data_width_bits 0x3 +#define GHWCFG4_ded_fifo_en (1 << 25) /** Dedicated Tx FIFOs */ +#define GHWCFG4_num_in_ep_bitp 26 /** Number of IN endpoints */ +#define GHWCFG4_num_in_ep_bits 0xf + #endif /* __AS3525V2_H__ */ diff --git a/firmware/export/usb-s3c6400x.h b/firmware/export/usb-s3c6400x.h index 4c5f57e5ad..165ab4e461 100644 --- a/firmware/export/usb-s3c6400x.h +++ b/firmware/export/usb-s3c6400x.h @@ -480,6 +480,14 @@ /** Device Endpoint (ep) DMA Address Register */ #define DEPDMA(x,out) (*((const void* volatile*)(OTGBASE + 0x914 + (0x200 * (!!out)) + 0x20 * (x)))) +#if 0 /* Those are present in as3525v2, not s5l870x */ +/** Device IN Endpoint (ep) Transmit FIFO Status Register */ +#define DTXFSTS(ep) (*((const void* volatile*)(OTGBASE + 0x918 + 0x20 * (x)))) + +/** Device OUT Endpoint (ep) Frame number Register */ +#define DOEPFN(ep) (*((const void* volatile*)(OTGBASE + 0xB04 + 0x20 * (x)))) +#endif + /* Power and Clock Gating Register */ #define PCGCCTL (*((uint32_t volatile*)(OTGBASE + 0xE00))) -- cgit v1.2.3