From d03fe64dcf80633c7ec78f122682e78fb59fe2d8 Mon Sep 17 00:00:00 2001 From: Michael Sparmann Date: Tue, 20 Oct 2009 06:37:07 +0000 Subject: iPod Nano 2G USB support based on the S3C6400X datasheet. Disabled by default for now. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23285 a1c6a512-1295-4272-9138-f99709370657 --- firmware/export/usb-s3c6400x.h | 341 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 341 insertions(+) create mode 100644 firmware/export/usb-s3c6400x.h (limited to 'firmware/export/usb-s3c6400x.h') diff --git a/firmware/export/usb-s3c6400x.h b/firmware/export/usb-s3c6400x.h new file mode 100644 index 0000000000..22b0769681 --- /dev/null +++ b/firmware/export/usb-s3c6400x.h @@ -0,0 +1,341 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2009 Michael Sparmann + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef USB_S3C6400X_H +#define USB_S3C6400X_H + + +#define REG32_PTR_T volatile uint32_t * + + +/*** OTG PHY CONTROL REGISTERS ***/ +#define OPHYPWR *(REG32_PTR_T)(PHYBASE + 0x000) +#define OPHYCLK *(REG32_PTR_T)(PHYBASE + 0x004) +#define ORSTCON *(REG32_PTR_T)(PHYBASE + 0x008) + +/*** OTG LINK CORE REGISTERS ***/ +/* Core Global Registers */ +#define GOTGCTL *(REG32_PTR_T)(OTGBASE + 0x000) +#define GOTGINT *(REG32_PTR_T)(OTGBASE + 0x004) +#define GAHBCFG *(REG32_PTR_T)(OTGBASE + 0x008) +#define GUSBCFG *(REG32_PTR_T)(OTGBASE + 0x00C) +#define GRSTCTL *(REG32_PTR_T)(OTGBASE + 0x010) +#define GINTSTS *(REG32_PTR_T)(OTGBASE + 0x014) +#define GINTMSK *(REG32_PTR_T)(OTGBASE + 0x018) +#define GRXSTSR *(REG32_PTR_T)(OTGBASE + 0x01C) +#define GRXSTSP *(REG32_PTR_T)(OTGBASE + 0x020) +#define GRXFSIZ *(REG32_PTR_T)(OTGBASE + 0x024) +#define GNPTXFSIZ *(REG32_PTR_T)(OTGBASE + 0x028) +#define GNPTXSTS *(REG32_PTR_T)(OTGBASE + 0x02C) +#define HPTXFSIZ *(REG32_PTR_T)(OTGBASE + 0x100) +#define DPTXFSIZ(x) *(REG32_PTR_T)(OTGBASE + 0x100 + 4 * x) +#define DPTXFSIZ1 *(REG32_PTR_T)(OTGBASE + 0x104) +#define DPTXFSIZ2 *(REG32_PTR_T)(OTGBASE + 0x108) +#define DPTXFSIZ3 *(REG32_PTR_T)(OTGBASE + 0x10C) +#define DPTXFSIZ4 *(REG32_PTR_T)(OTGBASE + 0x110) +#define DPTXFSIZ5 *(REG32_PTR_T)(OTGBASE + 0x114) +#define DPTXFSIZ6 *(REG32_PTR_T)(OTGBASE + 0x118) +#define DPTXFSIZ7 *(REG32_PTR_T)(OTGBASE + 0x11C) +#define DPTXFSIZ8 *(REG32_PTR_T)(OTGBASE + 0x120) +#define DPTXFSIZ9 *(REG32_PTR_T)(OTGBASE + 0x124) +#define DPTXFSIZ10 *(REG32_PTR_T)(OTGBASE + 0x128) +#define DPTXFSIZ11 *(REG32_PTR_T)(OTGBASE + 0x12C) +#define DPTXFSIZ12 *(REG32_PTR_T)(OTGBASE + 0x130) +#define DPTXFSIZ13 *(REG32_PTR_T)(OTGBASE + 0x134) +#define DPTXFSIZ14 *(REG32_PTR_T)(OTGBASE + 0x138) +#define DPTXFSIZ15 *(REG32_PTR_T)(OTGBASE + 0x13C) + +/*** HOST MODE REGISTERS ***/ +/* Host Global Registers */ +#define HCFG *(REG32_PTR_T)(OTGBASE + 0x400) +#define HFIR *(REG32_PTR_T)(OTGBASE + 0x404) +#define HFNUM *(REG32_PTR_T)(OTGBASE + 0x408) +#define HPTXSTS *(REG32_PTR_T)(OTGBASE + 0x410) +#define HAINT *(REG32_PTR_T)(OTGBASE + 0x414) +#define HAINTMSK *(REG32_PTR_T)(OTGBASE + 0x418) + +/* Host Port Control and Status Registers */ +#define HPRT *(REG32_PTR_T)(OTGBASE + 0x440) + +/* Host Channel-Specific Registers */ +#define HCCHAR(x) *(REG32_PTR_T)(OTGBASE + 0x500 + 0x20 * x) +#define HCSPLT(x) *(REG32_PTR_T)(OTGBASE + 0x504 + 0x20 * x) +#define HCINT(x) *(REG32_PTR_T)(OTGBASE + 0x508 + 0x20 * x) +#define HCINTMSK(x) *(REG32_PTR_T)(OTGBASE + 0x50C + 0x20 * x) +#define HCTSIZ(x) *(REG32_PTR_T)(OTGBASE + 0x510 + 0x20 * x) +#define HCDMA(x) *(REG32_PTR_T)(OTGBASE + 0x514 + 0x20 * x) +#define HCCHAR0 *(REG32_PTR_T)(OTGBASE + 0x500) +#define HCSPLT0 *(REG32_PTR_T)(OTGBASE + 0x504) +#define HCINT0 *(REG32_PTR_T)(OTGBASE + 0x508) +#define HCINTMSK0 *(REG32_PTR_T)(OTGBASE + 0x50C) +#define HCTSIZ0 *(REG32_PTR_T)(OTGBASE + 0x510) +#define HCDMA0 *(REG32_PTR_T)(OTGBASE + 0x514) +#define HCCHAR1 *(REG32_PTR_T)(OTGBASE + 0x520) +#define HCSPLT1 *(REG32_PTR_T)(OTGBASE + 0x524) +#define HCINT1 *(REG32_PTR_T)(OTGBASE + 0x528) +#define HCINTMSK1 *(REG32_PTR_T)(OTGBASE + 0x52C) +#define HCTSIZ1 *(REG32_PTR_T)(OTGBASE + 0x530) +#define HCDMA1 *(REG32_PTR_T)(OTGBASE + 0x534) +#define HCCHAR2 *(REG32_PTR_T)(OTGBASE + 0x540) +#define HCSPLT2 *(REG32_PTR_T)(OTGBASE + 0x544) +#define HCINT2 *(REG32_PTR_T)(OTGBASE + 0x548) +#define HCINTMSK2 *(REG32_PTR_T)(OTGBASE + 0x54C) +#define HCTSIZ2 *(REG32_PTR_T)(OTGBASE + 0x550) +#define HCDMA2 *(REG32_PTR_T)(OTGBASE + 0x554) +#define HCCHAR3 *(REG32_PTR_T)(OTGBASE + 0x560) +#define HCSPLT3 *(REG32_PTR_T)(OTGBASE + 0x564) +#define HCINT3 *(REG32_PTR_T)(OTGBASE + 0x568) +#define HCINTMSK3 *(REG32_PTR_T)(OTGBASE + 0x56C) +#define HCTSIZ3 *(REG32_PTR_T)(OTGBASE + 0x570) +#define HCDMA3 *(REG32_PTR_T)(OTGBASE + 0x574) +#define HCCHAR4 *(REG32_PTR_T)(OTGBASE + 0x580) +#define HCSPLT4 *(REG32_PTR_T)(OTGBASE + 0x584) +#define HCINT4 *(REG32_PTR_T)(OTGBASE + 0x588) +#define HCINTMSK4 *(REG32_PTR_T)(OTGBASE + 0x58C) +#define HCTSIZ4 *(REG32_PTR_T)(OTGBASE + 0x590) +#define HCDMA4 *(REG32_PTR_T)(OTGBASE + 0x594) +#define HCCHAR5 *(REG32_PTR_T)(OTGBASE + 0x5A0) +#define HCSPLT5 *(REG32_PTR_T)(OTGBASE + 0x5A4) +#define HCINT5 *(REG32_PTR_T)(OTGBASE + 0x5A8) +#define HCINTMSK5 *(REG32_PTR_T)(OTGBASE + 0x5AC) +#define HCTSIZ5 *(REG32_PTR_T)(OTGBASE + 0x5B0) +#define HCDMA5 *(REG32_PTR_T)(OTGBASE + 0x5B4) +#define HCCHAR6 *(REG32_PTR_T)(OTGBASE + 0x5C0) +#define HCSPLT6 *(REG32_PTR_T)(OTGBASE + 0x5C4) +#define HCINT6 *(REG32_PTR_T)(OTGBASE + 0x5C8) +#define HCINTMSK6 *(REG32_PTR_T)(OTGBASE + 0x5CC) +#define HCTSIZ6 *(REG32_PTR_T)(OTGBASE + 0x5D0) +#define HCDMA6 *(REG32_PTR_T)(OTGBASE + 0x5D4) +#define HCCHAR7 *(REG32_PTR_T)(OTGBASE + 0x5E0) +#define HCSPLT7 *(REG32_PTR_T)(OTGBASE + 0x5E4) +#define HCINT7 *(REG32_PTR_T)(OTGBASE + 0x5E8) +#define HCINTMSK7 *(REG32_PTR_T)(OTGBASE + 0x5EC) +#define HCTSIZ7 *(REG32_PTR_T)(OTGBASE + 0x5F0) +#define HCDMA7 *(REG32_PTR_T)(OTGBASE + 0x5F4) +#define HCCHAR8 *(REG32_PTR_T)(OTGBASE + 0x600) +#define HCSPLT8 *(REG32_PTR_T)(OTGBASE + 0x604) +#define HCINT8 *(REG32_PTR_T)(OTGBASE + 0x608) +#define HCINTMSK8 *(REG32_PTR_T)(OTGBASE + 0x60C) +#define HCTSIZ8 *(REG32_PTR_T)(OTGBASE + 0x610) +#define HCDMA8 *(REG32_PTR_T)(OTGBASE + 0x614) +#define HCCHAR9 *(REG32_PTR_T)(OTGBASE + 0x620) +#define HCSPLT9 *(REG32_PTR_T)(OTGBASE + 0x624) +#define HCINT9 *(REG32_PTR_T)(OTGBASE + 0x628) +#define HCINTMSK9 *(REG32_PTR_T)(OTGBASE + 0x62C) +#define HCTSIZ9 *(REG32_PTR_T)(OTGBASE + 0x630) +#define HCDMA9 *(REG32_PTR_T)(OTGBASE + 0x634) +#define HCCHAR10 *(REG32_PTR_T)(OTGBASE + 0x640) +#define HCSPLT10 *(REG32_PTR_T)(OTGBASE + 0x644) +#define HCINT10 *(REG32_PTR_T)(OTGBASE + 0x648) +#define HCINTMSK10 *(REG32_PTR_T)(OTGBASE + 0x64C) +#define HCTSIZ10 *(REG32_PTR_T)(OTGBASE + 0x650) +#define HCDMA10 *(REG32_PTR_T)(OTGBASE + 0x654) +#define HCCHAR11 *(REG32_PTR_T)(OTGBASE + 0x660) +#define HCSPLT11 *(REG32_PTR_T)(OTGBASE + 0x664) +#define HCINT11 *(REG32_PTR_T)(OTGBASE + 0x668) +#define HCINTMSK11 *(REG32_PTR_T)(OTGBASE + 0x66C) +#define HCTSIZ11 *(REG32_PTR_T)(OTGBASE + 0x670) +#define HCDMA11 *(REG32_PTR_T)(OTGBASE + 0x674) +#define HCCHAR12 *(REG32_PTR_T)(OTGBASE + 0x680) +#define HCSPLT12 *(REG32_PTR_T)(OTGBASE + 0x684) +#define HCINT12 *(REG32_PTR_T)(OTGBASE + 0x688) +#define HCINTMSK12 *(REG32_PTR_T)(OTGBASE + 0x68C) +#define HCTSIZ12 *(REG32_PTR_T)(OTGBASE + 0x690) +#define HCDMA12 *(REG32_PTR_T)(OTGBASE + 0x694) +#define HCCHAR13 *(REG32_PTR_T)(OTGBASE + 0x6A0) +#define HCSPLT13 *(REG32_PTR_T)(OTGBASE + 0x6A4) +#define HCINT13 *(REG32_PTR_T)(OTGBASE + 0x6A8) +#define HCINTMSK13 *(REG32_PTR_T)(OTGBASE + 0x6AC) +#define HCTSIZ13 *(REG32_PTR_T)(OTGBASE + 0x6B0) +#define HCDMA13 *(REG32_PTR_T)(OTGBASE + 0x6B4) +#define HCCHAR14 *(REG32_PTR_T)(OTGBASE + 0x6C0) +#define HCSPLT14 *(REG32_PTR_T)(OTGBASE + 0x6C4) +#define HCINT14 *(REG32_PTR_T)(OTGBASE + 0x6C8) +#define HCINTMSK14 *(REG32_PTR_T)(OTGBASE + 0x6CC) +#define HCTSIZ14 *(REG32_PTR_T)(OTGBASE + 0x6D0) +#define HCDMA14 *(REG32_PTR_T)(OTGBASE + 0x6D4) +#define HCCHAR15 *(REG32_PTR_T)(OTGBASE + 0x6E0) +#define HCSPLT15 *(REG32_PTR_T)(OTGBASE + 0x6E4) +#define HCINT15 *(REG32_PTR_T)(OTGBASE + 0x6E8) +#define HCINTMSK15 *(REG32_PTR_T)(OTGBASE + 0x6EC) +#define HCTSIZ15 *(REG32_PTR_T)(OTGBASE + 0x6F0) +#define HCDMA15 *(REG32_PTR_T)(OTGBASE + 0x6F4) + +/*** DEVICE MODE REGISTERS ***/ +/* Device Global Registers */ +#define DCFG *(REG32_PTR_T)(OTGBASE + 0x800) +#define DCTL *(REG32_PTR_T)(OTGBASE + 0x804) +#define DSTS *(REG32_PTR_T)(OTGBASE + 0x808) +#define DIEPMSK *(REG32_PTR_T)(OTGBASE + 0x810) +#define DOEPMSK *(REG32_PTR_T)(OTGBASE + 0x814) +#define DAINT *(REG32_PTR_T)(OTGBASE + 0x818) +#define DAINTMSK *(REG32_PTR_T)(OTGBASE + 0x81C) +#define DTKNQR1 *(REG32_PTR_T)(OTGBASE + 0x820) +#define DTKNQR2 *(REG32_PTR_T)(OTGBASE + 0x824) +#define DVBUSDIS *(REG32_PTR_T)(OTGBASE + 0x828) +#define DVBUSPULSE *(REG32_PTR_T)(OTGBASE + 0x82C) +#define DTKNQR3 *(REG32_PTR_T)(OTGBASE + 0x830) +#define DTKNQR4 *(REG32_PTR_T)(OTGBASE + 0x834) + +/* Device Logical IN Endpoint-Specific Registers */ +#define DIEPCTL(x) *(REG32_PTR_T)(OTGBASE + 0x900 + 0x20 * x) +#define DIEPINT(x) *(REG32_PTR_T)(OTGBASE + 0x908 + 0x20 * x) +#define DIEPTSIZ(x) *(REG32_PTR_T)(OTGBASE + 0x910 + 0x20 * x) +#define DIEPDMA(x) *(REG32_PTR_T)(OTGBASE + 0x914 + 0x20 * x) +#define DIEPCTL0 *(REG32_PTR_T)(OTGBASE + 0x900) +#define DIEPINT0 *(REG32_PTR_T)(OTGBASE + 0x908) +#define DIEPTSIZ0 *(REG32_PTR_T)(OTGBASE + 0x910) +#define DIEPDMA0 *(REG32_PTR_T)(OTGBASE + 0x914) +#define DIEPCTL1 *(REG32_PTR_T)(OTGBASE + 0x920) +#define DIEPINT1 *(REG32_PTR_T)(OTGBASE + 0x928) +#define DIEPTSIZ1 *(REG32_PTR_T)(OTGBASE + 0x930) +#define DIEPDMA1 *(REG32_PTR_T)(OTGBASE + 0x934) +#define DIEPCTL2 *(REG32_PTR_T)(OTGBASE + 0x940) +#define DIEPINT2 *(REG32_PTR_T)(OTGBASE + 0x948) +#define DIEPTSIZ2 *(REG32_PTR_T)(OTGBASE + 0x950) +#define DIEPDMA2 *(REG32_PTR_T)(OTGBASE + 0x954) +#define DIEPCTL3 *(REG32_PTR_T)(OTGBASE + 0x960) +#define DIEPINT3 *(REG32_PTR_T)(OTGBASE + 0x968) +#define DIEPTSIZ3 *(REG32_PTR_T)(OTGBASE + 0x970) +#define DIEPDMA3 *(REG32_PTR_T)(OTGBASE + 0x974) +#define DIEPCTL4 *(REG32_PTR_T)(OTGBASE + 0x980) +#define DIEPINT4 *(REG32_PTR_T)(OTGBASE + 0x988) +#define DIEPTSIZ4 *(REG32_PTR_T)(OTGBASE + 0x990) +#define DIEPDMA4 *(REG32_PTR_T)(OTGBASE + 0x994) +#define DIEPCTL5 *(REG32_PTR_T)(OTGBASE + 0x9A0) +#define DIEPINT5 *(REG32_PTR_T)(OTGBASE + 0x9A8) +#define DIEPTSIZ5 *(REG32_PTR_T)(OTGBASE + 0x9B0) +#define DIEPDMA5 *(REG32_PTR_T)(OTGBASE + 0x9B4) +#define DIEPCTL6 *(REG32_PTR_T)(OTGBASE + 0x9C0) +#define DIEPINT6 *(REG32_PTR_T)(OTGBASE + 0x9C8) +#define DIEPTSIZ6 *(REG32_PTR_T)(OTGBASE + 0x9D0) +#define DIEPDMA6 *(REG32_PTR_T)(OTGBASE + 0x9D4) +#define DIEPCTL7 *(REG32_PTR_T)(OTGBASE + 0x9E0) +#define DIEPINT7 *(REG32_PTR_T)(OTGBASE + 0x9E8) +#define DIEPTSIZ7 *(REG32_PTR_T)(OTGBASE + 0x9F0) +#define DIEPDMA7 *(REG32_PTR_T)(OTGBASE + 0x9F4) +#define DIEPCTL8 *(REG32_PTR_T)(OTGBASE + 0xA00) +#define DIEPINT8 *(REG32_PTR_T)(OTGBASE + 0xA08) +#define DIEPTSIZ8 *(REG32_PTR_T)(OTGBASE + 0xA10) +#define DIEPDMA8 *(REG32_PTR_T)(OTGBASE + 0xA14) +#define DIEPCTL9 *(REG32_PTR_T)(OTGBASE + 0xA20) +#define DIEPINT9 *(REG32_PTR_T)(OTGBASE + 0xA28) +#define DIEPTSIZ9 *(REG32_PTR_T)(OTGBASE + 0xA30) +#define DIEPDMA9 *(REG32_PTR_T)(OTGBASE + 0xA34) +#define DIEPCTL10 *(REG32_PTR_T)(OTGBASE + 0xA40) +#define DIEPINT10 *(REG32_PTR_T)(OTGBASE + 0xA48) +#define DIEPTSIZ10 *(REG32_PTR_T)(OTGBASE + 0xA50) +#define DIEPDMA10 *(REG32_PTR_T)(OTGBASE + 0xA54) +#define DIEPCTL11 *(REG32_PTR_T)(OTGBASE + 0xA60) +#define DIEPINT11 *(REG32_PTR_T)(OTGBASE + 0xA68) +#define DIEPTSIZ11 *(REG32_PTR_T)(OTGBASE + 0xA70) +#define DIEPDMA11 *(REG32_PTR_T)(OTGBASE + 0xA74) +#define DIEPCTL12 *(REG32_PTR_T)(OTGBASE + 0xA80) +#define DIEPINT12 *(REG32_PTR_T)(OTGBASE + 0xA88) +#define DIEPTSIZ12 *(REG32_PTR_T)(OTGBASE + 0xA90) +#define DIEPDMA12 *(REG32_PTR_T)(OTGBASE + 0xA94) +#define DIEPCTL13 *(REG32_PTR_T)(OTGBASE + 0xAA0) +#define DIEPINT13 *(REG32_PTR_T)(OTGBASE + 0xAA8) +#define DIEPTSIZ13 *(REG32_PTR_T)(OTGBASE + 0xAB0) +#define DIEPDMA13 *(REG32_PTR_T)(OTGBASE + 0xAB4) +#define DIEPCTL14 *(REG32_PTR_T)(OTGBASE + 0xAC0) +#define DIEPINT14 *(REG32_PTR_T)(OTGBASE + 0xAC8) +#define DIEPTSIZ14 *(REG32_PTR_T)(OTGBASE + 0xAD0) +#define DIEPDMA14 *(REG32_PTR_T)(OTGBASE + 0xAD4) +#define DIEPCTL15 *(REG32_PTR_T)(OTGBASE + 0xAE0) +#define DIEPINT15 *(REG32_PTR_T)(OTGBASE + 0xAE8) +#define DIEPTSIZ15 *(REG32_PTR_T)(OTGBASE + 0xAF0) +#define DIEPDMA15 *(REG32_PTR_T)(OTGBASE + 0xAF4) + +/* Device Logical OUT Endpoint-Specific Registers */ +#define DOEPCTL(x) *(REG32_PTR_T)(OTGBASE + 0xB00 + 0x20 * x) +#define DOEPINT(x) *(REG32_PTR_T)(OTGBASE + 0xB08 + 0x20 * x) +#define DOEPTSIZ(x) *(REG32_PTR_T)(OTGBASE + 0xB10 + 0x20 * x) +#define DOEPDMA(x) *(REG32_PTR_T)(OTGBASE + 0xB14 + 0x20 * x) +#define DOEPCTL0 *(REG32_PTR_T)(OTGBASE + 0xB00) +#define DOEPINT0 *(REG32_PTR_T)(OTGBASE + 0xB08) +#define DOEPTSIZ0 *(REG32_PTR_T)(OTGBASE + 0xB10) +#define DOEPDMA0 *(REG32_PTR_T)(OTGBASE + 0xB14) +#define DOEPCTL1 *(REG32_PTR_T)(OTGBASE + 0xB20) +#define DOEPINT1 *(REG32_PTR_T)(OTGBASE + 0xB28) +#define DOEPTSIZ1 *(REG32_PTR_T)(OTGBASE + 0xB30) +#define DOEPDMA1 *(REG32_PTR_T)(OTGBASE + 0xB34) +#define DOEPCTL2 *(REG32_PTR_T)(OTGBASE + 0xB40) +#define DOEPINT2 *(REG32_PTR_T)(OTGBASE + 0xB48) +#define DOEPTSIZ2 *(REG32_PTR_T)(OTGBASE + 0xB50) +#define DOEPDMA2 *(REG32_PTR_T)(OTGBASE + 0xB54) +#define DOEPCTL3 *(REG32_PTR_T)(OTGBASE + 0xB60) +#define DOEPINT3 *(REG32_PTR_T)(OTGBASE + 0xB68) +#define DOEPTSIZ3 *(REG32_PTR_T)(OTGBASE + 0xB70) +#define DOEPDMA3 *(REG32_PTR_T)(OTGBASE + 0xB74) +#define DOEPCTL4 *(REG32_PTR_T)(OTGBASE + 0xB80) +#define DOEPINT4 *(REG32_PTR_T)(OTGBASE + 0xB88) +#define DOEPTSIZ4 *(REG32_PTR_T)(OTGBASE + 0xB90) +#define DOEPDMA4 *(REG32_PTR_T)(OTGBASE + 0xB94) +#define DOEPCTL5 *(REG32_PTR_T)(OTGBASE + 0xBA0) +#define DOEPINT5 *(REG32_PTR_T)(OTGBASE + 0xBA8) +#define DOEPTSIZ5 *(REG32_PTR_T)(OTGBASE + 0xBB0) +#define DOEPDMA5 *(REG32_PTR_T)(OTGBASE + 0xBB4) +#define DOEPCTL6 *(REG32_PTR_T)(OTGBASE + 0xBC0) +#define DOEPINT6 *(REG32_PTR_T)(OTGBASE + 0xBC8) +#define DOEPTSIZ6 *(REG32_PTR_T)(OTGBASE + 0xBD0) +#define DOEPDMA6 *(REG32_PTR_T)(OTGBASE + 0xBD4) +#define DOEPCTL7 *(REG32_PTR_T)(OTGBASE + 0xBE0) +#define DOEPINT7 *(REG32_PTR_T)(OTGBASE + 0xBE8) +#define DOEPTSIZ7 *(REG32_PTR_T)(OTGBASE + 0xBF0) +#define DOEPDMA7 *(REG32_PTR_T)(OTGBASE + 0xBF4) +#define DOEPCTL8 *(REG32_PTR_T)(OTGBASE + 0xC00) +#define DOEPINT8 *(REG32_PTR_T)(OTGBASE + 0xC08) +#define DOEPTSIZ8 *(REG32_PTR_T)(OTGBASE + 0xC10) +#define DOEPDMA8 *(REG32_PTR_T)(OTGBASE + 0xC14) +#define DOEPCTL9 *(REG32_PTR_T)(OTGBASE + 0xC20) +#define DOEPINT9 *(REG32_PTR_T)(OTGBASE + 0xC28) +#define DOEPTSIZ9 *(REG32_PTR_T)(OTGBASE + 0xC30) +#define DOEPDMA9 *(REG32_PTR_T)(OTGBASE + 0xC34) +#define DOEPCTL10 *(REG32_PTR_T)(OTGBASE + 0xC40) +#define DOEPINT10 *(REG32_PTR_T)(OTGBASE + 0xC48) +#define DOEPTSIZ10 *(REG32_PTR_T)(OTGBASE + 0xC50) +#define DOEPDMA10 *(REG32_PTR_T)(OTGBASE + 0xC54) +#define DOEPCTL11 *(REG32_PTR_T)(OTGBASE + 0xC60) +#define DOEPINT11 *(REG32_PTR_T)(OTGBASE + 0xC68) +#define DOEPTSIZ11 *(REG32_PTR_T)(OTGBASE + 0xC70) +#define DOEPDMA11 *(REG32_PTR_T)(OTGBASE + 0xC74) +#define DOEPCTL12 *(REG32_PTR_T)(OTGBASE + 0xC80) +#define DOEPINT12 *(REG32_PTR_T)(OTGBASE + 0xC88) +#define DOEPTSIZ12 *(REG32_PTR_T)(OTGBASE + 0xC90) +#define DOEPDMA12 *(REG32_PTR_T)(OTGBASE + 0xC94) +#define DOEPCTL13 *(REG32_PTR_T)(OTGBASE + 0xCA0) +#define DOEPINT13 *(REG32_PTR_T)(OTGBASE + 0xCA8) +#define DOEPTSIZ13 *(REG32_PTR_T)(OTGBASE + 0xCB0) +#define DOEPDMA13 *(REG32_PTR_T)(OTGBASE + 0xCB4) +#define DOEPCTL14 *(REG32_PTR_T)(OTGBASE + 0xCC0) +#define DOEPINT14 *(REG32_PTR_T)(OTGBASE + 0xCC8) +#define DOEPTSIZ14 *(REG32_PTR_T)(OTGBASE + 0xCD0) +#define DOEPDMA14 *(REG32_PTR_T)(OTGBASE + 0xCD4) +#define DOEPCTL15 *(REG32_PTR_T)(OTGBASE + 0xCE0) +#define DOEPINT15 *(REG32_PTR_T)(OTGBASE + 0xCE8) +#define DOEPTSIZ15 *(REG32_PTR_T)(OTGBASE + 0xCF0) +#define DOEPDMA15 *(REG32_PTR_T)(OTGBASE + 0xCF4) + +/* Power and Clock Gating Register */ +#define PCGCCTL *(REG32_PTR_T)(OTGBASE + 0xE00) + + +#endif /* USB_S3C6400X_H */ -- cgit v1.2.3