From b7da52bb65dd3ecfc5f3695b97c8c0058c1fd92a Mon Sep 17 00:00:00 2001 From: Linus Nielsen Feltzing Date: Tue, 28 Mar 2006 20:35:08 +0000 Subject: Some corrections of the TLV320 register bit definitions git-svn-id: svn://svn.rockbox.org/rockbox/trunk@9324 a1c6a512-1295-4272-9138-f99709370657 --- firmware/export/tlv320.h | 43 +++++++++++++++++++++---------------------- 1 file changed, 21 insertions(+), 22 deletions(-) (limited to 'firmware/export/tlv320.h') diff --git a/firmware/export/tlv320.h b/firmware/export/tlv320.h index c4599f02b2..93a79780c0 100644 --- a/firmware/export/tlv320.h +++ b/firmware/export/tlv320.h @@ -39,61 +39,60 @@ extern void tlv320_disable_recording(void); /* registers */ /* REG_LLIV: Left line input channel volume control */ #define REG_LLIV 0x0 -#define LLIV_LRS (0 << 8) /* simultaneous volume/mute update */ +#define LLIV_LRS (1 << 8) /* simultaneous volume/mute update */ #define LLIV_LIM (1 << 7) /* Left line input mute */ #define LLIV_LIV(x) ((x) & 0x1f)/* Left line input volume control */ /* REG_RLIV: Right line input channel volume control */ #define REG_RLIV 0x1 -#define RLIV_RLS (0 << 8) /* simultaneous volume/mute update */ -#define RLIV_RIM (0 << 7) /* Right line input mute */ +#define RLIV_RLS (1 << 8) /* simultaneous volume/mute update */ +#define RLIV_RIM (1 << 7) /* Right line input mute */ #define RLIV_RIV(x) ((x) & 0x1f)/* Right line input volume control */ /* REG_LHV: Left Channel Headphone Volume Control */ #define REG_LHV 0x2 -#define LHV_LRS (0 << 8) /* simultaneous volume/mute update */ -#define LHV_LZC (0 << 7) /* Left-channel zero-cross detect */ +#define LHV_LRS (1 << 8) /* simultaneous volume/mute update */ +#define LHV_LZC (1 << 7) /* Left-channel zero-cross detect */ #define LHV_LHV(x) ((x) & 0x7f)/* Left headphone volume control */ /* REG_RHV: Right Channel Headphone Volume Control */ #define REG_RHV 0x3 -#define RHV_LRS (0 << 8) /* simultaneous volume/mute update */ -#define RHV_RZC (0 << 7) /* Right-channel zero-cross detect */ +#define RHV_LRS (1 << 8) /* simultaneous volume/mute update */ +#define RHV_RZC (1 << 7) /* Right-channel zero-cross detect */ #define RHV_RHV(x) ((x) & 0x7f)/* Right headphone volume control */ /* REG_AAP: Analog Audio Path Control */ #define REG_AAP 0x4 #define AAP_DAC (1 << 4) /* DAC select */ #define AAP_BYPASS (1 << 3) /* bypass */ -#define AAP_INSEL (0 << 2) /* Input select for ADC */ +#define AAP_INSEL (1 << 2) /* Input select for ADC */ #define AAP_MICM (1 << 1) /* Microphone mute */ #define AAP_MICB (1 << 0) /* Microphone boost */ /* REG_DAP: Digital Audio Path Control */ #define REG_DAP 0x5 #define DAP_DACM (1 << 3) /* DAC soft mute */ -#define DAP_DEEMP_DIS (0 << 1) /* De-emphasis control: disabled */ #define DAP_DEEMP_32 (1 << 1) /* De-emphasis control: 32 kHz */ #define DAP_DEEMP_44 (2 << 1) /* De-emphasis control: 44.1 kHz */ #define DAP_DEEMP_48 (3 << 1) /* De-emphasis control: 48 kHz */ -#define DAP_ADCHP (0 << 0) /* ADC high-pass filter */ +#define DAP_ADCHP (1 << 0) /* ADC high-pass filter */ /* REG_PC: Power Down Control */ #define REG_PC 0x6 -#define PC_ON (0 << 7) /* Device power */ -#define PC_CLK (0 << 6) /* Clock */ -#define PC_OSC (0 << 5) /* Oscillator */ -#define PC_OUT (0 << 4) /* Outputs */ -#define PC_DAC (0 << 3) /* DAC */ -#define PC_ADC (0 << 2) /* ADC */ -#define PC_MIC (0 << 1) /* Microphone input */ -#define PC_LINE (0 << 0) /* Line input */ +#define PC_ON (1 << 7) /* Device power */ +#define PC_CLK (1 << 6) /* Clock */ +#define PC_OSC (1 << 5) /* Oscillator */ +#define PC_OUT (1 << 4) /* Outputs */ +#define PC_DAC (1 << 3) /* DAC */ +#define PC_ADC (1 << 2) /* ADC */ +#define PC_MIC (1 << 1) /* Microphone input */ +#define PC_LINE (1 << 0) /* Line input */ /* REG_DAIF: Digital Audio Interface Format */ #define REG_DAIF 0x7 #define DAIF_MS (1 << 6) /* Master/slave mode */ #define DAIF_LRSWAP (1 << 5) /* DAC left/right swap */ -#define DAIF_LRP (0 << 4) /* DAC left/right phase */ +#define DAIF_LRP (1 << 4) /* DAC left/right phase */ #define DAIF_IWL_16 (0 << 2) /* Input bit length: 16 bit */ #define DAIF_IWL_20 (1 << 2) /* Input bit length: 20 bit */ #define DAIF_IWL_24 (2 << 2) /* Input bit length: 24 bit */ @@ -105,15 +104,15 @@ extern void tlv320_disable_recording(void); /* REG_SRC: Sample Rate Control */ #define REG_SRC 0x8 -#define SRC_CLKIN (0 << 6) /* Clock input divider */ -#define SRC_CLKOUT (0 << 7) /* Clock output divider */ +#define SRC_CLKIN (1 << 6) /* Clock input divider */ +#define SRC_CLKOUT (1 << 7) /* Clock output divider */ /*#define SRC_SR ()*/ #define SRC_BOSR (1 << 1) /* Base oversampling rate, depends on SRC_USB */ #define SRC_USB (1 << 0) /* Clock mode select */ /* REG_DIA: Digital Interface Activation */ #define REG_DIA 0x9 -#define DIA_ACT (1 << 6) /* Activate interface */ +#define DIA_ACT (1 << 0) /* Activate interface */ /* REG_RR: Reset Register */ #define REG_RR 0xf -- cgit v1.2.3