From 19a5dfea283c89540b61d0103ba0fe8ddee17612 Mon Sep 17 00:00:00 2001
From: Rob Purchase <shotofadds@rockbox.org>
Date: Tue, 1 Sep 2009 21:35:37 +0000
Subject: D2: Enable ARM cache coherency functions (eg. during codec load),
 which should eliminate data aborts/freezes on track changes. NOTE: The linker
 script reserves space at the end of DRAM for the TTB, but this is not
 currently used.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22595 a1c6a512-1295-4272-9138-f99709370657
---
 firmware/export/tcc780x.h | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'firmware/export/tcc780x.h')

diff --git a/firmware/export/tcc780x.h b/firmware/export/tcc780x.h
index 497f1514e0..aca3bec2bd 100644
--- a/firmware/export/tcc780x.h
+++ b/firmware/export/tcc780x.h
@@ -21,6 +21,11 @@
 #ifndef __TCC780X_H__
 #define __TCC780X_H__
 
+#define TTB_SIZE      (0x4000)
+/* must be 16Kb (0x4000) aligned */
+#define TTB_BASE_ADDR (0x20000000 + (MEMORYSIZE*1024*1024) - TTB_SIZE)
+#define TTB_BASE      ((unsigned long *)TTB_BASE_ADDR) /* End of memory */
+
 /* General-purpose IO */
 
 #define PORTCFG0    (*(volatile unsigned long *)0xF005A000)
-- 
cgit v1.2.3