From 7b861eca95b54f4132e2ed6a8f9c0edbf0a65ab8 Mon Sep 17 00:00:00 2001 From: Jens Arnold Date: Tue, 3 Jul 2007 00:42:42 +0000 Subject: More PP502x clock setup rework. This should fix the freezes on PP5020 once and for all. Enabled clock scaling for H10. * CPUFREQ_MAX changed to 78MHz * To be cleaned up soon. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13767 a1c6a512-1295-4272-9138-f99709370657 --- firmware/export/pp5020.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'firmware/export/pp5020.h') diff --git a/firmware/export/pp5020.h b/firmware/export/pp5020.h index 7475cc7b61..f35b4c4d27 100644 --- a/firmware/export/pp5020.h +++ b/firmware/export/pp5020.h @@ -131,6 +131,11 @@ #define DEV_IDE0 0x2000000 #define DEV_LCD 0x4000000 +/* clock control */ +#define CLOCK_SOURCE (*(volatile unsigned long *)(0x60006020)) +#define PLL_CONTROL (*(volatile unsigned long *)(0x60006034)) +#define PLL_STATUS (*(volatile unsigned long *)(0x6000603c)) + /* Processors Control */ #define CPU_CTL (*(volatile unsigned long *)(0x60007000)) #define COP_CTL (*(volatile unsigned long *)(0x60007004)) -- cgit v1.2.3