From e541c98a7e19f22ab62a0adb370ea9f4c922e666 Mon Sep 17 00:00:00 2001 From: Fred Bauer Date: Wed, 29 Dec 2010 16:07:15 +0000 Subject: revert r28834 because it causes problems with uSD git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28925 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/as3525/clock-target.h | 15 +++-------- firmware/target/arm/as3525/debug-as3525.c | 11 +++----- firmware/target/arm/as3525/sd-as3525.c | 42 +++++------------------------- firmware/target/arm/as3525/system-as3525.c | 42 ++---------------------------- 4 files changed, 16 insertions(+), 94 deletions(-) diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 135164b25b..97d6edb3d1 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h @@ -114,19 +114,17 @@ /* *5/8 = 240MHz 120, 80, 60, 48, 40 */ //#define AS3525_PLLA_SETTING 0x2630 -#define AS3525_FCLK_PREDIV 2 /* div = (8-n)/8 Enter manually & postdiv will be calculated*/ +#define AS3525_FCLK_PREDIV 0 /* div = (8-n)/8 Enter manually & postdiv will be calculated*/ /* 0 gives you the PLLA 1st line choices, 1 the 2nd line etc. */ -#define AS3525_FCLK_FREQ 186000000 /* Boosted FCLK frequency - over 200MHz */ - /* requires CVDDp bumped to 1.2V */ -#define AS3525_DRAM_FREQ 31000000 /* Initial DRAM frequency */ -#define AS3525_DRAM_FREQ_BOOSTED 62000000 +#define AS3525_FCLK_FREQ 248000000 /* Boosted FCLK frequency */ +#define AS3525_DRAM_FREQ 62000000 /* Initial DRAM frequency */ /* AS3525_PCLK_FREQ != AS3525_DRAM_FREQ/1 will boot to white lcd screen */ #endif /* CONFIG_CPU == AS3525v2 */ #define AS3525_PCLK_FREQ (AS3525_DRAM_FREQ/1) /* PCLK divided from DRAM freq */ -#define AS3525_PCLK_FREQ_BOOSTED (AS3525_DRAM_FREQ_BOOSTED/1) + #define AS3525_DBOP_FREQ (AS3525_PCLK_FREQ/1) /* DBOP divided from PCLK freq */ /** ****************************************************************************/ @@ -171,9 +169,6 @@ /*unable to use AS3525_PCLK_DIV1 != 0 successfuly so far*/ #define AS3525_PCLK_DIV1 (CLK_DIV(AS3525_DRAM_FREQ, AS3525_PCLK_FREQ) - 1)/* div = 1/(n+1)*/ #define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_PLLA_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/ -#define AS3525_PCLK_DIV1_BOOSTED (CLK_DIV(AS3525_DRAM_FREQ_BOOSTED, AS3525_PCLK_FREQ_BOOSTED) - 1) -#define AS3525_PCLK_DIV0_BOOSTED (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ_BOOSTED) - 1) - #else #define AS3525_PCLK_SEL AS3525_CLK_FCLK @@ -184,10 +179,8 @@ /* PCLK as Source */ #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/ #define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ) - #define AS3525_I2C_PRESCALER_BOOSTED CLK_DIV(AS3525_PCLK_FREQ_BOOSTED, AS3525_I2C_FREQ) #define AS3525_I2C_FREQ 400000 #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) - #define AS3525_SD_IDENT_DIV_BOOSTED ((CLK_DIV(AS3525_PCLK_FREQ_BOOSTED, AS3525_SD_IDENT_FREQ) / 2) - 1) #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ #define AS3525_SSP_PRESCALER ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ) + 1) & ~1) /* must be an even number */ #define AS3525_SSP_FREQ 12000000 diff --git a/firmware/target/arm/as3525/debug-as3525.c b/firmware/target/arm/as3525/debug-as3525.c index 9950ccd9c6..513295edcb 100644 --- a/firmware/target/arm/as3525/debug-as3525.c +++ b/firmware/target/arm/as3525/debug-as3525.c @@ -182,12 +182,7 @@ static int calc_freq(int clk) return 0; } case CLK_I2C: -#if CONFIG_CPU == AS3525 - if (cpu_frequency == CPUFREQ_MAX) - return calc_freq(CLK_PCLK)/AS3525_I2C_PRESCALER_BOOSTED; - else -#endif - return calc_freq(CLK_PCLK)/AS3525_I2C_PRESCALER; + return calc_freq(CLK_PCLK)/AS3525_I2C_PRESCALER; case CLK_I2SI: switch((CGU_AUDIO>>12) & 3) { case 0: @@ -223,7 +218,7 @@ static int calc_freq(int clk) case CLK_SD_MCLK_MSD: if(!(MCI_SD & (1<<8))) return 0; - else if(MCI_SD & (1<<10)) /* bypass */ + else if(MCI_SD & (1<<10)) return calc_freq(CLK_PCLK); else return calc_freq(CLK_PCLK)/(((MCI_SD & 0xff)+1)*2); @@ -352,7 +347,7 @@ bool __dbg_hw_info(void) calc_freq(CLK_SD_MCLK_NAND)/1000000); #ifdef HAVE_MULTIDRIVE lcd_putsf(0, line++, "uSD :%3dMHz %3dMHz", - ((calc_freq(CLK_PCLK)/ 1000000) / + ((AS3525_PCLK_FREQ/ 1000000) / ((last_sd & MCI_CLOCK_BYPASS) ? 1: (((last_sd & 0xff) + 1) * 2))), calc_freq(CLK_SD_MCLK_MSD)/1000000); #endif diff --git a/firmware/target/arm/as3525/sd-as3525.c b/firmware/target/arm/as3525/sd-as3525.c index 6f11145ee6..0dc29c8aa5 100644 --- a/firmware/target/arm/as3525/sd-as3525.c +++ b/firmware/target/arm/as3525/sd-as3525.c @@ -116,8 +116,9 @@ static void init_pl180_controller(const int drive); static tCardInfo card_info[NUM_DRIVES]; /* maximum timeouts recommanded in the SD Specification v2.00 */ -#define SD_MAX_READ_TIMEOUT ((AS3525_PCLK_FREQ*(cpu_frequency==CPUFREQ_MAX?2:1)) / 1000 * 100) /* 100 ms */ -#define SD_MAX_WRITE_TIMEOUT ((AS3525_PCLK_FREQ*(cpu_frequency==CPUFREQ_MAX?2:1)) / 1000 * 250) /* 250 ms */ +#define SD_MAX_READ_TIMEOUT ((AS3525_PCLK_FREQ) / 1000 * 100) /* 100 ms */ +#define SD_MAX_WRITE_TIMEOUT ((AS3525_PCLK_FREQ) / 1000 * 250) /* 250 ms */ + /* for compatibility */ static long last_disk_activity = -1; @@ -139,8 +140,6 @@ static struct wakeup transfer_completion_signal; static volatile unsigned int transfer_error[NUM_VOLUMES]; #define PL180_MAX_TRANSFER_ERRORS 10 -extern long cpu_frequency; - #define UNALIGNED_NUM_SECTORS 10 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32))); /* align on cache line size */ static unsigned char *uncached_buffer = AS3525_UNCACHED_ADDR(&aligned_buffer[0]); @@ -284,7 +283,7 @@ static bool send_cmd(const int drive, const int cmd, const int arg, #define MCI_HALFSPEED (MCI_CLOCK_ENABLE) /* MCLK/2 */ #define MCI_QUARTERSPEED (MCI_CLOCK_ENABLE | 1) /* MCLK/4 */ #define MCI_IDENTSPEED (MCI_CLOCK_ENABLE | AS3525_SD_IDENT_DIV) /* IDENT */ -#define MCI_IDENTSPEED_BOOSTED (MCI_CLOCK_ENABLE | AS3525_SD_IDENT_DIV_BOOSTED) + static int sd_init_card(const int drive) { unsigned long response; @@ -294,10 +293,7 @@ static int sd_init_card(const int drive) card_info[drive].rca = 0; /* MCLCK on and set to 400kHz ident frequency */ - if (cpu_frequency == CPUFREQ_MAX) - MCI_CLOCK(drive) = MCI_IDENTSPEED_BOOSTED; - else - MCI_CLOCK(drive) = MCI_IDENTSPEED; + MCI_CLOCK(drive) = MCI_IDENTSPEED; /* 100 - 400kHz clock required for Identification Mode */ /* Start of Card Identification Mode ************************************/ @@ -379,12 +375,8 @@ static int sd_init_card(const int drive) MCI_CLOCK(drive) = MCI_HALFSPEED; /* MCICLK = IDE_CLK/2 = 25 MHz */ #if defined(HAVE_MULTIDRIVE) else - { /* PCLK = 31Mhz (62 boosted) MCI = 31Mhz(hs) or 15.5 */ - if (cpu_frequency == CPUFREQ_MAX ) - MCI_CLOCK(drive) = (hs_card ? MCI_HALFSPEED : MCI_QUARTERSPEED); - else - MCI_CLOCK(drive) = (hs_card ? MCI_FULLSPEED : MCI_HALFSPEED); - } + /* MCICLK = PCLK/2 = 31MHz(HS) or PCLK/4 = 15.5 Mhz (STD)*/ + MCI_CLOCK(drive) = (hs_card ? MCI_HALFSPEED : MCI_QUARTERSPEED); #endif /* CMD7 w/rca: Select card to put it in TRAN state */ @@ -531,26 +523,6 @@ static void sd_thread(void) } } -#ifdef HAVE_MULTIDRIVE -void sd_set_boosted_divider(void) -{ - if ( !sd_enabled ) - return; - /* 62Mhz/2 - 62/4 */ - MCI_CLOCK(SD_SLOT_AS3525) = (hs_card ? - MCI_HALFSPEED : MCI_QUARTERSPEED); -} - -void sd_set_unboosted_divider(void) -{ - if ( !sd_enabled ) - return; - /* 31Mhz/1 - 31/2 */ - MCI_CLOCK(SD_SLOT_AS3525) = (hs_card ? - MCI_FULLSPEED : MCI_HALFSPEED); -} -#endif - static void init_pl180_controller(const int drive) { MCI_COMMAND(drive) = MCI_DATA_CTRL(drive) = 0; diff --git a/firmware/target/arm/as3525/system-as3525.c b/firmware/target/arm/as3525/system-as3525.c index 2c4543fa33..d8059715d0 100644 --- a/firmware/target/arm/as3525/system-as3525.c +++ b/firmware/target/arm/as3525/system-as3525.c @@ -33,12 +33,6 @@ #include "backlight-target.h" #include "lcd.h" -/* FIXME */ -#define I2C2_CPSR0 *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x1C)) -#define I2C2_CPSR1 *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x20)) -extern void sd_set_boosted_divider(void); -extern void sd_set_unboosted_divider(void); - #define default_interrupt(name) \ extern __attribute__((weak,alias("UIRQ"))) void name (void) @@ -292,12 +286,7 @@ void system_init(void) #endif /* Initialize power management settings */ -#if CONFIG_CPU == AS3525 - ascodec_write(AS3514_CVDD_DCDC3, AS314_CP_DCDC3_SETTING|CVDD_1_10); -#else ascodec_write(AS3514_CVDD_DCDC3, AS314_CP_DCDC3_SETTING); -#endif - #if CONFIG_TUNER fmradio_i2c_init(); #endif @@ -365,9 +354,7 @@ void set_cpu_frequency(long frequency) { if(frequency == CPUFREQ_MAX) { -#if defined(HAVE_ADJUSTABLE_CPU_VOLTAGE) && (CPUFREQ_MAX > 200000000) - /* This doesn't work anymore. It was written before ascodec - was switched to use interrupts */ +#ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE /* Increasing frequency so boost voltage before change */ ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_20)); @@ -387,35 +374,10 @@ void set_cpu_frequency(long frequency) "mcr p15, 0, r0, c1, c0 \n" : : : "r0" ); -#ifdef HAVE_MULTIDRIVE - /* Set uSD frequency */ - sd_set_boosted_divider(); -#endif - /* Set I2C frequency */ - I2C2_CPSR0 = AS3525_I2C_PRESCALER_BOOSTED & 0xFF; /* 8 lsb */ - I2C2_CPSR1 = (AS3525_I2C_PRESCALER_BOOSTED >> 8) & 0x3; /* 2 msb */ - /* Set PCLK frequency */ - CGU_PERI = ((CGU_PERI & ~0x7F) | /* reset divider & clksel bits */ - (AS3525_PCLK_DIV0_BOOSTED << 2) | - (AS3525_PCLK_DIV1_BOOSTED << 6) | - AS3525_PCLK_SEL); cpu_frequency = CPUFREQ_MAX; } else { - /* Set I2C frequency */ - I2C2_CPSR0 = AS3525_I2C_PRESCALER & 0xFF; /* 8 lsb */ - I2C2_CPSR1 = (AS3525_I2C_PRESCALER >> 8) & 0x3; /* 2 msb */ - /* Set PCLK frequency */ - CGU_PERI = ((CGU_PERI & ~0x7F) | /* reset divider & clksel bits */ - (AS3525_PCLK_DIV0 << 2) | - (AS3525_PCLK_DIV1 << 6) | - AS3525_PCLK_SEL); - -#ifdef HAVE_MULTIDRIVE - /* Set uSD frequency */ - sd_set_unboosted_divider(); -#endif asm volatile( "mrc p15, 0, r0, c1, c0 \n" "bic r0, r0, #3<<30 \n" /* fastbus clocking */ @@ -425,7 +387,7 @@ void set_cpu_frequency(long frequency) /* FCLK is unused so put it to the lowest freq we can */ CGU_PROC = ((0xf << 4) | (0x3 << 2) | AS3525_CLK_MAIN); -#if defined(HAVE_ADJUSTABLE_CPU_VOLTAGE) && (CPUFREQ_MAX > 200000000) +#ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE /* Decreasing frequency so reduce voltage after change */ ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_10)); #endif /* HAVE_ADJUSTABLE_CPU_VOLTAGE */ -- cgit v1.2.3