From 5a9a2b7bc4e1e2a97ec731524bb7e127f5c8cacf Mon Sep 17 00:00:00 2001
From: Karl Kurbjun <kkurbjun@gmail.com>
Date: Tue, 23 Oct 2007 03:29:15 +0000
Subject: Unify the Gigabeat F/X and M:Robe MMU code while enabling it for the
 M:Robe

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15275 a1c6a512-1295-4272-9138-f99709370657
---
 bootloader/gigabeat.c                              |   2 +-
 firmware/SOURCES                                   |   6 +-
 firmware/app.lds                                   |   2 +-
 firmware/export/dm320.h                            |   5 +-
 firmware/export/s3c2440.h                          |   2 +-
 firmware/target/arm/mmu-arm.c                      | 226 ++++++++++++++++++++
 firmware/target/arm/mmu-arm.h                      |  43 ++++
 .../target/arm/s3c2440/gigabeat-fx/ata-meg-fx.c    |   1 -
 .../target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.c    | 235 ---------------------
 .../target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.h    |  35 ---
 .../target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c    |   1 -
 .../target/arm/s3c2440/gigabeat-fx/system-meg-fx.c |  16 +-
 .../target/arm/s3c2440/gigabeat-fx/system-target.h |   2 +-
 firmware/target/arm/tms320dm320/crt0.S             |  18 +-
 .../target/arm/tms320dm320/mrobe-500/lcd-mr500.c   |   1 -
 firmware/target/arm/tms320dm320/system-dm320.c     |  15 +-
 firmware/target/arm/tms320dm320/uart-dm320.c       |   3 +-
 17 files changed, 319 insertions(+), 294 deletions(-)
 create mode 100644 firmware/target/arm/mmu-arm.c
 create mode 100644 firmware/target/arm/mmu-arm.h
 delete mode 100644 firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.c
 delete mode 100644 firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.h

diff --git a/bootloader/gigabeat.c b/bootloader/gigabeat.c
index 704548b65a..8860b42c43 100644
--- a/bootloader/gigabeat.c
+++ b/bootloader/gigabeat.c
@@ -41,7 +41,7 @@
 #include "common.h"
 #include "rbunicode.h"
 #include "usb.h"
-#include "mmu-meg-fx.h"
+#include "mmu-arm.h"
 
 #include <stdarg.h>
 
diff --git a/firmware/SOURCES b/firmware/SOURCES
index a30e57f6d1..9e501b661a 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -576,6 +576,7 @@ target/arm/usb-fw-pp502x.c
 #ifdef GIGABEAT_F
 #ifndef SIMULATOR
 target/arm/lcd-as-memframe.S
+target/arm/mmu-arm.c
 target/arm/s3c2440/gigabeat-fx/adc-meg-fx.c
 target/arm/s3c2440/gigabeat-fx/ata-meg-fx.c
 target/arm/s3c2440/gigabeat-fx/backlight-meg-fx.c
@@ -591,7 +592,6 @@ target/arm/s3c2440/gigabeat-fx/usb-meg-fx.c
 target/arm/s3c2440/gigabeat-fx/wmcodec-meg-fx.c
 target/arm/s3c2440/gigabeat-fx/dma_start.c
 target/arm/s3c2440/gigabeat-fx/system-meg-fx.c
-target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.c
 #ifndef BOOTLOADER
 target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c
 #endif
@@ -626,6 +626,7 @@ target/arm/imx31/gigabeat-s/pcm-imx31.c
 #ifdef MROBE_500
 #ifndef SIMULATOR
 target/arm/lcd-as-memframe.S
+target/arm/mmu-arm.c
 target/arm/tms320dm320/mrobe-500/adc-mr500.c
 target/arm/tms320dm320/mrobe-500/ata-mr500.c
 target/arm/tms320dm320/mrobe-500/backlight-mr500.c
@@ -645,9 +646,6 @@ target/arm/tms320dm320/spi-dm320.c
 target/arm/tms320dm320/system-dm320.c
 target/arm/tms320dm320/timer-dm320.c
 target/arm/tms320dm320/uart-dm320.c
-#ifndef BOOTLOADER
-
-#endif
 #endif /* SIMULATOR */
 #endif /* MROBE_500 */
 
diff --git a/firmware/app.lds b/firmware/app.lds
index a95d871def..f77d0a1c22 100644
--- a/firmware/app.lds
+++ b/firmware/app.lds
@@ -35,7 +35,7 @@ INPUT(target/sh/crt0.o)
 #define DRAMSIZE (MEMORYSIZE * 0x100000) - 0x100 - PLUGINSIZE - STUBOFFSET - CODECSIZE - LCD_BUFFER_SIZE - TTB_SIZE
 #elif CONFIG_CPU==DM320
 #include "dm320.h"
-#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - STUBOFFSET - CODECSIZE - LCD_BUFFER_SIZE
+#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - STUBOFFSET - CODECSIZE - LCD_BUFFER_SIZE - TTB_SIZE
 #else
 #define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - STUBOFFSET - CODECSIZE
 #endif
diff --git a/firmware/export/dm320.h b/firmware/export/dm320.h
index 0c84444a66..4dfc55dcd3 100644
--- a/firmware/export/dm320.h
+++ b/firmware/export/dm320.h
@@ -25,7 +25,10 @@
 #define __DM320_H__
 
 #define LCD_BUFFER_SIZE (640*480*4)
-#define FRAME ((short *) (0x4900000-LCD_BUFFER_SIZE)) /* Put the buffer at the end of mem */
+#define TTB_SIZE (0x4000)
+/* must be 16Kb (0x4000) aligned */
+#define TTB_BASE   ((unsigned int *)(0x04900000 - TTB_SIZE)) /* End of memory */
+#define FRAME   ((short *) (TTB_BASE - LCD_BUFFER_SIZE))  /* Right before TTB */
 
 #define PHY_IO_BASE 0x00030000
 #define DM320_REG(addr) (*(volatile unsigned short *)(PHY_IO_BASE + (addr)))
diff --git a/firmware/export/s3c2440.h b/firmware/export/s3c2440.h
index 1eaa77bf80..e43dd7688d 100644
--- a/firmware/export/s3c2440.h
+++ b/firmware/export/s3c2440.h
@@ -229,7 +229,7 @@
 #define TTB_SIZE (0x4000)
 /*#define FRAME   ( (short *) 0x31E00000  ) */ /* LCD Frame buffer - Firmware Address */
 /* must be 16Kb (0x4000) aligned */
-#define TTB_BASE   (0x30000000 + (32*1024*1024) - TTB_SIZE) /* End of memory */
+#define TTB_BASE   ((unsigned int *)(0x30000000 + (32*1024*1024) - TTB_SIZE)) /* End of memory */
 #define FRAME   ((short *) (TTB_BASE - LCD_BUFFER_SIZE))  /* Right before TTB */
 /* NAND Flash */
 
diff --git a/firmware/target/arm/mmu-arm.c b/firmware/target/arm/mmu-arm.c
new file mode 100644
index 0000000000..db7f5e59cd
--- /dev/null
+++ b/firmware/target/arm/mmu-arm.c
@@ -0,0 +1,226 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006,2007 by Greg White
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "cpu.h"
+#include "mmu-arm.h"
+#include "panic.h"
+
+#define SECTION_ADDRESS_MASK (-1 << 20)
+#define MB (1 << 20)
+
+void ttb_init(void) {
+    unsigned int* ttbPtr;
+
+    /* must be 16Kb (0x4000) aligned - clear out the TTB */
+    for (ttbPtr=TTB_BASE; ttbPtr<(TTB_SIZE+TTB_BASE); ttbPtr++)
+    {
+        *ttbPtr = 0;
+    }
+
+    /* Set the TTB base address */
+    asm volatile("mcr p15, 0, %0, c2, c0, 0" : : "r" (TTB_BASE));
+
+    /* Set all domains to manager status */
+    asm volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (0xFFFFFFFF));
+}
+
+void map_section(unsigned int pa, unsigned int va, int mb, int cache_flags) {
+    unsigned int* ttbPtr;
+    int i;
+    int section_no;
+
+    section_no = va >> 20; /* sections are 1Mb size */
+    ttbPtr = TTB_BASE + section_no;
+    pa &= SECTION_ADDRESS_MASK; /* align to 1Mb */
+    for(i=0; i<mb; i++, pa += MB) {
+        *(ttbPtr + i) =
+            pa |
+            1 << 10 |    /* superuser - r/w, user - no access */
+            0 << 5 |    /* domain 0th */
+            1 << 4 |    /* should be "1" */
+            cache_flags |
+            1 << 1;    /* Section signature */
+    }
+}
+
+void enable_mmu(void) {
+    int regread;
+
+    asm volatile(
+        "MRC p15, 0, %r0, c1, c0, 0\n"  /* Read reg1, control register */
+    : /* outputs */
+        "=r"(regread)
+    : /* inputs */
+    : /* clobbers */
+        "r0"
+    );
+
+    if ( !(regread & 0x04) || !(regread & 0x00001000) ) /* Was the ICache or DCache Enabled? */
+        clean_dcache(); /* If so we need to clean the DCache before invalidating below */
+
+    asm volatile("mov r0, #0\n"
+        "mcr p15, 0, r0, c8, c7, 0\n" /* invalidate TLB */
+
+        "mcr p15, 0, r0, c7, c7,0\n" /* invalidate both icache and dcache */
+
+        "mrc p15, 0, r0, c1, c0, 0\n"
+        "orr r0, r0, #1<<0\n" /* enable mmu bit, icache and dcache */
+        "orr r0, r0, #1<<2\n" /* enable dcache */
+        "orr r0, r0, #1<<12\n" /* enable icache */
+        "mcr p15, 0, r0, c1, c0, 0" : : : "r0");
+    asm volatile("nop \n nop \n nop \n nop");
+}
+
+/* Invalidate DCache for this range  */
+/* Will do write back */
+void invalidate_dcache_range(const void *base, unsigned int size) {
+    unsigned int addr = (((int) base) & ~31);    /* Align start to cache line*/
+    unsigned int end = ((addr+size) & ~31)+64;  /* Align end to cache line, pad */
+    asm volatile(
+"inv_start: \n"
+    "mcr p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
+    "add %0, %0, #32 \n"
+    "cmp %0, %1 \n"
+    "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
+    "addne %0, %0, #32 \n"
+    "cmpne %0, %1 \n"
+    "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
+    "addne %0, %0, #32 \n"
+    "cmpne %0, %1 \n"
+    "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
+    "addne %0, %0, #32 \n"
+    "cmpne %0, %1 \n"
+    "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
+    "addne %0, %0, #32 \n"
+    "cmpne %0, %1 \n"
+    "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
+    "addne %0, %0, #32 \n"
+    "cmpne %0, %1 \n"
+    "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
+    "addne %0, %0, #32 \n"
+    "cmpne %0, %1 \n"
+    "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
+    "addne %0, %0, #32 \n"
+    "cmpne %0, %1 \n"
+    "bne inv_start \n"
+    "mov %0, #0\n"
+    "mcr p15,0,%0,c7,c10,4\n"    /* Drain write buffer */
+        : : "r" (addr), "r" (end));
+}
+
+/* clean DCache for this range  */
+/* forces DCache writeback for the specified range */
+void clean_dcache_range(const void *base, unsigned int size) {
+    unsigned int addr = (int) base;
+    unsigned int end = addr+size+32;
+    asm      volatile(
+    "bic %0, %0, #31 \n"
+"clean_start: \n"
+    "mcr p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
+    "add %0, %0, #32 \n"
+    "cmp %0, %1 \n"
+    "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
+    "addlo %0, %0, #32 \n"
+    "cmplo %0, %1 \n"
+    "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
+    "addlo %0, %0, #32 \n"
+    "cmplo %0, %1 \n"
+    "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
+    "addlo %0, %0, #32 \n"
+    "cmplo %0, %1 \n"
+    "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
+    "addlo %0, %0, #32 \n"
+    "cmplo %0, %1 \n"
+    "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
+    "addlo %0, %0, #32 \n"
+    "cmplo %0, %1 \n"
+    "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
+    "addlo %0, %0, #32 \n"
+    "cmplo %0, %1 \n"
+    "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
+    "addlo %0, %0, #32 \n"
+    "cmplo %0, %1 \n"
+    "blo clean_start \n"
+    "mov %0, #0\n"
+    "mcr p15,0,%0,c7,c10,4 \n"    /* Drain write buffer */
+        : : "r" (addr), "r" (end));
+}
+
+/* Dump DCache for this range  */
+/* Will *NOT* do write back */
+void dump_dcache_range(const void *base, unsigned int size) {
+    unsigned int addr = (int) base;
+    unsigned int end = addr+size;
+    asm volatile(
+    "tst %0, #31 \n"                    /* Check to see if low five bits are set */
+    "bic %0, %0, #31 \n"                /* Clear them */
+    "mcrne p15, 0, %0, c7, c14, 1 \n"     /* Clean and invalidate this line, if those bits were set */
+    "add %0, %0, #32 \n"                /* Move to the next cache line */
+    "tst %1, #31 \n"                    /* Check last line for bits set */
+    "bic %1, %1, #31 \n"                /* Clear those bits */
+    "mcrne p15, 0, %1, c7, c14, 1 \n"     /* Clean and invalidate this line, if not cache aligned */
+"dump_start: \n"
+    "mcr p15, 0, %0, c7, c6, 1 \n"         /* Invalidate this line */
+    "add %0, %0, #32 \n"                /* Next cache line */
+    "cmp %0, %1 \n"
+    "bne dump_start \n"
+"dump_end: \n"
+    "mcr p15,0,%0,c7,c10,4 \n"    /* Drain write buffer */
+        : : "r" (addr), "r" (end));
+}
+/* Cleans entire DCache */
+void clean_dcache(void)
+{
+    unsigned int index, addr;
+
+    for(index = 0; index <= 63; index++) {
+        addr = (0 << 5) | (index << 26);
+        asm volatile(
+            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
+            : : "r" (addr));
+        addr = (1 << 5) | (index << 26);
+        asm volatile(
+            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
+            : : "r" (addr));
+        addr = (2 << 5) | (index << 26);
+        asm volatile(
+            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
+            : : "r" (addr));
+        addr = (3 << 5) | (index << 26);
+        asm volatile(
+            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
+            : : "r" (addr));
+        addr = (4 << 5) | (index << 26);
+        asm volatile(
+            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
+            : : "r" (addr));
+        addr = (5 << 5) | (index << 26);
+        asm volatile(
+            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
+            : : "r" (addr));
+        addr = (6 << 5) | (index << 26);
+        asm volatile(
+            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
+            : : "r" (addr));
+        addr = (7 << 5) | (index << 26);
+        asm volatile(
+            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
+            : : "r" (addr));
+    }
+}
+
diff --git a/firmware/target/arm/mmu-arm.h b/firmware/target/arm/mmu-arm.h
new file mode 100644
index 0000000000..b744305dbd
--- /dev/null
+++ b/firmware/target/arm/mmu-arm.h
@@ -0,0 +1,43 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006,2007 by Greg White
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#define CACHE_ALL (1 << 3 | 1 << 2 )
+#define CACHE_NONE 0
+#define BUFFERED (1 << 2)
+
+void ttb_init(void);
+void enable_mmu(void);
+void map_section(unsigned int pa, unsigned int va, int mb, int cache_flags);
+
+/* Invalidate DCache for this range  */
+/* Will do write back */
+void invalidate_dcache_range(const void *base, unsigned int size);
+
+/* clean DCache for this range  */
+/* forces DCache writeback for the specified range */
+void clean_dcache_range(const void *base, unsigned int size);
+
+/* Dump DCache for this range  */
+/* Will *NOT* do write back */
+void dump_dcache_range(const void *base, unsigned int size);
+
+/* Cleans entire DCache */
+void clean_dcache(void);
+
+void memory_init(void);
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/ata-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/ata-meg-fx.c
index d33bcaaf6e..1f5c5c8fbe 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/ata-meg-fx.c
+++ b/firmware/target/arm/s3c2440/gigabeat-fx/ata-meg-fx.c
@@ -25,7 +25,6 @@
 #include "panic.h"
 #include "pcf50606.h"
 #include "ata-target.h"
-#include "mmu-meg-fx.h"
 #include "backlight-target.h"
 
 /* ARESET on C7C68300 and RESET on ATA interface (Active Low) */
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.c
deleted file mode 100644
index c47c1330bc..0000000000
--- a/firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.c
+++ /dev/null
@@ -1,235 +0,0 @@
-#include <string.h>
-#include "s3c2440.h"
-#include "mmu-meg-fx.h"
-#include "panic.h"
-
-static void enable_mmu(void);
-static void set_ttb(void);
-static void set_page_tables(void);
-static void map_section(unsigned int pa, unsigned int va, int mb, int cache_flags);
-
-#define SECTION_ADDRESS_MASK (-1 << 20)
-#define CACHE_ALL (1 << 3 | 1 << 2 )
-#define CACHE_NONE 0
-#define BUFFERED (1 << 2)
-#define MB (1 << 20)
-
-void memory_init(void) {
-    set_ttb();
-    set_page_tables();
-    enable_mmu();
-}
-
-unsigned int* ttb_base = (unsigned int *) TTB_BASE;
-const int ttb_size = 4096;
-
-void set_ttb() {
-    int i;
-    int* ttbPtr;
-    int domain_access;
-
-    /* must be 16Kb (0x4000) aligned */
-    ttb_base = (int*) TTB_BASE;
-    for (i=0; i<ttb_size; i++,ttbPtr++)
-    ttbPtr = 0;
-    asm volatile("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttb_base));
-
-    /* set domain D0 to "client" permission access */
-
-    domain_access = 3;
-    asm volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (domain_access));
-
-}
-
-void set_page_tables() {
-
-    map_section(0, 0, 0x1000, CACHE_NONE); /* map every memory region to itself */
-    map_section(0x30000000, 0, 32, CACHE_ALL); /* map RAM to 0 and enable caching for it */
-    map_section((int)FRAME, (int)FRAME, 1, BUFFERED); /* enable buffered writing for the framebuffer */
-}
-
-void map_section(unsigned int pa, unsigned int va, int mb, int cache_flags) {
-    unsigned int* ttbPtr;
-    int i;
-    int section_no;
-
-    section_no = va >> 20; /* sections are 1Mb size */
-    ttbPtr = ttb_base + section_no;
-    pa &= SECTION_ADDRESS_MASK; /* align to 1Mb */
-    for(i=0; i<mb; i++, pa += MB) {
-    *(ttbPtr + i) =
-        pa |
-        1 << 10 |    /* superuser - r/w, user - no access */
-        0 << 5 |    /* domain 0th */
-        1 << 4 |    /* should be "1" */
-        cache_flags |
-        1 << 1;    /* Section signature */
-    }
-}
-
-static void enable_mmu(void) {
-    int regread;
-
-    asm volatile(
-        "MRC p15, 0, %r0, c1, c0, 0\n"  /* Read reg1, control register */
-    : /* outputs */
-        "=r"(regread)
-    : /* inputs */
-    : /* clobbers */
-        "r0"
-    );
-
-    if ( !(regread & 0x04) || !(regread & 0x00001000) ) /* Was the ICache or DCache Enabled? */
-        clean_dcache(); /* If so we need to clean the DCache before invalidating below */
-
-    asm volatile("mov r0, #0\n"
-        "mcr p15, 0, r0, c8, c7, 0\n" /* invalidate TLB */
-
-        "mcr p15, 0, r0, c7, c7,0\n" /* invalidate both icache and dcache */
-
-        "mrc p15, 0, r0, c1, c0, 0\n"
-        "orr r0, r0, #1<<0\n" /* enable mmu bit, icache and dcache */
-        "orr r0, r0, #1<<2\n" /* enable dcache */
-        "orr r0, r0, #1<<12\n" /* enable icache */
-        "mcr p15, 0, r0, c1, c0, 0" : : : "r0");
-    asm volatile("nop \n nop \n nop \n nop");
-}
-
-/* Invalidate DCache for this range  */
-/* Will do write back */
-void invalidate_dcache_range(const void *base, unsigned int size) {
-    unsigned int addr = (((int) base) & ~31);    /* Align start to cache line*/
-    unsigned int end = ((addr+size) & ~31)+64;  /* Align end to cache line, pad */
-    asm volatile(
-"inv_start: \n"
-    "mcr p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
-    "add %0, %0, #32 \n"
-    "cmp %0, %1 \n"
-    "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
-    "addne %0, %0, #32 \n"
-    "cmpne %0, %1 \n"
-    "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
-    "addne %0, %0, #32 \n"
-    "cmpne %0, %1 \n"
-    "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
-    "addne %0, %0, #32 \n"
-    "cmpne %0, %1 \n"
-    "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
-    "addne %0, %0, #32 \n"
-    "cmpne %0, %1 \n"
-    "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
-    "addne %0, %0, #32 \n"
-    "cmpne %0, %1 \n"
-    "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
-    "addne %0, %0, #32 \n"
-    "cmpne %0, %1 \n"
-    "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
-    "addne %0, %0, #32 \n"
-    "cmpne %0, %1 \n"
-    "bne inv_start \n"
-    "mov %0, #0\n"
-    "mcr p15,0,%0,c7,c10,4\n"    /* Drain write buffer */
-        : : "r" (addr), "r" (end));
-}
-
-/* clean DCache for this range  */
-/* forces DCache writeback for the specified range */
-void clean_dcache_range(const void *base, unsigned int size) {
-    unsigned int addr = (int) base;
-    unsigned int end = addr+size+32;
-    asm      volatile(
-    "bic %0, %0, #31 \n"
-"clean_start: \n"
-    "mcr p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
-    "add %0, %0, #32 \n"
-    "cmp %0, %1 \n"
-    "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
-    "addlo %0, %0, #32 \n"
-    "cmplo %0, %1 \n"
-    "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
-    "addlo %0, %0, #32 \n"
-    "cmplo %0, %1 \n"
-    "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
-    "addlo %0, %0, #32 \n"
-    "cmplo %0, %1 \n"
-    "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
-    "addlo %0, %0, #32 \n"
-    "cmplo %0, %1 \n"
-    "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
-    "addlo %0, %0, #32 \n"
-    "cmplo %0, %1 \n"
-    "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
-    "addlo %0, %0, #32 \n"
-    "cmplo %0, %1 \n"
-    "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
-    "addlo %0, %0, #32 \n"
-    "cmplo %0, %1 \n"
-    "blo clean_start \n"
-    "mov %0, #0\n"
-    "mcr p15,0,%0,c7,c10,4 \n"    /* Drain write buffer */
-        : : "r" (addr), "r" (end));
-}
-
-/* Dump DCache for this range  */
-/* Will *NOT* do write back */
-void dump_dcache_range(const void *base, unsigned int size) {
-    unsigned int addr = (int) base;
-    unsigned int end = addr+size;
-    asm volatile(
-    "tst %0, #31 \n"                    /* Check to see if low five bits are set */
-    "bic %0, %0, #31 \n"                /* Clear them */
-    "mcrne p15, 0, %0, c7, c14, 1 \n"     /* Clean and invalidate this line, if those bits were set */
-    "add %0, %0, #32 \n"                /* Move to the next cache line */
-    "tst %1, #31 \n"                    /* Check last line for bits set */
-    "bic %1, %1, #31 \n"                /* Clear those bits */
-    "mcrne p15, 0, %1, c7, c14, 1 \n"     /* Clean and invalidate this line, if not cache aligned */
-"dump_start: \n"
-    "mcr p15, 0, %0, c7, c6, 1 \n"         /* Invalidate this line */
-    "add %0, %0, #32 \n"                /* Next cache line */
-    "cmp %0, %1 \n"
-    "bne dump_start \n"
-"dump_end: \n"
-    "mcr p15,0,%0,c7,c10,4 \n"    /* Drain write buffer */
-        : : "r" (addr), "r" (end));
-}
-/* Cleans entire DCache */
-void clean_dcache(void)
-{
-    unsigned int index, addr;
-
-    for(index = 0; index <= 63; index++) {
-        addr = (0 << 5) | (index << 26);
-        asm volatile(
-            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
-            : : "r" (addr));
-        addr = (1 << 5) | (index << 26);
-        asm volatile(
-            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
-            : : "r" (addr));
-        addr = (2 << 5) | (index << 26);
-        asm volatile(
-            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
-            : : "r" (addr));
-        addr = (3 << 5) | (index << 26);
-        asm volatile(
-            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
-            : : "r" (addr));
-        addr = (4 << 5) | (index << 26);
-        asm volatile(
-            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
-            : : "r" (addr));
-        addr = (5 << 5) | (index << 26);
-        asm volatile(
-            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
-            : : "r" (addr));
-        addr = (6 << 5) | (index << 26);
-        asm volatile(
-            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
-            : : "r" (addr));
-        addr = (7 << 5) | (index << 26);
-        asm volatile(
-            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
-            : : "r" (addr));
-    }
-}
-
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.h b/firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.h
deleted file mode 100644
index 524978852d..0000000000
--- a/firmware/target/arm/s3c2440/gigabeat-fx/mmu-meg-fx.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * $Id$
- *
- * Copyright (C) 2006,2007 by Greg White
- *
- * All files in this archive are subject to the GNU General Public License.
- * See the file COPYING in the source tree root for full license agreement.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-
-/* Invalidate DCache for this range  */
-/* Will do write back */
-void invalidate_dcache_range(const void *base, unsigned int size);
-
-/* clean DCache for this range  */
-/* forces DCache writeback for the specified range */
-void clean_dcache_range(const void *base, unsigned int size);
-
-/* Dump DCache for this range  */
-/* Will *NOT* do write back */
-void dump_dcache_range(const void *base, unsigned int size);
-
-/* Cleans entire DCache */
-void clean_dcache(void);
-
-void memory_init(void);
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c
index a38b4e424e..7f25cb6a15 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c
+++ b/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c
@@ -23,7 +23,6 @@
 #include "audio.h"
 #include "sound.h"
 #include "file.h"
-#include "mmu-meg-fx.h"
 
 /* All exact rates for 16.9344MHz clock */
 #define GIGABEAT_11025HZ     (0x19 << 1)
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c
index 00cf626ab3..c7b1b77c9f 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c
+++ b/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c
@@ -1,7 +1,8 @@
 #include "kernel.h"
 #include "system.h"
 #include "panic.h"
-#include "mmu-meg-fx.h"
+#include "mmu-arm.h"
+#include "cpu.h"
 
 #define default_interrupt(name) \
   extern __attribute__((weak,alias("UIRQ"))) void name (void)
@@ -90,6 +91,19 @@ void system_reboot(void)
         ;
 }
 
+static void set_page_tables(void)
+{
+    map_section(0, 0, 0x1000, CACHE_NONE); /* map every memory region to itself */
+    map_section(0x30000000, 0, 32, CACHE_ALL); /* map RAM to 0 and enable caching for it */
+    map_section((int)FRAME, (int)FRAME, 1, BUFFERED); /* enable buffered writing for the framebuffer */
+}
+
+void memory_init(void) {
+    ttb_init();
+    set_page_tables();
+    enable_mmu();
+}
+
 void system_init(void)
 {
     /* Disable interrupts and set all to IRQ mode */
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h b/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h
index 215b5a4daa..2fab652596 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h
+++ b/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h
@@ -19,8 +19,8 @@
 #ifndef SYSTEM_TARGET_H
 #define SYSTEM_TARGET_H
 
-#include "mmu-meg-fx.h"
 #include "system-arm.h"
+#include "mmu-arm.h"
 
 #define CPUFREQ_DEFAULT 98784000
 #define CPUFREQ_NORMAL  98784000
diff --git a/firmware/target/arm/tms320dm320/crt0.S b/firmware/target/arm/tms320dm320/crt0.S
index 68c0d9e1c5..8c747f7a51 100755
--- a/firmware/target/arm/tms320dm320/crt0.S
+++ b/firmware/target/arm/tms320dm320/crt0.S
@@ -48,14 +48,19 @@ start:
     str    r0, [r1, #28]
 #endif
 
-    /* Disable high vectors (at 0xffff0000 instead of 0x00000000) */
-    mrc    p15, 0, r0, c1, c0
-    and    r0, r0, #~(1<<13)
-    mcr    p15, 0, r0, c1, c0
+    /* Disable data and instruction cache, high vectors (at 0xffff0000 instead of 0x00000000) */
+	mrc	p15, 0, r0, c1, c0, 0
+	/* clear bits 13, 9:8 (--VI --RS) */
+	bic	r0, r0, #0x00003300
+	/* clear bits 7, 2:0 (B--- -C-M) */
+	bic	r0, r0, #0x00000085
+	/* make sure bit 2 (A) Align is set */
+	orr	r0, r0, #0x00000002
+	mcr	p15, 0, r0, c1, c0, 0
 
 #if !defined(BOOTLOADER)
 
-#if 0//!defined(STUB)
+#if !defined(STUB)
     /* Zero out IBSS */
     ldr    r2, =_iedata
     ldr    r3, =_iend
@@ -64,8 +69,7 @@ start:
     cmp    r3, r2
     strhi  r4, [r2], #4
     bhi    1b
-#endif
-#if 1
+
     /* Copy the IRAM */
     ldr    r2, =_iramcopy
     ldr    r3, =_iramstart
diff --git a/firmware/target/arm/tms320dm320/mrobe-500/lcd-mr500.c b/firmware/target/arm/tms320dm320/mrobe-500/lcd-mr500.c
index 37286bffc4..bc1439762d 100644
--- a/firmware/target/arm/tms320dm320/mrobe-500/lcd-mr500.c
+++ b/firmware/target/arm/tms320dm320/mrobe-500/lcd-mr500.c
@@ -82,7 +82,6 @@ void lcd_init_device(void)
 void lcd_update_rect(int x, int y, int width, int height)
 {
     fb_data *dst, *src;
-    int yc;
 
     if (!lcd_on)
         return;
diff --git a/firmware/target/arm/tms320dm320/system-dm320.c b/firmware/target/arm/tms320dm320/system-dm320.c
index 8a50ba7f08..f3f8dcea26 100644
--- a/firmware/target/arm/tms320dm320/system-dm320.c
+++ b/firmware/target/arm/tms320dm320/system-dm320.c
@@ -16,7 +16,8 @@
  * KIND, either express or implied.
  *
  ****************************************************************************/
- 
+#include "cpu.h"
+#include "mmu-arm.h"
 #include "kernel.h"
 #include "system.h"
 #include "panic.h"
@@ -26,6 +27,9 @@
 #define default_interrupt(name) \
   extern __attribute__((weak,alias("UIRQ"))) void name (void)
 
+void irq_handler(void) __attribute__((interrupt ("IRQ"), naked));
+void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked));
+
 default_interrupt(TIMER0);
 default_interrupt(TIMER1);
 default_interrupt(TIMER2);
@@ -101,7 +105,6 @@ static void UIRQ(void)
     panicf("Unhandled IRQ %02X: %s", offset, irqname[offset]);
 }
 
-void irq_handler(void) __attribute__((interrupt ("IRQ"), naked));
 void irq_handler(void)
 {
     /*
@@ -116,7 +119,6 @@ void irq_handler(void)
                     "subs  pc, lr, #4           \n"); /* Return from FIQ */
 }
 
-void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked));
 void fiq_handler(void)
 {
     /*
@@ -179,6 +181,13 @@ void system_init(void)
     enable_interrupts();
     uart_init();
     spi_init();
+ 
+    /* MMU initialization (Starts data and instruction cache) */   
+    ttb_init();
+    map_section(0, 0, 0x1000, CACHE_NONE); /* Make sure everything is mapped on itself */
+    map_section(0x00900000, 0x00900000, 64, CACHE_ALL); /* Enable caching for RAM */
+    map_section((int)FRAME, (int)FRAME, 2, BUFFERED); /* enable buffered writing for the framebuffer */
+    enable_mmu();
 }
 
 int system_memory_guard(int newmode)
diff --git a/firmware/target/arm/tms320dm320/uart-dm320.c b/firmware/target/arm/tms320dm320/uart-dm320.c
index 6425b75960..5168cb11c6 100644
--- a/firmware/target/arm/tms320dm320/uart-dm320.c
+++ b/firmware/target/arm/tms320dm320/uart-dm320.c
@@ -24,7 +24,8 @@
 
 #define CONFIG_UART_BRSR    87
 #define MAX_UART_BUFFER     31
-unsigned char uart1buffer[MAX_UART_BUFFER];
+unsigned char uart1buffer[MAX_UART_BUFFER], uart1_send_buffer_ring[512];
+int uart1_send_count=0,uart1_send_point=0;
 int uart1read = 0, uart1write = 0, uart1count = 0;
 
 /*
-- 
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