From 50e6e896aded4a6b0f4720a27cd02b6d9c1f8b4b Mon Sep 17 00:00:00 2001 From: Amaury Pouly Date: Sat, 12 Jun 2010 05:26:23 +0000 Subject: usb-as3535v2: add more defines, reorganize/simplify things, add code for interrupt handling git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26810 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/as3525/usb-drv-as3525v2.c | 343 ++++++++++++++++++-------- firmware/target/arm/as3525/usb-drv-as3525v2.h | 250 ++++++++++++++----- 2 files changed, 431 insertions(+), 162 deletions(-) diff --git a/firmware/target/arm/as3525/usb-drv-as3525v2.c b/firmware/target/arm/as3525/usb-drv-as3525v2.c index 98805ca578..db79ac4d20 100644 --- a/firmware/target/arm/as3525/usb-drv-as3525v2.c +++ b/firmware/target/arm/as3525/usb-drv-as3525v2.c @@ -25,8 +25,12 @@ #include "clock-target.h" #include "ascodec.h" #include "as3514.h" -#include +#include "stdbool.h" +#include "string.h" +#include "stdio.h" #include "panic.h" +#include "mmu-arm.h" +#include "system.h" #define LOGF_ENABLE #include "logf.h" #include "usb-drv-as3525v2.h" @@ -47,9 +51,11 @@ struct usb_endpoint #if 0 static struct usb_endpoint endpoints[USB_NUM_ENDPOINTS*2]; #endif +static struct usb_ctrlrequest ep0_setup_pkt; void usb_attach(void) { + logf("usb: attach"); usb_enable(true); } @@ -79,7 +85,7 @@ static void as3525v2_connect(void) USB_PCGCCTL &= ~0x8; usb_delay(); /* 6) set "power on program done" */ - USB_DCTL |= 0x800; + USB_DCTL |= USB_DCTL_pwronprgdone; usb_delay(); /* 7) core soft reset */ USB_GRSTCTL |= USB_GRSTCTL_csftrst; @@ -91,8 +97,8 @@ static void as3525v2_connect(void) USB_GRSTCTL |= 0x3f; usb_delay(); /* 10) force device mode*/ - USB_GUSBCFG &= ~0x20000000; - USB_GUSBCFG |= 0x40000000; + USB_GUSBCFG &= ~USB_GUSBCFG_force_host_mode; + USB_GUSBCFG |= USB_GUSBCFG_force_device_mode; usb_delay(); /* 11) Do something that is probably CCU related but undocumented*/ CCU_USB_THINGY &= ~0x1000; @@ -111,14 +117,9 @@ static void usb_enable_common_interrupts(void) /* Clear any pending interrupt */ USB_GINTSTS = 0Xffffffff; /* Enable interrupts */ - USB_GINTMSK |= USB_GINTMSK_modemismatch | - USB_GINTMSK_otgintr | - USB_GINTMSK_rxstsqlvl | /* for dma */ - USB_GINTMSK_conidstschng | - USB_GINTMSK_wkupintr | - USB_GINTMSK_disconnect | - USB_GINTMSK_usbsuspend | - USB_GINTMSK_sessreqintr; + USB_GINTMSK = USB_GINTMSK_otgintr + | USB_GINTMSK_conidstschng + | USB_GINTMSK_disconnect; } static void usb_enable_device_interrupts(void) @@ -130,20 +131,10 @@ static void usb_enable_device_interrupts(void) /* Enable common interrupts */ usb_enable_common_interrupts(); /* Enable interrupts */ - USB_GINTMSK |= - USB_GINTMSK_usb_rst - | USB_GINTMSK_enumdone - | USB_GINTMSK_inepintr - | USB_GINTMSK_outepintr - | USB_GINTMSK_erlysuspend - | USB_GINTMSK_epmismatch /* only if multiple tx fifos enabled */ -#if 0 /* only if periodic fifo used */ - | USB_GINTMSK_isooutdrop - | USB_GINTMSK_eopframe - | USB_GINTMSK_incomplisoin - | USB_GINTMSK_incomplisoout -#endif - ; + USB_GINTMSK |= USB_GINTMSK_usbreset + | USB_GINTMSK_enumdone + | USB_GINTMSK_inepintr + | USB_GINTMSK_outepintr; } static void usb_flush_tx_fifos(int nums) @@ -158,31 +149,28 @@ static void usb_flush_tx_fifos(int nums) if(USB_GRSTCTL & USB_GRSTCTL_txfflsh_flush) panicf("usb: hang of flush tx fifos (%x)", nums); /* wait 3 phy clocks */ - sleep(1); + udelay(1); } static void usb_flush_rx_fifo(void) { unsigned int i = 0; - USB_GRSTCTL |= USB_GRSTCTL_rxfflsh_flush; + USB_GRSTCTL = USB_GRSTCTL_rxfflsh_flush; while(USB_GRSTCTL & USB_GRSTCTL_rxfflsh_flush && i < 0x300) i++; if(USB_GRSTCTL & USB_GRSTCTL_rxfflsh_flush) panicf("usb: hang of flush rx fifo"); /* wait 3 phy clocks */ - sleep(1); + udelay(1); } static void core_reset(void) { unsigned int i = 0; /* Wait for AHB master IDLE state. */ - while((USB_GRSTCTL & USB_GRSTCTL_ahbidle) == 0); - { - /*udelay(10);*/ - sleep(1); - } + while((USB_GRSTCTL & USB_GRSTCTL_ahbidle) == 0) + udelay(10); /* Core Soft Reset */ USB_GRSTCTL |= USB_GRSTCTL_csftrst; /* Waits for the hardware to clear reset bit */ @@ -193,8 +181,7 @@ static void core_reset(void) panicf("oops, usb core soft reset hang :("); /* Wait for 3 PHY Clocks */ - /*mdelay(100);*/ - sleep(1); + udelay(1); } static void core_dev_init(void) @@ -216,12 +203,6 @@ static void core_dev_init(void) panicf("usb: wrong HS phy type (%ld)", USB_GHWCFG2_HS_PHY_TYPE); if(USB_GHWCFG2_FS_PHY_TYPE != USB_PHY_TYPE_UNSUPPORTED) panicf("usb: wrong FS phy type (%ld)", USB_GHWCFG2_FS_PHY_TYPE); - #ifdef USB_USE_CUSTOM_FIFO_LAYOUT - if(USB_GHWCFG2_DYN_FIFO != 1) - panicf("usb: no dynamic fifo"); - if(USB_GRXFSIZ != USB_DATA_FIFO_DEPTH) - panicf("usb: wrong data fifo size"); - #endif /* USB_USE_CUSTOM_FIFO_LAYOUT */ if(USB_GHWCFG4_UTMI_PHY_DATA_WIDTH != 0x2) panicf("usb: wrong utmi data width (%ld)", USB_GHWCFG4_UTMI_PHY_DATA_WIDTH); if(USB_GHWCFG4_DED_FIFO_EN != 1) /* it seems to be multiple tx fifo support */ @@ -264,52 +245,12 @@ static void core_dev_init(void) USB_GET_FIFOSIZE_DEPTH(USB_DIEPTXFSIZ(i))); } - #ifdef USB_USE_CUSTOM_FIFO_LAYOUT - /* Setup FIFOs */ - /* Organize FIFO as follow: - * 0 -> rxfsize : RX fifo - * rxfsize -> rxfsize + nptxfsize : TX fifo for first IN ep - * rxfsize + nptxfsize -> rxfsize + 2 * nptxfsize : TX fifo for second IN ep - * rxfsize + 2 * nptxfsize -> rxfsize + 3 * nptxfsize : TX fifo for third IN ep - * ... - */ - - unsigned short adr = 0; - unsigned short depth = USB_RX_FIFO_SIZE; - USB_GRXFSIZ = depth; - adr += depth; - depth = USB_NPTX_FIFO_SIZE; - USB_GNPTXFSIZ = USB_MAKE_FIFOSIZE_DATA(adr, depth); - adr += depth; - - for(i = 1; i <= USB_NUM_IN_EP; i++) - { - depth = USB_EPTX_FIFO_SIZE; - USB_DIEPTXFSIZ(i) = USB_MAKE_FIFOSIZE_DATA(adr, depth); - adr += depth; - } - - logf("used:"); - logf(" rx fifo: [%04x,+%4lx]", 0, USB_GRXFSIZ); - logf(" nptx fifo: [%04lx,+%4lx]", USB_GET_FIFOSIZE_START_ADR(USB_GNPTXFSIZ), - USB_GET_FIFOSIZE_DEPTH(USB_GNPTXFSIZ)); - for(i = 1; i <= USB_NUM_IN_EP; i++) - { - logf(" dieptx fifo(%2u): [%04lx,+%4lx]", i, - USB_GET_FIFOSIZE_START_ADR(USB_DIEPTXFSIZ(i)), - USB_GET_FIFOSIZE_DEPTH(USB_DIEPTXFSIZ(i))); - } - - if(adr > USB_DATA_FIFO_DEPTH) - panicf("usb: total data fifo size exceeded"); - #endif /* USB_USE_CUSTOM_FIFO_LAYOUT */ - /* flush the fifos */ usb_flush_tx_fifos(0x10); /* flush all */ usb_flush_rx_fifo(); /* flush learning queue */ - USB_GRSTCTL |= USB_GRSTCTL_intknqflsh; + USB_GRSTCTL = USB_GRSTCTL_intknqflsh; /* Clear all pending device interrupts */ USB_DIEPMSK = 0; @@ -361,33 +302,30 @@ static void core_dev_init(void) static void core_init(void) { - /* Reset the Controller */ + /* Setup phy for high speed */ + USB_GUSBCFG &= ~USB_GUSBCFG_ulpi_ext_vbus_drv; + /* Disable external TS Dline pulsing (???) */ + USB_GUSBCFG &= ~USB_GUSBCFG_term_sel_dl_pulse; + /* core reset */ core_reset(); - /* Setup phy for high speed */ - /* 1) select utmi */ - /* fixme: the clip+ hardware support utmi only, this is useless */ - //USB_GUSBCFG &= ~USB_GUSBCFG_ulpi_utmi_sel; - /* 2) select utmi 16-bit wide bus */ + /* Select UTMI */ + USB_GUSBCFG &= ~USB_GUSBCFG_ulpi_utmi_sel; + /* Select UTMI+ 16 */ USB_GUSBCFG |= USB_GUSBCFG_phy_if; - /* 3) core reset */ - /* fixme: linux patch says the phy parameters survive the soft reset so - * perhaps this part can be done only one type but I don't know - * what happened when phy goes to standby mode and clock are disabled */ + /* core reset */ core_reset(); - /* fixme: at this point, the linux patch sets ulpi bits to 0 on utmi selection - * but the clip+ hardware does not support it so don't bother with - * that */ + /* fixme: the linux code does that but the clip+ doesn't use ULPI it seems */ + USB_GUSBCFG &= ~(USB_GUSBCFG_ulpi_fsls | USB_GUSBCFG_ulpi_clk_sus_m); /* fixme: the current code is for internal DMA only, the clip+ architecture * define the internal DMA model */ - /* Set burstlen */ - USB_GAHBCFG |= USB_GAHBCFG_INT_DMA_BURST_INCR << USB_GAHBCFG_hburstlen_bit_pos; - /* Enable DMA */ - USB_GAHBCFG |= USB_GAHBCFG_dma_enable; + /* Set burstlen and enable DMA*/ + USB_GAHBCFG = (USB_GAHBCFG_INT_DMA_BURST_INCR << USB_GAHBCFG_hburstlen_bit_pos) + | USB_GAHBCFG_dma_enable; /* Disable HNP and SRP, not sure it's useful because we already forced dev mode */ - USB_GUSBCFG &= ~(USB_GUSBCFG_SRP_cap | USB_GUSBCFG_HNP_cap); + USB_GUSBCFG &= ~(USB_GUSBCFG_srpcap | USB_GUSBCFG_hnpcapp); /* enable basic interrupts */ usb_enable_common_interrupts(); @@ -472,13 +410,212 @@ int usb_drv_send_nonblocking(int ep, void *ptr, int len) return -1; } +static void activate_ep0(void) +{ + /* Setup EP0 OUT to receive setup packets and + * EP0 IN to transmit packets + * The setup takes enumeration speed into account + */ + + /* Setup packet size of IN ep based of enumerated speed */ + switch((USB_DSTS & USB_DSTS_enumspd_bits) >> USB_DSTS_enumspd_bit_pos) + { + case USB_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: + case USB_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: + case USB_DSTS_ENUMSPD_FS_PHY_48MHZ: + /* Use 64 bytes packet size */ + USB_DIEPCTL(0) = (USB_DIEPCTL(0) & (~USB_DEPCTL_mps_bits)) + | (USB_DEPCTL_MPS_64 << USB_DEPCTL_mps_bit_pos); + break; + case USB_DSTS_ENUMSPD_LS_PHY_6MHZ: + USB_DIEPCTL(0) = (USB_DIEPCTL(0) & (~USB_DEPCTL_mps_bits)) + | (USB_DEPCTL_MPS_8 << USB_DEPCTL_mps_bit_pos); + break; + default: + panicf("usb: invalid enum speed"); + } + + /* Enable OUT ep for receive */ + USB_DOEPCTL(0) |= USB_DEPCTL_epena; + + /* Clear non periodic NAK for IN ep */ + USB_DCTL |= USB_DCTL_cgnpinnak; +} + +static void ep0_out_start(void) +{ + /* Setup EP0 OUT with the following parameters: + * packet count = 1 + * setup packet count = 1 + * transfer size = 8 (=sizeof setup packet) + */ + + USB_DOEPTSIZ(0) = (1 << USB_DEPTSIZ0_supcnt_bit_pos) + | (1 << USB_DEPTSIZ0_pkcnt_bit_pos) + | 8; + + /* setup DMA */ + clean_dcache_range((void*)&ep0_setup_pkt, sizeof ep0_setup_pkt); /* force write back */ + USB_DOEPDMA(0) = (unsigned long)&ep0_setup_pkt; /* virtual address=physical address */ + + /* enable EP */ + USB_DOEPCTL(0) |= USB_DEPCTL_epena | USB_DEPCTL_usbactep; +} + +static bool handle_usb_reset(void) +{ + unsigned int i; + logf("usb: bus reset"); + + /* Clear the Remote Wakeup Signalling */ + USB_DCTL &= ~USB_DCTL_rmtwkupsig; + + /* Set NAK for all OUT EPs */ + for(i = 0; i <= USB_NUM_OUT_EP; i++) + USB_DOEPCTL(i) = USB_DEPCTL_snak; + + /* Flush the NP Tx FIFO */ + usb_flush_tx_fifos(0); + + /* Flush the Learning Queue */ + USB_GRSTCTL = USB_GRSTCTL_intknqflsh; + + /* Setup interrupt masks */ + USB_DAINTMSK = USB_DAINT_IN_EP(0) | USB_DAINT_OUT_EP(0); + USB_DOEPMSK = USB_DOEPINT_setup | USB_DOEPINT_xfercompl | USB_DOEPINT_ahberr + | USB_DOEPINT_epdisabled; + USB_DIEPMSK = USB_DIEPINT_xfercompl | USB_DIEPINT_timeout + | USB_DIEPINT_epdisabled | USB_DIEPINT_ahberr + | USB_DIEPINT_intknepmis; + + /* Reset Device Address */ + USB_DCFG &= ~USB_DCFG_devadr_bits; + + /* setup EP0 to receive SETUP packets */ + ep0_out_start(); + /* Clear interrupt */ + USB_GINTSTS = USB_GINTMSK_usbreset; + + usb_disable_global_interrupts(); + + return true; +} + +static bool handle_enum_done(void) +{ + logf("usb: enum done"); + + /* Enable EP0 to receive SETUP packets */ + activate_ep0(); + + /* Set USB turnaround time + * fixme: unsure about this */ + //USB_GUSBCFG = (USB_GUSBCFG & ~USB_GUSBCFG_usbtrdtim_bits) | (5 << USB_GUSBCFG_usbtrdtim_bit_pos); + //panicf("usb: turnaround time is %d", (USB_GUSBCFG & USB_GUSBCFG_usbtrdtim_bits) >> USB_GUSBCFG_usbtrdtim_bit_pos); + + /* Clear interrupt */ + USB_GINTSTS = USB_GINTMSK_enumdone; + + return true; +} + +static bool handle_in_ep_int(void) +{ + logf("usb: in ep int"); + return false; +} + +static bool handle_out_ep_int(void) +{ + logf("usb: out ep int"); + return false; +} + +static void dump_intsts(char *buffer, size_t size, unsigned long sts) +{ + (void) size; + buffer[0] = 0; + #define DUMP_CASE(name) \ + if(sts & USB_GINTMSK_##name) strcat(buffer, #name " "); + + DUMP_CASE(modemismatch) + DUMP_CASE(otgintr) + DUMP_CASE(sofintr) + DUMP_CASE(rxstsqlvl) + DUMP_CASE(nptxfempty) + DUMP_CASE(ginnakeff) + DUMP_CASE(goutnakeff) + DUMP_CASE(i2cintr) + DUMP_CASE(erlysuspend) + DUMP_CASE(usbsuspend) + DUMP_CASE(usbreset) + DUMP_CASE(enumdone) + DUMP_CASE(isooutdrop) + DUMP_CASE(eopframe) + DUMP_CASE(epmismatch) + DUMP_CASE(inepintr) + DUMP_CASE(outepintr) + DUMP_CASE(incomplisoin) + DUMP_CASE(incomplisoout) + DUMP_CASE(portintr) + DUMP_CASE(hcintr) + DUMP_CASE(ptxfempty) + DUMP_CASE(conidstschng) + DUMP_CASE(disconnect) + DUMP_CASE(sessreqintr) + DUMP_CASE(wkupintr) + + buffer[strlen(buffer) - 1] = 0; +} + /* interrupt service routine */ void INT_USB(void) { - panicf("USB interrupt !"); + static char buffer[256]; + /* some bits in GINTSTS can be set even though we didn't enable the interrupt source + * so AND it with the actual mask */ + unsigned long sts = USB_GINTSTS & USB_GINTMSK; + unsigned long handled_one = 0; /* mask of all listed one (either handled or not) */ + + #define HANDLED_CASE(bitmask, callfn) \ + handled_one |= bitmask; \ + if(sts & bitmask) \ + { \ + if(!callfn()) \ + goto Lerr; \ + } + + #define UNHANDLED_CASE(bitmask) \ + handled_one |= bitmask; \ + if(sts & bitmask) \ + goto Lunhandled; + + /* device part */ + HANDLED_CASE(USB_GINTMSK_usbreset, handle_usb_reset) + HANDLED_CASE(USB_GINTMSK_enumdone, handle_enum_done) + HANDLED_CASE(USB_GINTMSK_inepintr, handle_in_ep_int) + HANDLED_CASE(USB_GINTMSK_outepintr, handle_out_ep_int) + + /* common part */ + UNHANDLED_CASE(USB_GINTMSK_otgintr) + UNHANDLED_CASE(USB_GINTMSK_conidstschng) + UNHANDLED_CASE(USB_GINTMSK_disconnect) + + /* unlisted ones */ + if(sts & ~handled_one) + goto Lunhandled; + + return; + + Lunhandled: + dump_intsts(buffer, sizeof buffer, sts); + panicf("unhandled usb int: %lx (%s)", sts, buffer); + + Lerr: + dump_intsts(buffer, sizeof buffer, sts); + panicf("error in usb int: %lx (%s)", sts, buffer); } -/* (not essential? , not implemented in usb-tcc.c) */ void usb_drv_set_test_mode(int mode) { (void) mode; diff --git a/firmware/target/arm/as3525/usb-drv-as3525v2.h b/firmware/target/arm/as3525/usb-drv-as3525v2.h index 4d312a833e..e2932d0dd6 100644 --- a/firmware/target/arm/as3525/usb-drv-as3525v2.h +++ b/firmware/target/arm/as3525/usb-drv-as3525v2.h @@ -54,22 +54,25 @@ /** Device IN Endpoint Transmit FIFO (ep) Size Register */ #define USB_DIEPTXFSIZ(ep) (*(volatile unsigned long *)(USB_BASE + 0x100 + 4 * (ep))) +/** Build the content of a FIFO size register like USB_DIEPTXFSIZ(i) and USB_GNPTXFSIZ*/ #define USB_MAKE_FIFOSIZE_DATA(startadr, depth) \ (((startadr) & 0xffff) | ((depth) << 16)) +/** Retrieve fifo size for such registers */ #define USB_GET_FIFOSIZE_DEPTH(data) \ ((data) >> 16) +/** Retrieve fifo start address for such registers */ #define USB_GET_FIFOSIZE_START_ADR(data) \ ((data) & 0xffff) #define USB_GRSTCTL_csftrst (1 << 0) /** Core soft reset */ #define USB_GRSTCTL_hsftrst (1 << 1) /** Hclk soft reset */ #define USB_GRSTCTL_intknqflsh (1 << 3) /** In Token Sequence Learning Queue Flush */ +#define USB_GRSTCTL_rxfflsh_flush (1 << 4) /** RxFIFO Flush */ +#define USB_GRSTCTL_txfflsh_flush (1 << 5) /** TxFIFO Flush */ #define USB_GRSTCTL_txfnum_bit_pos 6 /** TxFIFO Number */ #define USB_GRSTCTL_txfnum_bits (0x1f << 6) -#define USB_GRSTCTL_txfflsh_flush (1 << 5) /** TxFIFO Flush */ -#define USB_GRSTCTL_rxfflsh_flush (1 << 4) /** RxFIFO Flush */ #define USB_GRSTCTL_ahbidle (1 << 31) /** AHB idle state*/ #define USB_GHWCFG1_IN_EP(ep) ((USB_GHWCFG1 >> ((ep) *2)) & 0x1) /** 1 if EP(ep) has in cap */ @@ -81,59 +84,75 @@ #define USB_GHWCFG2_NUM_EP ((USB_GHWCFG2 >> 10) & 0xf) /** Number of endpoints */ #define USB_GHWCFG2_DYN_FIFO ((USB_GHWCFG2 >> 19) & 0x1) /** Dynamic FIFO */ +/* For USB_GHWCFG2_HS_PHY_TYPE and USB_GHWCFG2_SS_PHY_TYPE */ #define USB_PHY_TYPE_UNSUPPORTED 0 #define USB_PHY_TYPE_UTMI 1 #define USB_INT_DMA_ARCH 2 #define USB_GHWCFG3_DFIFO_LEN (USB_GHWCFG3 >> 16) /** Total fifo size */ -#define USB_GHWCFG4_UTMI_PHY_DATA_WIDTH ((USB_GHWCFG4 >> 14) & 0x3) -#define USB_GHWCFG4_DED_FIFO_EN ((USB_GHWCFG4 >> 25) & 0x1) +#define USB_GHWCFG4_UTMI_PHY_DATA_WIDTH ((USB_GHWCFG4 >> 14) & 0x3) /** UTMI+ data bus width (format is unsure) */ +#define USB_GHWCFG4_DED_FIFO_EN ((USB_GHWCFG4 >> 25) & 0x1) /** Dedicated Tx FIFOs */ #define USB_GHWCFG4_NUM_IN_EP ((USB_GHWCFG4 >> 26) & 0xf) /** Number of IN endpoints */ -#define USB_GUSBCFG_ulpi_utmi_sel (1 << 4) /** select ulpi:1 or utmi:0 */ +#define USB_GUSBCFG_toutcal_bit_pos 0 +#define USB_GUSBCFG_toutcal_bits (0x7 << USB_GUSBCFG_toutcal_bit_pos) #define USB_GUSBCFG_phy_if (1 << 3) /** select utmi bus width ? */ -#define USB_GUSBCFG_SRP_cap 0x100 -#define USB_GUSBCFG_HNP_cap 0x200 +#define USB_GUSBCFG_ulpi_utmi_sel (1 << 4) /** select ulpi:1 or utmi:0 */ +#define USB_GUSBCFG_fsintf (1 << 5) +#define USB_GUSBCFG_physel (1 << 6) +#define USB_GUSBCFG_ddrsel (1 << 7) +#define USB_GUSBCFG_srpcap (1 << 8) +#define USB_GUSBCFG_hnpcapp (1 << 9) +#define USB_GUSBCFG_usbtrdtim_bit_pos 10 +#define USB_GUSBCFG_usbtrdtim_bits (0xf << USB_GUSBCFG_usbtrdtim_bit_pos) +#define USB_GUSBCFG_nptxfrwnden (1 << 14) +#define USB_GUSBCFG_phylpwrclksel (1 << 15) +#define USB_GUSBCFG_otgutmifssel (1 << 16) +#define USB_GUSBCFG_ulpi_fsls (1 << 17) +#define USB_GUSBCFG_ulpi_auto_res (1 << 18) +#define USB_GUSBCFG_ulpi_clk_sus_m (1 << 19) +#define USB_GUSBCFG_ulpi_ext_vbus_drv (1 << 20) +#define USB_GUSBCFG_ulpi_int_vbus_indicator (1 << 21) +#define USB_GUSBCFG_term_sel_dl_pulse (1 << 22) +#define USB_GUSBCFG_force_host_mode (1 << 29) +#define USB_GUSBCFG_force_device_mode (1 << 30) +#define USB_GUSBCFG_corrupt_tx_packet (1 << 31) -#define USB_GAHBCFG_glblintrmsk (1 << 0) +#define USB_GAHBCFG_glblintrmsk (1 << 0) /** Global interrupt mask */ #define USB_GAHBCFG_hburstlen_bit_pos 1 #define USB_GAHBCFG_INT_DMA_BURST_INCR 1 /** note: the linux patch has several other value, this is one picked for internal dma */ -#define USB_GAHBCFG_dma_enable (1 << 5) - -#define USB_GINTMSK_usb_rst 0x00001000 /*!< USB Reset Mask */ -#define USB_GINTMSK_EnumDone 0x00000200 /*!< Enumeration Done Mask */ -#define USB_GINTMSK_ErlySusp 0x00000400 /*!< Early Suspend Mask */ -#define USB_GINTMSK_USBSusp 0x00000800 /*!< USB Suspend Mask */ -#define USB_GINTMSK_SOF 0x00000008 /*!< Start of (micro)Frame Mask */ -#define USB_GINTMSK_NPTxFEmp 0x00000020 /*!< Non-periodic TxFIFO Empty Mask */ - -#define USB_GINTMSK_wkupintr (1 << 31) -#define USB_GINTMSK_sessreqintr (1 << 30) -#define USB_GINTMSK_disconnect (1 << 29) -#define USB_GINTMSK_conidstschng (1 << 28) -#define USB_GINTMSK_ptxfempty (1 << 26) -#define USB_GINTMSK_hcintr (1 << 25) -#define USB_GINTMSK_portintr (1 << 24) -#define USB_GINTMSK_incomplisoout (1 << 21) -#define USB_GINTMSK_incomplisoin (1 << 20) -#define USB_GINTMSK_outepintr (1 << 19) -#define USB_GINTMSK_inepintr (1 << 18) -#define USB_GINTMSK_epmismatch (1 << 17) -#define USB_GINTMSK_eopframe (1 << 15) -#define USB_GINTMSK_isooutdrop (1 << 14) -#define USB_GINTMSK_enumdone (1 << 13) -#define USB_GINTMSK_usbreset (1 << 12) -#define USB_GINTMSK_usbsuspend (1 << 11) -#define USB_GINTMSK_erlysuspend (1 << 10) -#define USB_GINTMSK_i2cintr (1 << 9) -#define USB_GINTMSK_goutnakeff (1 << 7) -#define USB_GINTMSK_ginnakeff (1 << 6) -#define USB_GINTMSK_nptxfempty (1 << 5) -#define USB_GINTMSK_rxstsqlvl (1 << 4) -#define USB_GINTMSK_sofintr (1 << 3) +#define USB_GAHBCFG_dma_enable (1 << 5) /** Enable DMA */ + +/* NOTE: USB_GINTSTS bits are the same as in USB_GINTMSK plus the following one */ +#define USB_GINTSTS_curmode (1 << 0) /** Current mode: 1 for host, 0 for device */ + +#define USB_GINTMSK_modemismatch (1 << 1) /** mode mismatch ? */ #define USB_GINTMSK_otgintr (1 << 2) -#define USB_GINTMSK_modemismatch (1 << 1) +#define USB_GINTMSK_sofintr (1 << 3) +#define USB_GINTMSK_rxstsqlvl (1 << 4) +#define USB_GINTMSK_nptxfempty (1 << 5) /** Non-periodic TX fifo empty ? */ +#define USB_GINTMSK_ginnakeff (1 << 6) +#define USB_GINTMSK_goutnakeff (1 << 7) +#define USB_GINTMSK_i2cintr (1 << 9) +#define USB_GINTMSK_erlysuspend (1 << 10) +#define USB_GINTMSK_usbsuspend (1 << 11) /** USB suspend */ +#define USB_GINTMSK_usbreset (1 << 12) /** USB reset */ +#define USB_GINTMSK_enumdone (1 << 13) /** Enumeration done */ +#define USB_GINTMSK_isooutdrop (1 << 14) +#define USB_GINTMSK_eopframe (1 << 15) +#define USB_GINTMSK_epmismatch (1 << 17) /** endpoint mismatch ? */ +#define USB_GINTMSK_inepintr (1 << 18) /** in pending ? */ +#define USB_GINTMSK_outepintr (1 << 19) /** out pending ? */ +#define USB_GINTMSK_incomplisoin (1 << 20) /** ISP in complete ? */ +#define USB_GINTMSK_incomplisoout (1 << 21) /** ISO out complete ? */ +#define USB_GINTMSK_portintr (1 << 24) /** Port status change ? */ +#define USB_GINTMSK_hcintr (1 << 25) +#define USB_GINTMSK_ptxfempty (1 << 26) /** Periodic TX fifof empty ? */ +#define USB_GINTMSK_conidstschng (1 << 28) +#define USB_GINTMSK_disconnect (1 << 29) /** Disconnect */ +#define USB_GINTMSK_sessreqintr (1 << 30) /** Session request */ +#define USB_GINTMSK_wkupintr (1 << 31) /** Wake up */ /** * Device Registers Base Addresses @@ -157,9 +176,25 @@ #define USB_DTKNQR4 (*(volatile unsigned long *)(USB_DEVICE + 0x34)) /** Device IN Token Queue Read Register 4 (RO) */ #define USB_FFEMPTYMSK (*(volatile unsigned long *)(USB_DEVICE + 0x34)) /** Device IN EPs empty Inr. Mask Register */ -#define USB_DCFG_devspd_bits 0x3 +#define USB_DCTL_rmtwkupsig (1 << 0) /** Remote Wakeup */ +#define USB_DCTL_sftdiscon (1 << 1) /** Soft Disconnect */ +#define USB_DCTL_gnpinnaksts (1 << 2) /** Global Non-Periodic IN NAK Status */ +#define USB_DCTL_goutnaksts (1 << 3) /** Global OUT NAK Status */ +#define USB_DCTL_tstctl_bit_pos 4 /** Test Control */ +#define USB_DCTL_tstctl_bits (0x7 << USB_DCTL_tstctl_bit_pos) +#define USB_DCTL_sgnpinnak (1 << 7) /** Set Global Non-Periodic IN NAK */ +#define USB_DCTL_cgnpinnak (1 << 8) /** Clear Global Non-Periodic IN NAK */ +#define USB_DCTL_sgoutnak (1 << 9) /** Set Global OUT NAK */ +#define USB_DCTL_cgoutnak (1 << 10) /** Clear Global OUT NAK */ +/* "documented" in usb_constants.h only */ +#define USB_DCTL_pwronprgdone (1 << 11) /** Power on Program Done ? */ + +#define USB_DCFG_devspd_bits 0x3 /** Device Speed */ #define USB_DCFG_devspd_hs_phy_hs 0 /** High speed PHY running at high speed */ #define USB_DCFG_devspd_hs_phy_fs 1 /** High speed PHY running at full speed */ +#define USB_DCFG_nzstsouthshk (1 << 2) /** Non Zero Length Status OUT Handshake */ +#define USB_DCFG_devadr_bit_pos 4 /** Device Address */ +#define USB_DCFG_devadr_bits (0x7f << USB_DCFG_devadr_bit_pos) #define USB_DCFG_perfrint_bit_pos 11 /** Periodic Frame Interval */ #define USB_DCFG_perfrint_bits (0x3 << USB_DCFG_perfrint_bit_pos) #define USB_DCFG_FRAME_INTERVAL_80 0 @@ -167,6 +202,17 @@ #define USB_DCFG_FRAME_INTERVAL_90 2 #define USB_DCFG_FRAME_INTERVAL_95 3 +#define USB_DSTS_suspsts (1 << 0) /** Suspend status */ +#define USB_DSTS_enumspd_bit_pos 1 /** Enumerated speed */ +#define USB_DSTS_enumspd_bits (0x3 << USB_DSTS_enumspd_bit_pos) +#define USB_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 +#define USB_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 +#define USB_DSTS_ENUMSPD_LS_PHY_6MHZ 2 +#define USB_DSTS_ENUMSPD_FS_PHY_48MHZ 3 +#define USB_DSTS_errticerr (1 << 3) /** Erratic errors ? */ +#define USB_DSTS_soffn_bit_pos 7 /** Frame or Microframe Number of the received SOF */ +#define USB_DSTS_soffn_bits (0x3fff << USB_DSTS_soffn_bit_pos) + #define USB_DTHRCTL_non_iso_thr_en (1 << 0) #define USB_DTHRCTL_iso_thr_en (1 << 1) #define USB_DTHRCTL_tx_thr_len_bit_pos 2 @@ -198,6 +244,13 @@ #define USB_DIEPINT_emptyintr (1 << 7) /** linux doc broken on this, empty fifo ? */ #define USB_DIEPINT_txfifoundrn (1 << 8) /** linux doc void on this, tx fifo underrun ? */ +/* the following also apply to DOEPMSK */ +#define USB_DOEPINT_xfercompl (1 << 0) /** Transfer complete */ +#define USB_DOEPINT_epdisabled (1 << 1) /** Endpoint disabled */ +#define USB_DOEPINT_ahberr (1 << 2) /** AHB error */ +#define USB_DOEPINT_setup (1 << 3) /** Setup Phase Done (control EPs)*/ + +/* 0<=ep<=15, you can use ep=0 */ /** Device OUT Endpoint (ep) Control Register */ #define USB_DOEPCTL(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x300 + (ep) * 0x20)) /** Device OUT Endpoint (ep) Frame number Register */ @@ -209,27 +262,106 @@ /** Device Endpoint (ep) DMA Address Register */ #define USB_DOEPDMA(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x300 + (ep) * 0x20 + 0x14)) -#define USB_PCGCCTL (*(volatile unsigned long *)(USB_BASE + 0xE00)) /** Power and Clock Gating Control Register */ +#define USB_PCGCCTL (*(volatile unsigned long *)(USB_BASE + 0xE00)) /** Power and Clock Gating Control Register */ + + +/** Maximum Packet Size + * IN/OUT EPn + * IN/OUT EP0 - 2 bits + * 2'b00: 64 Bytes + * 2'b01: 32 + * 2'b10: 16 + * 2'b11: 8 */ +#define USB_DEPCTL_mps_bits 0x7ff +#define USB_DEPCTL_mps_bit_pos 0 +#define USB_DEPCTL_MPS_64 0 +#define USB_DEPCTL_MPS_32 1 +#define USB_DEPCTL_MPS_16 2 +#define USB_DEPCTL_MPS_8 3 +/** Next Endpoint + * IN EPn/IN EP0 + * OUT EPn/OUT EP0 - reserved */ +#define USB_DEPCTL_nextep_bit_pos 11 +#define USB_DEPCTL_nextep_bits (0xf << USB_DEPCTL_nextep_bit_pos) +#define USB_DEPCTL_usbactep (1 << 15) /** USB Active Endpoint */ +/** Endpoint DPID (INTR/Bulk IN and OUT endpoints) + * This field contains the PID of the packet going to + * be received or transmitted on this endpoint. The + * application should program the PID of the first + * packet going to be received or transmitted on this + * endpoint , after the endpoint is + * activated. Application use the SetD1PID and + * SetD0PID fields of this register to program either + * D0 or D1 PID. + * + * The encoding for this field is + * - 0: D0 + * - 1: D1 + */ +#define USB_DEPCTL_dpid (1 << 16) +#define USB_DEPCTL_naksts (1 << 17) /** NAK Status */ +/** Endpoint Type + * 2'b00: Control + * 2'b01: Isochronous + * 2'b10: Bulk + * 2'b11: Interrupt */ +#define USB_DEPCTL_eptype_bit_pos 18 +#define USB_DEPCTL_eptype_bits (0x3 << USB_DEPCTL_eptype_bit_pos) +/** Snoop Mode + * OUT EPn/OUT EP0 + * IN EPn/IN EP0 - reserved */ +#define USB_DEPCTL_snp (1 << 20) +#define USB_DEPCTL_stall (1 << 21) /** Stall Handshake */ +/** Tx Fifo Number + * IN EPn/IN EP0 + * OUT EPn/OUT EP0 - reserved */ +#define USB_DEPCTL_txfnum_bit_pos 22 +#define USB_DEPCTL_txfnum_bits (0xf << USB_DEPCTL_txfnum_bit_pos) + +#define USB_DEPCTL_cnak (1 << 26) /** Clear NAK */ +#define USB_DEPCTL_snak (1 << 27) /** Set NAK */ +/** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) + * Writing to this field sets the Endpoint DPID (DPID) + * field in this register to DATA0. Set Even + * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) + * Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) + * frame. + */ +#define USB_DEPCTL_setd0pid (1 << 28) +/** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) + * Writing to this field sets the Endpoint DPID (DPID) + * field in this register to DATA1 Set Odd + * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) + * Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to odd (micro) frame. + */ +#define USB_DEPCTL_setd1pid (1 << 29) +#define USB_DEPCTL_epdis (1 << 30) /** Endpoint disable */ +#define USB_DEPCTL_epena (1 << 31) /** Endpoint enable */ + + +/* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */ +#define USB_DEPTSIZ_xfersize_bits 0x7ffff /** Transfer Size */ +#define USB_DEPTSIZ_pkcnt_bit_pos 19 /** Packet Count */ +#define USB_DEPTSIZ_pkcnt_bits (0x3ff << USB_DEPTSIZ_pkcnt_bit_pos) +#define USB_DEPTSIZ_mc_bit_pos 29 /** Multi Count - Periodic IN endpoints */ +#define USB_DEPTSIZ_mc_bits (0x3 << USB_DEPTSIZ_mc_bit_pos) + +/* idem but for i=0 */ +#define USB_DEPTSIZ0_xfersize_bits 0x7f /** Transfer Size */ +#define USB_DEPTSIZ0_pkcnt_bit_pos 19 /** Packet Count */ +#define USB_DEPTSIZ0_pkcnt_bits (0x1 << USB_DEPTSIZ0_pkcnt_bit_pos) +#define USB_DEPTSIZ0_supcnt_bit_pos 29 /** Setup Packet Count (DOEPTSIZ0 Only) */ +#define USB_DEPTSIZ0_supcnt_bits (0x3 << USB_DEPTSIZ0_supcnt_bit_pos) -#define USB_DEPCTL_epena (1 << 31) /** Endpoint enable */ -#define USB_DEPCTL_epdis (1 << 30) /** Endpoint disable */ -#define USB_DEPCTL_snak (1 << 27) /** Set NAK */ -#define USB_DEPCTL_cnak (1 << 28) /** Clear NAK */ +/* valid for USB_DAINT and USB_DAINTMSK, for 0<=ep<=15 */ +#define USB_DAINT_IN_EP(i) (1 << (i)) +#define USB_DAINT_OUT_EP(i) (1 << ((i) + 16)) /** * Parameters */ -#ifdef USB_USE_CUSTOM_FIFO_LAYOUT -/* Data fifo: includes RX fifo, non period TX fifo and periodic fifos - * NOTE: this is a hardware parameter, it cannot be changed ! */ -#define USB_DATA_FIFO_DEPTH 1333u -/* size of the FX fifo */ -#define USB_RX_FIFO_SIZE 256u -/* size of the non periodic TX fifo */ -#define USB_NPTX_FIFO_SIZE 256u -/* size of each TX ep fifo size */ -#define USB_EPTX_FIFO_SIZE 256u -#endif /* USB_USE_CUSTOM_FIFO_LAYOUT */ /* Number of IN/OUT endpoints */ #define USB_NUM_IN_EP 3u #define USB_NUM_OUT_EP 2u -- cgit v1.2.3