From 3f70b661a3b4c7f0814d61ff36678675305e5ce1 Mon Sep 17 00:00:00 2001
From: Bertrik Sikken <bertrik@sikken.nl>
Date: Fri, 6 Nov 2009 22:47:09 +0000
Subject: Meizu M6SP: initialise and use SDRAM

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23544 a1c6a512-1295-4272-9138-f99709370657
---
 firmware/target/arm/s5l8700/boot.lds |  2 +-
 firmware/target/arm/s5l8700/crt0.S   | 69 +++++++++++++++++++++++++++++++++---
 2 files changed, 66 insertions(+), 5 deletions(-)

diff --git a/firmware/target/arm/s5l8700/boot.lds b/firmware/target/arm/s5l8700/boot.lds
index 6f43177c86..ba5a4a4cac 100644
--- a/firmware/target/arm/s5l8700/boot.lds
+++ b/firmware/target/arm/s5l8700/boot.lds
@@ -104,7 +104,7 @@ SECTIONS
      *(COMMON);
     . = ALIGN(0x4);
      _end = .;
-#ifdef IPOD_NANO2G
+#if defined(IPOD_NANO2G) || defined(MEIZU_M6SP)
   } > DRAM
 #else /* other targets don't have DRAM set up yet */
   } > IRAM
diff --git a/firmware/target/arm/s5l8700/crt0.S b/firmware/target/arm/s5l8700/crt0.S
index 4904c18dd3..5faaf4e834 100644
--- a/firmware/target/arm/s5l8700/crt0.S
+++ b/firmware/target/arm/s5l8700/crt0.S
@@ -55,7 +55,7 @@ newstart2:
     orr r0, r0, r1
     mcr 15, 0, r0, c1, c0, 0 // set bigendian
 #endif
-			 
+             
     ldr r1, =0x3c800000 // disable watchdog
     mov r0, #0xa5
     str r0, [r1]
@@ -107,7 +107,7 @@ start_loc:
 #if !(CONFIG_CPU==S5L8701 && defined(BOOTLOADER))
     ldr r1, =0x3c500000 
     ldr r0, =0x00800080
-    str r0, [r1]		// CLKCON
+    str r0, [r1]        // CLKCON
     mov r0, #0
     str r0, [r1,#0x24]  // PLLCON
 #ifdef IPOD_NANO2G
@@ -136,7 +136,7 @@ start_loc:
     orr r0, r0, r2
     mcr 15, 0, r0, c1, c0, 0 // asynchronous clocking mode
     nop
-    nop					        
+    nop                         
     nop
     nop
 #endif
@@ -236,6 +236,67 @@ start_loc:
     mov r0, #0  // 0x0
     str r0, [r1, #44] // do not enter any power saving mode
 
+#ifdef MEIZU_M6SP
+    /* setup SDRAM for Meizu M6SP */
+    ldr r1, =0x38200000
+    // configure SDR drive strength and pad settings
+    mov r0, #5
+    str r0, [r1, #0x4C] // MIU_DSS_SEL_B
+    mov r0, #2
+    str r0, [r1, #0x50] // MIU_DSS_SEL_O
+    str r0, [r1, #0x54] // MIU_DSS_SEL_C
+    mov r0, #2
+    str r0, [r1, #0x60] // SSTL2_PAD_ON
+    // select SDR mode
+    ldr r0, [r1, #0x40]
+    mov r2, #0xFFFDFFFF
+    and r0, r0, r2
+    orr r0, r0, #1
+    str r0, [r1, #0x40] // MIUORG
+    // set controller configuration
+    mov r0, #0x700
+    str r0, [r1]        // MIUCON
+    // set SDRAM timing
+    ldr r0, =0x6A4965
+    str r0, [r1, #0x10] // MIUSDPARA
+    // set refresh rate
+    mov r0, #0x1080
+    str r0, [r1, #0x08] // MIUAREF
+    // initialise SDRAM 
+    mov r0, #0x003
+    str r0, [r1, #0x04] // MIUCOM = nop
+    ldr r0, =0x203
+    str r0, [r1, #0x04] // MIUCOM = precharge all banks
+    nop
+    nop
+    nop
+    ldr r0, =0x303
+    str r0, [r1, #0x04] // MIUCOM = auto-refresh
+    nop
+    nop
+    nop
+    nop
+    str r0, [r1, #0x04] // MIUCOM = auto-refresh
+    nop
+    nop
+    nop
+    nop
+    str r0, [r1, #0x04] // MIUCOM = auto-refresh
+    nop
+    nop
+    nop
+    nop
+    // set mode register
+    mov r0, #0x33
+    str r0, [r1, #0x0C] // MIUMRS
+    ldr r0, =0x103
+    str r0, [r1, #0x04] // MIUCOM = mode register set
+    ldr r0, =0x4033
+    str r0, [r1, #0x0C] // MIUMRS
+    ldr r0, =0x103
+    str r0, [r1, #0x04] // MIUCOM = mode register set
+#endif /* MEIZU_M6SP */
+
     mov r1, #0x1
     mrc 15, 0, r0, c1, c0, 0
     bic r0, r0, r1
@@ -364,7 +425,7 @@ start_loc:
     ldrhi   r1, [r4], #4
     strhi   r1, [r2], #4
     bhi     1b
-	
+    
     /* Initialise ibss section to zero */
     ldr     r2, =_iedata
     ldr     r3, =_iend
-- 
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