From 3c5aa754de9c9e572232b469398a981dccfff127 Mon Sep 17 00:00:00 2001 From: Cástor Muñoz Date: Sun, 31 Jul 2016 03:40:32 +0200 Subject: iPod Classic: use the new USB DesignWare driver Change-Id: I36aabb5cb9cfe2d8c4f8fbcea944efec58ef9671 --- firmware/SOURCES | 2 +- firmware/export/config/ipod6g.h | 7 +- firmware/export/s5l8702.h | 17 +++- firmware/target/arm/s5l8702/usb-s5l8702.c | 137 ++++++++++++++++++++++++++++++ 4 files changed, 158 insertions(+), 5 deletions(-) create mode 100644 firmware/target/arm/s5l8702/usb-s5l8702.c diff --git a/firmware/SOURCES b/firmware/SOURCES index 9aab3c1115..2550475e15 100644 --- a/firmware/SOURCES +++ b/firmware/SOURCES @@ -1615,7 +1615,7 @@ target/arm/s5l8702/postmortemstub.S #endif target/arm/s5l8702/ipod6g/pmu-ipod6g.c target/arm/s5l8702/ipod6g/rtc-ipod6g.c -target/arm/s5l8700/usb-nano2g-6g.c +target/arm/s5l8702/usb-s5l8702.c #ifdef HAVE_SERIAL target/arm/uc870x.c target/arm/s5l8702/uart-s5l8702.c diff --git a/firmware/export/config/ipod6g.h b/firmware/export/config/ipod6g.h index cb8100bb55..01934a0cc2 100644 --- a/firmware/export/config/ipod6g.h +++ b/firmware/export/config/ipod6g.h @@ -238,12 +238,15 @@ #define DEFAULT_BRIGHTNESS_SETTING 0x20 /* USB defines */ +#define CONFIG_USBOTG USBOTG_DESIGNWARE +#define USB_DW_CLOCK 0 +#define USB_DW_TURNAROUND 5 +/* logf() over USB serial (http://www.rockbox.org/wiki/PortalPlayerUsb) */ +//#define USB_ENABLE_SERIAL #define HAVE_USBSTACK #define HAVE_USB_HID_MOUSE -#define CONFIG_USBOTG USBOTG_S3C6400X #define USB_VENDOR_ID 0x05AC #define USB_PRODUCT_ID 0x1261 -#define USB_NUM_ENDPOINTS 6 #define USB_DEVBSS_ATTR __attribute__((aligned(32))) #define USB_READ_BUFFER_SIZE (1024*24) diff --git a/firmware/export/s5l8702.h b/firmware/export/s5l8702.h index 6500f69d37..4799b05d4f 100644 --- a/firmware/export/s5l8702.h +++ b/firmware/export/s5l8702.h @@ -175,8 +175,21 @@ /////USB///// #define OTGBASE 0x38400000 #define PHYBASE 0x3C400000 -#define SYNOPSYSOTG_CLOCK 0 -#define SYNOPSYSOTG_AHBCFG (GAHBCFG_dma_enable | (GAHBCFG_INT_DMA_BURST_INCR8 << GAHBCFG_hburstlen_bitp) | GAHBCFG_glblintrmsk) + +/* OTG PHY control registers */ +#define OPHYPWR (*((uint32_t volatile*)(PHYBASE + 0x000))) +#define OPHYCLK (*((uint32_t volatile*)(PHYBASE + 0x004))) +#define ORSTCON (*((uint32_t volatile*)(PHYBASE + 0x008))) +#define OPHYUNK3 (*((uint32_t volatile*)(PHYBASE + 0x018))) +#define OPHYUNK1 (*((uint32_t volatile*)(PHYBASE + 0x01c))) +#define OPHYUNK2 (*((uint32_t volatile*)(PHYBASE + 0x044))) + +/* 9 available EPs (0b00000001111101010000000111101011), 6 used */ +#define USB_NUM_ENDPOINTS 6 + +/* Define this if the DWC implemented on this SoC does not support + DMA or you want to disable it. */ +// #define USB_DW_ARCH_SLAVE /////I2C///// diff --git a/firmware/target/arm/s5l8702/usb-s5l8702.c b/firmware/target/arm/s5l8702/usb-s5l8702.c new file mode 100644 index 0000000000..7a349f74f4 --- /dev/null +++ b/firmware/target/arm/s5l8702/usb-s5l8702.c @@ -0,0 +1,137 @@ +/*************************************************************************** +* __________ __ ___. +* Open \______ \ ____ ____ | | _\_ |__ _______ ___ +* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / +* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < +* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ +* \/ \/ \/ \/ \/ +* $Id$ +* +* Copyright (C) 2014 Michael Sparmann +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY +* KIND, either express or implied. +* +****************************************************************************/ +#include + +#include "config.h" +#include "usb.h" +#include "usb_drv.h" +#ifdef HAVE_USBSTACK +#include "usb_core.h" +#endif + +#include "s5l8702.h" +#include "clocking-s5l8702.h" +#include "usb-designware.h" + + +const struct usb_dw_config usb_dw_config = +{ + .phytype = DWC_PHYTYPE_UTMI_16, + + /* Available FIFO memory: 0x820 words */ + .rx_fifosz = 0x360, + .nptx_fifosz = 0x40, /* 1 dedicated FIFO for IN0 */ + .ptx_fifosz = 0x180, /* 3 dedicated FIFOs for IN1,IN3,IN5 */ + +#ifdef USB_DW_ARCH_SLAVE + .disable_double_buffering = false, +#else + .ahb_burst_len = HBSTLEN_INCR8, + .ahb_threshold = 8, +#endif +}; + +void usb_dw_target_enable_clocks() +{ + clockgate_enable(CLOCKGATE_USBOTG, true); + clockgate_enable(CLOCKGATE_USBPHY, true); + + OPHYPWR = 0; /* PHY: Power up */ + udelay(10); + OPHYUNK1 = 1; + OPHYUNK2 = 0xe3f; + ORSTCON = 1; /* PHY: Assert Software Reset */ + udelay(10); + ORSTCON = 0; /* PHY: Deassert Software Reset */ + udelay(10); + OPHYUNK3 = 0x600; + OPHYCLK = USB_DW_CLOCK; + udelay(400); +} + +void usb_dw_target_disable_clocks() +{ + OPHYPWR = 0xf; /* PHY: Power down */ + udelay(10); + ORSTCON = 7; /* PHY: Assert Software Reset */ + udelay(10); + + clockgate_enable(CLOCKGATE_USBOTG, false); + clockgate_enable(CLOCKGATE_USBPHY, false); +} + +void usb_dw_target_enable_irq() +{ + VICINTENABLE(IRQ_USB_FUNC >> 5) = 1 << (IRQ_USB_FUNC & 0x1f); +} + +void usb_dw_target_disable_irq() +{ + VICINTENCLEAR(IRQ_USB_FUNC >> 5) = 1 << (IRQ_USB_FUNC & 0x1f); +} + +void usb_dw_target_clear_irq() +{ +} + +/* RB API */ +static int usb_status = USB_EXTRACTED; + +void usb_enable(bool on) +{ +#ifdef HAVE_USBSTACK + if (on) usb_core_init(); + else usb_core_exit(); +#else + (void)on; +#endif +} + +int usb_detect(void) +{ + return usb_status; +} + +void usb_insert_int(void) +{ + usb_status = USB_INSERTED; +#ifdef USB_STATUS_BY_EVENT + usb_status_event(USB_INSERTED); +#endif +} + +void usb_remove_int(void) +{ + usb_status = USB_EXTRACTED; +#ifdef USB_STATUS_BY_EVENT + usb_status_event(USB_EXTRACTED); +#endif +} + +void usb_init_device(void) +{ + /* Power up the core clocks to allow writing + to some registers needed to power it down */ + usb_dw_target_disable_irq(); + usb_dw_target_enable_clocks(); + + usb_drv_exit(); +} -- cgit v1.2.3