From 2b0e43673993193eb8ee5b4da7927ef260f4be63 Mon Sep 17 00:00:00 2001 From: Maurus Cuelenaere Date: Sat, 3 May 2008 18:51:20 +0000 Subject: Add OF LCD init git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17334 a1c6a512-1295-4272-9138-f99709370657 --- firmware/export/dm320.h | 99 +++++++++++++++++++++- .../arm/tms320dm320/creative-zvm/lcd-creativezvm.c | 82 ++++++++++++------ 2 files changed, 151 insertions(+), 30 deletions(-) diff --git a/firmware/export/dm320.h b/firmware/export/dm320.h index a70083331e..311ac01f29 100644 --- a/firmware/export/dm320.h +++ b/firmware/export/dm320.h @@ -411,9 +411,9 @@ #define IO_CLK_LPCTL0 DM320_REG(0x089E) #define IO_CLK_LPCTL1 DM320_REG(0x08A0) #define IO_CLK_OSEL DM320_REG(0x08A2) -#define IO_CLK_00DIV DM320_REG(0x08A4) +#define IO_CLK_O0DIV DM320_REG(0x08A4) #define IO_CLK_O1DIV DM320_REG(0x08A6) -#define IO_CLK_02DIV DM320_REG(0x08A8) +#define IO_CLK_O2DIV DM320_REG(0x08A8) #define IO_CLK_PWM0C DM320_REG(0x08AA) #define IO_CLK_PWM0H DM320_REG(0x08AC) #define IO_CLK_PWM1C DM320_REG(0x08AE) @@ -838,6 +838,15 @@ #define CLK_MOD2_TMR0 (1 << 1) #define CLK_MOD2_WDT (1 << 0) +#define CLK_SEL1_OSD (1 << 12) +#define CLK_SEL1_CCD (1 << 8) +#define CLK_SEL1_VENCPLL (1 << 4) +#define CLK_SEL1_VENC(x) (x << 0) + +#define CLK_OSEL_O2SEL(x) (x << 8) +#define CLK_OSEL_O1SEL(x) (x << 4) +#define CLK_OSEL_O0SEL(x) (x << 0) + /* * IO_EINTx bits */ @@ -905,4 +914,90 @@ #define INTR_IRQ1_EXT2 INTR_EINT1_EXT2 #define INTR_IRQ1_EXT7 INTR_EINT1_EXT7 +/* +* HPIBCTL bits +*/ +#define HPIBCTL_DBIO (1 << 10) +#define HPIBCTL_DHOLD (1 << 9) +#define HPIBCTL_DRST (1 << 8) +#define HPIBCTL_DINT0 (1 << 7) +#define HPIBCTL_EXCHG (1 << 5) +#define HPIBCTL_HPNMI (1 << 3) +#define HPIBCTL_HPIEN (1 << 0) + +/* +* Video Encoder bits +*/ +#define VENC_VMOD_VDMD(x) (x << 12) +#define VENC_VMOD_ITLC (1 << 10) +#define VENC_VMOD_CBTYP (1 << 9) +#define VENC_VMOD_CBMD (1 << 8) +#define VENC_VMOD_NTPLS(x) (x << 6) +#define VENC_VMOD_SLAVE (1 << 5) +#define VENC_VMOD_VMD (1 << 4) +#define VENC_VMOD_BLNK (1 << 3) +#define VENC_VMOD_DACPD (1 << 2) +#define VENC_VMOD_VIE (1 << 1) +#define VENC_VMOD_VENC (1 << 0) + +#define VENC_VDCTL_VCLKP (1 << 14) +#define VENC_VDCTL_VCLKE (1 << 13) +#define VENC_VDCTL_VCLKZ (1 << 12) +#define VENC_VDCTL_DOMD(x) (x << 4) +#define VENC_VDCTL_YCDC (1 << 2) +#define VENC_VDCTL_INPTRU (1 << 1) +#define VENC_VDCTL_YCDIR (1 << 0) + +#define VENC_VDPRO_PFLTY(x) (x << 12) +#define VENC_VDPRO_PFLTR (1 << 11) +#define VENC_VDPRO_YCDLY(x) (x << 8) +#define VENC_VDPRO_RGBMAT (1 << 7) +#define VENC_VDPRO_ATRGB (1 << 6) +#define VENC_VDPRO_ATYCC (1 << 5) +#define VENC_VDPRO_ATCOM (1 << 4) +#define VENC_VDPRO_STUP (1 << 3) +#define VENC_VDPRO_CRCUT (1 << 2) +#define VENC_VDPRO_CUPS (1 << 1) +#define VENC_VDPRO_YUPS (1 << 0) + +#define VENC_SYNCCTL_EXFEN (1 << 12) +#define VENC_SYNCCTL_EXFIV (1 << 11) +#define VENC_SYNCCTL_EXSYNC (1 << 10) +#define VENC_SYNCCTL_EXVIV (1 << 9) +#define VENC_SYNCCTL_EXHIV (1 << 8) +#define VENC_SYNCCTL_CSP (1 << 7) +#define VENC_SYNCCTL_CSE (1 << 6) +#define VENC_SYNCCTL_SYSW (1 << 5) +#define VENC_SYNCCTL_VSYNCS (1 << 4) +#define VENC_SYNCCTL_VPL (1 << 3) +#define VENC_SYNCCTL_HPL (1 << 2) +#define VENC_SYNCCTL_SYE (1 << 1) +#define VENC_SYNCCTL_SYDIR (1 << 0) + +#define VENC_RGBCTL_IRONM (1 << 11) +#define VENC_RGBCTL_DFLTR (1 << 10) +#define VENC_RGBCTL_DFLTS(x) (x << 8) +#define VENC_RGBCTL_RGBEF(x) (x << 4) +#define VENC_RGBCTL_RGBOF(x) (x << 0) + +#define VENC_RGBCLP_UCLIP(x) (x << 8) +#define VENC_RGBCLP_OFST(x) (x << 0) + +#define VENC_LCDOUT_FIDS (1 << 8) +#define VENC_LCDOUT_FIDP (1 << 7) +#define VENC_LCDOUT_PWMP (1 << 6) +#define VENC_LCDOUT_PWME (1 << 5) +#define VENC_LCDOUT_ACE (1 << 4) +#define VENC_LCDOUT_BRP (1 << 3) +#define VENC_LCDOUT_BRE (1 << 2) +#define VENC_LCDOUT_OEP (1 << 1) +#define VENC_LCDOUT_OEE (1 << 0) + +#define VENC_DCLKCTL_DOFST(x) (x << 12) +#define VENC_DCLKCTL_DCKEC (1 << 11) +#define VENC_DCLKCTL_DCKME (1 << 10) +#define VENC_DCLKCTL_DCKOH (1 << 9) +#define VENC_DCLKCTL_DCKIH (1 << 8) +#define VENC_DCLKCTL_DCKPW(x) (x << 0) + #endif diff --git a/firmware/target/arm/tms320dm320/creative-zvm/lcd-creativezvm.c b/firmware/target/arm/tms320dm320/creative-zvm/lcd-creativezvm.c index 14a9febe59..5ed4054c8c 100644 --- a/firmware/target/arm/tms320dm320/creative-zvm/lcd-creativezvm.c +++ b/firmware/target/arm/tms320dm320/creative-zvm/lcd-creativezvm.c @@ -46,8 +46,7 @@ int lcd_default_contrast(void) void lcd_set_contrast(int val) { - /* iirc there is an ltv250qv command to do this */ - #warning function not implemented + /* find S6F2002 controller datasheet first */ (void)val; } @@ -61,7 +60,6 @@ void lcd_set_flip(bool yesno) { /* TODO: */ } - /* LTV250QV panel functions */ #ifdef ENABLE_DISPLAY_FUNCS static void lcd_write_reg(unsigned char reg, unsigned short val) @@ -161,14 +159,12 @@ static void lcd_display_on(void) lcd_write_reg(9, 0xA55); lcd_write_reg(10, 0x111A); sleep_ms(10); - - /*TODO: other stuff! */ /* tell that we're on now */ display_on = true; } -static void lcd_display_off(void) +void lcd_display_off(void) { display_on = false; @@ -250,6 +246,48 @@ void lcd_init_device(void) /* Clear the Frame */ memset16(FRAME, 0x0000, LCD_WIDTH*LCD_HEIGHT); + +#ifdef ENABLE_DISPLAY_FUNCS + lcd_display_on(); + + /* Set OSD clock */ + IO_CLK_MOD1 &= ~(CLK_MOD1_VENC | CLK_MOD1_OSD); /* disable OSD clock and VENC clock */ + IO_CLK_O2DIV = 3; + + IO_CLK_OSEL &= ~CLK_OSEL_O2SEL(0xF); /* reset 'General purpose clock output (GIO26, GIO34)' and */ + IO_CLK_OSEL |= CLK_OSEL_O2SEL(4); /* set to 'PLLIN clock' */ + + IO_CLK_SEL1 |= (CLK_SEL1_OSD | CLK_SEL1_VENC(7)); /* set to 'GP clock output 2 (GIO26, GIO34)' and turn on 'VENC clock' */ + IO_CLK_MOD1 |= (CLK_MOD1_VENC | CLK_MOD1_OSD); /* enable OSD clock and VENC clock */ + + /* Set LCD values in Video Encoder */ + IO_VID_ENC_VMOD &= 0x8800; /* Clear all values */ + IO_VID_ENC_VMOD |= (VENC_VMOD_DACPD | VENC_VMOD_VMD | VENC_VMOD_ITLC | VENC_VMOD_VDMD(2)); /* set mode to RGB666 parallel 16 bit */ + IO_VID_ENC_VDTL &= 8FE8; /* Clear all values */ + IO_VID_ENC_VDCTL |= (VENC_VDCTL_VCLKP | VENC_VDCTL_DOMD(2)), + IO_VID_ENC_VPRO = VENC_VDPRO_PFLTR; + IO_VID_ENC_SYNCCTL &= 0xE000; /* Clear all values */ + IO_VID_ENC_SYNCCTL |= (VENC_SYNCCTL_VPL | VENC_SYNCCTL_HPL); + IO_VID_ENC_HSDLY = 0; + IO_VID_ENC_HSPLS = 0x12; + IO_VID_ENC_HSTART = 0x1B; + IO_VID_ENC_HVALID = 0x140; + IO_VID_ENC_HINT = 0x168; + IO_VID_ENC_VSDLY = 0; + IO_VID_ENC_VSPLS = 3; + IO_VID_ENC_VSTART = 5; + IO_VID_ENC_VVALID = 0xF0; + IO_VID_ENC_VINT = 0x118; + IO_VID_ENC_RGBCTL &= 0x088; /* Clear all values */ + IO_VID_ENC_RGBCTL |= VENC_RGBCTL_DFLTR; + IO_VID_ENC_RGBCLP = VENC_RGBCLP_UCLIP(0xFF); + IO_VID_ENC_LCDOUT &= 0xFE00; /* Clear all values */ + IO_VID_ENC_LCDOUT |= (VENC_LCDOUT_OEE | VENC_LCDOUT_FIDS); + IO_VID_ENC_DCLKCTL &= 0xC0C0; /* Clear all values */ + IO_VID_ENC_DCLKCTL |= VENC_DCLKCTL_DCKEC; + IO_VID_ENC_DCLKPTN0 = 1; + DM320_REG(0x0864) = 0; /* ???? */ +#endif IO_OSD_MODE = 0x00ff; IO_OSD_VIDWINMD = 0x0002; @@ -264,35 +302,23 @@ void lcd_init_device(void) IO_OSD_OSDWIN0ADL = addr & 0xFFFF; #ifndef ZEN_VISION - IO_OSD_BASEPX=26; - IO_OSD_BASEPY=5; + IO_OSD_BASEPX = 26; + IO_OSD_BASEPY = 5; #else - IO_OSD_BASEPX=80; - IO_OSD_BASEPY=0; + IO_OSD_BASEPX = 80; + IO_OSD_BASEPY = 0; #endif IO_OSD_OSDWIN0XP = 0; IO_OSD_OSDWIN0YP = 0; IO_OSD_OSDWIN0XL = LCD_WIDTH; IO_OSD_OSDWIN0YL = LCD_HEIGHT; -#if 0 - /*TODO: set LCD clock! */ - IO_CLK_MOD1 &= ~0x18; /* disable OSD clock and VENC clock */ - IO_CLK_02DIV = 3; - - /* reset 'General purpose clock output (GIO26, GIO34)' and set to 'PLLIN - clock' */ - IO_CLK_OSEL = (IO_CLK_OSEL & ~0xF00) | 0x400; - - /* set to 'GP clock output 2 (GIO26, GIO34)' and turn on 'VENC clock' */ - IO_CLK_SEL1 = (IO_CLK_SEL1 | 7) | 0x1000; - IO_CLK_MOD1 |= 0x18; /* enable OSD clock and VENC clock */ - - /* Set LCD values in OSD */ - /* disable NTSC/PAL encoder & set mode to RGB666 parallel 18 bit */ - IO_VID_ENC_VMOD = ( ( (IO_VID_ENC_VMOD & 0xFFFF8C00) | 0x14) | 0x2400 ); - IO_VID_ENC_VDCTL = ( ( (IO_VID_ENC_VDCTL & 0xFFFFCFE8) | 0x20) | 0x4000 ); - /* TODO: finish this... */ + +#ifdef ENABLE_DISPLAY_FUNCS + IO_VID_ENC_VDCTL |= VENC_VDCTL_VCLKE; /* Enable VCLK */ + IO_VID_ENC_VMOD |= VENC_VMOD_VENC; /* Enable video encoder */ + IO_VID_ENC_SYNCCTL |= VENC_SYNCCTL_SYE; /* Enable sync output */ + IO_VID_ENC_VDCTL &= ~VENC_VDCTL_DOMD(3); /* Normal digital data output */ #endif } -- cgit v1.2.3