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-rw-r--r--utils/regtools/desc/regs-rk27xx.xml1387
1 files changed, 1387 insertions, 0 deletions
diff --git a/utils/regtools/desc/regs-rk27xx.xml b/utils/regtools/desc/regs-rk27xx.xml
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+++ b/utils/regtools/desc/regs-rk27xx.xml
@@ -0,0 +1,1387 @@
1<?xml version="1.0"?>
2<!--
3 __________ __ ___.
4 Open \______ \ ____ ____ | | _\_ |__ _______ ___
5 Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
6 Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
7 Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
8 \/ \/ \/ \/ \/
9Copyright (C) 2013 by Marcin Bukat
10
11This program is free software; you can redistribute it and/or
12modify it under the terms of the GNU General Public License
13as published by the Free Software Foundation; either version 2
14of the License, or (at your option) any later version.
15
16This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
17KIND, either express or implied.
18-->
19<soc name="rk27xx" desc="Rockchip rk27xx">
20 <dev name="TIMER" long_name="TIMER" desc="Timer module" version="1.0">
21 <addr name="TIMER0" addr="0x18000000" />
22 <addr name="TIMER1" addr="0x18000010" />
23 <addr name="TIMER2" addr="0x18000020" />
24 <reg name="TMRnLR">
25 <formula string="n*0x10" />
26 <addr name="TMR0LR" addr="0x00" />
27 <addr name="TMR1LR" addr="0x10" />
28 <addr name="TMR2LR" addr="0x20" />
29 </reg>
30 <reg name="TMRnCVR">
31 <formula string="0x04+n*0x10" />
32 <addr name="TMR0CVR" addr="0x04" />
33 <addr name="TMR1CVR" addr="0x14" />
34 <addr name="TMR2CVR" addr="0x24" />
35 </reg>
36 <reg name="TMRnCON">
37 <formula string="0x08+n*0x10" />
38 <addr name="TMR0CON" addr="0x08" />
39 <addr name="TMR1CON" addr="0x18" />
40 <addr name="TMR2CON" addr="0x28" />
41 </reg>
42 </dev>
43 <dev name="UART" long_name="UART" desc="UART" version="1.0">
44 <addr name="UART0" addr="0x18004000" />
45 <addr name="UART1" addr="0x18008000" />
46 <reg name="UARTn_RBR" addr="0x00">
47 <formula string="n*0x4000" />
48 <addr name="UART0_RBR" addr="0x00" />
49 <addr name="UART1_RBR" addr="0x4000" />
50 </reg>
51 <reg name="UARTn_THR" addr="0x00">
52 <formula string="n*0x4000" />
53 <addr name="UART0_THR" addr="0x00" />
54 <addr name="UART1_THR" addr="0x4000" />
55 </reg>
56 <reg name="UARTn_DLL" addr="0x00">
57 <formula string="n*0x4000" />
58 <addr name="UART0_DLL" addr="0x00" />
59 <addr name="UART1_DLL" addr="0x4000" />
60 </reg>
61 <reg name="UARTn_DLH" addr="0x04">
62 <formula string="0x04+n*0x4000" />
63 <addr name="UART0_DLH" addr="0x04" />
64 <addr name="UART1_DLH" addr="0x4004" />
65 </reg>
66 <reg name="UARTn_IER" addr="0x04">
67 <formula string="0x04+n*0x4000" />
68 <addr name="UART0_IER" addr="0x04" />
69 <addr name="UART1_IER" addr="0x4004" />
70 </reg>
71 <reg name="UARTn_IIR" addr="0x08">
72 <formula string="0x08+n*0x4000" />
73 <addr name="UART0_IIR" addr="0x08" />
74 <addr name="UART1_IIR" addr="0x4008" />
75 </reg>
76 <reg name="UARTn_FCR" addr="0x08">
77 <formula string="0x08+n*0x4000" />
78 <addr name="UART0_FCR" addr="0x08" />
79 <addr name="UART1_FCR" addr="0x4008" />
80 </reg>
81 <reg name="UARTn_LCR" addr="0x0c">
82 <formula string="0x0c+n*0x4000" />
83 <addr name="UART0_LCR" addr="0x0c" />
84 <addr name="UART1_LCR" addr="0x400c" />
85 </reg>
86 <reg name="UARTn_MCR" addr="0x10">
87 <formula string="0x10+n*0x4000" />
88 <addr name="UART0_MCR" addr="0x10" />
89 <addr name="UART1_MCR" addr="0x4010" />
90 </reg>
91 <reg name="UARTn_LSR" addr="0x14">
92 <formula string="0x14+n*0x4000" />
93 <addr name="UART0_LSR" addr="0x14" />
94 <addr name="UART1_LSR" addr="0x4014" />
95 </reg>
96 <reg name="UARTn_MSR" addr="0x18">
97 <formula string="0x18+n*0x4000" />
98 <addr name="UART0_MSR" addr="0x18" />
99 <addr name="UART1_MSR" addr="0x4018" />
100 </reg>
101 </dev>
102 <dev name="GPIO" long_name="GPIO" desc="GPIO" version="1.0">
103 <addr name="GPIO0" addr="0x1800c000" />
104 <reg name="GPIO_PADR" addr="0x00">
105 </reg>
106 <reg name="GPIO_PACON" addr="0x04">
107 </reg>
108 <reg name="GPIO_PBDR" addr="0x08">
109 </reg>
110 <reg name="GPIO_PBCON" addr="0x0c">
111 </reg>
112 <reg name="GPIO_PCDR" addr="0x10">
113 </reg>
114 <reg name="GPIO_PCCON" addr="0x14">
115 </reg>
116 <reg name="GPIO_PDDR" addr="0x18">
117 </reg>
118 <reg name="GPIO_PDCON" addr="0x1c">
119 </reg>
120 <reg name="GPIO_TEST" addr="0x20">
121 </reg>
122 <reg name="GPIO_IEA" addr="0x24">
123 </reg>
124 <reg name="GPIO_IEB" addr="0x28">
125 </reg>
126 <reg name="GPIO_IEC" addr="0x2c">
127 </reg>
128 <reg name="GPIO_IED" addr="0x30">
129 </reg>
130 <reg name="GPIO_ISA" addr="0x34">
131 </reg>
132 <reg name="GPIO_ISB" addr="0x38">
133 </reg>
134 <reg name="GPIO_ISC" addr="0x3c">
135 </reg>
136 <reg name="GPIO_ISD" addr="0x40">
137 </reg>
138 <reg name="GPIO_IBEA" addr="0x44">
139 </reg>
140 <reg name="GPIO_IBEB" addr="0x48">
141 </reg>
142 <reg name="GPIO_IBEC" addr="0x4c">
143 </reg>
144 <reg name="GPIO_IBED" addr="0x50">
145 </reg>
146 <reg name="GPIO_IEVA" addr="0x54">
147 </reg>
148 <reg name="GPIO_IEVB" addr="0x58">
149 </reg>
150 <reg name="GPIO_IEVC" addr="0x5c">
151 </reg>
152 <reg name="GPIO_IEVD" addr="0x60">
153 </reg>
154 <reg name="GPIO_ICA" addr="0x64">
155 </reg>
156 <reg name="GPIO_ICB" addr="0x68">
157 </reg>
158 <reg name="GPIO_ICC" addr="0x6c">
159 </reg>
160 <reg name="GPIO_ICD" addr="0x70">
161 </reg>
162 <reg name="GPIO_ISR" addr="0x74">
163 </reg>
164 </dev>
165 <dev name="WDT" long_name="Watchdog" desc="Watchdog" version="1.0">
166 <addr name="WDT" addr="0x18010000" />
167 <reg name="WDTLR" addr="0x00">
168 </reg>
169 <reg name="WDTCVR" addr="0x04">
170 </reg>
171 <reg name="WDTCON" addr="0x08">
172 </reg>
173 </dev>
174 <dev name="RTC" long_name="Real time clock" desc="Real time clock" version="1.0">
175 <addr name="RTC" addr="0x18014000" />
176 <reg name="RTC_TIME" addr="0x00">
177 </reg>
178 <reg name="RTC_DATE" addr="0x04">
179 </reg>
180 <reg name="RTC_TALARM" addr="0x08">
181 </reg>
182 <reg name="RTC_DALARM" addr="0x0c">
183 </reg>
184 <reg name="RTC_CTRL" addr="0x10">
185 </reg>
186 <reg name="RTC_RESET" addr="0x14">
187 </reg>
188 <reg name="RTC_PWOFF" addr="0x18">
189 </reg>
190 <reg name="RTC_PWFAIL" addr="0x1c">
191 </reg>
192 </dev>
193 <dev name="SPI" long_name="Serial peripherial interface" desc="Serial peripherial interface" version="1.0">
194 <addr name="SPI" addr="0x18018000" />
195 <reg name="SPI_TXR" addr="0x00">
196 </reg>
197 <reg name="SPI_RXR" addr="0x00">
198 </reg>
199 <reg name="SPI_IER" addr="0x04">
200 </reg>
201 <reg name="SPI_FCR" addr="0x08">
202 </reg>
203 <reg name="SPI_FWCR" addr="0x0c">
204 </reg>
205 <reg name="SPI_DLYCR" addr="0x10">
206 </reg>
207 <reg name="SPI_TXCR" addr="0x14">
208 </reg>
209 <reg name="SPI_RXCR" addr="0x18">
210 </reg>
211 <reg name="SPI_SSCR" addr="0x1c">
212 </reg>
213 <reg name="SPI_ISR" addr="0x20">
214 </reg>
215 </dev>
216 <dev name="SCU" long_name="System control unit" desc="System control unit" version="1.0">
217 <addr name="SCU" addr="0x1801c000" />
218 <reg name="SCU_ID" addr="0x00">
219 <field name="SOC_ID" bitrange="31:0">
220 <value name="REVISION_A" value="0xa1000604" />
221 <value name="REVISION_B" value="0xa100027b" />
222 </field>
223 </reg>
224 <reg name="SCU_REMAP" addr="0x04">
225 <field name="MEM_REMAP" bitrange="31:0">
226 <value name="IRAM_0x000000" value="0xdeadbeef" />
227 <value name="ROM_0x000000" value="0x00000000" />
228 </field>
229 </reg>
230 <reg name="SCU_PLLCON1" addr="0x08">
231 <field name="ARM_PLL_TEST_CONTROL" bitrange="25:25">
232 <value name="TEST" value="0x01" />
233 <value name="NORMAL" value="0x00" />
234 </field>
235 <field name="ARM_PLL_SATURATION" bitrange="24:24">
236 <value name="ENABLE" value="0x01" />
237 <value name="DISABLE" value="0x00" />
238 </field>
239 <field name="ARM_PLL_FAST_LOCK" bitrange="23:23">
240 <value name="ENABLE" value="0x01" />
241 <value name="DISABLE" value="0x00" />
242 </field>
243 <field name="ARM_PLL_POWERDOWN" bitrange="22:22">
244 <value name="PLL_OFF" value="0x01" />
245 <value name="PLL_ON" value="0x00" />
246 </field>
247 <field name="ARM_PLL_CLKR" bitrange="21:16"></field>
248 <field name="ARM_PLL_CLKF" bitrange="15:4"></field>
249 <field name="ARM_PLL_CLKOD" bitrange="3:1"></field>
250 <field name="ARM_PLL_BYPASS" bitrange="0:0">
251 <value name="ENABLE" value="0x01" />
252 <value name="DISABLE" value="0x00" />
253 </field>
254 </reg>
255 <reg name="SCU_PLLCON2" addr="0x0c">
256 <field name="DSP_PLL_TEST_CONTROL" bitrange="25:25">
257 <value name="TEST" value="0x01" />
258 <value name="NORMAL" value="0x00" />
259 </field>
260 <field name="DSP_PLL_SATURATION" bitrange="24:24">
261 <value name="ENABLE" value="0x01" />
262 <value name="DISABLE" value="0x00" />
263 </field>
264 <field name="DSP_PLL_FAST_LOCK" bitrange="23:23">
265 <value name="ENABLE" value="0x01" />
266 <value name="DISABLE" value="0x00" />
267 </field>
268 <field name="DSP_PLL_POWERDOWN" bitrange="22:22">
269 <value name="PLL_OFF" value="0x01" />
270 <value name="PLL_ON" value="0x00" />
271 </field>
272 <field name="DSP_PLL_CLKR" bitrange="21:16"></field>
273 <field name="DSP_PLL_CLKF" bitrange="15:4"></field>
274 <field name="DSP_PLL_CLKOD" bitrange="3:1"></field>
275 <field name="DSP_PLL_BYPASS" bitrange="0:0">
276 <value name="ENABLE" value="0x01" />
277 <value name="DISABLE" value="0x00" />
278 </field>
279 </reg>
280 <reg name="SCU_PLLCON3" addr="0x10">
281 <field name="CODEC_PLL_TEST_CONTROL" bitrange="25:25">
282 <value name="TEST" value="0x01" />
283 <value name="NORMAL" value="0x00" />
284 </field>
285 <field name="CODEC_PLL_SATURATION" bitrange="24:24">
286 <value name="ENABLE" value="0x01" />
287 <value name="DISABLE" value="0x00" />
288 </field>
289 <field name="CODEC_PLL_FAST_LOCK" bitrange="23:23">
290 <value name="ENABLE" value="0x01" />
291 <value name="DISABLE" value="0x00" />
292 </field>
293 <field name="CODEC_PLL_POWERDOWN" bitrange="22:22">
294 <value name="PLL_OFF" value="0x01" />
295 <value name="PLL_ON" value="0x00" />
296 </field>
297 <field name="CODEC_PLL_CLKR" bitrange="21:16"></field>
298 <field name="CODEC_PLL_CLKF" bitrange="15:4"></field>
299 <field name="CODEC_PLL_CLKOD" bitrange="3:1"></field>
300 <field name="CODEC_PLL_BYPASS" bitrange="0:0">
301 <value name="ENABLE" value="0x01" />
302 <value name="DISABLE" value="0x00" />
303 </field>
304 </reg>
305 <reg name="SCU_DIVCON1" addr="0x14">
306 <field name="USB_PHY_CLK" bitrange="31:31">
307 <value name="12MHz" value="0x01" />
308 <value name="24MHz" value="0x00" />
309 </field>
310 <field name="VIP_SENSOR_CLK" bitrange="30:29">
311 <value name="27MHz" value="0x02" />
312 <value name="48MHz" value="0x01" />
313 <value name="24MHz" value="0x00" />
314 </field>
315 <field name="LCDC_CLK" bitrange="28:28">
316 <value name="LCDC_CLK_DIV_OUT" value="0x01" />
317 <value name="EXT_SOC_27MHz" value="0x00" />
318 </field>
319 <field name="LCDC_CLK_DIV" bitrange="27:20"></field>
320 <field name="LCDC_CLK_DIV_SRC" bitrange="19:18">
321 <value name="CODEC_PLL" value="0x02" />
322 <value name="DSP_PLL" value="0x01" />
323 <value name="ARM_PLL" value="0x00" />
324 </field>
325 <field name="LSADC_CLK_DIV" bitrange="17:10"></field>
326 <field name="CODEC_CLK_SRC" bitrange="9:9">
327 <value name="12MHz_OSC" value="0x01" />
328 <value name="CODEC_CLK_DIV_OUT" value="0x00" />
329 </field>
330 <field name="CODEC_CLK_DIV" bitrange="8:5"></field>
331 <field name="PCLK_CLK_DIV" bitrange="4:3">
332 <value name="HCLK/PCLK_4:1" value="0x02" />
333 <value name="HCLK/PCLK_2:1" value="0x01" />
334 <value name="HCLK/PCLK_1:1" value="0x00" />
335 </field>
336 <field name="ARM_CLK_DIV" bitrange="2:2">
337 <value name="ARMPLL/ARMCLK_2:1" value="0x01" />
338 <value name="ARMPLL/ARMCLK_1:1" value="0x00" />
339 </field>
340 <field name="DSP_SLOW_MODE" bitrange="1:1">
341 <value name="ENABLE" value="0x01" />
342 <value name="DISABLE" value="0x00" />
343 </field>
344 <field name="ARM_SLOW_MODE" bitrange="0:0">
345 <value name="ENABLE" value="0x01" />
346 <value name="DISABLE" value="0x00" />
347 </field>
348 </reg>
349 <reg name="SCU_CLKCFG" addr="0x18">
350 <field name="WDT_PCLK" bitrange="31:31">
351 <value name="GATE" value="0x01" />
352 <value name="UNGATE" value="0x00" />
353 </field>
354 <field name="RTC_PCLK" bitrange="30:30">
355 <value name="GATE" value="0x01" />
356 <value name="UNGATE" value="0x00" />
357 </field>
358 <field name="PWM_PCLK" bitrange="29:29">
359 <value name="GATE" value="0x01" />
360 <value name="UNGATE" value="0x00" />
361 </field>
362 <field name="TIMER_PCLK" bitrange="28:28">
363 <value name="GATE" value="0x01" />
364 <value name="UNGATE" value="0x00" />
365 </field>
366 <field name="GPIO_PCLK" bitrange="27:27">
367 <value name="GATE" value="0x01" />
368 <value name="UNGATE" value="0x00" />
369 </field>
370 <field name="HSADC_PCLK" bitrange="26:26">
371 <value name="GATE" value="0x01" />
372 <value name="UNGATE" value="0x00" />
373 </field>
374 <field name="HSADC_HCLK" bitrange="25:25">
375 <value name="GATE" value="0x01" />
376 <value name="UNGATE" value="0x00" />
377 </field>
378 <field name="LSADC_CLK" bitrange="24:24">
379 <value name="GATE" value="0x01" />
380 <value name="UNGATE" value="0x00" />
381 </field>
382 <field name="LSADC_PCLK" bitrange="23:23">
383 <value name="GATE" value="0x01" />
384 <value name="UNGATE" value="0x00" />
385 </field>
386 <field name="SD_CLK" bitrange="22:22">
387 <value name="GATE" value="0x01" />
388 <value name="UNGATE" value="0x00" />
389 </field>
390 <field name="SPI_CLK" bitrange="21:21">
391 <value name="GATE" value="0x01" />
392 <value name="UNGATE" value="0x00" />
393 </field>
394 <field name="I2C_CLK" bitrange="20:20">
395 <value name="GATE" value="0x01" />
396 <value name="UNGATE" value="0x00" />
397 </field>
398 <field name="UART1_CLK" bitrange="19:19">
399 <value name="GATE" value="0x01" />
400 <value name="UNGATE" value="0x00" />
401 </field>
402 <field name="UART0_CLK" bitrange="18:18">
403 <value name="GATE" value="0x01" />
404 <value name="UNGATE" value="0x00" />
405 </field>
406 <field name="I2S_PCLK" bitrange="17:17">
407 <value name="GATE" value="0x01" />
408 <value name="UNGATE" value="0x00" />
409 </field>
410 <field name="I2S_CLK" bitrange="16:16">
411 <value name="GATE" value="0x01" />
412 <value name="UNGATE" value="0x00" />
413 </field>
414 <field name="VIP_CLK" bitrange="15:15">
415 <value name="GATE" value="0x01" />
416 <value name="UNGATE" value="0x00" />
417 </field>
418 <field name="VIP_HCLK" bitrange="14:14">
419 <value name="GATE" value="0x01" />
420 <value name="UNGATE" value="0x00" />
421 </field>
422 <field name="LCDC_CLK" bitrange="13:13">
423 <value name="GATE" value="0x01" />
424 <value name="UNGATE" value="0x00" />
425 </field>
426 <field name="LCDC_HCLK" bitrange="12:12">
427 <value name="GATE" value="0x01" />
428 <value name="UNGATE" value="0x00" />
429 </field>
430 <field name="IRAM_HCLK" bitrange="11:11">
431 <value name="GATE" value="0x01" />
432 <value name="UNGATE" value="0x00" />
433 </field>
434 <field name="A2A_HCLK" bitrange="10:10">
435 <value name="GATE" value="0x01" />
436 <value name="UNGATE" value="0x00" />
437 </field>
438 <field name="NANDC_HCLK" bitrange="9:9">
439 <value name="GATE" value="0x01" />
440 <value name="UNGATE" value="0x00" />
441 </field>
442 <field name="UDC_CLK" bitrange="6:6">
443 <value name="GATE" value="0x01" />
444 <value name="UNGATE" value="0x00" />
445 </field>
446 <field name="UHC_CLK" bitrange="5:5">
447 <value name="GATE" value="0x01" />
448 <value name="UNGATE" value="0x00" />
449 </field>
450 <field name="DWDMA_CLK" bitrange="4:4">
451 <value name="GATE" value="0x01" />
452 <value name="UNGATE" value="0x00" />
453 </field>
454 <field name="HDMA_CLK" bitrange="3:3">
455 <value name="GATE" value="0x01" />
456 <value name="UNGATE" value="0x00" />
457 </field>
458 <field name="SDRAM_HCLK" bitrange="2:2">
459 <value name="GATE" value="0x01" />
460 <value name="UNGATE" value="0x00" />
461 </field>
462 <field name="DSP_CLK" bitrange="1:1">
463 <value name="GATE" value="0x01" />
464 <value name="UNGATE" value="0x00" />
465 </field>
466 <field name="OTP_CLK" bitrange="0:0">
467 <value name="GATE" value="0x01" />
468 <value name="UNGATE" value="0x00" />
469 </field>
470 </reg>
471 <reg name="SCU_RSTCFG" addr="0x1c">
472 <field name="ARM_RST" bitrange="12:12">
473 <value name="ASSERT" value="0x01" />
474 <value name="DEASSERT" value="0x00" />
475 </field>
476 <field name="DUALCORE_ECT_RST" bitrange="11:11">
477 <value name="ASSERT" value="0x01" />
478 <value name="DEASSERT" value="0x00" />
479 </field>
480 <field name="DUALCORE_MAILBOX_RST" bitrange="10:10">
481 <value name="ASSERT" value="0x01" />
482 <value name="DEASSERT" value="0x00" />
483 </field>
484 <field name="SD_RST" bitrange="9:9">
485 <value name="ASSERT" value="0x01" />
486 <value name="DEASSERT" value="0x00" />
487 </field>
488 <field name="HSADC_RST" bitrange="8:8">
489 <value name="ASSERT" value="0x01" />
490 <value name="DEASSERT" value="0x00" />
491 </field>
492 <field name="LSADC_RST" bitrange="7:7">
493 <value name="ASSERT" value="0x01" />
494 <value name="DEASSERT" value="0x00" />
495 </field>
496 <field name="CODEC_RST" bitrange="6:6">
497 <value name="ASSERT" value="0x01" />
498 <value name="DEASSERT" value="0x00" />
499 </field>
500 <field name="DSP_PERIPHERAL_RST" bitrange="5:5">
501 <value name="ASSERT" value="0x01" />
502 <value name="DEASSERT" value="0x00" />
503 </field>
504 <field name="DSP_CORE_RST" bitrange="4:4">
505 <value name="ASSERT" value="0x01" />
506 <value name="DEASSERT" value="0x00" />
507 </field>
508 <field name="VIP_RST" bitrange="3:3">
509 <value name="ASSERT" value="0x01" />
510 <value name="DEASSERT" value="0x00" />
511 </field>
512 <field name="LCDC_RST" bitrange="2:2">
513 <value name="ASSERT" value="0x01" />
514 <value name="DEASSERT" value="0x00" />
515 </field>
516 <field name="UDC_RST" bitrange="1:1">
517 <value name="ASSERT" value="0x01" />
518 <value name="DEASSERT" value="0x00" />
519 </field>
520 <field name="UHC_RST" bitrange="0:0">
521 <value name="ASSERT" value="0x01" />
522 <value name="DEASSERT" value="0x00" />
523 </field>
524 </reg>
525 <reg name="SCU_PWM" addr="0x20">
526 <field name="PLL_LOCK_PERIOD" bitrange="31:16"></field>
527 <field name="EXT_WAKEUP_PIN_POLARITY" bitrange="6:6">
528 <value name="NEGATIVE" value="0x01" />
529 <value name="POSITIVE" value="0x00" />
530 </field>
531 <field name="RTC_ALARM_WAKEUP" bitrange="5:5">
532 <value name="DISABLE" value="0x01" />
533 <value name="ENABLE" value="0x00" />
534 </field>
535 <field name="EXT_WAKEUP" bitrange="4:4">
536 <value name="DISABLE" value="0x01" />
537 <value name="ENABLE" value="0x00" />
538 </field>
539 <field name="SCU_IRQ_CLEAR" bitrange="3:3">
540 <value name="CLEAR" value="0x01" />
541 <value name="PENDING" value="0x00" />
542 </field>
543 <field name="POWERMANAGEMENT_MODE" bitrange="2:0">
544 <value name="STOP" value="0x08" />
545 <value name="NORMAL" value="0x00" />
546 </field>
547 </reg>
548 <reg name="SCU_CPUPD" addr="0x24"></reg>
549 <reg name="SCU_CHIPCFG" addr="0x28">
550 <field name="NOR_FLASH_BUSWIDTH" bitrange="19:19">
551 <value name="8BIT" value="0x01" />
552 <value name="16BIT" value="0x00" />
553 </field>
554 <field name="DSP2ARM_IRQ" bitrange="17:17"></field>
555 <field name="ARM2DSP_IRQ" bitrange="16:16"></field>
556 <field name="ARM_HIGHVECTOR" bitrange="3:3"></field>
557 <field name="UHC_DATABUS_WIDTH" bitrange="2:2">
558 <value name="16BIT" value="0x01" />
559 <value name="8BIT" value="0x00" />
560 </field>
561 <field name="USB_PHY_MUX" bitrange="1:1">
562 <value name="USB_PHY_UHC" value="0x01" />
563 <value name="USB_PHY_UDC" value="0x00" />
564 </field>
565 </reg>
566 <reg name="SCU_STATUS" addr="0x2c">
567 <field name="DSPSYSCLKVALID" bitrange="4:4">
568 <value name="VALID" value="0x01" />
569 <value name="UNSTABLE" value="0x00" />
570 </field>
571 <field name="ARMSYSCLKVALID" bitrange="3:3">
572 <value name="VALID" value="0x01" />
573 <value name="UNSTABLE" value="0x00" />
574 </field>
575 <field name="CODEC_PLL_LOCKED" bitrange="2:2">
576 <value name="LOCKED" value="0x01" />
577 <value name="UNSTABLE" value="0x00" />
578 </field>
579 <field name="DSP_PLL_LOCKED" bitrange="1:1">
580 <value name="LOCKED" value="0x01" />
581 <value name="UNSTABLE" value="0x00" />
582 </field>
583 <field name="ARM_PLL_LOCKED" bitrange="0:0">
584 <value name="LOCKED" value="0x01" />
585 <value name="UNSTABLE" value="0x00" />
586 </field>
587 </reg>
588 <reg name="SCU_IOMUXA_CON" addr="0x30">
589 <field name="I2S_CODEC_EXT_SEL" bitrange="19:19">
590 <value name="PIN" value="0x01" />
591 <value name="INTERNAL_CODEC" value="0x00" />
592 </field>
593 <field name="I2C_CODEC_EXT_SEL" bitrange="18:18">
594 <value name="PIN" value="0x01" />
595 <value name="INTERNAL_CODEC" value="0x00" />
596 </field>
597 <field name="I2C_FLASHCS3_GPIOB_SEL" bitrange="17:16">
598 <value name="GPIOB7" value="0x02" />
599 <value name="FLASH_CS3" value="0x01" />
600 <value name="I2C_SDA" value="0x00" />
601 </field>
602 <field name="I2C_FLASHCS2_GPIOB_SEL" bitrange="15:14">
603 <value name="GPIOB6" value="0x02" />
604 <value name="FLASH_CS2" value="0x01" />
605 <value name="I2C_SCL" value="0x00" />
606 </field>
607 <field name="GPIOB_SD_SPI_SEL" bitrange="13:12">
608 <value name="SPI" value="0x02" />
609 <value name="SD" value="0x01" />
610 <value name="GPIOB[0:5]" value="0x00" />
611 </field>
612 <field name="GPIO_LCDVSYN_SEL" bitrange="11:11">
613 <value name="LCD_VSYN" value="0x01" />
614 <value name="GPIOA7" value="0x00" />
615 </field>
616 <field name="GPIO_LCDEN_SEL" bitrange="10:10">
617 <value name="LCD_DATA_ENABLE" value="0x01" />
618 <value name="GPIOA6" value="0x00" />
619 </field>
620 <field name="GPIO_FLASHCS1_SEL" bitrange="9:9">
621 <value name="FLASH_CS1" value="0x01" />
622 <value name="GPIOA5" value="0x00" />
623 </field>
624 <field name="GPIO_LCD22_SEL" bitrange="8:8">
625 <value name="LCD_DATA22" value="0x01" />
626 <value name="GPIOA4" value="0x00" />
627 </field>
628 <field name="GPIOA_LCD20_NRTS0_SEL" bitrange="7:6">
629 <value name="UART0_NRTS" value="0x02" />
630 <value name="LCD_DATA20" value="0x01" />
631 <value name="GPIOA3" value="0x00" />
632 </field>
633 <field name="GPIOA_LCD18_NCTS0_SEL" bitrange="5:4">
634 <value name="UART0_NCTS" value="0x02" />
635 <value name="LCD_DATA18" value="0x01" />
636 <value name="GPIOA2" value="0x00" />
637 </field>
638 <field name="GPIOA_LCD17_TXD0_SEL" bitrange="3:2">
639 <value name="UART0_TXD" value="0x02" />
640 <value name="LCD_DATA17" value="0x01" />
641 <value name="GPIOA1" value="0x00" />
642 </field>
643 <field name="GPIOA_LCD16_RXD0_SEL" bitrange="1:0">
644 <value name="UART0_RXD" value="0x02" />
645 <value name="LCD_DATA16" value="0x01" />
646 <value name="GPIOA0" value="0x00" />
647 </field>
648 </reg>
649 <reg name="SCU_IOMUXB_CON" addr="0x34">
650 <field name="VIP_HSADC_SEL" bitrange="22:22">
651 <value name="HSADC" value="0x01" />
652 <value name="VIP" value="0x00" />
653 </field>
654 <field name="GPIOD_SDCKE_SEL" bitrange="21:21">
655 <value name="SDRAM_CKE" value="0x01" />
656 <value name="GPIOD3" value="0x00" />
657 </field>
658 <field name="GPIOF_UHCVBUS_SEL" bitrange="20:20">
659 <value name="UHC_VBUS" value="0x01" />
660 <value name="GPIOF4" value="0x00" />
661 </field>
662 <field name="GPIOF_UHCOCUR_SEL" bitrange="19:19">
663 <value name="UHC_OCUR" value="0x01" />
664 <value name="GPIOF3" value="0x00" />
665 </field>
666 <field name="SDTADDR12_GPIOF_SEL" bitrange="18:18">
667 <value name="GPIOF2" value="0x01" />
668 <value name="SDT_ADDR12" value="0x00" />
669 </field>
670 <field name="SDTADDR11_GPIOF_SEL" bitrange="17:17">
671 <value name="GPIOF1" value="0x01" />
672 <value name="SDT_ADDR11" value="0x00" />
673 </field>
674 <field name="GPIOF_VIPCLK_SEL" bitrange="16:16">
675 <value name="VIP_CLK" value="0x01" />
676 <value name="GPIOF0" value="0x00" />
677 </field>
678 <field name="GPIOE_LCD_SEL" bitrange="15:15">
679 <value name="LCD_DATA[8:15]" value="0x01" />
680 <value name="GPIOE[0:7]" value="0x00" />
681 </field>
682 <field name="GPIOD_PWM3_SEL" bitrange="14:14">
683 <value name="PWM3" value="0x01" />
684 <value name="GPIOD7" value="0x00" />
685 </field>
686 <field name="GPIOD_PWM2_SEL" bitrange="13:13">
687 <value name="PWM2" value="0x01" />
688 <value name="GPIOD6" value="0x00" />
689 </field>
690 <field name="GPIOD_PWM1_SEL" bitrange="12:12">
691 <value name="PWM1" value="0x01" />
692 <value name="GPIOD5" value="0x00" />
693 </field>
694 <field name="GPIOD_PWM0_SEL" bitrange="11:11">
695 <value name="PWM0" value="0x01" />
696 <value name="GPIOD4" value="0x00" />
697 </field>
698 <field name="GPIOD_SDWPA_SEL" bitrange="10:10">
699 <value name="SD_WPA" value="0x01" />
700 <value name="GPIOD2" value="0x00" />
701 </field>
702 <field name="GPIOD_SDCDA_RXD1_SEL" bitrange="9:8">
703 <value name="UART1_RXD" value="0x02" />
704 <value name="SD_CDA" value="0x01" />
705 <value name="GPIOD1" value="0x00" />
706 </field>
707 <field name="GPIOD_SDPCA_TXD1_SEL" bitrange="7:6">
708 <value name="UART1_RXD" value="0x02" />
709 <value name="SD_PCA" value="0x01" />
710 <value name="GPIOD0" value="0x00" />
711 </field>
712 <field name="GPIOC_STCS1_SEL" bitrange="5:5">
713 <value name="ST_CS1" value="0x01" />
714 <value name="GPIOC7" value="0x00" />
715 </field>
716 <field name="GPIOC_I2SCLK1_SEL" bitrange="4:4">
717 <value name="I2S_CLK" value="0x01" />
718 <value name="GPIOC6" value="0x00" />
719 </field>
720 <field name="GPIOC_I2SSDO_SEL" bitrange="3:3">
721 <value name="I2S_SDO" value="0x01" />
722 <value name="GPIOC5" value="0x00" />
723 </field>
724 <field name="GPIOC_I2SSDI_SEL" bitrange="2:2">
725 <value name="I2S_SDI" value="0x01" />
726 <value name="GPIOC4" value="0x00" />
727 </field>
728 <field name="GPIOC_I2SLRCK_SEL" bitrange="1:1">
729 <value name="I2S_LRCK" value="0x01" />
730 <value name="GPIOC3" value="0x00" />
731 </field>
732 <field name="GPIOC_I2SSCLK_SEL" bitrange="0:0">
733 <value name="I2S_SCLK" value="0x01" />
734 <value name="GPIOC2" value="0x00" />
735 </field>
736 </reg>
737 <reg name="SCU_GPIOUPCON" addr="0x38"></reg>
738 <reg name="SCU_DIVCON2" addr="0x3c"></reg>
739 </dev>
740 <dev name="I2C" long_name="I2C controller" desc="I2C controller" version="1.0">
741 <addr name="I2C" addr="0x18020000" />
742 <reg name="I2C_MTXR" addr="0x00"></reg>
743 <reg name="I2C_MRXR" addr="0x04"></reg>
744 <reg name="I2C_STXR" addr="0x08"></reg>
745 <reg name="I2C_SRXR" addr="0x0c"></reg>
746 <reg name="I2C_SADDR" addr="0x10"></reg>
747 <reg name="I2C_IER" addr="0x14"></reg>
748 <reg name="I2C_ISR" addr="0x18"></reg>
749 <reg name="I2C_LCMR" addr="0x1c"></reg>
750 <reg name="I2C_LSR" addr="0x20"></reg>
751 <reg name="I2C_CONR" addr="0x24"></reg>
752 <reg name="I2C_OPR" addr="0x28"></reg>
753 </dev>
754 <dev name="SD" long_name="SD controller" desc="SD controller" version="1.0">
755 <addr name="SD" addr="0x18024000" />
756 <reg name="MMU_CTRL" addr="0x00"></reg>
757 <reg name="MMU_PNRI" addr="0x04"></reg>
758 <reg name="CUR_PNRI" addr="0x08"></reg>
759 <reg name="MMU_PNRII" addr="0x0c"></reg>
760 <reg name="CUR_PNRII" addr="0x10"></reg>
761 <reg name="MMU_ADDR" addr="0x14"></reg>
762 <reg name="CUR_ADDR" addr="0x18"></reg>
763 <reg name="MMU_DATA" addr="0x1c"></reg>
764 <reg name="SD_CTRL" addr="0x20"></reg>
765 <reg name="SD_INT" addr="0x24"></reg>
766 <reg name="SD_CARD" addr="0x28"></reg>
767 <reg name="SD_CMDREST" addr="0x30"></reg>
768 <reg name="SD_CMDRES" addr="0x34"></reg>
769 <reg name="SD_DATAT" addr="0x3c"></reg>
770 <reg name="SD_CMD" addr="0x40"></reg>
771 <reg name="SD_RES3" addr="0x44"></reg>
772 <reg name="SD_RES2" addr="0x48"></reg>
773 <reg name="SD_RES1" addr="0x4c"></reg>
774 <reg name="SD_RES0" addr="0x50"></reg>
775 </dev>
776 <dev name="I2S" long_name="I2S controller" desc="I2S controller" version="1.0">
777 <addr name="I2S" addr="0x18028000" />
778 <reg name="I2S_OPR" addr="0x00"></reg>
779 <reg name="I2S_TXR" addr="0x04"></reg>
780 <reg name="I2S_RXR" addr="0x08"></reg>
781 <reg name="I2S_TXCTL" addr="0x0c"></reg>
782 <reg name="I2S_RXCTL" addr="0x10"></reg>
783 <reg name="I2S_FIFOSTS" addr="0x14"></reg>
784 <reg name="I2S_IER" addr="0x18"></reg>
785 <reg name="I2S_ISR" addr="0x1c"></reg>
786 </dev>
787 <dev name="PWM" long_name="PWM timer" desc="PWM timer" version="1.0">
788 <addr name="PWM0" addr="0x1802c000" />
789 <addr name="PWM1" addr="0x1802c010" />
790 <addr name="PWM2" addr="0x1802c020" />
791 <addr name="PWM3" addr="0x1802c030" />
792 <reg name="PWMTn_CNTR">
793 <formula string="n*0x10" />
794 <addr name="PWMT0_CNTR" addr="0x00" />
795 <addr name="PWMT1_CNTR" addr="0x10" />
796 <addr name="PWMT2_CNTR" addr="0x20" />
797 <addr name="PWMT3_CNTR" addr="0x30" />
798 </reg>
799 <reg name="PWMTn_HRC">
800 <formula string="n*0x10 + 0x04" />
801 <addr name="PWMT0_HRC" addr="0x04" />
802 <addr name="PWMT1_HRC" addr="0x14" />
803 <addr name="PWMT2_HRC" addr="0x24" />
804 <addr name="PWMT3_HRC" addr="0x34" />
805 </reg>
806 <reg name="PWMTn_LRC">
807 <formula string="n*0x10 + 0x08" />
808 <addr name="PWMT0_LRC" addr="0x08" />
809 <addr name="PWMT1_LRC" addr="0x18" />
810 <addr name="PWMT2_LRC" addr="0x28" />
811 <addr name="PWMT3_LRC" addr="0x38" />
812 </reg>
813 <reg name="PWMTn_CTRL">
814 <formula string="n*0x10 + 0x0c" />
815 <addr name="PWMT0_CTRL" addr="0x0c" />
816 <addr name="PWMT1_CTRL" addr="0x1c" />
817 <addr name="PWMT2_CTRL" addr="0x2c" />
818 <addr name="PWMT3_CTRL" addr="0x3c" />
819 </reg>
820 </dev>
821 <dev name="ADC" long_name="ADC" desc="4 channels 10-bit SAR A/D converter" version="1.0">
822 <addr name="ADC" addr="0x18030000" />
823 <reg name="ADC_DATA" addr="0x00"></reg>
824 <reg name="ADC_STAT" addr="0x04"></reg>
825 <reg name="ADC_CTRL" addr="0x08"></reg>
826 </dev>
827 <dev name="GPIO" long_name="GPIO" desc="GPIO" version="1.0">
828 <addr name="GPIO1" addr="0x18038000" />
829 <reg name="GPIO_PEDR" addr="0x00"></reg>
830 <reg name="GPIO_PECON" addr="0x04"></reg>
831 <reg name="GPIO_PFDR" addr="0x08"></reg>
832 <reg name="GPIO_PFCON" addr="0x0c"></reg>
833 <reg name="GPIO1_TEST" addr="0x20"></reg>
834 <reg name="GPIO_IEE" addr="0x24"></reg>
835 <reg name="GPIO_IEF" addr="0x28"></reg>
836 <reg name="GPIO_ISE" addr="0x34"></reg>
837 <reg name="GPIO_ISF" addr="0x38"></reg>
838 <reg name="GPIO_IBEE" addr="0x44"></reg>
839 <reg name="GPIO_IBEF" addr="0x48"></reg>
840 <reg name="GPIO_IEVE" addr="0x54"></reg>
841 <reg name="GPIO_IEVF" addr="0x58"></reg>
842 <reg name="GPIO_ICE" addr="0x64"></reg>
843 <reg name="GPIO_ICF" addr="0x68"></reg>
844 <reg name="GPIO1_ISR" addr="0x74"></reg>
845 </dev>
846 <dev name="INTC" long_name="Interrupt controller" desc="Interrupt controller" version="1.0">
847 <addr name="INTC" addr="0x18080000" />
848 <reg name="INTC_SCRn">
849 <formula string="n*0x04" />
850 <addr name="INTC_SCR0" addr="0x00" />
851 <addr name="INTC_SCR1" addr="0x04" />
852 <addr name="INTC_SCR2" addr="0x08" />
853 <addr name="INTC_SCR3" addr="0x0c" />
854 <addr name="INTC_SCR4" addr="0x10" />
855 <addr name="INTC_SCR5" addr="0x14" />
856 <addr name="INTC_SCR6" addr="0x18" />
857 <addr name="INTC_SCR7" addr="0x1c" />
858 <addr name="INTC_SCR8" addr="0x20" />
859 <addr name="INTC_SCR9" addr="0x24" />
860 <addr name="INTC_SCR10" addr="0x28" />
861 <addr name="INTC_SCR11" addr="0x2c" />
862 <addr name="INTC_SCR12" addr="0x30" />
863 <addr name="INTC_SCR13" addr="0x34" />
864 <addr name="INTC_SCR14" addr="0x38" />
865 <addr name="INTC_SCR15" addr="0x3c" />
866 <addr name="INTC_SCR16" addr="0x40" />
867 <addr name="INTC_SCR17" addr="0x44" />
868 <addr name="INTC_SCR18" addr="0x48" />
869 <addr name="INTC_SCR19" addr="0x4c" />
870 <addr name="INTC_SCR20" addr="0x50" />
871 <addr name="INTC_SCR21" addr="0x54" />
872 <addr name="INTC_SCR22" addr="0x58" />
873 <addr name="INTC_SCR23" addr="0x5c" />
874 <addr name="INTC_SCR24" addr="0x60" />
875 <addr name="INTC_SCR25" addr="0x64" />
876 <addr name="INTC_SCR26" addr="0x68" />
877 <addr name="INTC_SCR27" addr="0x6c" />
878 <addr name="INTC_SCR28" addr="0x70" />
879 <addr name="INTC_SCR29" addr="0x74" />
880 <addr name="INTC_SCR30" addr="0x78" />
881 <addr name="INTC_SCR31" addr="0x7c" />
882 </reg>
883 <reg name="INTC_ISR" addr="0x104"></reg>
884 <reg name="INTC_IPR" addr="0x108"></reg>
885 <reg name="INTC_IMR" addr="0x10c"></reg>
886 <reg name="INTC_IECR" addr="0x114"></reg>
887 <reg name="INTC_ICCR" addr="0x118"></reg>
888 <reg name="INTC_ISCR" addr="0x11c"></reg>
889 <reg name="INTC_TEST" addr="0x124"></reg>
890 </dev>
891 <dev name="ARB" long_name="AHB bus arbiter" desc="AHB bus arbiter" version="1.0">
892 <addr name="ARB" addr="0x18084000" />
893 <reg name="ARB_MODE" addr="0x00"></reg>
894 <reg name="ARB_PRIOn">
895 <formula string="n*0x04 + 0x04" />
896 <addr name="ARB_PRIO1" addr="0x04" />
897 <addr name="ARB_PRIO2" addr="0x08" />
898 <addr name="ARB_PRIO3" addr="0x0c" />
899 <addr name="ARB_PRIO4" addr="0x10" />
900 <addr name="ARB_PRIO5" addr="0x14" />
901 <addr name="ARB_PRIO6" addr="0x18" />
902 <addr name="ARB_PRIO7" addr="0x1c" />
903 <addr name="ARB_PRIO8" addr="0x20" />
904 <addr name="ARB_PRIO9" addr="0x24" />
905 <addr name="ARB_PRIO10" addr="0x28" />
906 <addr name="ARB_PRIO11" addr="0x2c" />
907 <addr name="ARB_PRIO12" addr="0x30" />
908 <addr name="ARB_PRIO13" addr="0x34" />
909 <addr name="ARB_PRIO14" addr="0x38" />
910 <addr name="ARB_PRIO15" addr="0x3c" />
911 </reg>
912 </dev>
913 <dev name="MAILBOX" long_name="CPU-DSP mailbox" desc="CPU-DSP mailbox" version="1.0">
914 <addr name="MAILBOX" addr="0x18088000" />
915 <reg name="MAILBOX_ID" addr="0x00"></reg>
916 <reg name="H2C_STA" addr="0x10"></reg>
917 <reg name="H2Cn_DATA">
918 <formula string="n*0x08 + 0x20" />
919 <addr name="H2C0_DATA" addr="0x20" />
920 <addr name="H2C1_DATA" addr="0x28" />
921 <addr name="H2C2_DATA" addr="0x30" />
922 <addr name="H2C3_DATA" addr="0x38" />
923 </reg>
924 <reg name="H2Cn_CMD">
925 <formula string="n*0x08 + 0x24" />
926 <addr name="H2C0_CMD" addr="0x24" />
927 <addr name="H2C1_CMD" addr="0x2c" />
928 <addr name="H2C2_CMD" addr="0x34" />
929 <addr name="H2C3_CMD" addr="0x3c" />
930 </reg>
931 <reg name="C2H_STA" addr="0x40"></reg>
932 <reg name="C2Hn_DATA">
933 <formula string="n*0x08 + 0x50" />
934 <addr name="C2H0_DATA" addr="0x50" />
935 <addr name="C2H1_DATA" addr="0x58" />
936 <addr name="C2H2_DATA" addr="0x60" />
937 <addr name="C2H3_DATA" addr="0x68" />
938 </reg>
939 <reg name="C2Hn_CMD">
940 <formula string="n*0x08 + 0x54" />
941 <addr name="C2H0_CMD" addr="0x54" />
942 <addr name="C2H1_CMD" addr="0x5c" />
943 <addr name="C2H2_CMD" addr="0x64" />
944 <addr name="C2H3_CMD" addr="0x6c" />
945 </reg>
946 </dev>
947 <dev name="HDMA" long_name="AHB DMA" desc="AHB DMA" version="1.0">
948 <addr name="HDMA" addr="0x18090000" />
949 <reg name="HDMA_CON0" addr="0x00"></reg>
950 <reg name="HDMA_CON1" addr="0x04"></reg>
951 <reg name="HDMA_ISRC0" addr="0x08"></reg>
952 <reg name="HDMA_IDST0" addr="0x0C"></reg>
953 <reg name="HDMA_ICNT0" addr="0x10"></reg>
954 <reg name="HDMA_ISRC1" addr="0x14"></reg>
955 <reg name="HDMA_IDST1" addr="0x18"></reg>
956 <reg name="HDMA_ICNT1" addr="0x1C"></reg>
957 <reg name="HDMA_CSRC0" addr="0x20"></reg>
958 <reg name="HDMA_CDST0" addr="0x24"></reg>
959 <reg name="HDMA_CCNT0" addr="0x28"></reg>
960 <reg name="HDMA_CSRC1" addr="0x2C"></reg>
961 <reg name="HDMA_CDST1" addr="0x30"></reg>
962 <reg name="HDMA_CCNT1" addr="0x34"></reg>
963 <reg name="HDMA_ISR" addr="0x38"></reg>
964 <reg name="HDMA_DSR" addr="0x3C"></reg>
965 <reg name="HDMA_ISCNT0" addr="0x40"></reg>
966 <reg name="HDMA_IPNCNTD0" addr="0x44"></reg>
967 <reg name="HDMA_IADDR_BS0" addr="0x48"></reg>
968 <reg name="HDMA_ISCNT1" addr="0x4C"></reg>
969 <reg name="HDMA_IPNCNTD1" addr="0x50"></reg>
970 <reg name="HDMA_IADDR_BS1" addr="0x54"></reg>
971 <reg name="HDMA_CSCNT0" addr="0x58"></reg>
972 <reg name="HDMA_CPNCNTD0" addr="0x5C"></reg>
973 <reg name="HDMA_CADDR_BS0" addr="0x60"></reg>
974 <reg name="HDMA_CSCNT1" addr="0x64"></reg>
975 <reg name="HDMA_CPNCNTD1" addr="0x68"></reg>
976 <reg name="HDMA_CADDR_BS1" addr="0x6C"></reg>
977 <reg name="HDMA_PACNT0" addr="0x70"></reg>
978 <reg name="HDMA_PACNT1" addr="0x74"></reg>
979 </dev>
980 <dev name="A2A_DMA" long_name="AHB-to-AHB bridge" desc="AHB-to-AHB bridge with DMA" version="1.0">
981 <addr name="A2A_DMA" addr="0x18094000" />
982 <reg name="A2A_CON0" addr="0x00"></reg>
983 <reg name="A2A_ISRC0" addr="0x04"></reg>
984 <reg name="A2A_IDST0" addr="0x08"></reg>
985 <reg name="A2A_ICNT0" addr="0x0C"></reg>
986 <reg name="A2A_CSRC0" addr="0x10"></reg>
987 <reg name="A2A_CDST0" addr="0x14"></reg>
988 <reg name="A2A_CCNT0" addr="0x18"></reg>
989 <reg name="A2A_CON1" addr="0x1C"></reg>
990 <reg name="A2A_ISRC1" addr="0x20"></reg>
991 <reg name="A2A_IDST1" addr="0x24"></reg>
992 <reg name="A2A_ICNT1" addr="0x28"></reg>
993 <reg name="A2A_CSRC1" addr="0x2C"></reg>
994 <reg name="A2A_CDST1" addr="0x30"></reg>
995 <reg name="A2A_CCNT1" addr="0x34"></reg>
996 <reg name="A2A_INT_STS" addr="0x38"></reg>
997 <reg name="A2A_DMA_STS" addr="0x3C"></reg>
998 <reg name="A2A_ERR_ADR0" addr="0x40"></reg>
999 <reg name="A2A_ERR_OP0" addr="0x44"></reg>
1000 <reg name="A2A_ERR_ADR1" addr="0x48"></reg>
1001 <reg name="A2A_ERR_OP1" addr="0x4C"></reg>
1002 <reg name="A2A_LCNT0" addr="0x50"></reg>
1003 <reg name="A2A_LCNT1" addr="0x54"></reg>
1004 <reg name="A2A_DOMAIN" addr="0x58"></reg>
1005 </dev>
1006 <dev name="UDC" long_name="USB 2.0 Device Controller" desc="USB 2.0 Device Controller" version="1.0">
1007 <addr name="UDC" addr="0x180a0000" />
1008 <reg name="DEV_CTL" addr="0x08"></reg>
1009 <reg name="DEV_INFO" addr="0x10"></reg>
1010 <reg name="EN_INT" addr="0x14"></reg>
1011 <reg name="INT2FLAG" addr="0x18"></reg>
1012 <reg name="INTCON" addr="0x1C"></reg>
1013 <reg name="SETUP1" addr="0x20"></reg>
1014 <reg name="SETUP2" addr="0x24"></reg>
1015 <reg name="AHBCON" addr="0x28"></reg>
1016 <reg name="RX0STAT" addr="0x30"></reg>
1017 <reg name="RX0CON" addr="0x34"></reg>
1018 <reg name="RX0DMACTLO" addr="0x38"></reg>
1019 <reg name="RX0DMAOUTLMADDR" addr="0x3C"></reg>
1020 <reg name="TX0STAT" addr="0x40"></reg>
1021 <reg name="TX0CON" addr="0x44"></reg>
1022 <reg name="TX0BUF" addr="0x48"></reg>
1023 <reg name="TX0DMAINCTL" addr="0x4C"></reg>
1024 <reg name="TX0DMALM_IADDR" addr="0x50"></reg>
1025 <reg name="RX1STAT" addr="0x54"></reg>
1026 <reg name="RX1CON" addr="0x58"></reg>
1027 <reg name="RX1DMACTLO" addr="0x5C"></reg>
1028 <reg name="RX1DMAOUTLMADDR" addr="0x60"></reg>
1029 <reg name="TX2STAT" addr="0x64"></reg>
1030 <reg name="TX2CON" addr="0x68"></reg>
1031 <reg name="TX2BUF" addr="0x6C"></reg>
1032 <reg name="TX2DMAINCTL" addr="0x70"></reg>
1033 <reg name="TX2DMALM_IADDR" addr="0x74"></reg>
1034 <reg name="TX3STAT" addr="0x78"></reg>
1035 <reg name="TX3CON" addr="0x7C"></reg>
1036 <reg name="TX3BUF" addr="0x80"></reg>
1037 <reg name="TX3DMAINCTL" addr="0x84"></reg>
1038 <reg name="TX3DMALM_IADDR" addr="0x88"></reg>
1039 <reg name="RX4STAT" addr="0x8C"></reg>
1040 <reg name="RX4CON" addr="0x90"></reg>
1041 <reg name="RX4DMACTLO" addr="0x94"></reg>
1042 <reg name="RX4DMAOUTLMADDR" addr="0x98"></reg>
1043 <reg name="TX5STAT" addr="0x9C"></reg>
1044 <reg name="TX5CON" addr="0xA0"></reg>
1045 <reg name="TX5BUF" addr="0xA4"></reg>
1046 <reg name="TX5DMAINCTL" addr="0xA8"></reg>
1047 <reg name="TX5DMALM_IADDR" addr="0xAC"></reg>
1048 <reg name="TX6STAT" addr="0xB0"></reg>
1049 <reg name="TX6CON" addr="0xB4"></reg>
1050 <reg name="TX6BUF" addr="0xB8"></reg>
1051 <reg name="TX6DMAINCTL" addr="0xBC"></reg>
1052 <reg name="TX6DMALM_IADDR" addr="0xC0"></reg>
1053 <reg name="RX7STAT" addr="0xC4"></reg>
1054 <reg name="RX7CON" addr="0xC8"></reg>
1055 <reg name="RX7DMACTLO" addr="0xCC"></reg>
1056 <reg name="RX7DMAOUTLMADDR" addr="0xD0"></reg>
1057 <reg name="TX8STAT" addr="0xD4"></reg>
1058 <reg name="TX8CON" addr="0xD8"></reg>
1059 <reg name="TX8BUF" addr="0xDC"></reg>
1060 <reg name="TX8DMAINCTL" addr="0xE0"></reg>
1061 <reg name="TX8DMALM_IADDR" addr="0xE4"></reg>
1062 <reg name="TX9STAT" addr="0xE8"></reg>
1063 <reg name="TX9CON" addr="0xEC"></reg>
1064 <reg name="TX9BUF" addr="0xF0"></reg>
1065 <reg name="TX9DMAINCTL" addr="0xF4"></reg>
1066 <reg name="TX9DMALM_IADDR" addr="0xF8"></reg>
1067 <reg name="RX10STAT" addr="0xFC"></reg>
1068 <reg name="RX10CON" addr="0x100"></reg>
1069 <reg name="RX10DMACTLO" addr="0x104"></reg>
1070 <reg name="RX10DMAOUTLMADDR" addr="0x108"></reg>
1071 <reg name="TX11STAT" addr="0x10C"></reg>
1072 <reg name="TX11CON" addr="0x110"></reg>
1073 <reg name="TX11BUF" addr="0x114"></reg>
1074 <reg name="TX11DMAINCTL" addr="0x118"></reg>
1075 <reg name="TX11DMALM_IADDR" addr="0x11C"></reg>
1076 <reg name="TX12STAT" addr="0x120"></reg>
1077 <reg name="TX12CON" addr="0x124"></reg>
1078 <reg name="TX12BUF" addr="0x128"></reg>
1079 <reg name="TX12DMAINCTL" addr="0x12C"></reg>
1080 <reg name="TX12DMALM_IADDR" addr="0x130"></reg>
1081 <reg name="RX13STAT" addr="0x134"></reg>
1082 <reg name="RX13CON" addr="0x138"></reg>
1083 <reg name="RX13DMACTLO" addr="0x13C"></reg>
1084 <reg name="RX13DMAOUTLMADDR" addr="0x140"></reg>
1085 <reg name="TX14STAT" addr="0x144"></reg>
1086 <reg name="TX14CON" addr="0x148"></reg>
1087 <reg name="TX14BUF" addr="0x14C"></reg>
1088 <reg name="TX14DMAINCTL" addr="0x150"></reg>
1089 <reg name="TX14DMALM_IADDR" addr="0x154"></reg>
1090 <reg name="TX15STAT" addr="0x158"></reg>
1091 <reg name="TX15CON" addr="0x15C"></reg>
1092 <reg name="TX15BUF" addr="0x160"></reg>
1093 <reg name="TX15DMAINCTL" addr="0x164"></reg>
1094 <reg name="TX15DMALM_IADDR" addr="0x168"></reg>
1095 </dev>
1096 <dev name="UHC" long_name="USB 2.0 Host Controller" desc="USB 2.0 Host Controller" version="1.0">
1097 <addr name="UHC" addr="0x180a4000" />
1098 </dev>
1099 <dev name="SDRSTMC" long_name="SDRSTMC Static/SDRAM Memory Controller" desc="SDRSTMC Static/SDRAM Memory Controller" version="1.0">
1100 <addr name="SDRSTMC" addr="0x180b0000" />
1101 <reg name="MCSDR_MODE" addr="0x100"></reg>
1102 <reg name="MCSDR_ADDMAP" addr="0x104"></reg>
1103 <reg name="MCSDR_ADDCFG" addr="0x108"></reg>
1104 <reg name="MCSDR_BASIC" addr="0x10C"></reg>
1105 <reg name="MCSDR_T_REF" addr="0x110"></reg>
1106 <reg name="MCSDR_T_RFC" addr="0x114"></reg>
1107 <reg name="MCSDR_T_MRD" addr="0x118"></reg>
1108 <reg name="MCSDR_T_RP" addr="0x120"></reg>
1109 <reg name="MCSDR_T_RCD" addr="0x124"></reg>
1110 <reg name="MCST0_T_CEWD" addr="0x200"></reg>
1111 <reg name="MCST0_T_CE2WE" addr="0x204"></reg>
1112 <reg name="MCST0_WEWD" addr="0x208"></reg>
1113 <reg name="MCST0_T_WE2CE" addr="0x20C"></reg>
1114 <reg name="MCST0_T_CEWDR" addr="0x210"></reg>
1115 <reg name="MCST0_T_CE2RD" addr="0x214"></reg>
1116 <reg name="MCST0_T_RDWD" addr="0x218"></reg>
1117 <reg name="MCST0_T_RD2CE" addr="0x21C"></reg>
1118 <reg name="MCST0_BASIC" addr="0x220"></reg>
1119 <reg name="MCST1_T_CEWD" addr="0x300"></reg>
1120 <reg name="MCST1_T_CE2WE" addr="0x304"></reg>
1121 <reg name="MCST1_WEWD" addr="0x308"></reg>
1122 <reg name="MCST1_T_WE2CE" addr="0x30C"></reg>
1123 <reg name="MCST1_T_CEWDR" addr="0x310"></reg>
1124 <reg name="MCST1_T_CE2RD" addr="0x314"></reg>
1125 <reg name="MCST1_T_RDWD" addr="0x318"></reg>
1126 <reg name="MCST1_T_RD2CE" addr="0x31C"></reg>
1127 <reg name="MCST1_BASIC" addr="0x320"></reg>
1128 </dev>
1129 <dev name="VIP" long_name="VIP Video Input Processor" desc="VIP Video Input Processor" version="1.0">
1130 <addr name="VIP" addr="0x180c0000" />
1131 </dev>
1132 <dev name="NANDC" long_name="NAND Flash Controller" desc="NAND Flash Controller" version="1.0">
1133 <addr name="NANDC" addr="0x180e8000" />
1134 <reg name="FMCTL" addr="0x00"></reg>
1135 <reg name="FMWAIT" addr="0x04"></reg>
1136 <reg name="FLCTL" addr="0x08"></reg>
1137 <reg name="BCHCTL" addr="0x0C"></reg>
1138 <reg name="BCHST" addr="0xD0"></reg>
1139 <reg name="FLASH_DATAn">
1140 <formula string="0x200*n+0x200" />
1141 <addr name="FLASH_DATA0" addr="0x200" />
1142 <addr name="FLASH_DATA1" addr="0x400" />
1143 <addr name="FLASH_DATA2" addr="0x600" />
1144 <addr name="FLASH_DATA3" addr="0x800" />
1145 </reg>
1146 <reg name="FLASH_ADDRn">
1147 <formula string="0x200*n+0x204" />
1148 <addr name="FLASH_ADDR0" addr="0x204" />
1149 <addr name="FLASH_ADDR1" addr="0x404" />
1150 <addr name="FLASH_ADDR2" addr="0x604" />
1151 <addr name="FLASH_ADDR3" addr="0x804" />
1152 </reg>
1153 <reg name="FLASH_CMDn">
1154 <formula string="0x200*n+0x208" />
1155 <addr name="FLASH_CMD0" addr="0x208" />
1156 <addr name="FLASH_CMD1" addr="0x408" />
1157 <addr name="FLASH_CMD2" addr="0x608" />
1158 <addr name="FLASH_CMD3" addr="0x808" />
1159 </reg>
1160 <reg name="PAGE_BUF" addr="0xA00"></reg>
1161 <reg name="SPARE_BUF" addr="0x1200"></reg>
1162 </dev>
1163 <dev name="LCDC" long_name="LCD Interface Controller" desc="LCD Interface Controller" version="1.0">
1164 <addr name="LCDC" addr="0x186e8000" />
1165 <reg name="LCDC_CTRL" addr="0x00"></reg>
1166 <reg name="MCU_CTRL" addr="0x04"></reg>
1167 <reg name="HOR_PERIOD" addr="0x08"></reg>
1168 <reg name="VERT_PERIOD" addr="0x0C"></reg>
1169 <reg name="HOR_PW" addr="0x10"></reg>
1170 <reg name="VERT_PW" addr="0x14"></reg>
1171 <reg name="HOR_BP" addr="0x18"></reg>
1172 <reg name="VERT_BP" addr="0x1C"></reg>
1173 <reg name="HOR_ACT" addr="0x20"></reg>
1174 <reg name="VERT_ACT" addr="0x24"></reg>
1175 <reg name="LINE0_YADDR" addr="0x28"></reg>
1176 <reg name="LINE0_UVADDR" addr="0x2C"></reg>
1177 <reg name="LINE1_YADDR" addr="0x30"></reg>
1178 <reg name="LINE1_UVADDR" addr="0x34"></reg>
1179 <reg name="LINE2_YADDR" addr="0x38"></reg>
1180 <reg name="LINE2_UVADDR" addr="0x3C"></reg>
1181 <reg name="LINE3_YADDR" addr="0x40"></reg>
1182 <reg name="LINE3_UVADDR" addr="0x44"></reg>
1183 <reg name="START_X" addr="0x48"></reg>
1184 <reg name="START_Y" addr="0x4C"></reg>
1185 <reg name="DELTA_X" addr="0x50"></reg>
1186 <reg name="DELTA_Y" addr="0x54"></reg>
1187 <reg name="LCDC_INTR_MASK" addr="0x58"></reg>
1188 <reg name="ALPHA_ALX" addr="0x5C"></reg>
1189 <reg name="ALPHA_ATY" addr="0x60"></reg>
1190 <reg name="ALPHA_ARX" addr="0x64"></reg>
1191 <reg name="ALPHA_ABY" addr="0x68"></reg>
1192 <reg name="ALPHA_BLX" addr="0x6C"></reg>
1193 <reg name="ALPHA_BTY" addr="0x70"></reg>
1194 <reg name="ALPHA_BRX" addr="0x74"></reg>
1195 <reg name="ALPHA_BBY" addr="0x78"></reg>
1196 <reg name="LCDC_STA" addr="0x7C"></reg>
1197 <reg name="LCD_COMMAND" addr="0x1000"></reg>
1198 <reg name="LCD_DATA" addr="0x1004"></reg>
1199 <reg name="LCD_BUFF" addr="0x2000"></reg>
1200 </dev>
1201 <dev name="HSADC" long_name="High Speed ADC" desc="High Speed ADC" version="1.0">
1202 <reg name="HSADC_DATA" addr="0x00"></reg>
1203 <reg name="HSADC_CTRL" addr="0x04"></reg>
1204 <reg name="HSADC_IER" addr="0x08"></reg>
1205 <reg name="HSADC_ISR" addr="0x0C"></reg>
1206 </dev>
1207 <dev name="DWDMA" long_name="DMA Controller" desc="DMA Controller" version="1.0">
1208 <reg name="DWDMA_SARn">
1209 <formula string="n*0x58+0x00" />
1210 <addr name="DWDMA_SAR0" addr="0x00" />
1211 <addr name="DWDMA_SAR1" addr="0x58" />
1212 <addr name="DWDMA_SAR2" addr="0xb0" />
1213 <addr name="DWDMA_SAR3" addr="0x108" />
1214 </reg>
1215 <reg name="DWDMA_DARn">
1216 <formula string="n*0x58+0x08" />
1217 <addr name="DWDMA_DAR0" addr="0x08" />
1218 <addr name="DWDMA_DAR1" addr="0x60" />
1219 <addr name="DWDMA_DAR2" addr="0xb8" />
1220 <addr name="DWDMA_DAR3" addr="0x110" />
1221 </reg>
1222 <reg name="DWDMA_LLPn">
1223 <formula string="n*0x58+0x10" />
1224 <addr name="DWDMA_LLP0" addr="0x10" />
1225 <addr name="DWDMA_LLP1" addr="0x68" />
1226 <addr name="DWDMA_LLP2" addr="0xc0" />
1227 <addr name="DWDMA_LLP3" addr="0x118" />
1228 </reg>
1229 <reg name="DWDMA_CTL_Ln">
1230 <formula string="n*0x58+0x18" />
1231 <addr name="DWDMA_CTL_L0" addr="0x18" />
1232 <addr name="DWDMA_CTL_L1" addr="0x70" />
1233 <addr name="DWDMA_CTL_L2" addr="0xc8" />
1234 <addr name="DWDMA_CTL_L3" addr="0x120" />
1235 </reg>
1236 <reg name="DWDMA_CTL_Hn">
1237 <formula string="n*0x58+0x1c" />
1238 <addr name="DWDMA_CTL_H0" addr="0x1c" />
1239 <addr name="DWDMA_CTL_H1" addr="0x74" />
1240 <addr name="DWDMA_CTL_H2" addr="0xcc" />
1241 <addr name="DWDMA_CTL_H3" addr="0x124" />
1242 </reg>
1243 <reg name="DWDMA_SSTATn">
1244 <formula string="n*0x58+0x20" />
1245 <addr name="DWDMA_SSTAT0" addr="0x20" />
1246 <addr name="DWDMA_SSTAT1" addr="0x78" />
1247 <addr name="DWDMA_SSTAT2" addr="0xd0" />
1248 <addr name="DWDMA_SSTAT3" addr="0x128" />
1249 </reg>
1250 <reg name="DWDMA_DSTATn">
1251 <formula string="n*0x58+0x28" />
1252 <addr name="DWDMA_DSTAT0" addr="0x28" />
1253 <addr name="DWDMA_DSTAT1" addr="0x80" />
1254 <addr name="DWDMA_DSTAT2" addr="0xd8" />
1255 <addr name="DWDMA_DSTAT3" addr="0x130" />
1256 </reg>
1257 <reg name="DWDMA_SSTATARn">
1258 <formula string="n*0x58+0x30" />
1259 <addr name="DWDMA_SSTATAR0" addr="0x30" />
1260 <addr name="DWDMA_SSTATAR1" addr="0x88" />
1261 <addr name="DWDMA_SSTATAR2" addr="0xe0" />
1262 <addr name="DWDMA_SSTATAR3" addr="0x138" />
1263 </reg>
1264 <reg name="DWDMA_DSTATARn">
1265 <formula string="n*0x58+0x38" />
1266 <addr name="DWDMA_DSTATAR0" addr="0x38" />
1267 <addr name="DWDMA_DSTATAR1" addr="0x90" />
1268 <addr name="DWDMA_DSTATAR2" addr="0xe8" />
1269 <addr name="DWDMA_DSTATAR3" addr="0x140" />
1270 </reg>
1271 <reg name="DWDMA_CFG_Ln">
1272 <formula string="n*0x58+0x40" />
1273 <addr name="DWDMA_CFG_L0" addr="0x40" />
1274 <addr name="DWDMA_CFG_L1" addr="0x98" />
1275 <addr name="DWDMA_CFG_L2" addr="0xf0" />
1276 <addr name="DWDMA_CFG_L3" addr="0x148" />
1277 </reg>
1278 <reg name="DWDMA_CFG_Hn">
1279 <formula string="n*0x58+0x44" />
1280 <addr name="DWDMA_CFG_H0" addr="0x44" />
1281 <addr name="DWDMA_CFG_H1" addr="0x9c" />
1282 <addr name="DWDMA_CFG_H2" addr="0xf4" />
1283 <addr name="DWDMA_CFG_H3" addr="0x14c" />
1284 </reg>
1285 <reg name="DWDMA_SGRn">
1286 <formula string="n*0x58+0x48" />
1287 <addr name="DWDMA_SGR0" addr="0x48" />
1288 <addr name="DWDMA_SGR1" addr="0xa0" />
1289 <addr name="DWDMA_SGR2" addr="0xf8" />
1290 <addr name="DWDMA_SGR3" addr="0x150" />
1291 </reg>
1292 <reg name="DWDMA_DSRn">
1293 <formula string="n*0x58+0x50" />
1294 <addr name="DWDMA_DSR0" addr="0x50" />
1295 <addr name="DWDMA_DSR1" addr="0xa8" />
1296 <addr name="DWDMA_DSR2" addr="0x100" />
1297 <addr name="DWDMA_DSR3" addr="0x158" />
1298 </reg>
1299 <reg name="DWDMA_RAW_TFR" addr="0x2C0"></reg>
1300 <reg name="DWDMA_RAW_BLOCK" addr="0x2C8"></reg>
1301 <reg name="DWDMA_RAW_SRCTRAN" addr="0x2D0"></reg>
1302 <reg name="DWDMA_RAW_DSTTRAN" addr="0x2D8"></reg>
1303 <reg name="DWDMA_RAW_ERR" addr="0x2E0"></reg>
1304 <reg name="DWDMA_STATUS_TFR" addr="0x2E8"></reg>
1305 <reg name="DWDMA_STATUS_BLOCK" addr="0x2F0"></reg>
1306 <reg name="DWDMA_STATUS_SRCTRAN" addr="0x2F8"></reg>
1307 <reg name="DWDMA_STATUS_DSTTRAN" addr="0x300"></reg>
1308 <reg name="DWDMA_STATUS_ERR" addr="0x308"></reg>
1309 <reg name="DWDMA_MASK_TFR" addr="0x310"></reg>
1310 <reg name="DWDMA_MASK_BLOCK" addr="0x318"></reg>
1311 <reg name="DWDMA_MASK_SRCTRAN" addr="0x320"></reg>
1312 <reg name="DWDMA_MASK_DSTTRAN" addr="0x328"></reg>
1313 <reg name="DWDMA_MASK_ERR" addr="0x330"></reg>
1314 <reg name="DWDMA_CLEAR_TFR" addr="0x338"></reg>
1315 <reg name="DWDMA_CLEAR_BLOCK" addr="0x340"></reg>
1316 <reg name="DWDMA_CLEAR_SRCTRAN" addr="0x348"></reg>
1317 <reg name="DWDMA_CLEAR_DSTTRAN" addr="0x350"></reg>
1318 <reg name="DWDMA_CLEAR_ERR" addr="0x358"></reg>
1319 <reg name="DWDMA_STATUS_INT" addr="0x360"></reg>
1320 <reg name="DWDMA_REQ_SRC" addr="0x368"></reg>
1321 <reg name="DWDMA_REQ_DST" addr="0x370"></reg>
1322 <reg name="DWDMA_S_REQ_SRC" addr="0x378"></reg>
1323 <reg name="DWDMA_S_REQ_DST" addr="0x380"></reg>
1324 <reg name="DWDMA_L_REQ_SRC" addr="0x388"></reg>
1325 <reg name="DWDMA_L_REQ_DST" addr="0x390"></reg>
1326 <reg name="DWDMA_DMA_CFG" addr="0x398"></reg>
1327 <reg name="DWDMA_DMA_CHEN" addr="0x3A0"></reg>
1328 </dev>
1329 <dev name="CACHE" long_name="CACHE Controller" desc="CACHE Controller" version="1.0">
1330 <addr name="CACHE" addr="0xEFFF0000" />
1331 <reg name="DEVID" addr="0x00">
1332 <field name="CACHE_EN" bitrange="31:31"></field>
1333 </reg>
1334 <reg name="CACHEOP" addr="0x04">
1335 <field name="ADDRESS" bitrange="31:2"></field>
1336 <field name="OPCODE" bitrange="1:0">
1337 <value name="NOP" value="0x00" />
1338 <value name="INVALIDATE_SINGLE_ENTRY" value="0x01" />
1339 <value name="INVALIDATE_WAY" value="0x2" />
1340 </field>
1341 </reg>
1342 <reg name="CACHELKDN" addr="0x08">
1343 <field name="RESERVED" bitrange="31:2"></field>
1344 <field name="WAY_SELECT" bitrange="1:0">
1345 <value name="LOCK_NONE" value="0x00" />
1346 <value name="LOCK_WAY0" value="0x01" />
1347 <value name="LOCK_WAY1" value="0x02" />
1348 </field>
1349 </reg>
1350 <reg name="MEMMAPA" addr="0x10">
1351 <field name="MEMBASE" bitrange="31:25"></field>
1352 <field name="MAPSIZE" bitrange="7:0">
1353 <value name="MAP_32MB" value="0xfe" />
1354 <value name="MAP_64MB" value="0xfc" />
1355 <value name="MAP_128MB" value="0xf8" />
1356 </field>
1357 </reg>
1358 <reg name="MEMMAPB" addr="0x14">
1359 <field name="MEMBASE" bitrange="31:25"></field>
1360 <field name="MAPSIZE" bitrange="7:0">
1361 <value name="MAP_32MB" value="0xfe" />
1362 <value name="MAP_64MB" value="0xfc" />
1363 <value name="MAP_128MB" value="0xf8" />
1364 </field>
1365 </reg>
1366 <reg name="MEMMAPC" addr="0x18">
1367 <field name="MEMBASE" bitrange="31:25"></field>
1368 <field name="MAPSIZE" bitrange="7:0">
1369 <value name="MAP_32MB" value="0xfe" />
1370 <value name="MAP_64MB" value="0xfc" />
1371 <value name="MAP_128MB" value="0xf8" />
1372 </field>
1373 </reg>
1374 <reg name="MEMMAPD" addr="0x1C">
1375 <field name="MEMBASE" bitrange="31:25"></field>
1376 <field name="MAPSIZE" bitrange="7:0">
1377 <value name="MAP_32MB" value="0xfe" />
1378 <value name="MAP_64MB" value="0xfc" />
1379 <value name="MAP_128MB" value="0xf8" />
1380 </field>
1381 </reg>
1382 <reg name="PFCNTRA_CTRL" addr="0x20"></reg>
1383 <reg name="PFCNTRA" addr="0x24"></reg>
1384 <reg name="PFCNTRB_CTRL" addr="0x28"></reg>
1385 <reg name="PFCNTRB" addr="0x2C"></reg>
1386 </dev>
1387</soc>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-22 23:24:30 +0000