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1<?xml version="1.0"?>
2<soc version="2">
3 <name>jz4760b</name>
4 <author>Amaury Pouly</author>
5 <isa>mips (xburst)</isa>
6 <version>1.0</version>
7 <node>
8 <name>IPU_P</name>
9 <instance>
10 <name>IPU_P</name>
11 <address>0x13080000</address>
12 </instance>
13 </node>
14 <node>
15 <name>CPM</name>
16 <instance>
17 <name>CPM</name>
18 <address>0xb0000000</address>
19 </instance>
20 <node>
21 <name>CTRL</name>
22 <title>Clock control register</title>
23 <instance>
24 <name>CTRL</name>
25 <address>0x0</address>
26 </instance>
27 <register>
28 <field>
29 <name>ECS</name>
30 <position>31</position>
31 </field>
32 <field>
33 <name>MEM</name>
34 <position>30</position>
35 </field>
36 <field>
37 <name>SDIV</name>
38 <position>24</position>
39 <width>4</width>
40 </field>
41 <field>
42 <name>CE</name>
43 <position>22</position>
44 </field>
45 <field>
46 <name>PCS</name>
47 <position>21</position>
48 </field>
49 <field>
50 <name>H2DIV</name>
51 <position>16</position>
52 <width>4</width>
53 </field>
54 <field>
55 <name>MDIV</name>
56 <position>12</position>
57 <width>4</width>
58 </field>
59 <field>
60 <name>PDIV</name>
61 <position>8</position>
62 <width>4</width>
63 </field>
64 <field>
65 <name>HDIV</name>
66 <position>4</position>
67 <width>4</width>
68 </field>
69 <field>
70 <name>CDIV</name>
71 <position>0</position>
72 <width>4</width>
73 </field>
74 </register>
75 </node>
76 <node>
77 <name>LOW</name>
78 <title>Low power control register</title>
79 <instance>
80 <name>LOW</name>
81 <address>0x4</address>
82 </instance>
83 <register>
84 <field>
85 <name>PDAHB1</name>
86 <position>30</position>
87 </field>
88 <field>
89 <name>VBATIR</name>
90 <position>29</position>
91 </field>
92 <field>
93 <name>PDGPS</name>
94 <position>28</position>
95 </field>
96 <field>
97 <name>PDAHB1S</name>
98 <position>26</position>
99 </field>
100 <field>
101 <name>PDGPSS</name>
102 <position>24</position>
103 </field>
104 <field>
105 <name>PST</name>
106 <position>8</position>
107 <width>12</width>
108 </field>
109 <field>
110 <name>DUTY</name>
111 <position>3</position>
112 <width>5</width>
113 </field>
114 <field>
115 <name>DOZE</name>
116 <position>2</position>
117 </field>
118 <field>
119 <name>LPM</name>
120 <position>0</position>
121 <width>2</width>
122 <enum>
123 <name>IDLE</name>
124 <value>0x0</value>
125 </enum>
126 <enum>
127 <name>SLEEP</name>
128 <value>0x1</value>
129 </enum>
130 </field>
131 </register>
132 </node>
133 <node>
134 <name>RESET</name>
135 <title>Reset status register</title>
136 <instance>
137 <name>RESET</name>
138 <address>0x8</address>
139 </instance>
140 <register>
141 <field>
142 <name>P0R</name>
143 <position>2</position>
144 </field>
145 <field>
146 <name>WR</name>
147 <position>1</position>
148 </field>
149 <field>
150 <name>PR</name>
151 <position>0</position>
152 </field>
153 </register>
154 </node>
155 <node>
156 <name>PLL0</name>
157 <title>PLL control register 0</title>
158 <instance>
159 <name>PL</name>
160 <address>0x10</address>
161 </instance>
162 <register>
163 <field>
164 <name>PLLM</name>
165 <position>24</position>
166 <width>7</width>
167 </field>
168 <field>
169 <name>PLLN</name>
170 <position>18</position>
171 <width>4</width>
172 </field>
173 <field>
174 <name>PLLOD</name>
175 <position>16</position>
176 <width>2</width>
177 </field>
178 <field>
179 <name>LOCK</name>
180 <desc>LOCK0 bit</desc>
181 <position>15</position>
182 </field>
183 <field>
184 <name>ENLOCK</name>
185 <position>14</position>
186 </field>
187 <field>
188 <name>PLLS</name>
189 <position>10</position>
190 </field>
191 <field>
192 <name>PLLBP</name>
193 <position>9</position>
194 </field>
195 <field>
196 <name>PLLEN</name>
197 <position>8</position>
198 </field>
199 <field>
200 <name>PLLST</name>
201 <position>0</position>
202 <width>8</width>
203 </field>
204 </register>
205 </node>
206 <node>
207 <name>PLLSWITCH</name>
208 <title>PLL switch and status register</title>
209 <instance>
210 <name>PLLSWITCH</name>
211 <address>0x14</address>
212 </instance>
213 <register>
214 <field>
215 <name>PLLOFF</name>
216 <position>31</position>
217 </field>
218 <field>
219 <name>PLLBP</name>
220 <position>30</position>
221 </field>
222 <field>
223 <name>PLLON</name>
224 <position>29</position>
225 </field>
226 <field>
227 <name>PS</name>
228 <position>28</position>
229 </field>
230 <field>
231 <name>FS</name>
232 <position>27</position>
233 </field>
234 <field>
235 <name>CS</name>
236 <position>26</position>
237 </field>
238 <field>
239 <name>SM</name>
240 <position>2</position>
241 </field>
242 <field>
243 <name>PM</name>
244 <position>1</position>
245 </field>
246 <field>
247 <name>FM</name>
248 <position>0</position>
249 </field>
250 </register>
251 </node>
252 <node>
253 <name>GATE0</name>
254 <title>Clock gate register 0</title>
255 <instance>
256 <name>GATE0</name>
257 <address>0x20</address>
258 </instance>
259 <register>
260 <field>
261 <name>EMC</name>
262 <position>31</position>
263 </field>
264 <field>
265 <name>DDR</name>
266 <position>30</position>
267 </field>
268 <field>
269 <name>IPU</name>
270 <position>29</position>
271 </field>
272 <field>
273 <name>LCD</name>
274 <position>28</position>
275 </field>
276 <field>
277 <name>TVE</name>
278 <position>27</position>
279 </field>
280 <field>
281 <name>CIM</name>
282 <position>26</position>
283 </field>
284 <field>
285 <name>MDMA</name>
286 <position>25</position>
287 </field>
288 <field>
289 <name>UHC</name>
290 <position>24</position>
291 </field>
292 <field>
293 <name>MAC</name>
294 <position>23</position>
295 </field>
296 <field>
297 <name>GPS</name>
298 <position>22</position>
299 </field>
300 <field>
301 <name>DMAC</name>
302 <position>21</position>
303 </field>
304 <field>
305 <name>SSI2</name>
306 <position>20</position>
307 </field>
308 <field>
309 <name>SSI1</name>
310 <position>19</position>
311 </field>
312 <field>
313 <name>UART3</name>
314 <position>18</position>
315 </field>
316 <field>
317 <name>UART2</name>
318 <position>17</position>
319 </field>
320 <field>
321 <name>UART1</name>
322 <position>16</position>
323 </field>
324 <field>
325 <name>UART0</name>
326 <position>15</position>
327 </field>
328 <field>
329 <name>SADC</name>
330 <position>14</position>
331 </field>
332 <field>
333 <name>KBC</name>
334 <position>13</position>
335 </field>
336 <field>
337 <name>MSC2</name>
338 <position>12</position>
339 </field>
340 <field>
341 <name>MSC1</name>
342 <position>11</position>
343 </field>
344 <field>
345 <name>OWI</name>
346 <position>10</position>
347 </field>
348 <field>
349 <name>TSSI</name>
350 <position>9</position>
351 </field>
352 <field>
353 <name>AIC</name>
354 <position>8</position>
355 </field>
356 <field>
357 <name>SCC</name>
358 <position>7</position>
359 </field>
360 <field>
361 <name>I2C1</name>
362 <position>6</position>
363 </field>
364 <field>
365 <name>I2C0</name>
366 <position>5</position>
367 </field>
368 <field>
369 <name>SSI0</name>
370 <position>4</position>
371 </field>
372 <field>
373 <name>MSC0</name>
374 <position>3</position>
375 </field>
376 <field>
377 <name>OTG</name>
378 <position>2</position>
379 </field>
380 <field>
381 <name>BCH</name>
382 <position>1</position>
383 </field>
384 <field>
385 <name>NEMC</name>
386 <position>0</position>
387 </field>
388 </register>
389 </node>
390 <node>
391 <name>OSC</name>
392 <title>Oscillator and power control register</title>
393 <instance>
394 <name>OSC</name>
395 <address>0x24</address>
396 </instance>
397 <register>
398 <field>
399 <name>O1ST</name>
400 <position>8</position>
401 <width>8</width>
402 </field>
403 <field>
404 <name>OTGPHY_ENABLE</name>
405 <desc>SPENDN bit</desc>
406 <position>7</position>
407 </field>
408 <field>
409 <name>GPSEN</name>
410 <position>6</position>
411 </field>
412 <field>
413 <name>UHCPHY_DISABLE</name>
414 <desc>SPENDH bit</desc>
415 <position>5</position>
416 </field>
417 <field>
418 <name>O1SE</name>
419 <position>4</position>
420 </field>
421 <field>
422 <name>PD</name>
423 <position>3</position>
424 </field>
425 <field>
426 <name>ERCS</name>
427 <position>2</position>
428 </field>
429 </register>
430 </node>
431 <node>
432 <name>GATE1</name>
433 <title>Clock gate register 1</title>
434 <instance>
435 <name>GATE1</name>
436 <address>0x28</address>
437 </instance>
438 <register>
439 <field>
440 <name>AUX</name>
441 <position>11</position>
442 </field>
443 <field>
444 <name>OSD</name>
445 <position>10</position>
446 </field>
447 <field>
448 <name>GPU</name>
449 <position>9</position>
450 </field>
451 <field>
452 <name>PCM</name>
453 <position>8</position>
454 </field>
455 <field>
456 <name>AHB1</name>
457 <position>7</position>
458 </field>
459 <field>
460 <name>CABAC</name>
461 <position>6</position>
462 </field>
463 <field>
464 <name>SRAM</name>
465 <position>5</position>
466 </field>
467 <field>
468 <name>DCT</name>
469 <position>4</position>
470 </field>
471 <field>
472 <name>ME</name>
473 <position>3</position>
474 </field>
475 <field>
476 <name>DBLK</name>
477 <position>2</position>
478 </field>
479 <field>
480 <name>MC</name>
481 <position>1</position>
482 </field>
483 <field>
484 <name>BDMA</name>
485 <position>0</position>
486 </field>
487 </register>
488 </node>
489 <node>
490 <name>PLL1</name>
491 <title>PLL control register 1</title>
492 <instance>
493 <name>PLL1</name>
494 <address>0x30</address>
495 </instance>
496 <register>
497 <field>
498 <name>PLL1M</name>
499 <position>24</position>
500 <width>7</width>
501 </field>
502 <field>
503 <name>PLL1N</name>
504 <position>18</position>
505 <width>4</width>
506 </field>
507 <field>
508 <name>PLL1OD</name>
509 <position>16</position>
510 <width>2</width>
511 </field>
512 <field>
513 <name>P1SCS</name>
514 <position>15</position>
515 </field>
516 <field>
517 <name>P1SDIV</name>
518 <position>9</position>
519 <width>6</width>
520 </field>
521 <field>
522 <name>PLL1EN</name>
523 <position>7</position>
524 </field>
525 <field>
526 <name>PLL1S</name>
527 <position>6</position>
528 </field>
529 <field>
530 <name>LOCK</name>
531 <desc>LOCK1 bit</desc>
532 <position>2</position>
533 </field>
534 <field>
535 <name>PLL1OFF</name>
536 <position>1</position>
537 </field>
538 <field>
539 <name>PLL1ON</name>
540 <position>0</position>
541 </field>
542 </register>
543 </node>
544 <node>
545 <name>SCRATCH</name>
546 <title>CPM scratch pad register</title>
547 <instance>
548 <name>SCRATCH</name>
549 <address>0x34</address>
550 </instance>
551 <register/>
552 </node>
553 <node>
554 <name>SCRATCHPROT</name>
555 <title>CPM scratch pad protected register</title>
556 <instance>
557 <name>SCRATCHPROT</name>
558 <address>0x38</address>
559 </instance>
560 <register/>
561 </node>
562 <node>
563 <name>USBPARAM</name>
564 <title>OTG parameter control register</title>
565 <instance>
566 <name>USBPARAM</name>
567 <address>0x3c</address>
568 </instance>
569 <register>
570 <field>
571 <name>USB_MODE</name>
572 <position>31</position>
573 </field>
574 <field>
575 <name>AVLD_REG</name>
576 <position>30</position>
577 </field>
578 <field>
579 <name>IDPULLUP</name>
580 <desc>IDPULLUP_MASK bit</desc>
581 <position>28</position>
582 <width>2</width>
583 </field>
584 <field>
585 <name>INCRM</name>
586 <desc>INCR_MASK bit</desc>
587 <position>27</position>
588 </field>
589 <field>
590 <name>CLK12_EN</name>
591 <position>26</position>
592 </field>
593 <field>
594 <name>COMMONONN</name>
595 <position>25</position>
596 </field>
597 <field>
598 <name>VBUSVLDEXT</name>
599 <position>24</position>
600 </field>
601 <field>
602 <name>VBUSVLDEXTSEL</name>
603 <position>23</position>
604 </field>
605 <field>
606 <name>POR</name>
607 <position>22</position>
608 </field>
609 <field>
610 <name>SIDDQ</name>
611 <position>21</position>
612 </field>
613 <field>
614 <name>OTG_DISABLE</name>
615 <position>20</position>
616 </field>
617 <field>
618 <name>COMPDISTUNE</name>
619 <position>17</position>
620 <width>3</width>
621 </field>
622 <field>
623 <name>OTGTUNE</name>
624 <position>14</position>
625 <width>3</width>
626 </field>
627 <field>
628 <name>SQRXTUNE</name>
629 <position>11</position>
630 <width>3</width>
631 </field>
632 <field>
633 <name>TXFSLSTUNE</name>
634 <position>7</position>
635 <width>4</width>
636 </field>
637 <field>
638 <name>TXPREEMPHTUNE</name>
639 <position>6</position>
640 </field>
641 <field>
642 <name>TXRISETUNE</name>
643 <position>4</position>
644 <width>2</width>
645 </field>
646 <field>
647 <name>TXVREFTUNE</name>
648 <position>0</position>
649 <width>4</width>
650 </field>
651 </register>
652 </node>
653 <node>
654 <name>USBRESET</name>
655 <title>OTG reset detect timer register</title>
656 <instance>
657 <name>USBRESET</name>
658 <address>0x40</address>
659 </instance>
660 <register>
661 <field>
662 <name>VBFIL_LD_EN</name>
663 <position>25</position>
664 </field>
665 <field>
666 <name>IDDIG_EN</name>
667 <position>24</position>
668 </field>
669 <field>
670 <name>IDDIG_REG</name>
671 <position>23</position>
672 </field>
673 <field>
674 <name>USBRDT</name>
675 <position>0</position>
676 <width>23</width>
677 </field>
678 </register>
679 </node>
680 <node>
681 <name>USBVBUS</name>
682 <instance>
683 <name>USBVBUS</name>
684 <address>0x44</address>
685 </instance>
686 <register/>
687 </node>
688 <node>
689 <name>USB</name>
690 <title>OTG PHY clock divider register</title>
691 <instance>
692 <name>USB</name>
693 <address>0x50</address>
694 </instance>
695 <register>
696 <field>
697 <name>UCS</name>
698 <position>31</position>
699 </field>
700 <field>
701 <name>UPCS</name>
702 <position>30</position>
703 </field>
704 <field>
705 <name>OTGDIV</name>
706 <desc>USBCDR bit</desc>
707 <position>0</position>
708 <width>6</width>
709 </field>
710 </register>
711 </node>
712 <node>
713 <name>I2S</name>
714 <title>I2S device clock divider register</title>
715 <instance>
716 <name>I2S</name>
717 <address>0x60</address>
718 </instance>
719 <register>
720 <field>
721 <name>I2CS</name>
722 <position>31</position>
723 </field>
724 <field>
725 <name>I2PCS</name>
726 <position>30</position>
727 </field>
728 <field>
729 <name>I2SDIV</name>
730 <desc>I2SCDR bit</desc>
731 <position>0</position>
732 <width>9</width>
733 </field>
734 </register>
735 </node>
736 <node>
737 <name>LCD</name>
738 <title>LCD pix clock divider register</title>
739 <instance>
740 <name>LCD</name>
741 <address>0x64</address>
742 </instance>
743 <register>
744 <field>
745 <name>LTCS</name>
746 <position>30</position>
747 </field>
748 <field>
749 <name>LPCS</name>
750 <position>29</position>
751 </field>
752 <field>
753 <name>PIXDIV</name>
754 <desc>LPCDR bit</desc>
755 <position>0</position>
756 <width>11</width>
757 </field>
758 </register>
759 </node>
760 <node>
761 <name>MSC</name>
762 <title>MSC clock divider register</title>
763 <instance>
764 <name>MSC</name>
765 <address>0x68</address>
766 </instance>
767 <register>
768 <field>
769 <name>MCS</name>
770 <position>31</position>
771 </field>
772 <field>
773 <name>MSCDIV</name>
774 <desc>MSCCDR bit</desc>
775 <position>0</position>
776 <width>6</width>
777 </field>
778 </register>
779 </node>
780 <node>
781 <name>UHC</name>
782 <title>UHC device clock divider register</title>
783 <instance>
784 <name>UHC</name>
785 <address>0x6c</address>
786 </instance>
787 <register>
788 <field>
789 <name>UHPCS</name>
790 <position>31</position>
791 </field>
792 <field>
793 <name>UHCDIV</name>
794 <desc>UHCCDR bit</desc>
795 <position>0</position>
796 <width>4</width>
797 </field>
798 </register>
799 </node>
800 <node>
801 <name>SSI</name>
802 <title>SSI clock divider register</title>
803 <instance>
804 <name>SSI</name>
805 <address>0x74</address>
806 </instance>
807 <register>
808 <field>
809 <name>SCS</name>
810 <position>31</position>
811 </field>
812 <field>
813 <name>SSIDIV</name>
814 <desc>SSICDR bit</desc>
815 <position>0</position>
816 <width>6</width>
817 </field>
818 </register>
819 </node>
820 <node>
821 <name>CIM</name>
822 <title>CIM mclk clock divider register</title>
823 <instance>
824 <name>CIM</name>
825 <address>0x7c</address>
826 </instance>
827 <register>
828 <field>
829 <name>CIMDIV</name>
830 <desc>CIMCDR bit</desc>
831 <position>0</position>
832 <width>8</width>
833 </field>
834 </register>
835 </node>
836 <node>
837 <name>GPS</name>
838 <title>GPS clock divider register</title>
839 <instance>
840 <name>GPS</name>
841 <address>0x80</address>
842 </instance>
843 <register>
844 <field>
845 <name>GPCS</name>
846 <position>31</position>
847 </field>
848 <field>
849 <name>GPSDIV</name>
850 <desc>GPSCDR bit</desc>
851 <position>0</position>
852 <width>4</width>
853 </field>
854 </register>
855 </node>
856 <node>
857 <name>PCM</name>
858 <title>PCM device clock divider register</title>
859 <instance>
860 <name>PCM</name>
861 <address>0x84</address>
862 </instance>
863 <register>
864 <field>
865 <name>PCMS</name>
866 <position>31</position>
867 </field>
868 <field>
869 <name>PCMPCS</name>
870 <position>30</position>
871 </field>
872 <field>
873 <name>PCMDIV</name>
874 <desc>PCMCDR bit</desc>
875 <position>0</position>
876 <width>9</width>
877 </field>
878 </register>
879 </node>
880 <node>
881 <name>GPU</name>
882 <instance>
883 <name>GPU</name>
884 <address>0x88</address>
885 </instance>
886 <register>
887 <field>
888 <name>GPCS</name>
889 <position>31</position>
890 </field>
891 <field>
892 <name>GPUDIV</name>
893 <desc>GPUCDR bit</desc>
894 <position>0</position>
895 <width>3</width>
896 </field>
897 </register>
898 </node>
899 <node>
900 <name>PSWC0ST</name>
901 <instance>
902 <name>PSWC0ST</name>
903 <address>0x90</address>
904 </instance>
905 <register/>
906 </node>
907 <node>
908 <name>PSWC1ST</name>
909 <instance>
910 <name>PSWC1ST</name>
911 <address>0x94</address>
912 </instance>
913 <register/>
914 </node>
915 <node>
916 <name>PSWC2ST</name>
917 <instance>
918 <name>PSWC2ST</name>
919 <address>0x98</address>
920 </instance>
921 <register/>
922 </node>
923 <node>
924 <name>PSWC3ST</name>
925 <instance>
926 <name>PSWC3ST</name>
927 <address>0x9c</address>
928 </instance>
929 <register/>
930 </node>
931 </node>
932 <node>
933 <name>INTC</name>
934 <title>INTC (Interrupt Controller)</title>
935 <instance>
936 <name>INTC</name>
937 <address>0xb0001000</address>
938 </instance>
939 <node>
940 <name>ISR</name>
941 <instance>
942 <name>ISR</name>
943 <range>
944 <first>0</first>
945 <count>2</count>
946 <formula variable="n">0x00 + (n) * 0x20</formula>
947 </range>
948 </instance>
949 <register/>
950 </node>
951 <node>
952 <name>IMR</name>
953 <instance>
954 <name>IMR</name>
955 <range>
956 <first>0</first>
957 <count>2</count>
958 <formula variable="n">0x04 + (n) * 0x20</formula>
959 </range>
960 </instance>
961 <register/>
962 </node>
963 <node>
964 <name>IMSR</name>
965 <instance>
966 <name>IMSR</name>
967 <range>
968 <first>0</first>
969 <count>2</count>
970 <formula variable="n">0x08 + (n) * 0x20</formula>
971 </range>
972 </instance>
973 <register/>
974 </node>
975 <node>
976 <name>IMCR</name>
977 <instance>
978 <name>IMCR</name>
979 <range>
980 <first>0</first>
981 <count>2</count>
982 <formula variable="n">0x0c + (n) * 0x20</formula>
983 </range>
984 </instance>
985 <register/>
986 </node>
987 <node>
988 <name>IPR</name>
989 <instance>
990 <name>IPR</name>
991 <range>
992 <first>0</first>
993 <count>2</count>
994 <formula variable="n">0x10 + (n) * 0x20</formula>
995 </range>
996 </instance>
997 <register/>
998 </node>
999 </node>
1000 <node>
1001 <name>OST</name>
1002 <title>Operating System Timer</title>
1003 <instance>
1004 <name>OST</name>
1005 <address>0xb0002000</address>
1006 </instance>
1007 <node>
1008 <name>DATA</name>
1009 <title>Data register</title>
1010 <instance>
1011 <name>DATA</name>
1012 <address>0xe0</address>
1013 </instance>
1014 <register/>
1015 </node>
1016 <node>
1017 <name>COUNTL</name>
1018 <title>Count (low part)</title>
1019 <instance>
1020 <name>COUNTL</name>
1021 <address>0xe4</address>
1022 </instance>
1023 <register/>
1024 </node>
1025 <node>
1026 <name>COUNTH</name>
1027 <title>Count (high-part)</title>
1028 <instance>
1029 <name>COUNTH</name>
1030 <address>0xe8</address>
1031 </instance>
1032 <register/>
1033 </node>
1034 <node>
1035 <name>CTRL</name>
1036 <title>Operating system control register</title>
1037 <instance>
1038 <name>CTRL</name>
1039 <address>0xec</address>
1040 </instance>
1041 <register>
1042 <width>16</width>
1043 <field>
1044 <name>CNT_MD</name>
1045 <position>15</position>
1046 </field>
1047 <field>
1048 <name>SD</name>
1049 <position>9</position>
1050 </field>
1051 <field>
1052 <name>PRESCALE</name>
1053 <position>3</position>
1054 <width>3</width>
1055 <enum>
1056 <name>1</name>
1057 <value>0x0</value>
1058 </enum>
1059 <enum>
1060 <name>4</name>
1061 <value>0x1</value>
1062 </enum>
1063 <enum>
1064 <name>16</name>
1065 <value>0x2</value>
1066 </enum>
1067 <enum>
1068 <name>64</name>
1069 <value>0x3</value>
1070 </enum>
1071 <enum>
1072 <name>256</name>
1073 <value>0x4</value>
1074 </enum>
1075 <enum>
1076 <name>1024</name>
1077 <value>0x5</value>
1078 </enum>
1079 </field>
1080 <field>
1081 <name>EXT_EN</name>
1082 <position>2</position>
1083 </field>
1084 <field>
1085 <name>RTC_EN</name>
1086 <position>1</position>
1087 </field>
1088 <field>
1089 <name>PCK_EN</name>
1090 <position>0</position>
1091 </field>
1092 </register>
1093 </node>
1094 <node>
1095 <name>COUNTH_BUF</name>
1096 <instance>
1097 <name>OSTCNTH_BUF</name>
1098 <address>0xfc</address>
1099 </instance>
1100 <register/>
1101 </node>
1102 </node>
1103 <node>
1104 <name>TCU</name>
1105 <title>Timer and counter unit module</title>
1106 <instance>
1107 <name>TCU</name>
1108 <address>0xb0002000</address>
1109 </instance>
1110 <node>
1111 <name>ENABLE</name>
1112 <title>Timer counter enable register</title>
1113 <instance>
1114 <name>ENABLE</name>
1115 <address>0x10</address>
1116 </instance>
1117 <register>
1118 <width>16</width>
1119 <field>
1120 <name>OSTEN</name>
1121 <position>15</position>
1122 </field>
1123 <field>
1124 <name>TCEN</name>
1125 <position>0</position>
1126 <width>8</width>
1127 </field>
1128 <variant>
1129 <type>set</type>
1130 <offset>4</offset>
1131 </variant>
1132 <variant>
1133 <type>clr</type>
1134 <offset>8</offset>
1135 </variant>
1136 </register>
1137 </node>
1138 <node>
1139 <name>STOP</name>
1140 <title>Timer stop register</title>
1141 <instance>
1142 <name>STOP</name>
1143 <address>0x1c</address>
1144 </instance>
1145 <register>
1146 <field>
1147 <name>WDT_STOP</name>
1148 <position>16</position>
1149 </field>
1150 <field>
1151 <name>OST_STOP</name>
1152 <position>15</position>
1153 </field>
1154 <field>
1155 <name>TIMER_STOP</name>
1156 <position>0</position>
1157 <width>8</width>
1158 </field>
1159 <variant>
1160 <type>set</type>
1161 <offset>16</offset>
1162 </variant>
1163 <variant>
1164 <type>clr</type>
1165 <offset>32</offset>
1166 </variant>
1167 </register>
1168 </node>
1169 <node>
1170 <name>FLAG</name>
1171 <title>Timer flag register</title>
1172 <instance>
1173 <name>FLAG</name>
1174 <address>0x20</address>
1175 </instance>
1176 <register>
1177 <field>
1178 <name>HFLAG</name>
1179 <position>16</position>
1180 <width>8</width>
1181 </field>
1182 <field>
1183 <name>OSTFLAG</name>
1184 <position>15</position>
1185 </field>
1186 <field>
1187 <name>FFLAG</name>
1188 <position>0</position>
1189 <width>8</width>
1190 </field>
1191 <variant>
1192 <type>set</type>
1193 <offset>4</offset>
1194 </variant>
1195 <variant>
1196 <type>clr</type>
1197 <offset>8</offset>
1198 </variant>
1199 </register>
1200 </node>
1201 <node>
1202 <name>MASK</name>
1203 <title>Timer mask register</title>
1204 <instance>
1205 <name>TMR</name>
1206 <address>0x30</address>
1207 </instance>
1208 <register>
1209 <field>
1210 <name>HMASK</name>
1211 <position>16</position>
1212 <width>8</width>
1213 </field>
1214 <field>
1215 <name>OSTMASK</name>
1216 <position>15</position>
1217 </field>
1218 <field>
1219 <name>FMASK</name>
1220 <position>0</position>
1221 <width>8</width>
1222 </field>
1223 <variant>
1224 <type>set</type>
1225 <offset>4</offset>
1226 </variant>
1227 <variant>
1228 <type>clr</type>
1229 <offset>8</offset>
1230 </variant>
1231 </register>
1232 </node>
1233 <node>
1234 <name>DATA_FULL</name>
1235 <title>Timer data full register</title>
1236 <instance>
1237 <name>DATA_FULL</name>
1238 <range>
1239 <first>0</first>
1240 <count>8</count>
1241 <formula variable="n">(n) * 0x10 + 0x40</formula>
1242 </range>
1243 </instance>
1244 <register>
1245 <width>16</width>
1246 <field>
1247 <name>TDFR</name>
1248 <position>0</position>
1249 <width>16</width>
1250 </field>
1251 </register>
1252 </node>
1253 <node>
1254 <name>DATA_HALF</name>
1255 <title>Timer data half register</title>
1256 <instance>
1257 <name>DATA_HALF</name>
1258 <range>
1259 <first>0</first>
1260 <count>8</count>
1261 <formula variable="n">(n) * 0x10 + 0x44</formula>
1262 </range>
1263 </instance>
1264 <register>
1265 <width>16</width>
1266 <field>
1267 <name>TDHR</name>
1268 <position>0</position>
1269 <width>16</width>
1270 </field>
1271 </register>
1272 </node>
1273 <node>
1274 <name>COUNT</name>
1275 <title>Timer counter register</title>
1276 <instance>
1277 <name>COUNT</name>
1278 <range>
1279 <first>0</first>
1280 <count>8</count>
1281 <formula variable="n">(n) * 0x10 + 0x48</formula>
1282 </range>
1283 </instance>
1284 <register>
1285 <width>16</width>
1286 <field>
1287 <name>TCNT</name>
1288 <position>0</position>
1289 <width>16</width>
1290 </field>
1291 </register>
1292 </node>
1293 <node>
1294 <name>CTRL</name>
1295 <title>Timer control register</title>
1296 <instance>
1297 <name>CTRL</name>
1298 <range>
1299 <first>0</first>
1300 <count>8</count>
1301 <formula variable="n">(n) * 0x10 + 0x4c</formula>
1302 </range>
1303 </instance>
1304 <register>
1305 <width>16</width>
1306 <field>
1307 <name>CLRZ</name>
1308 <position>10</position>
1309 </field>
1310 <field>
1311 <name>SD_ABRUPT</name>
1312 <position>9</position>
1313 </field>
1314 <field>
1315 <name>INITL_HIGH</name>
1316 <position>8</position>
1317 </field>
1318 <field>
1319 <name>PWM_EN</name>
1320 <position>7</position>
1321 </field>
1322 <field>
1323 <name>PWM_IN_EN</name>
1324 <position>6</position>
1325 </field>
1326 <field>
1327 <name>PRESCALE</name>
1328 <position>3</position>
1329 <width>3</width>
1330 <enum>
1331 <name>1</name>
1332 <value>0x0</value>
1333 </enum>
1334 <enum>
1335 <name>4</name>
1336 <value>0x1</value>
1337 </enum>
1338 <enum>
1339 <name>16</name>
1340 <value>0x2</value>
1341 </enum>
1342 <enum>
1343 <name>64</name>
1344 <value>0x3</value>
1345 </enum>
1346 <enum>
1347 <name>256</name>
1348 <value>0x4</value>
1349 </enum>
1350 <enum>
1351 <name>1024</name>
1352 <value>0x5</value>
1353 </enum>
1354 </field>
1355 <field>
1356 <name>EXT_EN</name>
1357 <position>2</position>
1358 </field>
1359 <field>
1360 <name>RTC_EN</name>
1361 <position>1</position>
1362 </field>
1363 <field>
1364 <name>PCK_EN</name>
1365 <position>0</position>
1366 </field>
1367 </register>
1368 </node>
1369 <node>
1370 <name>STATUS</name>
1371 <title>Timer status register</title>
1372 <instance>
1373 <name>TSTR</name>
1374 <address>0xf0</address>
1375 </instance>
1376 <register>
1377 <field>
1378 <name>REAL2</name>
1379 <position>18</position>
1380 </field>
1381 <field>
1382 <name>REAL1</name>
1383 <position>17</position>
1384 </field>
1385 <field>
1386 <name>BUSY2</name>
1387 <position>2</position>
1388 </field>
1389 <field>
1390 <name>BUSY1</name>
1391 <position>1</position>
1392 </field>
1393 <variant>
1394 <type>set</type>
1395 <offset>4</offset>
1396 </variant>
1397 <variant>
1398 <type>clr</type>
1399 <offset>8</offset>
1400 </variant>
1401 </register>
1402 </node>
1403 </node>
1404 <node>
1405 <name>WDT</name>
1406 <title>Watchdog timer module</title>
1407 <instance>
1408 <name>WDT</name>
1409 <address>0xb0002000</address>
1410 </instance>
1411 <node>
1412 <name>DATA</name>
1413 <instance>
1414 <name>DATA</name>
1415 <address>0x0</address>
1416 </instance>
1417 <register>
1418 <width>16</width>
1419 </register>
1420 </node>
1421 <node>
1422 <name>ENABLE</name>
1423 <title>Watchdog counter enable register</title>
1424 <instance>
1425 <name>ENABLE</name>
1426 <address>0x4</address>
1427 </instance>
1428 <register>
1429 <width>8</width>
1430 <field>
1431 <name>TCEN</name>
1432 <position>0</position>
1433 </field>
1434 </register>
1435 </node>
1436 <node>
1437 <name>COUNT</name>
1438 <instance>
1439 <name>COUNT</name>
1440 <address>0x8</address>
1441 </instance>
1442 <register>
1443 <width>16</width>
1444 </register>
1445 </node>
1446 <node>
1447 <name>CTRL</name>
1448 <title>Watchdog control register</title>
1449 <instance>
1450 <name>CTRL</name>
1451 <address>0xc</address>
1452 </instance>
1453 <register>
1454 <width>16</width>
1455 <field>
1456 <name>PRESCALE</name>
1457 <position>3</position>
1458 <width>3</width>
1459 <enum>
1460 <name>1</name>
1461 <value>0x0</value>
1462 </enum>
1463 <enum>
1464 <name>4</name>
1465 <value>0x1</value>
1466 </enum>
1467 <enum>
1468 <name>16</name>
1469 <value>0x2</value>
1470 </enum>
1471 <enum>
1472 <name>64</name>
1473 <value>0x3</value>
1474 </enum>
1475 <enum>
1476 <name>256</name>
1477 <value>0x4</value>
1478 </enum>
1479 <enum>
1480 <name>1024</name>
1481 <value>0x5</value>
1482 </enum>
1483 </field>
1484 <field>
1485 <name>CLKIN</name>
1486 <position>0</position>
1487 <width>3</width>
1488 <enum>
1489 <name>PCK</name>
1490 <value>0x1</value>
1491 </enum>
1492 <enum>
1493 <name>RTC</name>
1494 <value>0x2</value>
1495 </enum>
1496 <enum>
1497 <name>EXT</name>
1498 <value>0x4</value>
1499 </enum>
1500 </field>
1501 </register>
1502 </node>
1503 </node>
1504 <node>
1505 <name>RTC</name>
1506 <title>Real time clock module(RTC) address definition</title>
1507 <instance>
1508 <name>RTC</name>
1509 <address>0xb0003000</address>
1510 </instance>
1511 <node>
1512 <name>RTCCR</name>
1513 <title>RTC control register</title>
1514 <instance>
1515 <name>RTCCR</name>
1516 <address>0x0</address>
1517 </instance>
1518 <register>
1519 <field>
1520 <name>WRDY</name>
1521 <position>7</position>
1522 </field>
1523 <field>
1524 <name>1HZ</name>
1525 <position>6</position>
1526 </field>
1527 <field>
1528 <name>1HZIE</name>
1529 <position>5</position>
1530 </field>
1531 <field>
1532 <name>AF</name>
1533 <position>4</position>
1534 </field>
1535 <field>
1536 <name>AIE</name>
1537 <position>3</position>
1538 </field>
1539 <field>
1540 <name>AE</name>
1541 <position>2</position>
1542 </field>
1543 <field>
1544 <name>SELEXC</name>
1545 <position>1</position>
1546 </field>
1547 <field>
1548 <name>RTCE</name>
1549 <position>0</position>
1550 </field>
1551 </register>
1552 </node>
1553 <node>
1554 <name>RTCSR</name>
1555 <instance>
1556 <name>RTCSR</name>
1557 <address>0x4</address>
1558 </instance>
1559 <register/>
1560 </node>
1561 <node>
1562 <name>RTCSAR</name>
1563 <instance>
1564 <name>RTCSAR</name>
1565 <address>0x8</address>
1566 </instance>
1567 <register/>
1568 </node>
1569 <node>
1570 <name>RTCGR</name>
1571 <title>RTC regulator register</title>
1572 <instance>
1573 <name>RTCGR</name>
1574 <address>0xc</address>
1575 </instance>
1576 <register>
1577 <field>
1578 <name>LOCK</name>
1579 <position>31</position>
1580 </field>
1581 <field>
1582 <name>ADJC</name>
1583 <position>16</position>
1584 <width>10</width>
1585 </field>
1586 <field>
1587 <name>NC1HZ</name>
1588 <position>0</position>
1589 <width>16</width>
1590 </field>
1591 </register>
1592 </node>
1593 <node>
1594 <name>HCR</name>
1595 <title>Hibernate control register</title>
1596 <instance>
1597 <name>HCR</name>
1598 <address>0x20</address>
1599 </instance>
1600 <register>
1601 <field>
1602 <name>PD</name>
1603 <position>0</position>
1604 </field>
1605 </register>
1606 </node>
1607 <node>
1608 <name>HWFCR</name>
1609 <title>Hibernate wakeup filter counter register</title>
1610 <instance>
1611 <name>HWFCR</name>
1612 <address>0x24</address>
1613 </instance>
1614 <register>
1615 <field>
1616 <name>HWFCR</name>
1617 <position>5</position>
1618 <width>11</width>
1619 </field>
1620 </register>
1621 </node>
1622 <node>
1623 <name>HRCR</name>
1624 <title>Hibernate reset counter register</title>
1625 <instance>
1626 <name>HRCR</name>
1627 <address>0x28</address>
1628 </instance>
1629 <register>
1630 <field>
1631 <name>HRCR</name>
1632 <position>5</position>
1633 <width>7</width>
1634 </field>
1635 </register>
1636 </node>
1637 <node>
1638 <name>HWCR</name>
1639 <title>Hibernate wakeup control register</title>
1640 <instance>
1641 <name>HWCR</name>
1642 <address>0x2c</address>
1643 </instance>
1644 <register>
1645 <field>
1646 <name>EPDET</name>
1647 <position>3</position>
1648 </field>
1649 <field>
1650 <name>WKUPVL</name>
1651 <position>2</position>
1652 </field>
1653 <field>
1654 <name>EALM</name>
1655 <position>0</position>
1656 </field>
1657 </register>
1658 </node>
1659 <node>
1660 <name>HWRSR</name>
1661 <title>Hibernate wakeup status register</title>
1662 <instance>
1663 <name>HWRSR</name>
1664 <address>0x30</address>
1665 </instance>
1666 <register>
1667 <field>
1668 <name>APD</name>
1669 <position>8</position>
1670 </field>
1671 <field>
1672 <name>HR</name>
1673 <position>5</position>
1674 </field>
1675 <field>
1676 <name>PPR</name>
1677 <position>4</position>
1678 </field>
1679 <field>
1680 <name>PIN</name>
1681 <position>1</position>
1682 </field>
1683 <field>
1684 <name>ALM</name>
1685 <position>0</position>
1686 </field>
1687 </register>
1688 </node>
1689 <node>
1690 <name>HSPR</name>
1691 <title>Hibernate scratch pattern register</title>
1692 <instance>
1693 <name>HSPR</name>
1694 <address>0x34</address>
1695 </instance>
1696 <register/>
1697 </node>
1698 <node>
1699 <name>WENR</name>
1700 <title>write enable pattern register</title>
1701 <instance>
1702 <name>WENR</name>
1703 <address>0x3c</address>
1704 </instance>
1705 <register>
1706 <field>
1707 <name>WEN</name>
1708 <position>31</position>
1709 </field>
1710 <field>
1711 <name>WENPAT</name>
1712 <position>0</position>
1713 <width>16</width>
1714 </field>
1715 </register>
1716 </node>
1717 </node>
1718 <node>
1719 <name>GPIO</name>
1720 <title>General purpose I/O port module(GPIO) address definition</title>
1721 <instance>
1722 <name>GPIO</name>
1723 <address>0xb0010000</address>
1724 </instance>
1725 <node>
1726 <name>IN</name>
1727 <title>Port IN</title>
1728 <instance>
1729 <name>IN</name>
1730 <range>
1731 <first>0</first>
1732 <count>6</count>
1733 <formula variable="n">(n)*0x100 + 0x00</formula>
1734 </range>
1735 </instance>
1736 <register/>
1737 </node>
1738 <node>
1739 <name>OUT</name>
1740 <title>Port OUT</title>
1741 <instance>
1742 <name>OUT</name>
1743 <range>
1744 <first>0</first>
1745 <count>6</count>
1746 <formula variable="n">(n)*0x100 + 0x10</formula>
1747 </range>
1748 </instance>
1749 <register>
1750 <variant>
1751 <type>set</type>
1752 <offset>4</offset>
1753 </variant>
1754 <variant>
1755 <type>clr</type>
1756 <offset>8</offset>
1757 </variant>
1758 </register>
1759 </node>
1760 <node>
1761 <name>FLGC</name>
1762 <instance>
1763 <name>FLGC</name>
1764 <range>
1765 <first>0</first>
1766 <count>6</count>
1767 <formula variable="n">(n)*0x100 + 0x14</formula>
1768 </range>
1769 </instance>
1770 <register/>
1771 </node>
1772 <node>
1773 <name>MASK</name>
1774 <instance>
1775 <name>MASK</name>
1776 <range>
1777 <first>0</first>
1778 <count>6</count>
1779 <formula variable="n">(n)*0x100 + 0x20</formula>
1780 </range>
1781 </instance>
1782 <register>
1783 <variant>
1784 <type>set</type>
1785 <offset>4</offset>
1786 </variant>
1787 <variant>
1788 <type>clr</type>
1789 <offset>8</offset>
1790 </variant>
1791 </register>
1792 </node>
1793 <node>
1794 <name>PULL</name>
1795 <instance>
1796 <name>PULL</name>
1797 <range>
1798 <first>0</first>
1799 <count>6</count>
1800 <formula variable="n">(n)*0x100 + 0x30</formula>
1801 </range>
1802 </instance>
1803 <register>
1804 <variant>
1805 <type>set</type>
1806 <offset>4</offset>
1807 </variant>
1808 <variant>
1809 <type>clr</type>
1810 <offset>8</offset>
1811 </variant>
1812 </register>
1813 </node>
1814 <node>
1815 <name>FUN</name>
1816 <title>Function</title>
1817 <instance>
1818 <name>FUN</name>
1819 <range>
1820 <first>0</first>
1821 <count>6</count>
1822 <formula variable="n">(n)*0x100 + 0x40</formula>
1823 </range>
1824 </instance>
1825 <register>
1826 <variant>
1827 <type>set</type>
1828 <offset>4</offset>
1829 </variant>
1830 <variant>
1831 <type>clr</type>
1832 <offset>8</offset>
1833 </variant>
1834 </register>
1835 </node>
1836 <node>
1837 <name>SEL</name>
1838 <title>Select</title>
1839 <instance>
1840 <name>SEL</name>
1841 <range>
1842 <first>0</first>
1843 <count>6</count>
1844 <formula variable="n">(n)*0x100 + 0x50</formula>
1845 </range>
1846 </instance>
1847 <register>
1848 <variant>
1849 <type>set</type>
1850 <offset>4</offset>
1851 </variant>
1852 <variant>
1853 <type>clr</type>
1854 <offset>8</offset>
1855 </variant>
1856 </register>
1857 </node>
1858 <node>
1859 <name>DIR</name>
1860 <title>Direction</title>
1861 <instance>
1862 <name>DIR</name>
1863 <range>
1864 <first>0</first>
1865 <count>6</count>
1866 <formula variable="n">(n)*0x100 + 0x60</formula>
1867 </range>
1868 </instance>
1869 <register>
1870 <variant>
1871 <type>set</type>
1872 <offset>4</offset>
1873 </variant>
1874 <variant>
1875 <type>clr</type>
1876 <offset>8</offset>
1877 </variant>
1878 </register>
1879 </node>
1880 <node>
1881 <name>TRG</name>
1882 <title>Trigger</title>
1883 <instance>
1884 <name>TRG</name>
1885 <range>
1886 <first>0</first>
1887 <count>6</count>
1888 <formula variable="n">(n)*0x100 + 0x70</formula>
1889 </range>
1890 </instance>
1891 <register>
1892 <variant>
1893 <type>set</type>
1894 <offset>4</offset>
1895 </variant>
1896 <variant>
1897 <type>clr</type>
1898 <offset>8</offset>
1899 </variant>
1900 </register>
1901 </node>
1902 <node>
1903 <name>FLG</name>
1904 <title>Flag</title>
1905 <instance>
1906 <name>FLG</name>
1907 <range>
1908 <first>0</first>
1909 <count>6</count>
1910 <formula variable="n">(n)*0x100 + 0x80</formula>
1911 </range>
1912 </instance>
1913 <register/>
1914 </node>
1915 <node>
1916 <name>DRIVE0</name>
1917 <title>Drive strength 0</title>
1918 <instance>
1919 <name>DRIVE0</name>
1920 <range>
1921 <first>0</first>
1922 <count>6</count>
1923 <formula variable="n">(n)*0x100 + 0xc0</formula>
1924 </range>
1925 </instance>
1926 <register>
1927 <variant>
1928 <type>set</type>
1929 <offset>4</offset>
1930 </variant>
1931 <variant>
1932 <type>clr</type>
1933 <offset>8</offset>
1934 </variant>
1935 </register>
1936 </node>
1937 <node>
1938 <name>DRIVE1</name>
1939 <instance>
1940 <name>DRIVE1</name>
1941 <range>
1942 <first>0</first>
1943 <count>6</count>
1944 <formula variable="n">(n)*0x100 + 0xd0</formula>
1945 </range>
1946 </instance>
1947 <register>
1948 <variant>
1949 <type>set</type>
1950 <offset>4</offset>
1951 </variant>
1952 <variant>
1953 <type>clr</type>
1954 <offset>8</offset>
1955 </variant>
1956 </register>
1957 </node>
1958 <node>
1959 <name>DRIVE2</name>
1960 <instance>
1961 <name>DRIVE2</name>
1962 <range>
1963 <first>0</first>
1964 <count>6</count>
1965 <formula variable="n">(n)*0x100 + 0xe0</formula>
1966 </range>
1967 </instance>
1968 <register>
1969 <variant>
1970 <type>set</type>
1971 <offset>4</offset>
1972 </variant>
1973 <variant>
1974 <type>clr</type>
1975 <offset>8</offset>
1976 </variant>
1977 </register>
1978 </node>
1979 <node>
1980 <name>SLEW</name>
1981 <title>Slew rate control</title>
1982 <instance>
1983 <name>SLEW</name>
1984 <range>
1985 <first>0</first>
1986 <count>6</count>
1987 <formula variable="n">(n)*0x100 + 0xf0</formula>
1988 </range>
1989 </instance>
1990 <register>
1991 <variant>
1992 <type>set</type>
1993 <offset>4</offset>
1994 </variant>
1995 <variant>
1996 <type>clr</type>
1997 <offset>8</offset>
1998 </variant>
1999 </register>
2000 </node>
2001 </node>
2002 <node>
2003 <name>AIC</name>
2004 <title>AC97 and I2S controller module</title>
2005 <instance>
2006 <name>AIC</name>
2007 <address>0xb0020000</address>
2008 </instance>
2009 <node>
2010 <name>FR</name>
2011 <title>AIC controller configuration register</title>
2012 <instance>
2013 <name>FR</name>
2014 <address>0x0</address>
2015 </instance>
2016 <register>
2017 <field>
2018 <name>RFTH</name>
2019 <position>24</position>
2020 <width>4</width>
2021 </field>
2022 <field>
2023 <name>TFTH</name>
2024 <position>16</position>
2025 <width>5</width>
2026 </field>
2027 <field>
2028 <name>LSMP</name>
2029 <position>6</position>
2030 </field>
2031 <field>
2032 <name>ICDC</name>
2033 <position>5</position>
2034 </field>
2035 <field>
2036 <name>AUSEL</name>
2037 <position>4</position>
2038 </field>
2039 <field>
2040 <name>RST</name>
2041 <position>3</position>
2042 </field>
2043 <field>
2044 <name>BCKD</name>
2045 <position>2</position>
2046 </field>
2047 <field>
2048 <name>SYNCD</name>
2049 <position>1</position>
2050 </field>
2051 <field>
2052 <name>ENB</name>
2053 <position>0</position>
2054 </field>
2055 </register>
2056 </node>
2057 <node>
2058 <name>CR</name>
2059 <title>AIC controller common control register</title>
2060 <instance>
2061 <name>CR</name>
2062 <address>0x4</address>
2063 </instance>
2064 <register>
2065 <field>
2066 <name>PACK16</name>
2067 <position>28</position>
2068 </field>
2069 <field>
2070 <name>CHANNEL</name>
2071 <position>24</position>
2072 <width>3</width>
2073 </field>
2074 <field>
2075 <name>OSS</name>
2076 <position>19</position>
2077 <width>3</width>
2078 </field>
2079 <field>
2080 <name>ISS</name>
2081 <position>16</position>
2082 <width>3</width>
2083 </field>
2084 <field>
2085 <name>RDMS</name>
2086 <position>15</position>
2087 </field>
2088 <field>
2089 <name>TDMS</name>
2090 <position>14</position>
2091 </field>
2092 <field>
2093 <name>M2S</name>
2094 <position>11</position>
2095 </field>
2096 <field>
2097 <name>ENDSW</name>
2098 <position>10</position>
2099 </field>
2100 <field>
2101 <name>AVSTSU</name>
2102 <position>9</position>
2103 </field>
2104 <field>
2105 <name>TFLUSH</name>
2106 <position>8</position>
2107 </field>
2108 <field>
2109 <name>RFLUSH</name>
2110 <position>7</position>
2111 </field>
2112 <field>
2113 <name>EROR</name>
2114 <position>6</position>
2115 </field>
2116 <field>
2117 <name>ETUR</name>
2118 <position>5</position>
2119 </field>
2120 <field>
2121 <name>ERFS</name>
2122 <position>4</position>
2123 </field>
2124 <field>
2125 <name>ETFS</name>
2126 <position>3</position>
2127 </field>
2128 <field>
2129 <name>ENLBF</name>
2130 <position>2</position>
2131 </field>
2132 <field>
2133 <name>ERPL</name>
2134 <position>1</position>
2135 </field>
2136 <field>
2137 <name>EREC</name>
2138 <position>0</position>
2139 </field>
2140 </register>
2141 </node>
2142 <node>
2143 <name>ACCR1</name>
2144 <title>AIC controller AC-link control register 1</title>
2145 <instance>
2146 <name>ACCR1</name>
2147 <address>0x8</address>
2148 </instance>
2149 <register>
2150 <field>
2151 <name>RS</name>
2152 <position>16</position>
2153 <width>10</width>
2154 </field>
2155 <field>
2156 <name>XS</name>
2157 <position>0</position>
2158 <width>10</width>
2159 </field>
2160 </register>
2161 </node>
2162 <node>
2163 <name>ACCR2</name>
2164 <title>AIC controller AC-link control register 2</title>
2165 <instance>
2166 <name>ACCR2</name>
2167 <address>0xc</address>
2168 </instance>
2169 <register>
2170 <field>
2171 <name>ERSTO</name>
2172 <position>18</position>
2173 </field>
2174 <field>
2175 <name>ESADR</name>
2176 <position>17</position>
2177 </field>
2178 <field>
2179 <name>ECADT</name>
2180 <position>16</position>
2181 </field>
2182 <field>
2183 <name>SO</name>
2184 <position>3</position>
2185 </field>
2186 <field>
2187 <name>SR</name>
2188 <position>2</position>
2189 </field>
2190 <field>
2191 <name>SS</name>
2192 <position>1</position>
2193 </field>
2194 <field>
2195 <name>SA</name>
2196 <position>0</position>
2197 </field>
2198 </register>
2199 </node>
2200 <node>
2201 <name>I2SCR</name>
2202 <title>AIC controller i2s/msb-justified control register</title>
2203 <instance>
2204 <name>I2SCR</name>
2205 <address>0x10</address>
2206 </instance>
2207 <register>
2208 <field>
2209 <name>RFIRST</name>
2210 <position>17</position>
2211 </field>
2212 <field>
2213 <name>SWLH</name>
2214 <position>16</position>
2215 </field>
2216 <field>
2217 <name>STPBK</name>
2218 <position>12</position>
2219 </field>
2220 <field>
2221 <name>ESCLK</name>
2222 <position>4</position>
2223 </field>
2224 <field>
2225 <name>AMSL</name>
2226 <position>0</position>
2227 </field>
2228 </register>
2229 </node>
2230 <node>
2231 <name>SR</name>
2232 <title>AIC controller FIFO status register</title>
2233 <instance>
2234 <name>SR</name>
2235 <address>0x14</address>
2236 </instance>
2237 <register>
2238 <field>
2239 <name>RFL</name>
2240 <position>24</position>
2241 <width>6</width>
2242 </field>
2243 <field>
2244 <name>TFL</name>
2245 <position>8</position>
2246 <width>6</width>
2247 </field>
2248 <field>
2249 <name>ROR</name>
2250 <position>6</position>
2251 </field>
2252 <field>
2253 <name>TUR</name>
2254 <position>5</position>
2255 </field>
2256 <field>
2257 <name>RFS</name>
2258 <position>4</position>
2259 </field>
2260 <field>
2261 <name>TFS</name>
2262 <position>3</position>
2263 </field>
2264 </register>
2265 </node>
2266 <node>
2267 <name>ACSR</name>
2268 <title>AIC controller AC-link status register</title>
2269 <instance>
2270 <name>ACSR</name>
2271 <address>0x18</address>
2272 </instance>
2273 <register>
2274 <field>
2275 <name>SLTERR</name>
2276 <position>21</position>
2277 </field>
2278 <field>
2279 <name>CRDY</name>
2280 <position>20</position>
2281 </field>
2282 <field>
2283 <name>CLPM</name>
2284 <position>19</position>
2285 </field>
2286 <field>
2287 <name>RSTO</name>
2288 <position>18</position>
2289 </field>
2290 <field>
2291 <name>SADR</name>
2292 <position>17</position>
2293 </field>
2294 <field>
2295 <name>CADT</name>
2296 <position>16</position>
2297 </field>
2298 </register>
2299 </node>
2300 <node>
2301 <name>I2SSR</name>
2302 <title>AIC controller I2S/MSB-justified status register</title>
2303 <instance>
2304 <name>I2SSR</name>
2305 <address>0x1c</address>
2306 </instance>
2307 <register>
2308 <field>
2309 <name>CHBSY</name>
2310 <position>5</position>
2311 </field>
2312 <field>
2313 <name>TBSY</name>
2314 <position>4</position>
2315 </field>
2316 <field>
2317 <name>RBSY</name>
2318 <position>3</position>
2319 </field>
2320 <field>
2321 <name>BSY</name>
2322 <position>2</position>
2323 </field>
2324 </register>
2325 </node>
2326 <node>
2327 <name>ACCAR</name>
2328 <title>AIC controller AC97 codec command address register</title>
2329 <instance>
2330 <name>ACCAR</name>
2331 <address>0x20</address>
2332 </instance>
2333 <register>
2334 <field>
2335 <name>CAR</name>
2336 <position>0</position>
2337 <width>20</width>
2338 </field>
2339 </register>
2340 </node>
2341 <node>
2342 <name>ACCDR</name>
2343 <title>AIC controller AC97 codec command data register</title>
2344 <instance>
2345 <name>ACCDR</name>
2346 <address>0x24</address>
2347 </instance>
2348 <register>
2349 <field>
2350 <name>CDR</name>
2351 <position>0</position>
2352 <width>20</width>
2353 </field>
2354 </register>
2355 </node>
2356 <node>
2357 <name>ACSAR</name>
2358 <title>AIC controller AC97 codec status address register</title>
2359 <instance>
2360 <name>ACSAR</name>
2361 <address>0x28</address>
2362 </instance>
2363 <register>
2364 <field>
2365 <name>SAR</name>
2366 <position>0</position>
2367 <width>20</width>
2368 </field>
2369 </register>
2370 </node>
2371 <node>
2372 <name>ACSDR</name>
2373 <title>AIC controller AC97 codec status data register</title>
2374 <instance>
2375 <name>ACSDR</name>
2376 <address>0x2c</address>
2377 </instance>
2378 <register>
2379 <field>
2380 <name>SDR</name>
2381 <position>0</position>
2382 <width>20</width>
2383 </field>
2384 </register>
2385 </node>
2386 <node>
2387 <name>I2SDIV</name>
2388 <title>AIC controller I2S/MSB-justified clock divider register</title>
2389 <instance>
2390 <name>I2SDIV</name>
2391 <address>0x30</address>
2392 </instance>
2393 <register>
2394 <field>
2395 <name>DIV</name>
2396 <position>0</position>
2397 <width>4</width>
2398 </field>
2399 </register>
2400 </node>
2401 <node>
2402 <name>DR</name>
2403 <instance>
2404 <name>DR</name>
2405 <address>0x34</address>
2406 </instance>
2407 <register/>
2408 </node>
2409 <node>
2410 <name>SPENA</name>
2411 <title>SPDIF enable register</title>
2412 <instance>
2413 <name>SPENA</name>
2414 <address>0x80</address>
2415 </instance>
2416 <register>
2417 <field>
2418 <name>SPEN</name>
2419 <position>0</position>
2420 </field>
2421 </register>
2422 </node>
2423 <node>
2424 <name>SPCTRL</name>
2425 <title>SPDIF control register</title>
2426 <instance>
2427 <name>SPCTRL</name>
2428 <address>0x84</address>
2429 </instance>
2430 <register>
2431 <field>
2432 <name>DMAEN</name>
2433 <position>15</position>
2434 </field>
2435 <field>
2436 <name>DTYPE</name>
2437 <position>14</position>
2438 </field>
2439 <field>
2440 <name>SIGN</name>
2441 <position>13</position>
2442 </field>
2443 <field>
2444 <name>INVALID</name>
2445 <position>12</position>
2446 </field>
2447 <field>
2448 <name>RST</name>
2449 <position>11</position>
2450 </field>
2451 <field>
2452 <name>SPDIFI2S</name>
2453 <position>10</position>
2454 </field>
2455 <field>
2456 <name>MTRIG</name>
2457 <position>1</position>
2458 </field>
2459 <field>
2460 <name>MFFUR</name>
2461 <position>0</position>
2462 </field>
2463 </register>
2464 </node>
2465 <node>
2466 <name>SPSTATE</name>
2467 <title>SPDIF state register</title>
2468 <instance>
2469 <name>SPSTATE</name>
2470 <address>0x88</address>
2471 </instance>
2472 <register>
2473 <field>
2474 <name>FLVL</name>
2475 <position>8</position>
2476 <width>7</width>
2477 </field>
2478 <field>
2479 <name>BUSY</name>
2480 <position>7</position>
2481 </field>
2482 <field>
2483 <name>FTRIG</name>
2484 <position>1</position>
2485 </field>
2486 <field>
2487 <name>FUR</name>
2488 <position>0</position>
2489 </field>
2490 </register>
2491 </node>
2492 <node>
2493 <name>SPCFG1</name>
2494 <title>SPDIF configure 1 register</title>
2495 <instance>
2496 <name>SPCFG1</name>
2497 <address>0x8c</address>
2498 </instance>
2499 <register>
2500 <field>
2501 <name>INITLVL</name>
2502 <position>17</position>
2503 </field>
2504 <field>
2505 <name>ZROVLD</name>
2506 <position>16</position>
2507 </field>
2508 <field>
2509 <name>TRIG</name>
2510 <position>12</position>
2511 <width>2</width>
2512 </field>
2513 <field>
2514 <name>SRCNUM</name>
2515 <position>8</position>
2516 <width>4</width>
2517 </field>
2518 <field>
2519 <name>CH1NUM</name>
2520 <position>4</position>
2521 <width>4</width>
2522 </field>
2523 <field>
2524 <name>CH2NUM</name>
2525 <position>0</position>
2526 <width>4</width>
2527 </field>
2528 </register>
2529 </node>
2530 <node>
2531 <name>SPCFG2</name>
2532 <title>SPDIF configure 2 register</title>
2533 <instance>
2534 <name>SPCFG2</name>
2535 <address>0x90</address>
2536 </instance>
2537 <register>
2538 <field>
2539 <name>FS</name>
2540 <position>26</position>
2541 <width>4</width>
2542 </field>
2543 <field>
2544 <name>ORGFRQ</name>
2545 <position>22</position>
2546 <width>4</width>
2547 </field>
2548 <field>
2549 <name>SAMWL</name>
2550 <position>19</position>
2551 <width>3</width>
2552 </field>
2553 <field>
2554 <name>MAXWL</name>
2555 <position>18</position>
2556 </field>
2557 <field>
2558 <name>CLKACU</name>
2559 <position>16</position>
2560 <width>2</width>
2561 </field>
2562 <field>
2563 <name>CATCODE</name>
2564 <position>8</position>
2565 <width>8</width>
2566 </field>
2567 <field>
2568 <name>CHMD</name>
2569 <position>6</position>
2570 <width>2</width>
2571 </field>
2572 <field>
2573 <name>PRE</name>
2574 <position>3</position>
2575 </field>
2576 <field>
2577 <name>COPYN</name>
2578 <position>2</position>
2579 </field>
2580 <field>
2581 <name>AUDION</name>
2582 <position>1</position>
2583 </field>
2584 <field>
2585 <name>CONPRO</name>
2586 <position>0</position>
2587 </field>
2588 </register>
2589 </node>
2590 <node>
2591 <name>SPFIFO</name>
2592 <instance>
2593 <name>SPFIFO</name>
2594 <address>0x94</address>
2595 </instance>
2596 <register/>
2597 </node>
2598 <node>
2599 <name>RGADW</name>
2600 <title>ICDC internal register access control register</title>
2601 <instance>
2602 <name>RGADW</name>
2603 <address>0xa4</address>
2604 </instance>
2605 <register>
2606 <field>
2607 <name>RGWR</name>
2608 <position>16</position>
2609 </field>
2610 <field>
2611 <name>RGADDR</name>
2612 <position>8</position>
2613 <width>7</width>
2614 </field>
2615 <field>
2616 <name>RGDIN</name>
2617 <position>0</position>
2618 <width>8</width>
2619 </field>
2620 </register>
2621 </node>
2622 <node>
2623 <name>RGDATA</name>
2624 <title>ICDC internal register data output register</title>
2625 <instance>
2626 <name>RGDATA</name>
2627 <address>0xa8</address>
2628 </instance>
2629 <register>
2630 <field>
2631 <name>IRQ</name>
2632 <position>8</position>
2633 </field>
2634 <field>
2635 <name>RGDOUT</name>
2636 <position>0</position>
2637 <width>8</width>
2638 </field>
2639 </register>
2640 </node>
2641 </node>
2642 <node>
2643 <name>MSC</name>
2644 <instance>
2645 <name>MSC</name>
2646 <range>
2647 <first>0</first>
2648 <address>0xb0021000</address>
2649 <address>0xb0022000</address>
2650 <address>0xb0023000</address>
2651 </range>
2652 </instance>
2653 <node>
2654 <name>STRPCL</name>
2655 <title>MSC Clock and Control Register</title>
2656 <instance>
2657 <name>STRPCL</name>
2658 <address>0x0</address>
2659 </instance>
2660 <register>
2661 <width>16</width>
2662 <field>
2663 <name>SEND_CCSD</name>
2664 <desc>send command completion signal disable to ceata</desc>
2665 <position>15</position>
2666 </field>
2667 <field>
2668 <name>SEND_AS_CCSD</name>
2669 <desc>send internally generated stop after sending ccsd</desc>
2670 <position>14</position>
2671 </field>
2672 <field>
2673 <name>EXIT_MULTIPLE</name>
2674 <position>7</position>
2675 </field>
2676 <field>
2677 <name>EXIT_TRANSFER</name>
2678 <position>6</position>
2679 </field>
2680 <field>
2681 <name>START_READWAIT</name>
2682 <position>5</position>
2683 </field>
2684 <field>
2685 <name>STOP_READWAIT</name>
2686 <position>4</position>
2687 </field>
2688 <field>
2689 <name>RESET</name>
2690 <position>3</position>
2691 </field>
2692 <field>
2693 <name>START_OP</name>
2694 <position>2</position>
2695 </field>
2696 <field>
2697 <name>CLOCK_CONTROL</name>
2698 <desc>Start MMC/SD clock</desc>
2699 <position>0</position>
2700 <width>2</width>
2701 <enum>
2702 <name>STOP</name>
2703 <value>0x1</value>
2704 </enum>
2705 <enum>
2706 <name>START</name>
2707 <value>0x2</value>
2708 </enum>
2709 </field>
2710 </register>
2711 </node>
2712 <node>
2713 <name>STAT</name>
2714 <title>MSC Status Register</title>
2715 <instance>
2716 <name>STAT</name>
2717 <address>0x4</address>
2718 </instance>
2719 <register>
2720 <field>
2721 <name>AUTO_CMD_DONE</name>
2722 <desc>12 is internally generated by controller has finished</desc>
2723 <position>31</position>
2724 </field>
2725 <field>
2726 <name>IS_RESETTING</name>
2727 <position>15</position>
2728 </field>
2729 <field>
2730 <name>SDIO_INT_ACTIVE</name>
2731 <position>14</position>
2732 </field>
2733 <field>
2734 <name>PRG_DONE</name>
2735 <position>13</position>
2736 </field>
2737 <field>
2738 <name>DATA_TRAN_DONE</name>
2739 <position>12</position>
2740 </field>
2741 <field>
2742 <name>END_CMD_RES</name>
2743 <position>11</position>
2744 </field>
2745 <field>
2746 <name>DATA_FIFO_AFULL</name>
2747 <position>10</position>
2748 </field>
2749 <field>
2750 <name>IS_READWAIT</name>
2751 <position>9</position>
2752 </field>
2753 <field>
2754 <name>CLK_EN</name>
2755 <position>8</position>
2756 </field>
2757 <field>
2758 <name>DATA_FIFO_FULL</name>
2759 <position>7</position>
2760 </field>
2761 <field>
2762 <name>DATA_FIFO_EMPTY</name>
2763 <position>6</position>
2764 </field>
2765 <field>
2766 <name>CRC_RES_ERR</name>
2767 <position>5</position>
2768 </field>
2769 <field>
2770 <name>CRC_READ_ERROR</name>
2771 <position>4</position>
2772 </field>
2773 <field>
2774 <name>CRC_WRITE_ERROR</name>
2775 <desc>No CRC status is sent back</desc>
2776 <position>2</position>
2777 <width>2</width>
2778 <enum>
2779 <name>NO</name>
2780 <value>0x0</value>
2781 </enum>
2782 <enum>
2783 <name>DATA</name>
2784 <value>0x1</value>
2785 </enum>
2786 <enum>
2787 <name>NOSTS</name>
2788 <value>0x2</value>
2789 </enum>
2790 </field>
2791 <field>
2792 <name>TIME_OUT_RES</name>
2793 <position>1</position>
2794 </field>
2795 <field>
2796 <name>TIME_OUT_READ</name>
2797 <position>0</position>
2798 </field>
2799 </register>
2800 </node>
2801 <node>
2802 <name>CLKRT</name>
2803 <title>MSC Bus Clock Control Register</title>
2804 <instance>
2805 <name>CLKRT</name>
2806 <address>0x8</address>
2807 </instance>
2808 <register>
2809 <width>16</width>
2810 <field>
2811 <name>CLK_RATE</name>
2812 <desc>1/128 of CLK_SRC</desc>
2813 <position>0</position>
2814 <width>3</width>
2815 <enum>
2816 <name>DIV_1</name>
2817 <value>0x0</value>
2818 </enum>
2819 <enum>
2820 <name>DIV_2</name>
2821 <value>0x1</value>
2822 </enum>
2823 <enum>
2824 <name>DIV_4</name>
2825 <value>0x2</value>
2826 </enum>
2827 <enum>
2828 <name>DIV_8</name>
2829 <value>0x3</value>
2830 </enum>
2831 <enum>
2832 <name>DIV_16</name>
2833 <value>0x4</value>
2834 </enum>
2835 <enum>
2836 <name>DIV_32</name>
2837 <value>0x5</value>
2838 </enum>
2839 <enum>
2840 <name>DIV_64</name>
2841 <value>0x6</value>
2842 </enum>
2843 <enum>
2844 <name>DIV_128</name>
2845 <value>0x7</value>
2846 </enum>
2847 </field>
2848 </register>
2849 </node>
2850 <node>
2851 <name>CMDAT</name>
2852 <title>MSC Command Sequence Control Register</title>
2853 <instance>
2854 <name>CMDAT</name>
2855 <address>0xc</address>
2856 </instance>
2857 <register>
2858 <field>
2859 <name>CCS_EXPECTED</name>
2860 <desc>interrupts are enabled in ce-ata</desc>
2861 <position>31</position>
2862 </field>
2863 <field>
2864 <name>READ_CEATA</name>
2865 <position>30</position>
2866 </field>
2867 <field>
2868 <name>SDIO_PRDT</name>
2869 <desc>exact 2 cycle</desc>
2870 <position>17</position>
2871 </field>
2872 <field>
2873 <name>SEND_AS_STOP</name>
2874 <position>16</position>
2875 </field>
2876 <field>
2877 <name>RTRG</name>
2878 <desc>reset value</desc>
2879 <position>14</position>
2880 <width>2</width>
2881 <enum>
2882 <name>EQUALT_8</name>
2883 <value>0x0</value>
2884 </enum>
2885 <enum>
2886 <name>EQUALT_16</name>
2887 <value>0x1</value>
2888 </enum>
2889 <enum>
2890 <name>EQUALT_24</name>
2891 <value>0x2</value>
2892 </enum>
2893 </field>
2894 <field>
2895 <name>TTRG</name>
2896 <desc>reset value</desc>
2897 <position>12</position>
2898 <width>2</width>
2899 <enum>
2900 <name>LESS_8</name>
2901 <value>0x0</value>
2902 </enum>
2903 <enum>
2904 <name>LESS_16</name>
2905 <value>0x1</value>
2906 </enum>
2907 <enum>
2908 <name>LESS_24</name>
2909 <value>0x2</value>
2910 </enum>
2911 </field>
2912 <field>
2913 <name>STOP_ABORT</name>
2914 <position>11</position>
2915 </field>
2916 <field>
2917 <name>BUS_WIDTH</name>
2918 <desc>8-bit data bus</desc>
2919 <position>9</position>
2920 <width>2</width>
2921 <enum>
2922 <name>1BIT</name>
2923 <value>0x0</value>
2924 </enum>
2925 <enum>
2926 <name>4BIT</name>
2927 <value>0x2</value>
2928 </enum>
2929 <enum>
2930 <name>8BIT</name>
2931 <value>0x3</value>
2932 </enum>
2933 </field>
2934 <field>
2935 <name>DMA_EN</name>
2936 <position>8</position>
2937 </field>
2938 <field>
2939 <name>INIT</name>
2940 <position>7</position>
2941 </field>
2942 <field>
2943 <name>BUSY</name>
2944 <position>6</position>
2945 </field>
2946 <field>
2947 <name>STREAM_BLOCK</name>
2948 <position>5</position>
2949 </field>
2950 <field>
2951 <name>WRITE</name>
2952 <position>4</position>
2953 </field>
2954 <field>
2955 <name>DATA_EN</name>
2956 <position>3</position>
2957 </field>
2958 <field>
2959 <name>RESPONSE</name>
2960 <desc>Format R6</desc>
2961 <position>0</position>
2962 <width>3</width>
2963 <enum>
2964 <name>NONE</name>
2965 <value>0x0</value>
2966 </enum>
2967 <enum>
2968 <name>R1</name>
2969 <value>0x1</value>
2970 </enum>
2971 <enum>
2972 <name>R2</name>
2973 <value>0x2</value>
2974 </enum>
2975 <enum>
2976 <name>R3</name>
2977 <value>0x3</value>
2978 </enum>
2979 <enum>
2980 <name>R4</name>
2981 <value>0x4</value>
2982 </enum>
2983 <enum>
2984 <name>R5</name>
2985 <value>0x5</value>
2986 </enum>
2987 <enum>
2988 <name>R6</name>
2989 <value>0x6</value>
2990 </enum>
2991 </field>
2992 </register>
2993 </node>
2994 <node>
2995 <name>RESTO</name>
2996 <instance>
2997 <name>RESTO</name>
2998 <address>0x10</address>
2999 </instance>
3000 <register>
3001 <width>16</width>
3002 </register>
3003 </node>
3004 <node>
3005 <name>RDTO</name>
3006 <instance>
3007 <name>RDTO</name>
3008 <address>0x14</address>
3009 </instance>
3010 <register/>
3011 </node>
3012 <node>
3013 <name>BLKLEN</name>
3014 <instance>
3015 <name>BLKLEN</name>
3016 <address>0x18</address>
3017 </instance>
3018 <register>
3019 <width>16</width>
3020 </register>
3021 </node>
3022 <node>
3023 <name>NOB</name>
3024 <instance>
3025 <name>NOB</name>
3026 <address>0x1c</address>
3027 </instance>
3028 <register>
3029 <width>16</width>
3030 </register>
3031 </node>
3032 <node>
3033 <name>SNOB</name>
3034 <instance>
3035 <name>SNOB</name>
3036 <address>0x20</address>
3037 </instance>
3038 <register>
3039 <width>16</width>
3040 </register>
3041 </node>
3042 <node>
3043 <name>IMASK</name>
3044 <title>MSC Interrupts Mask Register</title>
3045 <instance>
3046 <name>IMASK</name>
3047 <address>0x24</address>
3048 </instance>
3049 <register>
3050 <field>
3051 <name>AUTO_CMD_DONE</name>
3052 <position>15</position>
3053 </field>
3054 <field>
3055 <name>DATA_FIFO_FULL</name>
3056 <position>14</position>
3057 </field>
3058 <field>
3059 <name>DATA_FIFO_EMP</name>
3060 <position>13</position>
3061 </field>
3062 <field>
3063 <name>CRC_RES_ERR</name>
3064 <position>12</position>
3065 </field>
3066 <field>
3067 <name>CRC_READ_ERR</name>
3068 <position>11</position>
3069 </field>
3070 <field>
3071 <name>CRC_WRITE_ERR</name>
3072 <position>10</position>
3073 </field>
3074 <field>
3075 <name>TIMEOUT_RES</name>
3076 <position>9</position>
3077 </field>
3078 <field>
3079 <name>TIMEOUT_READ</name>
3080 <position>8</position>
3081 </field>
3082 <field>
3083 <name>SDIO</name>
3084 <position>7</position>
3085 </field>
3086 <field>
3087 <name>TXFIFO_WR_REQ</name>
3088 <position>6</position>
3089 </field>
3090 <field>
3091 <name>RXFIFO_RD_REQ</name>
3092 <position>5</position>
3093 </field>
3094 <field>
3095 <name>END_CMD_RES</name>
3096 <position>2</position>
3097 </field>
3098 <field>
3099 <name>PRG_DONE</name>
3100 <position>1</position>
3101 </field>
3102 <field>
3103 <name>DATA_TRAN_DONE</name>
3104 <position>0</position>
3105 </field>
3106 </register>
3107 </node>
3108 <node>
3109 <name>IREG</name>
3110 <title>MSC Interrupts Status Register</title>
3111 <instance>
3112 <name>IREG</name>
3113 <address>0x28</address>
3114 </instance>
3115 <register>
3116 <width>16</width>
3117 <field>
3118 <name>AUTO_CMD_DONE</name>
3119 <position>15</position>
3120 </field>
3121 <field>
3122 <name>DATA_FIFO_FULL</name>
3123 <position>14</position>
3124 </field>
3125 <field>
3126 <name>DATA_FIFO_EMP</name>
3127 <position>13</position>
3128 </field>
3129 <field>
3130 <name>CRC_RES_ERR</name>
3131 <position>12</position>
3132 </field>
3133 <field>
3134 <name>CRC_READ_ERR</name>
3135 <position>11</position>
3136 </field>
3137 <field>
3138 <name>CRC_WRITE_ERR</name>
3139 <position>10</position>
3140 </field>
3141 <field>
3142 <name>TIMEOUT_RES</name>
3143 <position>9</position>
3144 </field>
3145 <field>
3146 <name>TIMEOUT_READ</name>
3147 <position>8</position>
3148 </field>
3149 <field>
3150 <name>SDIO</name>
3151 <position>7</position>
3152 </field>
3153 <field>
3154 <name>TXFIFO_WR_REQ</name>
3155 <position>6</position>
3156 </field>
3157 <field>
3158 <name>RXFIFO_RD_REQ</name>
3159 <position>5</position>
3160 </field>
3161 <field>
3162 <name>END_CMD_RES</name>
3163 <position>2</position>
3164 </field>
3165 <field>
3166 <name>PRG_DONE</name>
3167 <position>1</position>
3168 </field>
3169 <field>
3170 <name>DATA_TRAN_DONE</name>
3171 <position>0</position>
3172 </field>
3173 </register>
3174 </node>
3175 <node>
3176 <name>CMD</name>
3177 <instance>
3178 <name>CMD</name>
3179 <address>0x2c</address>
3180 </instance>
3181 <register>
3182 <width>8</width>
3183 </register>
3184 </node>
3185 <node>
3186 <name>ARG</name>
3187 <instance>
3188 <name>ARG</name>
3189 <address>0x30</address>
3190 </instance>
3191 <register/>
3192 </node>
3193 <node>
3194 <name>RES</name>
3195 <instance>
3196 <name>RES</name>
3197 <address>0x34</address>
3198 </instance>
3199 <register>
3200 <width>16</width>
3201 </register>
3202 </node>
3203 <node>
3204 <name>RXFIFO</name>
3205 <instance>
3206 <name>RXFIFO</name>
3207 <address>0x38</address>
3208 </instance>
3209 <register/>
3210 </node>
3211 <node>
3212 <name>TXFIFO</name>
3213 <instance>
3214 <name>TXFIFO</name>
3215 <address>0x3c</address>
3216 </instance>
3217 <register/>
3218 </node>
3219 <node>
3220 <name>LPM</name>
3221 <title>MSC Low Power Mode Register</title>
3222 <instance>
3223 <name>LPM</name>
3224 <address>0x40</address>
3225 </instance>
3226 <register>
3227 <field>
3228 <name>LPM</name>
3229 <position>0</position>
3230 </field>
3231 </register>
3232 </node>
3233 </node>
3234 <node>
3235 <name>UART</name>
3236 <instance>
3237 <name>UART</name>
3238 <range>
3239 <first>0</first>
3240 <address>0xb0030000</address>
3241 <address>0xb0031000</address>
3242 <address>0xb0032000</address>
3243 <address>0xb0033000</address>
3244 </range>
3245 </instance>
3246 <node>
3247 <name>DLLR</name>
3248 <instance>
3249 <name>DLLR</name>
3250 <address>0x0</address>
3251 </instance>
3252 <register/>
3253 </node>
3254 <node>
3255 <name>RDR</name>
3256 <instance>
3257 <name>RDR</name>
3258 <address>0x0</address>
3259 </instance>
3260 <register/>
3261 </node>
3262 <node>
3263 <name>TDR</name>
3264 <instance>
3265 <name>TDR</name>
3266 <address>0x0</address>
3267 </instance>
3268 <register/>
3269 </node>
3270 <node>
3271 <name>DLHR</name>
3272 <instance>
3273 <name>DLHR</name>
3274 <address>0x4</address>
3275 </instance>
3276 <register/>
3277 </node>
3278 <node>
3279 <name>IER</name>
3280 <instance>
3281 <name>IER</name>
3282 <address>0x4</address>
3283 </instance>
3284 <register>
3285 <field>
3286 <name>RTIE</name>
3287 <desc>0: receive timeout interrupt disable</desc>
3288 <position>4</position>
3289 </field>
3290 <field>
3291 <name>MIE</name>
3292 <desc>0: modem status interrupt disable</desc>
3293 <position>3</position>
3294 </field>
3295 <field>
3296 <name>RLIE</name>
3297 <desc>0: receive line status interrupt disable</desc>
3298 <position>2</position>
3299 </field>
3300 <field>
3301 <name>TIE</name>
3302 <desc>0: transmit fifo empty interrupt disable</desc>
3303 <position>1</position>
3304 </field>
3305 <field>
3306 <name>RIE</name>
3307 <desc>0: receive fifo full interrupt disable</desc>
3308 <position>0</position>
3309 </field>
3310 </register>
3311 </node>
3312 <node>
3313 <name>FCR</name>
3314 <instance>
3315 <name>FCR</name>
3316 <address>0x8</address>
3317 </instance>
3318 <register>
3319 <field>
3320 <name>RTRG_4</name>
3321 <position>6</position>
3322 </field>
3323 <field>
3324 <name>UUE</name>
3325 <desc>0: disable UART</desc>
3326 <position>4</position>
3327 </field>
3328 <field>
3329 <name>DMS</name>
3330 <desc>0: disable DMA mode</desc>
3331 <position>3</position>
3332 </field>
3333 <field>
3334 <name>TFLS</name>
3335 <desc>write 1 to flush transmit FIFO</desc>
3336 <position>2</position>
3337 </field>
3338 <field>
3339 <name>RFLS</name>
3340 <desc>write 1 to flush receive FIFO</desc>
3341 <position>1</position>
3342 </field>
3343 <field>
3344 <name>FE</name>
3345 <desc>0: non-FIFO mode 1: FIFO mode</desc>
3346 <position>0</position>
3347 </field>
3348 </register>
3349 </node>
3350 <node>
3351 <name>ISR</name>
3352 <instance>
3353 <name>ISR</name>
3354 <address>0x8</address>
3355 </instance>
3356 <register>
3357 <field>
3358 <name>IID_THRI</name>
3359 <desc>Transmitter holding register empty</desc>
3360 <position>1</position>
3361 </field>
3362 <field>
3363 <name>IP</name>
3364 <desc>0: interrupt is pending 1: no interrupt</desc>
3365 <position>0</position>
3366 </field>
3367 </register>
3368 </node>
3369 <node>
3370 <name>LCR</name>
3371 <instance>
3372 <name>LCR</name>
3373 <address>0xc</address>
3374 </instance>
3375 <register>
3376 <field>
3377 <name>DLAB</name>
3378 <desc>0: access UARTRDR/TDR/IER 1: access UARTDLLR/DLHR</desc>
3379 <position>7</position>
3380 </field>
3381 <field>
3382 <name>SBRK</name>
3383 <desc>write 0 normal, write 1 send break</desc>
3384 <position>6</position>
3385 </field>
3386 <field>
3387 <name>SPAR</name>
3388 <desc>0: sticky parity disable</desc>
3389 <position>5</position>
3390 </field>
3391 <field>
3392 <name>PROE</name>
3393 <desc>0: even parity 1: odd parity</desc>
3394 <position>4</position>
3395 </field>
3396 <field>
3397 <name>PE</name>
3398 <desc>0: parity disable</desc>
3399 <position>3</position>
3400 </field>
3401 <field>
3402 <name>STOP2</name>
3403 <position>2</position>
3404 </field>
3405 <field>
3406 <name>WLEN_6</name>
3407 <position>0</position>
3408 </field>
3409 </register>
3410 </node>
3411 <node>
3412 <name>MCR</name>
3413 <instance>
3414 <name>MCR</name>
3415 <address>0x10</address>
3416 </instance>
3417 <register>
3418 <field>
3419 <name>MCE</name>
3420 <desc>0: modem function is disable</desc>
3421 <position>7</position>
3422 </field>
3423 <field>
3424 <name>FCM</name>
3425 <desc>0: software 1: hardware</desc>
3426 <position>6</position>
3427 </field>
3428 <field>
3429 <name>LOOP</name>
3430 <desc>0: normal 1: loopback mode</desc>
3431 <position>4</position>
3432 </field>
3433 <field>
3434 <name>RTS</name>
3435 <desc>0: RTS_ output high, 1: RTS_ output low</desc>
3436 <position>1</position>
3437 </field>
3438 </register>
3439 </node>
3440 <node>
3441 <name>LSR</name>
3442 <instance>
3443 <name>LSR</name>
3444 <address>0x14</address>
3445 </instance>
3446 <register>
3447 <field>
3448 <name>RFER</name>
3449 <desc>0: no receive error 1: receive error in FIFO mode</desc>
3450 <position>7</position>
3451 </field>
3452 <field>
3453 <name>TEMT</name>
3454 <desc>1: transmit FIFO and shift registers empty</desc>
3455 <position>6</position>
3456 </field>
3457 <field>
3458 <name>TDRQ</name>
3459 <desc>1: transmit FIFO half 'empty'</desc>
3460 <position>5</position>
3461 </field>
3462 <field>
3463 <name>BRK</name>
3464 <desc>0: no break detected 1: receive a break signal</desc>
3465 <position>4</position>
3466 </field>
3467 <field>
3468 <name>FER</name>
3469 <desc>0; no framing error</desc>
3470 <position>3</position>
3471 </field>
3472 <field>
3473 <name>PER</name>
3474 <desc>0: no parity error</desc>
3475 <position>2</position>
3476 </field>
3477 <field>
3478 <name>ORER</name>
3479 <desc>0: no overrun error</desc>
3480 <position>1</position>
3481 </field>
3482 <field>
3483 <name>DR</name>
3484 <desc>0: receive FIFO is empty 1: receive data is ready</desc>
3485 <position>0</position>
3486 </field>
3487 </register>
3488 </node>
3489 <node>
3490 <name>MSR</name>
3491 <instance>
3492 <name>MSR</name>
3493 <address>0x18</address>
3494 </instance>
3495 <register/>
3496 </node>
3497 <node>
3498 <name>SPR</name>
3499 <instance>
3500 <name>SPR</name>
3501 <address>0x1c</address>
3502 </instance>
3503 <register/>
3504 </node>
3505 <node>
3506 <name>SIRCR</name>
3507 <instance>
3508 <name>SIRCR</name>
3509 <address>0x20</address>
3510 </instance>
3511 <register>
3512 <field>
3513 <name>RDPL</name>
3514 <desc>0: decoder interprets positive pulse as 0</desc>
3515 <position>4</position>
3516 </field>
3517 <field>
3518 <name>TDPL</name>
3519 <desc>0: encoder generates a positive pulse for 0</desc>
3520 <position>3</position>
3521 </field>
3522 <field>
3523 <name>TPWS</name>
3524 <desc>0: transmit 0 pulse width is 3/16 of bit length, 1: 0 pulse width is 1.6us for 115.2Kbps</desc>
3525 <position>2</position>
3526 </field>
3527 <field>
3528 <name>RSIRE</name>
3529 <desc>0: receiver is in UART mode 1: SIR mode</desc>
3530 <position>1</position>
3531 </field>
3532 <field>
3533 <name>TSIRE</name>
3534 <desc>0: transmitter is in UART mode 1: SIR mode</desc>
3535 <position>0</position>
3536 </field>
3537 </register>
3538 </node>
3539 <node>
3540 <name>UMR</name>
3541 <instance>
3542 <name>UMR</name>
3543 <address>0x24</address>
3544 </instance>
3545 <register/>
3546 </node>
3547 <node>
3548 <name>UACR</name>
3549 <instance>
3550 <name>UACR</name>
3551 <address>0x28</address>
3552 </instance>
3553 <register/>
3554 </node>
3555 </node>
3556 <node>
3557 <name>SCC</name>
3558 <instance>
3559 <name>SCC</name>
3560 <address>0xb0040000</address>
3561 </instance>
3562 <node>
3563 <name>DR</name>
3564 <instance>
3565 <name>DR</name>
3566 <address>0x0</address>
3567 </instance>
3568 <register>
3569 <width>8</width>
3570 </register>
3571 </node>
3572 <node>
3573 <name>FDR</name>
3574 <title>SCC FIFO Data Count Register</title>
3575 <instance>
3576 <name>FDR</name>
3577 <address>0x4</address>
3578 </instance>
3579 <register>
3580 <width>8</width>
3581 </register>
3582 </node>
3583 <node>
3584 <name>CR</name>
3585 <title>SCC Control Register</title>
3586 <instance>
3587 <name>CR</name>
3588 <address>0x8</address>
3589 </instance>
3590 <register>
3591 <field>
3592 <name>SCCE</name>
3593 <position>31</position>
3594 </field>
3595 <field>
3596 <name>TRS</name>
3597 <position>30</position>
3598 </field>
3599 <field>
3600 <name>T2R</name>
3601 <position>29</position>
3602 </field>
3603 <field>
3604 <name>FDIV</name>
3605 <desc>SCC_CLK frequency is half of device clock</desc>
3606 <position>24</position>
3607 <width>2</width>
3608 <enum>
3609 <name>1</name>
3610 <value>0x0</value>
3611 </enum>
3612 <enum>
3613 <name>2</name>
3614 <value>0x1</value>
3615 </enum>
3616 </field>
3617 <field>
3618 <name>FLUSH</name>
3619 <position>23</position>
3620 </field>
3621 <field>
3622 <name>TRIG</name>
3623 <desc>Receive/Transmit-FIFO Trigger is 14</desc>
3624 <position>16</position>
3625 <width>2</width>
3626 <enum>
3627 <name>1</name>
3628 <value>0x0</value>
3629 </enum>
3630 <enum>
3631 <name>4</name>
3632 <value>0x1</value>
3633 </enum>
3634 <enum>
3635 <name>8</name>
3636 <value>0x2</value>
3637 </enum>
3638 <enum>
3639 <name>14</name>
3640 <value>0x3</value>
3641 </enum>
3642 </field>
3643 <field>
3644 <name>TP</name>
3645 <position>15</position>
3646 </field>
3647 <field>
3648 <name>CONV</name>
3649 <position>14</position>
3650 </field>
3651 <field>
3652 <name>TXIE</name>
3653 <position>13</position>
3654 </field>
3655 <field>
3656 <name>RXIE</name>
3657 <position>12</position>
3658 </field>
3659 <field>
3660 <name>TENDIE</name>
3661 <position>11</position>
3662 </field>
3663 <field>
3664 <name>RTOIE</name>
3665 <position>10</position>
3666 </field>
3667 <field>
3668 <name>ECIE</name>
3669 <position>9</position>
3670 </field>
3671 <field>
3672 <name>EPIE</name>
3673 <position>8</position>
3674 </field>
3675 <field>
3676 <name>RETIE</name>
3677 <position>7</position>
3678 </field>
3679 <field>
3680 <name>EOIE</name>
3681 <position>6</position>
3682 </field>
3683 <field>
3684 <name>TSEND</name>
3685 <position>3</position>
3686 </field>
3687 <field>
3688 <name>PX</name>
3689 <desc>SCC_CLK stops at state high</desc>
3690 <position>1</position>
3691 <width>2</width>
3692 <enum>
3693 <name>NOT_SUPPORT</name>
3694 <value>0x0</value>
3695 </enum>
3696 <enum>
3697 <name>STOP_LOW</name>
3698 <value>0x1</value>
3699 </enum>
3700 <enum>
3701 <name>STOP_HIGH</name>
3702 <value>0x2</value>
3703 </enum>
3704 </field>
3705 <field>
3706 <name>CLKSTP</name>
3707 <position>0</position>
3708 </field>
3709 </register>
3710 </node>
3711 <node>
3712 <name>SR</name>
3713 <title>SCC Status Register</title>
3714 <instance>
3715 <name>SR</name>
3716 <address>0xc</address>
3717 </instance>
3718 <register>
3719 <width>16</width>
3720 <field>
3721 <name>TRANS</name>
3722 <position>15</position>
3723 </field>
3724 <field>
3725 <name>ORER</name>
3726 <position>12</position>
3727 </field>
3728 <field>
3729 <name>RTO</name>
3730 <position>11</position>
3731 </field>
3732 <field>
3733 <name>PER</name>
3734 <position>10</position>
3735 </field>
3736 <field>
3737 <name>TFTG</name>
3738 <position>9</position>
3739 </field>
3740 <field>
3741 <name>RFTG</name>
3742 <position>8</position>
3743 </field>
3744 <field>
3745 <name>TEND</name>
3746 <position>7</position>
3747 </field>
3748 <field>
3749 <name>RETR_3</name>
3750 <position>4</position>
3751 </field>
3752 <field>
3753 <name>ECNTO</name>
3754 <position>0</position>
3755 </field>
3756 </register>
3757 </node>
3758 <node>
3759 <name>TFR</name>
3760 <instance>
3761 <name>TFR</name>
3762 <address>0x10</address>
3763 </instance>
3764 <register>
3765 <width>16</width>
3766 </register>
3767 </node>
3768 <node>
3769 <name>EGTR</name>
3770 <instance>
3771 <name>EGTR</name>
3772 <address>0x14</address>
3773 </instance>
3774 <register>
3775 <width>8</width>
3776 </register>
3777 </node>
3778 <node>
3779 <name>ECR</name>
3780 <instance>
3781 <name>ECR</name>
3782 <address>0x18</address>
3783 </instance>
3784 <register/>
3785 </node>
3786 <node>
3787 <name>RTOR</name>
3788 <instance>
3789 <name>RTOR</name>
3790 <address>0x1c</address>
3791 </instance>
3792 <register>
3793 <width>8</width>
3794 </register>
3795 </node>
3796 </node>
3797 <node>
3798 <name>SSI</name>
3799 <title>SSI (Synchronous Serial Interface)</title>
3800 <instance>
3801 <name>SSI</name>
3802 <range>
3803 <first>0</first>
3804 <address>0xb0043000</address>
3805 <address>0xb0044000</address>
3806 <address>0xb0045000</address>
3807 </range>
3808 </instance>
3809 <node>
3810 <name>DR</name>
3811 <title>SSI Data Register</title>
3812 <instance>
3813 <name>DR</name>
3814 <address>0x0</address>
3815 </instance>
3816 <register>
3817 <field>
3818 <name>GPC</name>
3819 <position>0</position>
3820 <width>9</width>
3821 </field>
3822 </register>
3823 </node>
3824 <node>
3825 <name>CR0</name>
3826 <title>SSI Control Register 0</title>
3827 <instance>
3828 <name>CR0</name>
3829 <address>0x4</address>
3830 </instance>
3831 <register>
3832 <width>16</width>
3833 <field>
3834 <name>SSIE</name>
3835 <position>15</position>
3836 </field>
3837 <field>
3838 <name>TIE</name>
3839 <position>14</position>
3840 </field>
3841 <field>
3842 <name>RIE</name>
3843 <position>13</position>
3844 </field>
3845 <field>
3846 <name>TEIE</name>
3847 <position>12</position>
3848 </field>
3849 <field>
3850 <name>REIE</name>
3851 <position>11</position>
3852 </field>
3853 <field>
3854 <name>LOOP</name>
3855 <position>10</position>
3856 </field>
3857 <field>
3858 <name>RFINE</name>
3859 <position>9</position>
3860 </field>
3861 <field>
3862 <name>RFINC</name>
3863 <position>8</position>
3864 </field>
3865 <field>
3866 <name>EACLRUN</name>
3867 <desc>hardware auto clear underrun when TxFifo no empty</desc>
3868 <position>7</position>
3869 </field>
3870 <field>
3871 <name>FSEL</name>
3872 <position>6</position>
3873 </field>
3874 <field>
3875 <name>TFLUSH</name>
3876 <position>2</position>
3877 </field>
3878 <field>
3879 <name>RFLUSH</name>
3880 <position>1</position>
3881 </field>
3882 <field>
3883 <name>DISREV</name>
3884 <position>0</position>
3885 </field>
3886 </register>
3887 </node>
3888 <node>
3889 <name>CR1</name>
3890 <title>SSI Control Register 1</title>
3891 <instance>
3892 <name>CR1</name>
3893 <address>0x8</address>
3894 </instance>
3895 <register>
3896 <field>
3897 <name>FRMHL</name>
3898 <desc>SSI_CE_ is high valid and SSI_CE2_ is high valid</desc>
3899 <position>30</position>
3900 <width>2</width>
3901 <enum>
3902 <name>CELOW_CE2LOW</name>
3903 <value>0x0</value>
3904 </enum>
3905 <enum>
3906 <name>CEHIGH_CE2LOW</name>
3907 <value>0x1</value>
3908 </enum>
3909 <enum>
3910 <name>CELOW_CE2HIGH</name>
3911 <value>0x2</value>
3912 </enum>
3913 <enum>
3914 <name>CEHIGH_CE2HIGH</name>
3915 <value>0x3</value>
3916 </enum>
3917 </field>
3918 <field>
3919 <name>TFVCK</name>
3920 <position>28</position>
3921 <width>2</width>
3922 <enum>
3923 <name>0</name>
3924 <value>0x0</value>
3925 </enum>
3926 <enum>
3927 <name>1</name>
3928 <value>0x1</value>
3929 </enum>
3930 <enum>
3931 <name>2</name>
3932 <value>0x2</value>
3933 </enum>
3934 <enum>
3935 <name>3</name>
3936 <value>0x3</value>
3937 </enum>
3938 </field>
3939 <field>
3940 <name>TCKFI</name>
3941 <position>26</position>
3942 <width>2</width>
3943 <enum>
3944 <name>0</name>
3945 <value>0x0</value>
3946 </enum>
3947 <enum>
3948 <name>1</name>
3949 <value>0x1</value>
3950 </enum>
3951 <enum>
3952 <name>2</name>
3953 <value>0x2</value>
3954 </enum>
3955 <enum>
3956 <name>3</name>
3957 <value>0x3</value>
3958 </enum>
3959 </field>
3960 <field>
3961 <name>LFST</name>
3962 <position>25</position>
3963 </field>
3964 <field>
3965 <name>ITFRM</name>
3966 <position>24</position>
3967 </field>
3968 <field>
3969 <name>UNFIN</name>
3970 <position>23</position>
3971 </field>
3972 <field>
3973 <name>MULTS</name>
3974 <position>22</position>
3975 </field>
3976 <field>
3977 <name>FMAT</name>
3978 <desc>National Microwire 2 format</desc>
3979 <position>20</position>
3980 <width>2</width>
3981 <enum>
3982 <name>SPI</name>
3983 <value>0x0</value>
3984 </enum>
3985 <enum>
3986 <name>SSP</name>
3987 <value>0x1</value>
3988 </enum>
3989 <enum>
3990 <name>MW1</name>
3991 <value>0x2</value>
3992 </enum>
3993 <enum>
3994 <name>MW2</name>
3995 <value>0x3</value>
3996 </enum>
3997 </field>
3998 <field>
3999 <name>TTRG</name>
4000 <desc>SSI1 TX trigger</desc>
4001 <position>16</position>
4002 <width>4</width>
4003 </field>
4004 <field>
4005 <name>MCOM</name>
4006 <desc>16-bit command selected</desc>
4007 <position>12</position>
4008 <width>4</width>
4009 <enum>
4010 <name>1BIT</name>
4011 <value>0x0</value>
4012 </enum>
4013 <enum>
4014 <name>2BIT</name>
4015 <value>0x1</value>
4016 </enum>
4017 <enum>
4018 <name>3BIT</name>
4019 <value>0x2</value>
4020 </enum>
4021 <enum>
4022 <name>4BIT</name>
4023 <value>0x3</value>
4024 </enum>
4025 <enum>
4026 <name>5BIT</name>
4027 <value>0x4</value>
4028 </enum>
4029 <enum>
4030 <name>6BIT</name>
4031 <value>0x5</value>
4032 </enum>
4033 <enum>
4034 <name>7BIT</name>
4035 <value>0x6</value>
4036 </enum>
4037 <enum>
4038 <name>8BIT</name>
4039 <value>0x7</value>
4040 </enum>
4041 <enum>
4042 <name>9BIT</name>
4043 <value>0x8</value>
4044 </enum>
4045 <enum>
4046 <name>10BIT</name>
4047 <value>0x9</value>
4048 </enum>
4049 <enum>
4050 <name>11BIT</name>
4051 <value>0xa</value>
4052 </enum>
4053 <enum>
4054 <name>12BIT</name>
4055 <value>0xb</value>
4056 </enum>
4057 <enum>
4058 <name>13BIT</name>
4059 <value>0xc</value>
4060 </enum>
4061 <enum>
4062 <name>14BIT</name>
4063 <value>0xd</value>
4064 </enum>
4065 <enum>
4066 <name>15BIT</name>
4067 <value>0xe</value>
4068 </enum>
4069 <enum>
4070 <name>16BIT</name>
4071 <value>0xf</value>
4072 </enum>
4073 </field>
4074 <field>
4075 <name>RTRG</name>
4076 <desc>SSI RX trigger</desc>
4077 <position>8</position>
4078 <width>4</width>
4079 </field>
4080 <field>
4081 <name>FLEN</name>
4082 <position>4</position>
4083 <width>4</width>
4084 <enum>
4085 <name>2BIT</name>
4086 <value>0x0</value>
4087 </enum>
4088 <enum>
4089 <name>3BIT</name>
4090 <value>0x1</value>
4091 </enum>
4092 <enum>
4093 <name>4BIT</name>
4094 <value>0x2</value>
4095 </enum>
4096 <enum>
4097 <name>5BIT</name>
4098 <value>0x3</value>
4099 </enum>
4100 <enum>
4101 <name>6BIT</name>
4102 <value>0x4</value>
4103 </enum>
4104 <enum>
4105 <name>7BIT</name>
4106 <value>0x5</value>
4107 </enum>
4108 <enum>
4109 <name>8BIT</name>
4110 <value>0x6</value>
4111 </enum>
4112 <enum>
4113 <name>9BIT</name>
4114 <value>0x7</value>
4115 </enum>
4116 <enum>
4117 <name>10BIT</name>
4118 <value>0x8</value>
4119 </enum>
4120 <enum>
4121 <name>11BIT</name>
4122 <value>0x9</value>
4123 </enum>
4124 <enum>
4125 <name>12BIT</name>
4126 <value>0xa</value>
4127 </enum>
4128 <enum>
4129 <name>13BIT</name>
4130 <value>0xb</value>
4131 </enum>
4132 <enum>
4133 <name>14BIT</name>
4134 <value>0xc</value>
4135 </enum>
4136 <enum>
4137 <name>15BIT</name>
4138 <value>0xd</value>
4139 </enum>
4140 <enum>
4141 <name>16BIT</name>
4142 <value>0xe</value>
4143 </enum>
4144 <enum>
4145 <name>17BIT</name>
4146 <value>0xf</value>
4147 </enum>
4148 </field>
4149 <field>
4150 <name>PHA</name>
4151 <position>1</position>
4152 </field>
4153 <field>
4154 <name>POL</name>
4155 <position>0</position>
4156 </field>
4157 </register>
4158 </node>
4159 <node>
4160 <name>SR</name>
4161 <title>SSI Status Register</title>
4162 <instance>
4163 <name>SR</name>
4164 <address>0xc</address>
4165 </instance>
4166 <register>
4167 <field>
4168 <name>TFIFONUM</name>
4169 <position>16</position>
4170 <width>8</width>
4171 </field>
4172 <field>
4173 <name>RFIFONUM</name>
4174 <position>8</position>
4175 <width>8</width>
4176 </field>
4177 <field>
4178 <name>END</name>
4179 <position>7</position>
4180 </field>
4181 <field>
4182 <name>BUSY</name>
4183 <position>6</position>
4184 </field>
4185 <field>
4186 <name>TFF</name>
4187 <position>5</position>
4188 </field>
4189 <field>
4190 <name>RFE</name>
4191 <position>4</position>
4192 </field>
4193 <field>
4194 <name>TFHE</name>
4195 <position>3</position>
4196 </field>
4197 <field>
4198 <name>RFHF</name>
4199 <position>2</position>
4200 </field>
4201 <field>
4202 <name>UNDR</name>
4203 <position>1</position>
4204 </field>
4205 <field>
4206 <name>OVER</name>
4207 <position>0</position>
4208 </field>
4209 </register>
4210 </node>
4211 <node>
4212 <name>ITR</name>
4213 <title>SSI Interval Time Control Register</title>
4214 <instance>
4215 <name>ITR</name>
4216 <address>0x10</address>
4217 </instance>
4218 <register>
4219 <width>16</width>
4220 <field>
4221 <name>CNTCLK</name>
4222 <position>15</position>
4223 </field>
4224 <field>
4225 <name>IVLTM</name>
4226 <position>0</position>
4227 <width>15</width>
4228 </field>
4229 </register>
4230 </node>
4231 <node>
4232 <name>ICR</name>
4233 <instance>
4234 <name>ICR</name>
4235 <address>0x14</address>
4236 </instance>
4237 <register>
4238 <width>8</width>
4239 </register>
4240 </node>
4241 <node>
4242 <name>GR</name>
4243 <instance>
4244 <name>GR</name>
4245 <address>0x18</address>
4246 </instance>
4247 <register>
4248 <width>16</width>
4249 </register>
4250 </node>
4251 </node>
4252 <node>
4253 <name>I2C</name>
4254 <title>I2C</title>
4255 <instance>
4256 <name>I2C</name>
4257 <range>
4258 <first>0</first>
4259 <address>0xb0050000</address>
4260 <address>0xb0051000</address>
4261 <address>0xb0055000</address>
4262 </range>
4263 </instance>
4264 <node>
4265 <name>CTRL</name>
4266 <title>I2C Control Register</title>
4267 <instance>
4268 <name>CTRL</name>
4269 <address>0x0</address>
4270 </instance>
4271 <register>
4272 <width>8</width>
4273 <field>
4274 <name>STPHLD</name>
4275 <position>7</position>
4276 </field>
4277 <field>
4278 <name>SLVDIS</name>
4279 <desc>after reset slave is disabled</desc>
4280 <position>6</position>
4281 </field>
4282 <field>
4283 <name>REST</name>
4284 <position>5</position>
4285 </field>
4286 <field>
4287 <name>MATP</name>
4288 <desc>1: 10bit address 0: 7bit addressing</desc>
4289 <position>4</position>
4290 </field>
4291 <field>
4292 <name>SATP</name>
4293 <desc>standard mode 100kbps</desc>
4294 <position>3</position>
4295 </field>
4296 <field>
4297 <name>SPD</name>
4298 <desc>standard mode 100kbps</desc>
4299 <position>1</position>
4300 <width>2</width>
4301 <enum>
4302 <name>SPDS</name>
4303 <value>0x1</value>
4304 </enum>
4305 <enum>
4306 <name>SPDF</name>
4307 <value>0x2</value>
4308 </enum>
4309 </field>
4310 <field>
4311 <name>MD</name>
4312 <desc>master enabled</desc>
4313 <position>0</position>
4314 </field>
4315 </register>
4316 </node>
4317 <node>
4318 <name>TAR</name>
4319 <title>I2C target address</title>
4320 <instance>
4321 <name>TAR</name>
4322 <address>0x4</address>
4323 </instance>
4324 <register>
4325 <width>16</width>
4326 <field>
4327 <name>MATP</name>
4328 <position>12</position>
4329 </field>
4330 <field>
4331 <name>SPECIAL</name>
4332 <position>11</position>
4333 </field>
4334 <field>
4335 <name>GC_OR_START</name>
4336 <position>10</position>
4337 </field>
4338 </register>
4339 </node>
4340 <node>
4341 <name>SAR</name>
4342 <instance>
4343 <name>SAR</name>
4344 <address>0x8</address>
4345 </instance>
4346 <register>
4347 <width>16</width>
4348 </register>
4349 </node>
4350 <node>
4351 <name>DC</name>
4352 <title>I2C data buffer and command</title>
4353 <instance>
4354 <name>DC</name>
4355 <address>0x10</address>
4356 </instance>
4357 <register>
4358 <width>16</width>
4359 <field>
4360 <name>CMD</name>
4361 <desc>1 read 0 write</desc>
4362 <position>8</position>
4363 </field>
4364 </register>
4365 </node>
4366 <node>
4367 <name>SHCNT</name>
4368 <title>I2C standard mode high count register</title>
4369 <instance>
4370 <name>SHCNT</name>
4371 <address>0x14</address>
4372 </instance>
4373 <register>
4374 <width>16</width>
4375 </register>
4376 </node>
4377 <node>
4378 <name>SLCNT</name>
4379 <title>I2C standard mode low count register</title>
4380 <instance>
4381 <name>SLCNT</name>
4382 <address>0x18</address>
4383 </instance>
4384 <register>
4385 <width>16</width>
4386 </register>
4387 </node>
4388 <node>
4389 <name>FHCNT</name>
4390 <title>I2C fast mode high count register</title>
4391 <instance>
4392 <name>FHCNT</name>
4393 <address>0x1c</address>
4394 </instance>
4395 <register>
4396 <width>16</width>
4397 </register>
4398 </node>
4399 <node>
4400 <name>FLCNT</name>
4401 <title>I2C fast mode low count register</title>
4402 <instance>
4403 <name>FLCNT</name>
4404 <address>0x20</address>
4405 </instance>
4406 <register>
4407 <width>16</width>
4408 </register>
4409 </node>
4410 <node>
4411 <name>INTST</name>
4412 <title>i2c interrupt status</title>
4413 <instance>
4414 <name>INTST</name>
4415 <address>0x2c</address>
4416 </instance>
4417 <register>
4418 <width>16</width>
4419 <field>
4420 <name>IGC</name>
4421 <position>11</position>
4422 </field>
4423 <field>
4424 <name>ISTT</name>
4425 <position>10</position>
4426 </field>
4427 <field>
4428 <name>ISTP</name>
4429 <position>9</position>
4430 </field>
4431 <field>
4432 <name>IACT</name>
4433 <position>8</position>
4434 </field>
4435 <field>
4436 <name>RXDN</name>
4437 <position>7</position>
4438 </field>
4439 <field>
4440 <name>TXABT</name>
4441 <position>6</position>
4442 </field>
4443 <field>
4444 <name>RDREQ</name>
4445 <position>5</position>
4446 </field>
4447 <field>
4448 <name>TXEMP</name>
4449 <position>4</position>
4450 </field>
4451 <field>
4452 <name>TXOF</name>
4453 <position>3</position>
4454 </field>
4455 <field>
4456 <name>RXFL</name>
4457 <position>2</position>
4458 </field>
4459 <field>
4460 <name>RXOF</name>
4461 <position>1</position>
4462 </field>
4463 <field>
4464 <name>RXUF</name>
4465 <position>0</position>
4466 </field>
4467 </register>
4468 </node>
4469 <node>
4470 <name>INTM</name>
4471 <title>i2c interrupt mask status</title>
4472 <instance>
4473 <name>INTM</name>
4474 <address>0x30</address>
4475 </instance>
4476 <register>
4477 <width>16</width>
4478 <field>
4479 <name>MIGC</name>
4480 <position>11</position>
4481 </field>
4482 <field>
4483 <name>MISTT</name>
4484 <position>10</position>
4485 </field>
4486 <field>
4487 <name>MISTP</name>
4488 <position>9</position>
4489 </field>
4490 <field>
4491 <name>MIACT</name>
4492 <position>8</position>
4493 </field>
4494 <field>
4495 <name>MRXDN</name>
4496 <position>7</position>
4497 </field>
4498 <field>
4499 <name>MTXABT</name>
4500 <position>6</position>
4501 </field>
4502 <field>
4503 <name>MRDREQ</name>
4504 <position>5</position>
4505 </field>
4506 <field>
4507 <name>MTXEMP</name>
4508 <position>4</position>
4509 </field>
4510 <field>
4511 <name>MTXOF</name>
4512 <position>3</position>
4513 </field>
4514 <field>
4515 <name>MRXFL</name>
4516 <position>2</position>
4517 </field>
4518 <field>
4519 <name>MRXOF</name>
4520 <position>1</position>
4521 </field>
4522 <field>
4523 <name>MRXUF</name>
4524 <position>0</position>
4525 </field>
4526 </register>
4527 </node>
4528 <node>
4529 <name>RXTL</name>
4530 <instance>
4531 <name>RXTL</name>
4532 <address>0x38</address>
4533 </instance>
4534 <register>
4535 <width>8</width>
4536 </register>
4537 </node>
4538 <node>
4539 <name>TXTL</name>
4540 <instance>
4541 <name>TXTL</name>
4542 <address>0x3c</address>
4543 </instance>
4544 <register>
4545 <width>8</width>
4546 </register>
4547 </node>
4548 <node>
4549 <name>CINTR</name>
4550 <title>I2C Clear Combined and Individual Interrupts</title>
4551 <instance>
4552 <name>CINTR</name>
4553 <address>0x40</address>
4554 </instance>
4555 <register>
4556 <width>8</width>
4557 </register>
4558 </node>
4559 <node>
4560 <name>CRXUF</name>
4561 <instance>
4562 <name>CRXUF</name>
4563 <address>0x44</address>
4564 </instance>
4565 <register>
4566 <width>8</width>
4567 </register>
4568 </node>
4569 <node>
4570 <name>CRXOF</name>
4571 <instance>
4572 <name>CRXOF</name>
4573 <address>0x48</address>
4574 </instance>
4575 <register>
4576 <width>8</width>
4577 </register>
4578 </node>
4579 <node>
4580 <name>CTXOF</name>
4581 <instance>
4582 <name>CTXOF</name>
4583 <address>0x4c</address>
4584 </instance>
4585 <register>
4586 <width>8</width>
4587 </register>
4588 </node>
4589 <node>
4590 <name>CRXREQ</name>
4591 <instance>
4592 <name>CRXREQ</name>
4593 <address>0x50</address>
4594 </instance>
4595 <register>
4596 <width>8</width>
4597 </register>
4598 </node>
4599 <node>
4600 <name>CTXABRT</name>
4601 <instance>
4602 <name>CTXABRT</name>
4603 <address>0x54</address>
4604 </instance>
4605 <register>
4606 <width>8</width>
4607 </register>
4608 </node>
4609 <node>
4610 <name>CRXDONE</name>
4611 <instance>
4612 <name>CRXDONE</name>
4613 <address>0x58</address>
4614 </instance>
4615 <register>
4616 <width>8</width>
4617 </register>
4618 </node>
4619 <node>
4620 <name>CACT</name>
4621 <instance>
4622 <name>CACT</name>
4623 <address>0x5c</address>
4624 </instance>
4625 <register>
4626 <width>8</width>
4627 </register>
4628 </node>
4629 <node>
4630 <name>CSTP</name>
4631 <instance>
4632 <name>CSTP</name>
4633 <address>0x60</address>
4634 </instance>
4635 <register>
4636 <width>8</width>
4637 </register>
4638 </node>
4639 <node>
4640 <name>CSTT</name>
4641 <instance>
4642 <name>CSTT</name>
4643 <address>0x64</address>
4644 </instance>
4645 <register>
4646 <width>16</width>
4647 </register>
4648 </node>
4649 <node>
4650 <name>CGC</name>
4651 <instance>
4652 <name>CGC</name>
4653 <address>0x68</address>
4654 </instance>
4655 <register>
4656 <width>8</width>
4657 </register>
4658 </node>
4659 <node>
4660 <name>ENB</name>
4661 <title>I2C Enable</title>
4662 <instance>
4663 <name>ENB</name>
4664 <address>0x6c</address>
4665 </instance>
4666 <register>
4667 <width>8</width>
4668 <field>
4669 <name>I2CENB</name>
4670 <desc>Enable the i2c</desc>
4671 <position>0</position>
4672 </field>
4673 </register>
4674 </node>
4675 <node>
4676 <name>STA</name>
4677 <title>I2C Status Register</title>
4678 <instance>
4679 <name>STA</name>
4680 <address>0x70</address>
4681 </instance>
4682 <register>
4683 <width>8</width>
4684 <field>
4685 <name>SLVACT</name>
4686 <desc>Slave FSM is not in IDLE state</desc>
4687 <position>6</position>
4688 </field>
4689 <field>
4690 <name>MSTACT</name>
4691 <desc>Master FSM is not in IDLE state</desc>
4692 <position>5</position>
4693 </field>
4694 <field>
4695 <name>RFF</name>
4696 <desc>RFIFO if full</desc>
4697 <position>4</position>
4698 </field>
4699 <field>
4700 <name>RFNE</name>
4701 <desc>RFIFO is not empty</desc>
4702 <position>3</position>
4703 </field>
4704 <field>
4705 <name>TFE</name>
4706 <desc>TFIFO is empty</desc>
4707 <position>2</position>
4708 </field>
4709 <field>
4710 <name>TFNF</name>
4711 <desc>TFIFO is not full</desc>
4712 <position>1</position>
4713 </field>
4714 <field>
4715 <name>ACT</name>
4716 <desc>I2C Activity Status</desc>
4717 <position>0</position>
4718 </field>
4719 </register>
4720 </node>
4721 <node>
4722 <name>TXFLR</name>
4723 <instance>
4724 <name>TXFLR</name>
4725 <address>0x74</address>
4726 </instance>
4727 <register>
4728 <width>8</width>
4729 </register>
4730 </node>
4731 <node>
4732 <name>RXFLR</name>
4733 <instance>
4734 <name>RXFLR</name>
4735 <address>0x78</address>
4736 </instance>
4737 <register>
4738 <width>8</width>
4739 </register>
4740 </node>
4741 <node>
4742 <name>TXABRT</name>
4743 <title>I2C Transmit Abort Status Register</title>
4744 <instance>
4745 <name>TXABRT</name>
4746 <address>0x80</address>
4747 </instance>
4748 <register>
4749 <width>16</width>
4750 <field>
4751 <name>SLVRD_INTX</name>
4752 <position>15</position>
4753 </field>
4754 <field>
4755 <name>SLV_ARBLOST</name>
4756 <position>14</position>
4757 </field>
4758 <field>
4759 <name>SLVFLUSH_TXFIFO</name>
4760 <position>13</position>
4761 </field>
4762 <field>
4763 <name>ARB_LOST</name>
4764 <position>12</position>
4765 </field>
4766 <field>
4767 <name>ABRT_MASTER_DIS</name>
4768 <position>11</position>
4769 </field>
4770 <field>
4771 <name>ABRT_10B_RD_NORSTRT</name>
4772 <position>10</position>
4773 </field>
4774 <field>
4775 <name>SBYTE_NORSTRT</name>
4776 <position>9</position>
4777 </field>
4778 <field>
4779 <name>ABRT_HS_NORSTRT</name>
4780 <position>8</position>
4781 </field>
4782 <field>
4783 <name>SBYTE_ACKDET</name>
4784 <position>7</position>
4785 </field>
4786 <field>
4787 <name>ABRT_HS_ACKD</name>
4788 <position>6</position>
4789 </field>
4790 <field>
4791 <name>ABRT_GCALL_READ</name>
4792 <position>5</position>
4793 </field>
4794 <field>
4795 <name>ABRT_GCALL_NOACK</name>
4796 <position>4</position>
4797 </field>
4798 <field>
4799 <name>ABRT_XDATA_NOACK</name>
4800 <position>3</position>
4801 </field>
4802 <field>
4803 <name>ABRT_10ADDR2_NOACK</name>
4804 <position>2</position>
4805 </field>
4806 <field>
4807 <name>ABRT_10ADDR1_NOACK</name>
4808 <position>1</position>
4809 </field>
4810 <field>
4811 <name>ABRT_7B_ADDR_NOACK</name>
4812 <position>0</position>
4813 </field>
4814 </register>
4815 </node>
4816 <node>
4817 <name>DMACR</name>
4818 <instance>
4819 <name>DMACR</name>
4820 <address>0x88</address>
4821 </instance>
4822 <register>
4823 <width>8</width>
4824 </register>
4825 </node>
4826 <node>
4827 <name>DMATDLR</name>
4828 <instance>
4829 <name>DMATDLR</name>
4830 <address>0x8c</address>
4831 </instance>
4832 <register>
4833 <width>8</width>
4834 </register>
4835 </node>
4836 <node>
4837 <name>DMARDLR</name>
4838 <instance>
4839 <name>DMARDLR</name>
4840 <address>0x90</address>
4841 </instance>
4842 <register>
4843 <width>8</width>
4844 </register>
4845 </node>
4846 <node>
4847 <name>SDASU</name>
4848 <instance>
4849 <name>SDASU</name>
4850 <address>0x94</address>
4851 </instance>
4852 <register>
4853 <width>8</width>
4854 </register>
4855 </node>
4856 <node>
4857 <name>ACKGC</name>
4858 <instance>
4859 <name>ACKGC</name>
4860 <address>0x98</address>
4861 </instance>
4862 <register>
4863 <width>8</width>
4864 </register>
4865 </node>
4866 <node>
4867 <name>ENSTA</name>
4868 <title>I2C Enable Status Register</title>
4869 <instance>
4870 <name>ENSTA</name>
4871 <address>0x9c</address>
4872 </instance>
4873 <register>
4874 <width>8</width>
4875 <field>
4876 <name>SLVRDLST</name>
4877 <position>2</position>
4878 </field>
4879 <field>
4880 <name>SLVDISB</name>
4881 <position>1</position>
4882 </field>
4883 <field>
4884 <name>I2CEN</name>
4885 <desc>when read as 1, i2c is deemed to be in an enabled state, when read as 0, i2c is deemed completely inactive. The cpu can, safely read this bit anytime .When this bit is read as 0 ,the cpu can, safely read SLVRDLST and SLVDISB</desc>
4886 <position>0</position>
4887 </field>
4888 </register>
4889 </node>
4890 <node>
4891 <name>SDAHD</name>
4892 <instance>
4893 <name>SDAHD</name>
4894 <address>0xd0</address>
4895 </instance>
4896 <register>
4897 <width>16</width>
4898 <field>
4899 <name>HOLD_TIME_EN</name>
4900 <position>8</position>
4901 </field>
4902 </register>
4903 </node>
4904 </node>
4905 <node>
4906 <name>PS2</name>
4907 <title>APB BUS Devices Base</title>
4908 <instance>
4909 <name>PS2</name>
4910 <address>0xb0060000</address>
4911 </instance>
4912 </node>
4913 <node>
4914 <name>SADC</name>
4915 <title>SAR A/D Controller</title>
4916 <instance>
4917 <name>SADC</name>
4918 <address>0xb0070000</address>
4919 </instance>
4920 <node>
4921 <name>ADENA</name>
4922 <title>ADC Enable Register</title>
4923 <instance>
4924 <name>ADENA</name>
4925 <address>0x0</address>
4926 </instance>
4927 <register>
4928 <width>8</width>
4929 <field>
4930 <name>POWER</name>
4931 <position>7</position>
4932 </field>
4933 <field>
4934 <name>SLP_MD</name>
4935 <position>6</position>
4936 </field>
4937 <field>
4938 <name>TCHEN</name>
4939 <position>2</position>
4940 </field>
4941 <field>
4942 <name>VBATEN</name>
4943 <position>1</position>
4944 </field>
4945 <field>
4946 <name>AUXEN</name>
4947 <position>0</position>
4948 </field>
4949 </register>
4950 </node>
4951 <node>
4952 <name>ADCFG</name>
4953 <title>ADC Configure Register</title>
4954 <instance>
4955 <name>ADCFG</name>
4956 <address>0x4</address>
4957 </instance>
4958 <register>
4959 <field>
4960 <name>SPZZ</name>
4961 <position>31</position>
4962 </field>
4963 <field>
4964 <name>DMA_EN</name>
4965 <position>15</position>
4966 </field>
4967 <field>
4968 <name>XYZ</name>
4969 <position>13</position>
4970 <width>2</width>
4971 <enum>
4972 <name>XYS</name>
4973 <value>0x0</value>
4974 </enum>
4975 <enum>
4976 <name>XYD</name>
4977 <value>0x1</value>
4978 </enum>
4979 <enum>
4980 <name>XYZ1Z2</name>
4981 <value>0x2</value>
4982 </enum>
4983 </field>
4984 <field>
4985 <name>SNUM</name>
4986 <position>10</position>
4987 <width>3</width>
4988 </field>
4989 <field>
4990 <name>CMD</name>
4991 <position>0</position>
4992 <width>2</width>
4993 </field>
4994 </register>
4995 </node>
4996 <node>
4997 <name>ADCTRL</name>
4998 <title>ADC Control Register</title>
4999 <instance>
5000 <name>ADCTRL</name>
5001 <address>0x8</address>
5002 </instance>
5003 <register>
5004 <width>8</width>
5005 <field>
5006 <name>SLPENDM</name>
5007 <position>5</position>
5008 </field>
5009 <field>
5010 <name>PENDM</name>
5011 <position>4</position>
5012 </field>
5013 <field>
5014 <name>PENUM</name>
5015 <position>3</position>
5016 </field>
5017 <field>
5018 <name>DTCHM</name>
5019 <position>2</position>
5020 </field>
5021 <field>
5022 <name>VRDYM</name>
5023 <position>1</position>
5024 </field>
5025 <field>
5026 <name>ARDYM</name>
5027 <position>0</position>
5028 </field>
5029 </register>
5030 </node>
5031 <node>
5032 <name>ADSTATE</name>
5033 <title>ADC Status Register</title>
5034 <instance>
5035 <name>ADSTATE</name>
5036 <address>0xc</address>
5037 </instance>
5038 <register>
5039 <width>8</width>
5040 <field>
5041 <name>SLP_RDY</name>
5042 <position>7</position>
5043 </field>
5044 <field>
5045 <name>SLPEND</name>
5046 <position>5</position>
5047 </field>
5048 <field>
5049 <name>PEND</name>
5050 <position>4</position>
5051 </field>
5052 <field>
5053 <name>PENU</name>
5054 <position>3</position>
5055 </field>
5056 <field>
5057 <name>DTCH</name>
5058 <position>2</position>
5059 </field>
5060 <field>
5061 <name>VRDY</name>
5062 <position>1</position>
5063 </field>
5064 <field>
5065 <name>ARDY</name>
5066 <position>0</position>
5067 </field>
5068 </register>
5069 </node>
5070 <node>
5071 <name>ADSAME</name>
5072 <title>ADC Same Point Time Register</title>
5073 <instance>
5074 <name>ADSAME</name>
5075 <address>0x10</address>
5076 </instance>
5077 <register>
5078 <width>16</width>
5079 <field>
5080 <name>SCNT</name>
5081 <position>0</position>
5082 <width>16</width>
5083 </field>
5084 </register>
5085 </node>
5086 <node>
5087 <name>ADWAIT</name>
5088 <title>ADC Wait Pen Down Time Register</title>
5089 <instance>
5090 <name>ADWAIT</name>
5091 <address>0x14</address>
5092 </instance>
5093 <register>
5094 <width>16</width>
5095 <field>
5096 <name>WCNT</name>
5097 <position>0</position>
5098 <width>16</width>
5099 </field>
5100 </register>
5101 </node>
5102 <node>
5103 <name>ADTCH</name>
5104 <title>ADC Touch Screen Data Register</title>
5105 <instance>
5106 <name>ADTCH</name>
5107 <address>0x18</address>
5108 </instance>
5109 <register>
5110 <field>
5111 <name>TYPE1</name>
5112 <position>31</position>
5113 </field>
5114 <field>
5115 <name>DATA1</name>
5116 <position>16</position>
5117 <width>12</width>
5118 </field>
5119 <field>
5120 <name>TYPE0</name>
5121 <position>15</position>
5122 </field>
5123 <field>
5124 <name>DATA0</name>
5125 <position>0</position>
5126 <width>12</width>
5127 </field>
5128 </register>
5129 </node>
5130 <node>
5131 <name>ADVDAT</name>
5132 <title>ADC VBAT Date Register</title>
5133 <instance>
5134 <name>ADVDAT</name>
5135 <address>0x1c</address>
5136 </instance>
5137 <register>
5138 <width>16</width>
5139 <field>
5140 <name>VDATA</name>
5141 <position>0</position>
5142 <width>12</width>
5143 </field>
5144 </register>
5145 </node>
5146 <node>
5147 <name>ADADAT</name>
5148 <title>ADC AUX Data Register</title>
5149 <instance>
5150 <name>ADADAT</name>
5151 <address>0x20</address>
5152 </instance>
5153 <register>
5154 <width>16</width>
5155 <field>
5156 <name>ADATA</name>
5157 <position>0</position>
5158 <width>12</width>
5159 </field>
5160 </register>
5161 </node>
5162 <node>
5163 <name>ADFLT</name>
5164 <title>ADC Filter Register</title>
5165 <instance>
5166 <name>ADFLT</name>
5167 <address>0x24</address>
5168 </instance>
5169 <register>
5170 <width>16</width>
5171 <field>
5172 <name>FLT_EN</name>
5173 <position>15</position>
5174 </field>
5175 <field>
5176 <name>FLT_D</name>
5177 <position>0</position>
5178 <width>12</width>
5179 </field>
5180 </register>
5181 </node>
5182 <node>
5183 <name>ADCLK</name>
5184 <title>ADC Clock Divide Register</title>
5185 <instance>
5186 <name>ADCLK</name>
5187 <address>0x28</address>
5188 </instance>
5189 <register>
5190 <field>
5191 <name>CLKDIV_MS</name>
5192 <position>16</position>
5193 <width>16</width>
5194 </field>
5195 <field>
5196 <name>CLKDIV_US</name>
5197 <position>8</position>
5198 <width>8</width>
5199 </field>
5200 <field>
5201 <name>CLKDIV</name>
5202 <position>0</position>
5203 <width>8</width>
5204 </field>
5205 </register>
5206 </node>
5207 </node>
5208 <node>
5209 <name>PCM</name>
5210 <title>Pulse-code modulation module(PCM) address definition</title>
5211 <instance>
5212 <name>PCM</name>
5213 <range>
5214 <first>0</first>
5215 <address>0xb0071000</address>
5216 <address>0xb0074000</address>
5217 </range>
5218 </instance>
5219 <node>
5220 <name>PCTL</name>
5221 <title>PCM controller control register</title>
5222 <instance>
5223 <name>PCTL</name>
5224 <address>0x0</address>
5225 </instance>
5226 <register>
5227 <field>
5228 <name>ERDMA</name>
5229 <position>9</position>
5230 </field>
5231 <field>
5232 <name>ETDMA</name>
5233 <position>8</position>
5234 </field>
5235 <field>
5236 <name>LSMP</name>
5237 <position>7</position>
5238 </field>
5239 <field>
5240 <name>ERPL</name>
5241 <position>6</position>
5242 </field>
5243 <field>
5244 <name>EREC</name>
5245 <position>5</position>
5246 </field>
5247 <field>
5248 <name>FLUSH</name>
5249 <position>4</position>
5250 </field>
5251 <field>
5252 <name>RST</name>
5253 <position>3</position>
5254 </field>
5255 <field>
5256 <name>CLKEN</name>
5257 <position>1</position>
5258 </field>
5259 <field>
5260 <name>PCMEN</name>
5261 <position>0</position>
5262 </field>
5263 </register>
5264 </node>
5265 <node>
5266 <name>PCFG</name>
5267 <title>PCM controller configure register</title>
5268 <instance>
5269 <name>PCFG</name>
5270 <address>0x4</address>
5271 </instance>
5272 <register>
5273 <field>
5274 <name>SLOT</name>
5275 <position>13</position>
5276 <width>2</width>
5277 </field>
5278 <field>
5279 <name>ISS_16BIT</name>
5280 <position>12</position>
5281 </field>
5282 <field>
5283 <name>OSS_16BIT</name>
5284 <position>11</position>
5285 </field>
5286 <field>
5287 <name>IMSBPOS</name>
5288 <position>10</position>
5289 </field>
5290 <field>
5291 <name>OMSBPOS</name>
5292 <position>9</position>
5293 </field>
5294 <field>
5295 <name>RFTH</name>
5296 <position>5</position>
5297 <width>4</width>
5298 </field>
5299 <field>
5300 <name>TFTH</name>
5301 <position>1</position>
5302 <width>4</width>
5303 </field>
5304 <field>
5305 <name>MODE_SLAVE</name>
5306 <position>0</position>
5307 </field>
5308 </register>
5309 </node>
5310 <node>
5311 <name>PDP</name>
5312 <instance>
5313 <name>PDP</name>
5314 <address>0x8</address>
5315 </instance>
5316 <register/>
5317 </node>
5318 <node>
5319 <name>PINTC</name>
5320 <title>PCM controller interrupt control register</title>
5321 <instance>
5322 <name>PINTC</name>
5323 <address>0xc</address>
5324 </instance>
5325 <register>
5326 <field>
5327 <name>ETFS</name>
5328 <position>3</position>
5329 </field>
5330 <field>
5331 <name>ETUR</name>
5332 <position>2</position>
5333 </field>
5334 <field>
5335 <name>ERFS</name>
5336 <position>1</position>
5337 </field>
5338 <field>
5339 <name>EROR</name>
5340 <position>0</position>
5341 </field>
5342 </register>
5343 </node>
5344 <node>
5345 <name>PINTS</name>
5346 <title>PCM controller interrupt status register</title>
5347 <instance>
5348 <name>PINTS</name>
5349 <address>0x10</address>
5350 </instance>
5351 <register>
5352 <field>
5353 <name>RSTS</name>
5354 <position>14</position>
5355 </field>
5356 <field>
5357 <name>TFL</name>
5358 <position>9</position>
5359 <width>5</width>
5360 </field>
5361 <field>
5362 <name>TFS</name>
5363 <position>8</position>
5364 </field>
5365 <field>
5366 <name>TUR</name>
5367 <position>7</position>
5368 </field>
5369 <field>
5370 <name>RFL</name>
5371 <position>2</position>
5372 <width>5</width>
5373 </field>
5374 <field>
5375 <name>RFS</name>
5376 <position>1</position>
5377 </field>
5378 <field>
5379 <name>ROR</name>
5380 <position>0</position>
5381 </field>
5382 </register>
5383 </node>
5384 <node>
5385 <name>PDIV</name>
5386 <title>PCM controller clock division register</title>
5387 <instance>
5388 <name>PDIV</name>
5389 <address>0x14</address>
5390 </instance>
5391 <register>
5392 <field>
5393 <name>SYNL</name>
5394 <position>11</position>
5395 <width>6</width>
5396 </field>
5397 <field>
5398 <name>SYNDIV</name>
5399 <position>6</position>
5400 <width>5</width>
5401 </field>
5402 <field>
5403 <name>CLKDIV</name>
5404 <position>0</position>
5405 <width>6</width>
5406 </field>
5407 </register>
5408 </node>
5409 </node>
5410 <node>
5411 <name>OWI</name>
5412 <instance>
5413 <name>OWI</name>
5414 <address>0xb0072000</address>
5415 </instance>
5416 <node>
5417 <name>OWICFG</name>
5418 <title>OWI configure register</title>
5419 <instance>
5420 <name>OWICFG</name>
5421 <address>0x0</address>
5422 </instance>
5423 <register>
5424 <width>8</width>
5425 <field>
5426 <name>MODE</name>
5427 <position>7</position>
5428 </field>
5429 <field>
5430 <name>RDDATA</name>
5431 <position>6</position>
5432 </field>
5433 <field>
5434 <name>WRDATA</name>
5435 <position>5</position>
5436 </field>
5437 <field>
5438 <name>RDST</name>
5439 <position>4</position>
5440 </field>
5441 <field>
5442 <name>WR1RD</name>
5443 <position>3</position>
5444 </field>
5445 <field>
5446 <name>WR0</name>
5447 <position>2</position>
5448 </field>
5449 <field>
5450 <name>RST</name>
5451 <position>1</position>
5452 </field>
5453 <field>
5454 <name>ENA</name>
5455 <position>0</position>
5456 </field>
5457 </register>
5458 </node>
5459 <node>
5460 <name>OWICTL</name>
5461 <title>OWI control register</title>
5462 <instance>
5463 <name>OWICTL</name>
5464 <address>0x4</address>
5465 </instance>
5466 <register>
5467 <width>8</width>
5468 <field>
5469 <name>EBYTE</name>
5470 <position>2</position>
5471 </field>
5472 <field>
5473 <name>EBIT</name>
5474 <position>1</position>
5475 </field>
5476 <field>
5477 <name>ERST</name>
5478 <position>0</position>
5479 </field>
5480 </register>
5481 </node>
5482 <node>
5483 <name>OWISTS</name>
5484 <title>OWI status register</title>
5485 <instance>
5486 <name>OWISTS</name>
5487 <address>0x8</address>
5488 </instance>
5489 <register>
5490 <width>8</width>
5491 <field>
5492 <name>PST</name>
5493 <position>7</position>
5494 </field>
5495 <field>
5496 <name>BYTE_RDY</name>
5497 <position>2</position>
5498 </field>
5499 <field>
5500 <name>BIT_RDY</name>
5501 <position>1</position>
5502 </field>
5503 <field>
5504 <name>PST_RDY</name>
5505 <position>0</position>
5506 </field>
5507 </register>
5508 </node>
5509 <node>
5510 <name>OWIDAT</name>
5511 <instance>
5512 <name>OWIDAT</name>
5513 <address>0xc</address>
5514 </instance>
5515 <register>
5516 <width>8</width>
5517 </register>
5518 </node>
5519 <node>
5520 <name>OWIDIV</name>
5521 <title>OWI clock divide register</title>
5522 <instance>
5523 <name>OWIDIV</name>
5524 <address>0x10</address>
5525 </instance>
5526 <register>
5527 <width>8</width>
5528 <field>
5529 <name>CLKDIV</name>
5530 <position>0</position>
5531 <width>6</width>
5532 </field>
5533 </register>
5534 </node>
5535 </node>
5536 <node>
5537 <name>TSSI</name>
5538 <title>TSSI MPEG 2-TS slave interface</title>
5539 <instance>
5540 <name>TSSI</name>
5541 <address>0xb0073000</address>
5542 </instance>
5543 <node>
5544 <name>ENA</name>
5545 <title>TSSI enable register</title>
5546 <instance>
5547 <name>ENA</name>
5548 <address>0x0</address>
5549 </instance>
5550 <register>
5551 <width>8</width>
5552 <field>
5553 <name>SFT_RST</name>
5554 <desc>soft reset bit</desc>
5555 <position>7</position>
5556 </field>
5557 <field>
5558 <name>FAIL</name>
5559 <desc>fail signal bit</desc>
5560 <position>4</position>
5561 </field>
5562 <field>
5563 <name>PEN_0</name>
5564 <desc>PID filter enable bit for PID</desc>
5565 <position>3</position>
5566 </field>
5567 <field>
5568 <name>PID_EN</name>
5569 <desc>soft filtering function enable bit</desc>
5570 <position>2</position>
5571 </field>
5572 <field>
5573 <name>DMA_EN</name>
5574 <desc>DMA enable bit</desc>
5575 <position>1</position>
5576 </field>
5577 <field>
5578 <name>ENA</name>
5579 <desc>TSSI enable bit</desc>
5580 <position>0</position>
5581 </field>
5582 </register>
5583 </node>
5584 <node>
5585 <name>CFG</name>
5586 <title>TSSI configure register</title>
5587 <instance>
5588 <name>CFG</name>
5589 <address>0x4</address>
5590 </instance>
5591 <register>
5592 <width>16</width>
5593 <field>
5594 <name>TRIG</name>
5595 <desc>fifo trig number</desc>
5596 <position>14</position>
5597 <width>2</width>
5598 <enum>
5599 <name>4</name>
5600 <value>0x0</value>
5601 </enum>
5602 <enum>
5603 <name>8</name>
5604 <value>0x1</value>
5605 </enum>
5606 <enum>
5607 <name>16</name>
5608 <value>0x2</value>
5609 </enum>
5610 <enum>
5611 <name>32</name>
5612 <value>0x3</value>
5613 </enum>
5614 </field>
5615 <field>
5616 <name>TRANS_MD</name>
5617 <position>10</position>
5618 <width>2</width>
5619 <enum>
5620 <name>0</name>
5621 <value>0x0</value>
5622 </enum>
5623 <enum>
5624 <name>1</name>
5625 <value>0x1</value>
5626 </enum>
5627 <enum>
5628 <name>2</name>
5629 <value>0x2</value>
5630 </enum>
5631 </field>
5632 <field>
5633 <name>END_WD</name>
5634 <desc>order of data in word</desc>
5635 <position>9</position>
5636 </field>
5637 <field>
5638 <name>END_BT</name>
5639 <desc>order of data in byte</desc>
5640 <position>8</position>
5641 </field>
5642 <field>
5643 <name>TSDI_H</name>
5644 <desc>data pin polarity</desc>
5645 <position>7</position>
5646 </field>
5647 <field>
5648 <name>USE_0</name>
5649 <desc>serial mode data pin select: 0 for TSDI7, 1 for TSDI0</desc>
5650 <position>6</position>
5651 </field>
5652 <field>
5653 <name>TSCLK_CH</name>
5654 <desc>clk channel select</desc>
5655 <position>5</position>
5656 </field>
5657 <field>
5658 <name>PARAL</name>
5659 <desc>mode select</desc>
5660 <position>4</position>
5661 </field>
5662 <field>
5663 <name>TSCLK_P</name>
5664 <desc>clk edge select</desc>
5665 <position>3</position>
5666 </field>
5667 <field>
5668 <name>TSFRM_H</name>
5669 <desc>TSFRM polarity select</desc>
5670 <position>2</position>
5671 </field>
5672 <field>
5673 <name>TSSTR_H</name>
5674 <desc>TSSTR polarity select</desc>
5675 <position>1</position>
5676 </field>
5677 <field>
5678 <name>TSFAIL_H</name>
5679 <desc>TSFAIL polarity select</desc>
5680 <position>0</position>
5681 </field>
5682 </register>
5683 </node>
5684 <node>
5685 <name>CTRL</name>
5686 <title>TSSI control register</title>
5687 <instance>
5688 <name>CTRL</name>
5689 <address>0x8</address>
5690 </instance>
5691 <register>
5692 <width>8</width>
5693 <field>
5694 <name>DTRM</name>
5695 <desc>FIFO data trigger interrupt mask bit</desc>
5696 <position>2</position>
5697 </field>
5698 <field>
5699 <name>OVRNM</name>
5700 <desc>FIFO overrun interrupt mask bit</desc>
5701 <position>1</position>
5702 </field>
5703 <field>
5704 <name>TRIGM</name>
5705 <desc>FIFO trigger interrupt mask bit</desc>
5706 <position>0</position>
5707 </field>
5708 </register>
5709 </node>
5710 <node>
5711 <name>STAT</name>
5712 <title>TSSI state register</title>
5713 <instance>
5714 <name>STAT</name>
5715 <address>0xc</address>
5716 </instance>
5717 <register>
5718 <width>8</width>
5719 <field>
5720 <name>DTR</name>
5721 <desc>FIFO data trigger interrupt flag bit</desc>
5722 <position>2</position>
5723 </field>
5724 <field>
5725 <name>OVRN</name>
5726 <desc>FIFO overrun interrupt flag bit</desc>
5727 <position>1</position>
5728 </field>
5729 <field>
5730 <name>TRIG</name>
5731 <desc>FIFO trigger interrupt flag bit</desc>
5732 <position>0</position>
5733 </field>
5734 </register>
5735 </node>
5736 <node>
5737 <name>FIFO</name>
5738 <title>TSSI FIFO register</title>
5739 <instance>
5740 <name>FIFO</name>
5741 <address>0x10</address>
5742 </instance>
5743 <register/>
5744 </node>
5745 <node>
5746 <name>PEN</name>
5747 <title>TSSI PID enable register</title>
5748 <instance>
5749 <name>PEN</name>
5750 <address>0x14</address>
5751 </instance>
5752 <register>
5753 <field>
5754 <name>EN151</name>
5755 <position>31</position>
5756 </field>
5757 <field>
5758 <name>EN141</name>
5759 <position>30</position>
5760 </field>
5761 <field>
5762 <name>EN131</name>
5763 <position>29</position>
5764 </field>
5765 <field>
5766 <name>EN121</name>
5767 <position>28</position>
5768 </field>
5769 <field>
5770 <name>EN111</name>
5771 <position>27</position>
5772 </field>
5773 <field>
5774 <name>EN101</name>
5775 <position>26</position>
5776 </field>
5777 <field>
5778 <name>EN91</name>
5779 <position>25</position>
5780 </field>
5781 <field>
5782 <name>EN81</name>
5783 <position>24</position>
5784 </field>
5785 <field>
5786 <name>EN71</name>
5787 <position>23</position>
5788 </field>
5789 <field>
5790 <name>EN61</name>
5791 <position>22</position>
5792 </field>
5793 <field>
5794 <name>EN51</name>
5795 <position>21</position>
5796 </field>
5797 <field>
5798 <name>EN41</name>
5799 <position>20</position>
5800 </field>
5801 <field>
5802 <name>EN31</name>
5803 <position>19</position>
5804 </field>
5805 <field>
5806 <name>EN21</name>
5807 <position>18</position>
5808 </field>
5809 <field>
5810 <name>EN11</name>
5811 <position>17</position>
5812 </field>
5813 <field>
5814 <name>EN01</name>
5815 <position>16</position>
5816 </field>
5817 <field>
5818 <name>EN150</name>
5819 <position>15</position>
5820 </field>
5821 <field>
5822 <name>EN140</name>
5823 <position>14</position>
5824 </field>
5825 <field>
5826 <name>EN130</name>
5827 <position>13</position>
5828 </field>
5829 <field>
5830 <name>EN120</name>
5831 <position>12</position>
5832 </field>
5833 <field>
5834 <name>EN110</name>
5835 <position>11</position>
5836 </field>
5837 <field>
5838 <name>EN100</name>
5839 <position>10</position>
5840 </field>
5841 <field>
5842 <name>EN90</name>
5843 <position>9</position>
5844 </field>
5845 <field>
5846 <name>EN80</name>
5847 <position>8</position>
5848 </field>
5849 <field>
5850 <name>EN70</name>
5851 <position>7</position>
5852 </field>
5853 <field>
5854 <name>EN60</name>
5855 <position>6</position>
5856 </field>
5857 <field>
5858 <name>EN50</name>
5859 <position>5</position>
5860 </field>
5861 <field>
5862 <name>EN40</name>
5863 <position>4</position>
5864 </field>
5865 <field>
5866 <name>EN30</name>
5867 <position>3</position>
5868 </field>
5869 <field>
5870 <name>EN20</name>
5871 <position>2</position>
5872 </field>
5873 <field>
5874 <name>EN10</name>
5875 <position>1</position>
5876 </field>
5877 <field>
5878 <name>EN00</name>
5879 <desc>enable PID n</desc>
5880 <position>0</position>
5881 </field>
5882 </register>
5883 </node>
5884 <node>
5885 <name>NUM</name>
5886 <instance>
5887 <name>NUM</name>
5888 <address>0x18</address>
5889 </instance>
5890 <register/>
5891 </node>
5892 <node>
5893 <name>DTR</name>
5894 <instance>
5895 <name>DTR</name>
5896 <address>0x1c</address>
5897 </instance>
5898 <register/>
5899 </node>
5900 <node>
5901 <name>PID</name>
5902 <title>TSSI PID filter register</title>
5903 <instance>
5904 <name>PID</name>
5905 <range>
5906 <first>0</first>
5907 <count>16</count>
5908 <formula variable="n">0x20 + 4*(n)</formula>
5909 </range>
5910 </instance>
5911 <register>
5912 <field>
5913 <name>PID1</name>
5914 <position>16</position>
5915 <width>13</width>
5916 </field>
5917 <field>
5918 <name>PID0</name>
5919 <position>0</position>
5920 <width>13</width>
5921 </field>
5922 </register>
5923 </node>
5924 <node>
5925 <name>DDA</name>
5926 <instance>
5927 <name>DDA</name>
5928 <address>0x60</address>
5929 </instance>
5930 <register/>
5931 </node>
5932 <node>
5933 <name>DTA</name>
5934 <instance>
5935 <name>DTA</name>
5936 <address>0x64</address>
5937 </instance>
5938 <register/>
5939 </node>
5940 <node>
5941 <name>DID</name>
5942 <instance>
5943 <name>DID</name>
5944 <address>0x68</address>
5945 </instance>
5946 <register/>
5947 </node>
5948 <node>
5949 <name>DCMD</name>
5950 <instance>
5951 <name>DCMD</name>
5952 <address>0x6c</address>
5953 </instance>
5954 <register>
5955 <field>
5956 <name>TLEN</name>
5957 <position>8</position>
5958 <width>8</width>
5959 </field>
5960 <field>
5961 <name>TEFE</name>
5962 <position>4</position>
5963 </field>
5964 <field>
5965 <name>TSZ</name>
5966 <position>2</position>
5967 <width>2</width>
5968 <enum>
5969 <name>4</name>
5970 <value>0x0</value>
5971 </enum>
5972 <enum>
5973 <name>8</name>
5974 <value>0x1</value>
5975 </enum>
5976 <enum>
5977 <name>16</name>
5978 <value>0x2</value>
5979 </enum>
5980 <enum>
5981 <name>32</name>
5982 <value>0x3</value>
5983 </enum>
5984 </field>
5985 <field>
5986 <name>TEIE</name>
5987 <position>1</position>
5988 </field>
5989 <field>
5990 <name>LINK</name>
5991 <position>0</position>
5992 </field>
5993 </register>
5994 </node>
5995 <node>
5996 <name>DST</name>
5997 <instance>
5998 <name>DST</name>
5999 <address>0x70</address>
6000 </instance>
6001 <register>
6002 <field>
6003 <name>DID</name>
6004 <position>16</position>
6005 <width>16</width>
6006 </field>
6007 <field>
6008 <name>TEND</name>
6009 <position>0</position>
6010 </field>
6011 </register>
6012 </node>
6013 <node>
6014 <name>TC</name>
6015 <instance>
6016 <name>TC</name>
6017 <address>0x74</address>
6018 </instance>
6019 <register>
6020 <field>
6021 <name>OP</name>
6022 <position>4</position>
6023 <width>2</width>
6024 </field>
6025 <field>
6026 <name>OPE</name>
6027 <position>2</position>
6028 </field>
6029 <field>
6030 <name>EME</name>
6031 <position>1</position>
6032 </field>
6033 <field>
6034 <name>APM</name>
6035 <position>0</position>
6036 </field>
6037 </register>
6038 </node>
6039 </node>
6040 <node>
6041 <name>HARB0</name>
6042 <title>AHB0 BUS Devices Base</title>
6043 <instance>
6044 <name>HARB0</name>
6045 <address>0xb3000000</address>
6046 </instance>
6047 </node>
6048 <node>
6049 <name>EMC</name>
6050 <title>EMC (External Memory Controller)</title>
6051 <instance>
6052 <name>EMC</name>
6053 <address>0xb3010000</address>
6054 </instance>
6055 <node>
6056 <name>BCR</name>
6057 <title>Bus Control Register</title>
6058 <instance>
6059 <name>BCR</name>
6060 <address>0x0</address>
6061 </instance>
6062 <register>
6063 <field>
6064 <name>BT_SEL</name>
6065 <position>30</position>
6066 <width>2</width>
6067 </field>
6068 <field>
6069 <name>PK_SEL</name>
6070 <position>24</position>
6071 </field>
6072 <field>
6073 <name>BSR</name>
6074 <desc>Nand and SDRAM Bus Share Select: 0, share; 1, unshare</desc>
6075 <position>2</position>
6076 <enum>
6077 <name>SHARE</name>
6078 <value>0x0</value>
6079 </enum>
6080 <enum>
6081 <name>UNSHARE</name>
6082 <value>0x1</value>
6083 </enum>
6084 </field>
6085 <field>
6086 <name>BRE</name>
6087 <position>1</position>
6088 </field>
6089 <field>
6090 <name>ENDIAN</name>
6091 <position>0</position>
6092 </field>
6093 </register>
6094 </node>
6095 <node>
6096 <name>SMCR</name>
6097 <title>Static Memory Control Register</title>
6098 <instance>
6099 <name>SMCR</name>
6100 <range>
6101 <first>0</first>
6102 <count>7</count>
6103 <formula variable="n">0x10 + (n)*4</formula>
6104 </range>
6105 </instance>
6106 <register>
6107 <field>
6108 <name>STRV</name>
6109 <position>24</position>
6110 <width>4</width>
6111 </field>
6112 <field>
6113 <name>TAW</name>
6114 <position>20</position>
6115 <width>4</width>
6116 </field>
6117 <field>
6118 <name>TBP</name>
6119 <position>16</position>
6120 <width>4</width>
6121 </field>
6122 <field>
6123 <name>TAH</name>
6124 <position>12</position>
6125 <width>3</width>
6126 </field>
6127 <field>
6128 <name>TAS</name>
6129 <position>8</position>
6130 <width>3</width>
6131 </field>
6132 <field>
6133 <name>BW</name>
6134 <position>6</position>
6135 <width>2</width>
6136 <enum>
6137 <name>8BIT</name>
6138 <value>0x0</value>
6139 </enum>
6140 <enum>
6141 <name>16BIT</name>
6142 <value>0x1</value>
6143 </enum>
6144 <enum>
6145 <name>32BIT</name>
6146 <value>0x2</value>
6147 </enum>
6148 </field>
6149 <field>
6150 <name>BCM</name>
6151 <position>3</position>
6152 </field>
6153 <field>
6154 <name>BL</name>
6155 <position>1</position>
6156 <width>2</width>
6157 <enum>
6158 <name>4</name>
6159 <value>0x0</value>
6160 </enum>
6161 <enum>
6162 <name>8</name>
6163 <value>0x1</value>
6164 </enum>
6165 <enum>
6166 <name>16</name>
6167 <value>0x2</value>
6168 </enum>
6169 <enum>
6170 <name>32</name>
6171 <value>0x3</value>
6172 </enum>
6173 </field>
6174 <field>
6175 <name>SMT</name>
6176 <position>0</position>
6177 </field>
6178 </register>
6179 </node>
6180 <node>
6181 <name>SACR</name>
6182 <title>Static Memory Bank Addr Config Reg</title>
6183 <instance>
6184 <name>SACR</name>
6185 <range>
6186 <first>0</first>
6187 <count>5</count>
6188 <formula variable="n">0x30 + (n)*4</formula>
6189 </range>
6190 </instance>
6191 <register>
6192 <field>
6193 <name>BASE</name>
6194 <position>8</position>
6195 <width>8</width>
6196 </field>
6197 <field>
6198 <name>MASK</name>
6199 <position>0</position>
6200 <width>8</width>
6201 </field>
6202 </register>
6203 </node>
6204 <node>
6205 <name>NFCSR</name>
6206 <title>NAND Flash Control/Status Register</title>
6207 <instance>
6208 <name>NFCSR</name>
6209 <address>0x50</address>
6210 </instance>
6211 <register>
6212 <field>
6213 <name>NFCE4</name>
6214 <desc>NAND Flash Enable</desc>
6215 <position>7</position>
6216 </field>
6217 <field>
6218 <name>NFE4</name>
6219 <desc>NAND Flash FCE# Assertion Enable</desc>
6220 <position>6</position>
6221 </field>
6222 <field>
6223 <name>NFCE3</name>
6224 <position>5</position>
6225 </field>
6226 <field>
6227 <name>NFE3</name>
6228 <position>4</position>
6229 </field>
6230 <field>
6231 <name>NFCE2</name>
6232 <position>3</position>
6233 </field>
6234 <field>
6235 <name>NFE2</name>
6236 <position>2</position>
6237 </field>
6238 <field>
6239 <name>NFCE1</name>
6240 <position>1</position>
6241 </field>
6242 <field>
6243 <name>NFE1</name>
6244 <position>0</position>
6245 </field>
6246 </register>
6247 </node>
6248 <node>
6249 <name>DMCR</name>
6250 <title>DRAM Control Register</title>
6251 <instance>
6252 <name>DMCR</name>
6253 <address>0x80</address>
6254 </instance>
6255 <register>
6256 <field>
6257 <name>BW</name>
6258 <position>31</position>
6259 </field>
6260 <field>
6261 <name>CA</name>
6262 <position>26</position>
6263 <width>3</width>
6264 <enum>
6265 <name>8</name>
6266 <value>0x0</value>
6267 </enum>
6268 <enum>
6269 <name>9</name>
6270 <value>0x1</value>
6271 </enum>
6272 <enum>
6273 <name>10</name>
6274 <value>0x2</value>
6275 </enum>
6276 <enum>
6277 <name>11</name>
6278 <value>0x3</value>
6279 </enum>
6280 <enum>
6281 <name>12</name>
6282 <value>0x4</value>
6283 </enum>
6284 </field>
6285 <field>
6286 <name>RMODE</name>
6287 <position>25</position>
6288 </field>
6289 <field>
6290 <name>RFSH</name>
6291 <position>24</position>
6292 </field>
6293 <field>
6294 <name>MRSET</name>
6295 <position>23</position>
6296 </field>
6297 <field>
6298 <name>RA</name>
6299 <position>20</position>
6300 <width>2</width>
6301 <enum>
6302 <name>11</name>
6303 <value>0x0</value>
6304 </enum>
6305 <enum>
6306 <name>12</name>
6307 <value>0x1</value>
6308 </enum>
6309 <enum>
6310 <name>13</name>
6311 <value>0x2</value>
6312 </enum>
6313 </field>
6314 <field>
6315 <name>BA</name>
6316 <position>19</position>
6317 </field>
6318 <field>
6319 <name>PDM</name>
6320 <position>18</position>
6321 </field>
6322 <field>
6323 <name>EPIN</name>
6324 <position>17</position>
6325 </field>
6326 <field>
6327 <name>MBSEL</name>
6328 <position>16</position>
6329 </field>
6330 <field>
6331 <name>TRAS</name>
6332 <position>13</position>
6333 <width>3</width>
6334 </field>
6335 <field>
6336 <name>RCD</name>
6337 <position>11</position>
6338 <width>2</width>
6339 </field>
6340 <field>
6341 <name>TPC</name>
6342 <position>8</position>
6343 <width>3</width>
6344 </field>
6345 <field>
6346 <name>TRWL</name>
6347 <position>5</position>
6348 <width>2</width>
6349 </field>
6350 <field>
6351 <name>TRC</name>
6352 <position>2</position>
6353 <width>3</width>
6354 </field>
6355 <field>
6356 <name>TCL</name>
6357 <position>0</position>
6358 <width>2</width>
6359 </field>
6360 </register>
6361 </node>
6362 <node>
6363 <name>RTCSR</name>
6364 <title>Refresh Time Control/Status Register</title>
6365 <instance>
6366 <name>RTCSR</name>
6367 <address>0x84</address>
6368 </instance>
6369 <register>
6370 <width>16</width>
6371 <field>
6372 <name>SFR</name>
6373 <desc>self refresh flag</desc>
6374 <position>8</position>
6375 </field>
6376 <field>
6377 <name>CMF</name>
6378 <position>7</position>
6379 </field>
6380 <field>
6381 <name>CKS</name>
6382 <position>0</position>
6383 <width>3</width>
6384 <enum>
6385 <name>DISABLE</name>
6386 <value>0x0</value>
6387 </enum>
6388 <enum>
6389 <name>4</name>
6390 <value>0x1</value>
6391 </enum>
6392 <enum>
6393 <name>16</name>
6394 <value>0x2</value>
6395 </enum>
6396 <enum>
6397 <name>64</name>
6398 <value>0x3</value>
6399 </enum>
6400 <enum>
6401 <name>256</name>
6402 <value>0x4</value>
6403 </enum>
6404 <enum>
6405 <name>1024</name>
6406 <value>0x5</value>
6407 </enum>
6408 <enum>
6409 <name>2048</name>
6410 <value>0x6</value>
6411 </enum>
6412 <enum>
6413 <name>4096</name>
6414 <value>0x7</value>
6415 </enum>
6416 </field>
6417 </register>
6418 </node>
6419 <node>
6420 <name>RTCNT</name>
6421 <title>Refresh Timer Counter</title>
6422 <instance>
6423 <name>RTCNT</name>
6424 <address>0x88</address>
6425 </instance>
6426 <register>
6427 <width>16</width>
6428 </register>
6429 </node>
6430 <node>
6431 <name>RTCOR</name>
6432 <title>Refresh Time Constant Register</title>
6433 <instance>
6434 <name>RTCOR</name>
6435 <address>0x8c</address>
6436 </instance>
6437 <register>
6438 <width>16</width>
6439 </register>
6440 </node>
6441 <node>
6442 <name>DMAR</name>
6443 <title>SDRAM Bank Address Configuration Register</title>
6444 <instance>
6445 <name>DMAR</name>
6446 <range>
6447 <first>0</first>
6448 <count>2</count>
6449 <formula variable="n">0x90 + (n)*4</formula>
6450 </range>
6451 </instance>
6452 <register>
6453 <field>
6454 <name>BASE</name>
6455 <position>8</position>
6456 <width>8</width>
6457 </field>
6458 <field>
6459 <name>MASK</name>
6460 <position>0</position>
6461 <width>8</width>
6462 </field>
6463 </register>
6464 </node>
6465 <node>
6466 <name>PMEMBS1</name>
6467 <instance>
6468 <name>PMEMBS1</name>
6469 <address>0x6004</address>
6470 </instance>
6471 <register/>
6472 </node>
6473 <node>
6474 <name>PMEMBS0</name>
6475 <instance>
6476 <name>PMEMBS0</name>
6477 <address>0x6008</address>
6478 </instance>
6479 <register/>
6480 </node>
6481 <node>
6482 <name>SDMR</name>
6483 <title>Mode Register of SDRAM bank</title>
6484 <instance>
6485 <name>SDMR</name>
6486 <address>0xa000</address>
6487 </instance>
6488 <register>
6489 <field>
6490 <name>BM</name>
6491 <desc>Write Burst Mode</desc>
6492 <position>9</position>
6493 </field>
6494 <field>
6495 <name>OM</name>
6496 <desc>Operating Mode</desc>
6497 <position>7</position>
6498 <width>2</width>
6499 <enum>
6500 <name>NORMAL</name>
6501 <value>0x0</value>
6502 </enum>
6503 </field>
6504 <field>
6505 <name>CAS</name>
6506 <desc>CAS Latency</desc>
6507 <position>4</position>
6508 <width>3</width>
6509 <enum>
6510 <name>1</name>
6511 <value>0x1</value>
6512 </enum>
6513 <enum>
6514 <name>2</name>
6515 <value>0x2</value>
6516 </enum>
6517 <enum>
6518 <name>3</name>
6519 <value>0x3</value>
6520 </enum>
6521 </field>
6522 <field>
6523 <name>BT</name>
6524 <desc>Interleave</desc>
6525 <position>3</position>
6526 <enum>
6527 <name>SEQ</name>
6528 <value>0x0</value>
6529 </enum>
6530 <enum>
6531 <name>INT</name>
6532 <value>0x1</value>
6533 </enum>
6534 </field>
6535 <field>
6536 <name>BL</name>
6537 <desc>Burst Length</desc>
6538 <position>0</position>
6539 <width>3</width>
6540 <enum>
6541 <name>1</name>
6542 <value>0x0</value>
6543 </enum>
6544 <enum>
6545 <name>2</name>
6546 <value>0x1</value>
6547 </enum>
6548 <enum>
6549 <name>4</name>
6550 <value>0x2</value>
6551 </enum>
6552 <enum>
6553 <name>8</name>
6554 <value>0x3</value>
6555 </enum>
6556 </field>
6557 </register>
6558 </node>
6559 </node>
6560 <node>
6561 <name>OTP</name>
6562 <title>OTP (One Time Programmable Module) [not sure about the address]</title>
6563 <instance>
6564 <name>OTP</name>
6565 <address>0xb3012000</address>
6566 </instance>
6567 <node>
6568 <name>ID0</name>
6569 <title>ID0 Register</title>
6570 <instance>
6571 <name>ID0</name>
6572 <address>0x0</address>
6573 </instance>
6574 <register>
6575 <field>
6576 <name>WID</name>
6577 <desc>Wafer ID</desc>
6578 <position>24</position>
6579 <width>8</width>
6580 </field>
6581 <field>
6582 <name>MID</name>
6583 <desc>MASK ID</desc>
6584 <position>16</position>
6585 <width>8</width>
6586 </field>
6587 <field>
6588 <name>FID</name>
6589 <desc>Foundary ID</desc>
6590 <position>8</position>
6591 <width>8</width>
6592 </field>
6593 <field>
6594 <name>PID</name>
6595 <desc>Product ID</desc>
6596 <position>0</position>
6597 <width>8</width>
6598 </field>
6599 </register>
6600 </node>
6601 <node>
6602 <name>ID1</name>
6603 <title>ID1 Register</title>
6604 <instance>
6605 <name>ID1</name>
6606 <address>0x4</address>
6607 </instance>
6608 <register>
6609 <field>
6610 <name>LID</name>
6611 <desc>Lot ID</desc>
6612 <position>8</position>
6613 <width>24</width>
6614 </field>
6615 <field>
6616 <name>TID</name>
6617 <desc>Test House ID</desc>
6618 <position>0</position>
6619 <width>8</width>
6620 </field>
6621 </register>
6622 </node>
6623 <node>
6624 <name>ID2</name>
6625 <title>ID2 Register</title>
6626 <instance>
6627 <name>ID2</name>
6628 <address>0x8</address>
6629 </instance>
6630 <register>
6631 <field>
6632 <name>XADR</name>
6633 <desc>Die X-dir Address</desc>
6634 <position>24</position>
6635 <width>8</width>
6636 </field>
6637 <field>
6638 <name>YADR</name>
6639 <desc>Die Y-dir Address</desc>
6640 <position>16</position>
6641 <width>8</width>
6642 </field>
6643 <field>
6644 <name>TDATE</name>
6645 <desc>Testing Date</desc>
6646 <position>0</position>
6647 <width>16</width>
6648 </field>
6649 </register>
6650 </node>
6651 <node>
6652 <name>ID3</name>
6653 <title>ID3 Register</title>
6654 <instance>
6655 <name>ID3</name>
6656 <address>0xc</address>
6657 </instance>
6658 <register>
6659 <field>
6660 <name>CID</name>
6661 <desc>Customer ID</desc>
6662 <position>16</position>
6663 <width>16</width>
6664 </field>
6665 <field>
6666 <name>CP</name>
6667 <desc>Chip Parameters</desc>
6668 <position>0</position>
6669 <width>16</width>
6670 </field>
6671 </register>
6672 </node>
6673 <node>
6674 <name>BR0</name>
6675 <title>BOOTROM0 Register</title>
6676 <instance>
6677 <name>BR0</name>
6678 <address>0x10</address>
6679 </instance>
6680 <register/>
6681 </node>
6682 <node>
6683 <name>BR1</name>
6684 <title>BOOTROM1 Register</title>
6685 <instance>
6686 <name>BR1</name>
6687 <address>0x14</address>
6688 </instance>
6689 <register>
6690 <field>
6691 <name>UDCBOOT</name>
6692 <desc>27MHz OSC</desc>
6693 <position>0</position>
6694 <width>8</width>
6695 <enum>
6696 <name>27M</name>
6697 <value>0x0</value>
6698 </enum>
6699 <enum>
6700 <name>26M</name>
6701 <value>0x3</value>
6702 </enum>
6703 <enum>
6704 <name>13M</name>
6705 <value>0xc</value>
6706 </enum>
6707 <enum>
6708 <name>24M</name>
6709 <value>0xf</value>
6710 </enum>
6711 <enum>
6712 <name>AUTO</name>
6713 <value>0xf0</value>
6714 </enum>
6715 </field>
6716 </register>
6717 </node>
6718 <node>
6719 <name>HW0</name>
6720 <title>Chip Hardware 0 Register</title>
6721 <instance>
6722 <name>HW0</name>
6723 <address>0x18</address>
6724 </instance>
6725 <register/>
6726 </node>
6727 <node>
6728 <name>HW1</name>
6729 <title>Chip Hardware 1 Register</title>
6730 <instance>
6731 <name>HW1</name>
6732 <address>0x1c</address>
6733 </instance>
6734 <register/>
6735 </node>
6736 </node>
6737 <node>
6738 <name>DDRC</name>
6739 <instance>
6740 <name>DDRC</name>
6741 <address>0xb3020000</address>
6742 </instance>
6743 <node>
6744 <name>STATUS</name>
6745 <title>DDR Status Register</title>
6746 <instance>
6747 <name>STATUS</name>
6748 <address>0x0</address>
6749 </instance>
6750 <register>
6751 <field>
6752 <name>ENDIAN</name>
6753 <desc>0 Little data endian, 1 Big data endian</desc>
6754 <position>7</position>
6755 </field>
6756 <field>
6757 <name>MISS</name>
6758 <position>6</position>
6759 </field>
6760 <field>
6761 <name>DPDN</name>
6762 <desc>0 DDR memory is NOT in deep-power-down state, 1 DDR memory is in deep-power-down state</desc>
6763 <position>5</position>
6764 </field>
6765 <field>
6766 <name>PDN</name>
6767 <desc>0 DDR memory is NOT in power-down state, 1 DDR memory is in power-down state</desc>
6768 <position>4</position>
6769 </field>
6770 <field>
6771 <name>AREF</name>
6772 <desc>0 DDR memory is NOT in auto-refresh state, 1 DDR memory is in auto-refresh state</desc>
6773 <position>3</position>
6774 </field>
6775 <field>
6776 <name>SREF</name>
6777 <desc>0 DDR memory is NOT in self-refresh state, 1 DDR memory is in self-refresh state</desc>
6778 <position>2</position>
6779 </field>
6780 <field>
6781 <name>CKE1</name>
6782 <desc>0 CKE1 Pin is low, 1 CKE1 Pin is high</desc>
6783 <position>1</position>
6784 </field>
6785 <field>
6786 <name>CKE0</name>
6787 <desc>0 CKE0 Pin is low, 1 CKE0 Pin is high</desc>
6788 <position>0</position>
6789 </field>
6790 </register>
6791 </node>
6792 <node>
6793 <name>CFG</name>
6794 <title>DDR Configure Register</title>
6795 <instance>
6796 <name>CFG</name>
6797 <address>0x4</address>
6798 </instance>
6799 <register>
6800 <field>
6801 <name>ROW1</name>
6802 <desc>Row Address width.</desc>
6803 <position>27</position>
6804 <width>2</width>
6805 <enum>
6806 <name>12</name>
6807 <value>0x0</value>
6808 </enum>
6809 <enum>
6810 <name>13</name>
6811 <value>0x1</value>
6812 </enum>
6813 <enum>
6814 <name>14</name>
6815 <value>0x2</value>
6816 </enum>
6817 </field>
6818 <field>
6819 <name>COL1</name>
6820 <desc>Row Address width.</desc>
6821 <position>25</position>
6822 <width>2</width>
6823 <enum>
6824 <name>8</name>
6825 <value>0x0</value>
6826 </enum>
6827 <enum>
6828 <name>9</name>
6829 <value>0x1</value>
6830 </enum>
6831 <enum>
6832 <name>10</name>
6833 <value>0x2</value>
6834 </enum>
6835 <enum>
6836 <name>11</name>
6837 <value>0x3</value>
6838 </enum>
6839 </field>
6840 <field>
6841 <name>BA1_BIT</name>
6842 <desc>bank width</desc>
6843 <position>24</position>
6844 <enum>
6845 <name>4</name>
6846 <value>0x0</value>
6847 </enum>
6848 <enum>
6849 <name>8</name>
6850 <value>0x1</value>
6851 </enum>
6852 </field>
6853 <field>
6854 <name>IMBA</name>
6855 <position>23</position>
6856 </field>
6857 <field>
6858 <name>BTRUN</name>
6859 <position>21</position>
6860 </field>
6861 <field>
6862 <name>MPRT</name>
6863 <desc>Miss CS protect: 0 will lock the bus on fault, 1 will return random data</desc>
6864 <position>15</position>
6865 </field>
6866 <field>
6867 <name>TYPE</name>
6868 <position>12</position>
6869 <width>3</width>
6870 <enum>
6871 <name>DDR1</name>
6872 <value>0x2</value>
6873 </enum>
6874 <enum>
6875 <name>MDDR</name>
6876 <value>0x3</value>
6877 </enum>
6878 <enum>
6879 <name>DDR2</name>
6880 <value>0x4</value>
6881 </enum>
6882 </field>
6883 <field>
6884 <name>ROW0</name>
6885 <desc>Row Address width.</desc>
6886 <position>10</position>
6887 <width>2</width>
6888 <enum>
6889 <name>12</name>
6890 <value>0x0</value>
6891 </enum>
6892 <enum>
6893 <name>13</name>
6894 <value>0x1</value>
6895 </enum>
6896 <enum>
6897 <name>14</name>
6898 <value>0x2</value>
6899 </enum>
6900 </field>
6901 <field>
6902 <name>COL0</name>
6903 <desc>Row Address width.</desc>
6904 <position>8</position>
6905 <width>2</width>
6906 <enum>
6907 <name>8</name>
6908 <value>0x0</value>
6909 </enum>
6910 <enum>
6911 <name>9</name>
6912 <value>0x1</value>
6913 </enum>
6914 <enum>
6915 <name>10</name>
6916 <value>0x2</value>
6917 </enum>
6918 <enum>
6919 <name>11</name>
6920 <value>0x3</value>
6921 </enum>
6922 </field>
6923 <field>
6924 <name>CS1EN</name>
6925 <desc>0 DDR Pin CS1 un-used, 1 There're DDR memory connected to CS1</desc>
6926 <position>7</position>
6927 </field>
6928 <field>
6929 <name>CS0EN</name>
6930 <desc>0 DDR Pin CS0 un-used, 1 There're DDR memory connected to CS0</desc>
6931 <position>6</position>
6932 </field>
6933 <field>
6934 <name>CL</name>
6935 <desc>CAS latency</desc>
6936 <position>2</position>
6937 <width>4</width>
6938 <enum>
6939 <name>3</name>
6940 <value>0x0</value>
6941 </enum>
6942 <enum>
6943 <name>4</name>
6944 <value>0x1</value>
6945 </enum>
6946 <enum>
6947 <name>5</name>
6948 <value>0x2</value>
6949 </enum>
6950 <enum>
6951 <name>6</name>
6952 <value>0x3</value>
6953 </enum>
6954 </field>
6955 <field>
6956 <name>BA0</name>
6957 <desc>bank width</desc>
6958 <position>1</position>
6959 <enum>
6960 <name>4</name>
6961 <value>0x0</value>
6962 </enum>
6963 <enum>
6964 <name>8</name>
6965 <value>0x1</value>
6966 </enum>
6967 </field>
6968 <field>
6969 <name>DW</name>
6970 <desc>External memory data width</desc>
6971 <position>0</position>
6972 <enum>
6973 <name>16</name>
6974 <value>0x0</value>
6975 </enum>
6976 <enum>
6977 <name>32</name>
6978 <value>0x1</value>
6979 </enum>
6980 </field>
6981 </register>
6982 </node>
6983 <node>
6984 <name>CTRL</name>
6985 <title>DDR Control Register</title>
6986 <instance>
6987 <name>CTRL</name>
6988 <address>0x8</address>
6989 </instance>
6990 <register>
6991 <field>
6992 <name>ACTPD</name>
6993 <desc>0 Precharge all banks before entering power-down, 1 Do not precharge banks before entering power-down</desc>
6994 <position>15</position>
6995 </field>
6996 <field>
6997 <name>PDT</name>
6998 <desc>Enter power-down after 128 tCK idle</desc>
6999 <position>12</position>
7000 <width>3</width>
7001 <enum>
7002 <name>DIS</name>
7003 <value>0x0</value>
7004 </enum>
7005 <enum>
7006 <name>8</name>
7007 <value>0x1</value>
7008 </enum>
7009 <enum>
7010 <name>16</name>
7011 <value>0x2</value>
7012 </enum>
7013 <enum>
7014 <name>32</name>
7015 <value>0x3</value>
7016 </enum>
7017 <enum>
7018 <name>64</name>
7019 <value>0x4</value>
7020 </enum>
7021 <enum>
7022 <name>128</name>
7023 <value>0x5</value>
7024 </enum>
7025 </field>
7026 <field>
7027 <name>PRET</name>
7028 <desc>Precharge active bank after 128 tCK idle</desc>
7029 <position>8</position>
7030 <width>3</width>
7031 <enum>
7032 <name>DIS</name>
7033 <value>0x0</value>
7034 </enum>
7035 <enum>
7036 <name>8</name>
7037 <value>0x1</value>
7038 </enum>
7039 <enum>
7040 <name>16</name>
7041 <value>0x2</value>
7042 </enum>
7043 <enum>
7044 <name>32</name>
7045 <value>0x3</value>
7046 </enum>
7047 <enum>
7048 <name>64</name>
7049 <value>0x4</value>
7050 </enum>
7051 <enum>
7052 <name>128</name>
7053 <value>0x5</value>
7054 </enum>
7055 </field>
7056 <field>
7057 <name>SR</name>
7058 <desc>1 Drive external DDR device entering self-refresh mode, 0 Drive external DDR device exiting self-refresh mode</desc>
7059 <position>5</position>
7060 </field>
7061 <field>
7062 <name>UNALIGN</name>
7063 <desc>0 Disable unaligned transfer on AXI BUS, 1 Enable unaligned transfer on AXI BUS</desc>
7064 <position>4</position>
7065 </field>
7066 <field>
7067 <name>ALH</name>
7068 <desc>Advanced Latency Hiding: 0 Disable ALH, 1 Enable ALH</desc>
7069 <position>3</position>
7070 </field>
7071 <field>
7072 <name>RDC</name>
7073 <desc>0 dclk clock frequency is lower than 60MHz, 1 dclk clock frequency is higher than 60MHz</desc>
7074 <position>2</position>
7075 </field>
7076 <field>
7077 <name>CKE</name>
7078 <desc>0 Not set CKE Pin High, 1 Set CKE Pin HIGH</desc>
7079 <position>1</position>
7080 </field>
7081 <field>
7082 <name>RESET</name>
7083 <desc>0 End resetting ddrc_controller, 1 Resetting ddrc_controller</desc>
7084 <position>0</position>
7085 </field>
7086 </register>
7087 </node>
7088 <node>
7089 <name>LMR</name>
7090 <title>DDR Load-Mode-Register</title>
7091 <instance>
7092 <name>LMR</name>
7093 <address>0xc</address>
7094 </instance>
7095 <register>
7096 <field>
7097 <name>DDR_ADDR</name>
7098 <position>16</position>
7099 <width>8</width>
7100 </field>
7101 <field>
7102 <name>BA</name>
7103 <desc>(For mobile DDR) Status Register set</desc>
7104 <position>8</position>
7105 <width>3</width>
7106 <enum>
7107 <name>MRS</name>
7108 <value>0x0</value>
7109 </enum>
7110 <enum>
7111 <name>M_MRS</name>
7112 <value>0x0</value>
7113 </enum>
7114 <enum>
7115 <name>EMRS1</name>
7116 <value>0x1</value>
7117 </enum>
7118 <enum>
7119 <name>M_SR</name>
7120 <value>0x1</value>
7121 </enum>
7122 <enum>
7123 <name>EMRS2</name>
7124 <value>0x2</value>
7125 </enum>
7126 <enum>
7127 <name>M_EMRS</name>
7128 <value>0x2</value>
7129 </enum>
7130 <enum>
7131 <name>EMRS3</name>
7132 <value>0x3</value>
7133 </enum>
7134 </field>
7135 <field>
7136 <name>CMD</name>
7137 <desc>Load Mode Register</desc>
7138 <position>4</position>
7139 <width>2</width>
7140 <enum>
7141 <name>PREC</name>
7142 <desc>Precharge one/all bank</desc>
7143 <value>0x0</value>
7144 </enum>
7145 <enum>
7146 <name>AUREF</name>
7147 <desc>Auto-refresh</desc>
7148 <value>0x1</value>
7149 </enum>
7150 <enum>
7151 <name>LMR</name>
7152 <desc>Load-Mode reister</desc>
7153 <value>0x2</value>
7154 </enum>
7155 </field>
7156 <field>
7157 <name>START</name>
7158 <desc>0 No command is performed, 1 On the posedge of START, perform a command defined by CMD field</desc>
7159 <position>0</position>
7160 </field>
7161 </register>
7162 </node>
7163 <node>
7164 <name>TIMING1</name>
7165 <title>DDR Timing Config Register 1</title>
7166 <instance>
7167 <name>TIMING1</name>
7168 <address>0x10</address>
7169 </instance>
7170 <register>
7171 <field>
7172 <name>TRAS</name>
7173 <desc>ACTIVE to PRECHARGE command period (2 * tRAS + 1)</desc>
7174 <position>28</position>
7175 <width>4</width>
7176 </field>
7177 <field>
7178 <name>TRTP</name>
7179 <desc>READ to PRECHARGE command period.</desc>
7180 <position>24</position>
7181 <width>2</width>
7182 </field>
7183 <field>
7184 <name>TRP</name>
7185 <desc>PRECHARGE command period.</desc>
7186 <position>20</position>
7187 <width>3</width>
7188 </field>
7189 <field>
7190 <name>TRCD</name>
7191 <desc>ACTIVE to READ or WRITE command period.</desc>
7192 <position>16</position>
7193 <width>3</width>
7194 </field>
7195 <field>
7196 <name>TRC</name>
7197 <desc>ACTIVE to ACTIVE command period.</desc>
7198 <position>12</position>
7199 <width>4</width>
7200 </field>
7201 <field>
7202 <name>TRRD</name>
7203 <desc>ACTIVE bank A to ACTIVE bank B command period.</desc>
7204 <position>8</position>
7205 <width>2</width>
7206 <enum>
7207 <name>DISABLE</name>
7208 <value>0x0</value>
7209 </enum>
7210 <enum>
7211 <name>2</name>
7212 <value>0x1</value>
7213 </enum>
7214 <enum>
7215 <name>3</name>
7216 <value>0x2</value>
7217 </enum>
7218 <enum>
7219 <name>4</name>
7220 <value>0x3</value>
7221 </enum>
7222 </field>
7223 <field>
7224 <name>TWR</name>
7225 <desc>WRITE Recovery Time defined by register MR of DDR2 memory</desc>
7226 <position>4</position>
7227 <width>3</width>
7228 <enum>
7229 <name>1</name>
7230 <value>0x0</value>
7231 </enum>
7232 <enum>
7233 <name>2</name>
7234 <value>0x1</value>
7235 </enum>
7236 <enum>
7237 <name>3</name>
7238 <value>0x2</value>
7239 </enum>
7240 <enum>
7241 <name>4</name>
7242 <value>0x3</value>
7243 </enum>
7244 <enum>
7245 <name>5</name>
7246 <value>0x4</value>
7247 </enum>
7248 <enum>
7249 <name>6</name>
7250 <value>0x5</value>
7251 </enum>
7252 </field>
7253 <field>
7254 <name>TWTR</name>
7255 <desc>WRITE to READ command delay.</desc>
7256 <position>0</position>
7257 <width>2</width>
7258 <enum>
7259 <name>1</name>
7260 <value>0x0</value>
7261 </enum>
7262 <enum>
7263 <name>2</name>
7264 <value>0x1</value>
7265 </enum>
7266 <enum>
7267 <name>3</name>
7268 <value>0x2</value>
7269 </enum>
7270 <enum>
7271 <name>4</name>
7272 <value>0x3</value>
7273 </enum>
7274 </field>
7275 </register>
7276 </node>
7277 <node>
7278 <name>TIMING2</name>
7279 <title>DDR Timing Config Register 2</title>
7280 <instance>
7281 <name>TIMING2</name>
7282 <address>0x14</address>
7283 </instance>
7284 <register>
7285 <field>
7286 <name>TRFC</name>
7287 <desc>AUTO-REFRESH command period.</desc>
7288 <position>24</position>
7289 <width>4</width>
7290 </field>
7291 <field>
7292 <name>RWCOV</name>
7293 <desc>Equal to Tsel of MDELAY.</desc>
7294 <position>19</position>
7295 <width>5</width>
7296 </field>
7297 <field>
7298 <name>TMINSR</name>
7299 <desc>Minimum Self-Refresh / Deep-Power-Down time</desc>
7300 <position>8</position>
7301 <width>4</width>
7302 </field>
7303 <field>
7304 <name>TXP</name>
7305 <desc>EXIT-POWER-DOWN to next valid command period.</desc>
7306 <position>4</position>
7307 <width>3</width>
7308 </field>
7309 <field>
7310 <name>TMRD</name>
7311 <desc>Load-Mode-Register to next valid command period.</desc>
7312 <position>0</position>
7313 <width>2</width>
7314 </field>
7315 </register>
7316 </node>
7317 <node>
7318 <name>REFCNT</name>
7319 <title>DDR Auto-Refresh Counter</title>
7320 <instance>
7321 <name>REFCNT</name>
7322 <address>0x18</address>
7323 </instance>
7324 <register>
7325 <field>
7326 <name>CON</name>
7327 <desc>Constant value used to compare with CNT value.</desc>
7328 <position>16</position>
7329 <width>8</width>
7330 </field>
7331 <field>
7332 <name>CNT</name>
7333 <desc>8-bit counter</desc>
7334 <position>8</position>
7335 <width>8</width>
7336 </field>
7337 <field>
7338 <name>CLKDIV</name>
7339 <desc>Clock Divider for auto-refresh counter.</desc>
7340 <position>1</position>
7341 <width>3</width>
7342 </field>
7343 <field>
7344 <name>REF_EN</name>
7345 <desc>Enable Refresh Counter</desc>
7346 <position>0</position>
7347 </field>
7348 </register>
7349 </node>
7350 <node>
7351 <name>DQS</name>
7352 <title>DDR DQS Delay Control Register</title>
7353 <instance>
7354 <name>DQS</name>
7355 <address>0x1c</address>
7356 </instance>
7357 <register>
7358 <field>
7359 <name>ERROR</name>
7360 <desc>ahb_clk Delay Detect ERROR, read-only.</desc>
7361 <position>29</position>
7362 </field>
7363 <field>
7364 <name>READY</name>
7365 <desc>ahb_clk Delay Detect READY, read-only.</desc>
7366 <position>28</position>
7367 </field>
7368 <field>
7369 <name>SRDET</name>
7370 <desc>Hardware auto-redetect &amp; set delay line</desc>
7371 <position>25</position>
7372 </field>
7373 <field>
7374 <name>DET</name>
7375 <desc>Start delay detecting.</desc>
7376 <position>24</position>
7377 </field>
7378 <field>
7379 <name>AUTO</name>
7380 <desc>Hardware auto-detect &amp; set delay line</desc>
7381 <position>23</position>
7382 </field>
7383 <field>
7384 <name>CLKD</name>
7385 <desc>CLKD is reference value for setting WDQS and RDQS.</desc>
7386 <position>16</position>
7387 <width>7</width>
7388 </field>
7389 <field>
7390 <name>WDQS</name>
7391 <desc>Set delay element number to write DQS delay-line.</desc>
7392 <position>8</position>
7393 <width>6</width>
7394 </field>
7395 <field>
7396 <name>RDQS</name>
7397 <desc>Set delay element number to read DQS delay-line.</desc>
7398 <position>0</position>
7399 <width>6</width>
7400 </field>
7401 </register>
7402 </node>
7403 <node>
7404 <name>DQSADJ</name>
7405 <title>DDR DQS Delay Adjust Register</title>
7406 <instance>
7407 <name>DQSADJ</name>
7408 <address>0x20</address>
7409 </instance>
7410 <register>
7411 <field>
7412 <name>WSIGN</name>
7413 <desc>The sign of WDQS value for WRITE DQS delay</desc>
7414 <position>13</position>
7415 </field>
7416 <field>
7417 <name>WDQS</name>
7418 <desc>The adjust value for WRITE DQS delay</desc>
7419 <position>8</position>
7420 <width>5</width>
7421 </field>
7422 <field>
7423 <name>RSIGN</name>
7424 <desc>The sign of RDQS value for READ DQS delay </desc>
7425 <position>5</position>
7426 </field>
7427 <field>
7428 <name>RDQS</name>
7429 <desc>The adjust value for READ DQS delay</desc>
7430 <position>0</position>
7431 <width>5</width>
7432 </field>
7433 </register>
7434 </node>
7435 <node>
7436 <name>MMAP</name>
7437 <title>DDR Memory Map Config Register</title>
7438 <instance>
7439 <name>MMAP</name>
7440 <range>
7441 <first>0</first>
7442 <count>2</count>
7443 <formula variable="n">0x24 + 4*(n)</formula>
7444 </range>
7445 </instance>
7446 <register>
7447 <field>
7448 <name>BASE</name>
7449 <position>8</position>
7450 <width>8</width>
7451 </field>
7452 <field>
7453 <name>MASK</name>
7454 <position>0</position>
7455 <width>8</width>
7456 </field>
7457 </register>
7458 </node>
7459 <node>
7460 <name>DELAYCTRL</name>
7461 <instance>
7462 <name>DELAYCTRL</name>
7463 <address>0x2c</address>
7464 </instance>
7465 <register>
7466 <field>
7467 <name>TSEL</name>
7468 <desc>Ready delay select: adds betweee 0 and 3tCK</desc>
7469 <position>18</position>
7470 <width>2</width>
7471 </field>
7472 <field>
7473 <name>MSEL</name>
7474 <desc>Mask delay select: adds betweee 0 and 3tCK</desc>
7475 <position>16</position>
7476 <width>2</width>
7477 </field>
7478 <field>
7479 <name>HL</name>
7480 <desc>Half-clock delay: 1 adds 1/2tCK</desc>
7481 <position>15</position>
7482 </field>
7483 <field>
7484 <name>QUAR</name>
7485 <desc> Quarter clock delay select: 1 adds 1/4tCK</desc>
7486 <position>14</position>
7487 </field>
7488 <field>
7489 <name>MAUTO</name>
7490 <position>6</position>
7491 </field>
7492 <field>
7493 <name>MSIGN</name>
7494 <desc>Mask sign</desc>
7495 <position>5</position>
7496 </field>
7497 <field>
7498 <name>MASK_DELAY_SEL_ADJ</name>
7499 <position>0</position>
7500 <width>5</width>
7501 </field>
7502 </register>
7503 </node>
7504 <node>
7505 <name>DELAYCTRL2</name>
7506 <instance>
7507 <name>DELAYCTRL2</name>
7508 <address>0x30</address>
7509 </instance>
7510 <register>
7511 <field>
7512 <name>MASK_DELAY_SEL</name>
7513 <position>0</position>
7514 <width>5</width>
7515 </field>
7516 </register>
7517 </node>
7518 <node>
7519 <name>PADCTRL0</name>
7520 <title>Pad control 0</title>
7521 <instance>
7522 <name>PADCTRL0</name>
7523 <address>0x50</address>
7524 </instance>
7525 <register>
7526 <field>
7527 <name>PDDQS</name>
7528 <position>28</position>
7529 <width>4</width>
7530 </field>
7531 <field>
7532 <name>PDDQ</name>
7533 <position>24</position>
7534 <width>4</width>
7535 </field>
7536 <field>
7537 <name>SCHMITT_TRIGGER_DQS</name>
7538 <position>20</position>
7539 <width>4</width>
7540 </field>
7541 <field>
7542 <name>SCHMITT_TRIGGER_DQ</name>
7543 <position>16</position>
7544 <width>4</width>
7545 </field>
7546 <field>
7547 <name>ENPULL_DQS</name>
7548 <position>12</position>
7549 <width>4</width>
7550 </field>
7551 <field>
7552 <name>ENPULL_DQ</name>
7553 <position>8</position>
7554 <width>4</width>
7555 </field>
7556 <field>
7557 <name>PULLUP_DQS</name>
7558 <position>4</position>
7559 <width>4</width>
7560 </field>
7561 <field>
7562 <name>PULLUP_DQ</name>
7563 <position>0</position>
7564 <width>4</width>
7565 </field>
7566 </register>
7567 </node>
7568 <node>
7569 <name>PADCTRL1</name>
7570 <title>Pad Control 1</title>
7571 <instance>
7572 <name>PADCTRL1</name>
7573 <address>0x54</address>
7574 </instance>
7575 <register>
7576 <field>
7577 <name>INEDQS</name>
7578 <position>28</position>
7579 <width>4</width>
7580 </field>
7581 <field>
7582 <name>INEDQ</name>
7583 <position>24</position>
7584 <width>4</width>
7585 </field>
7586 <field>
7587 <name>SSTL_MODE</name>
7588 <position>16</position>
7589 </field>
7590 <field>
7591 <name>STRENGTH_DQS</name>
7592 <position>8</position>
7593 <width>8</width>
7594 <enum>
7595 <name>HALF_DDR1</name>
7596 <value>0x0</value>
7597 </enum>
7598 <enum>
7599 <name>HALF_MDDR</name>
7600 <value>0x0</value>
7601 </enum>
7602 <enum>
7603 <name>HALF_SDRAM_12MA</name>
7604 <value>0x0</value>
7605 </enum>
7606 <enum>
7607 <name>HALF_DDR2</name>
7608 <value>0x55</value>
7609 </enum>
7610 <enum>
7611 <name>HALF_SDRAM_16MA</name>
7612 <value>0x55</value>
7613 </enum>
7614 <enum>
7615 <name>FULL_DDR1</name>
7616 <value>0xaa</value>
7617 </enum>
7618 <enum>
7619 <name>FULL_SDRAM_24MA</name>
7620 <value>0xaa</value>
7621 </enum>
7622 <enum>
7623 <name>FULL_DDR2</name>
7624 <value>0xff</value>
7625 </enum>
7626 <enum>
7627 <name>FULL_MDDR</name>
7628 <value>0xff</value>
7629 </enum>
7630 <enum>
7631 <name>FULL_SDRAM_30MA</name>
7632 <value>0xff</value>
7633 </enum>
7634 </field>
7635 <field>
7636 <name>STRENGTH_DQ</name>
7637 <position>0</position>
7638 <width>8</width>
7639 <enum>
7640 <name>HALF_DDR1</name>
7641 <value>0x0</value>
7642 </enum>
7643 <enum>
7644 <name>HALF_MDDR</name>
7645 <value>0x0</value>
7646 </enum>
7647 <enum>
7648 <name>HALF_SDRAM_12MA</name>
7649 <value>0x0</value>
7650 </enum>
7651 <enum>
7652 <name>HALF_DDR2</name>
7653 <value>0x55</value>
7654 </enum>
7655 <enum>
7656 <name>HALF_SDRAM_16MA</name>
7657 <value>0x55</value>
7658 </enum>
7659 <enum>
7660 <name>FULL_DDR1</name>
7661 <value>0xaa</value>
7662 </enum>
7663 <enum>
7664 <name>FULL_SDRAM_24MA</name>
7665 <value>0xaa</value>
7666 </enum>
7667 <enum>
7668 <name>FULL_DDR2</name>
7669 <value>0xff</value>
7670 </enum>
7671 <enum>
7672 <name>FULL_MDDR</name>
7673 <value>0xff</value>
7674 </enum>
7675 <enum>
7676 <name>FULL_SDRAM_30MA</name>
7677 <value>0xff</value>
7678 </enum>
7679 </field>
7680 </register>
7681 </node>
7682 <node>
7683 <name>PADCTRL2</name>
7684 <title>Pad Control 2</title>
7685 <instance>
7686 <name>PADCTRL2</name>
7687 <address>0x58</address>
7688 </instance>
7689 <register>
7690 <field>
7691 <name>STRENGTH_CKO</name>
7692 <position>18</position>
7693 <width>2</width>
7694 </field>
7695 <field>
7696 <name>STRENGTH_CKE</name>
7697 <position>16</position>
7698 </field>
7699 <field>
7700 <name>STRENGTH_ADDR</name>
7701 <position>14</position>
7702 </field>
7703 <field>
7704 <name>STRENGTH_DM3</name>
7705 <position>12</position>
7706 </field>
7707 <field>
7708 <name>STRENGTH_DM2</name>
7709 <position>10</position>
7710 </field>
7711 <field>
7712 <name>STRENGTH_DM1</name>
7713 <position>8</position>
7714 </field>
7715 <field>
7716 <name>STRENGTH_DM0</name>
7717 <position>6</position>
7718 </field>
7719 <field>
7720 <name>STRENGTH_CMD</name>
7721 <position>4</position>
7722 </field>
7723 <field>
7724 <name>STRENGTH_CS1</name>
7725 <position>2</position>
7726 </field>
7727 <field>
7728 <name>STRENGTH_CS0</name>
7729 <position>0</position>
7730 </field>
7731 </register>
7732 </node>
7733 <node>
7734 <name>PADCTRL3</name>
7735 <title>Pad Control 3</title>
7736 <instance>
7737 <name>PADCTRL3</name>
7738 <address>0x5c</address>
7739 </instance>
7740 <register/>
7741 </node>
7742 </node>
7743 <node>
7744 <name>MDMAC</name>
7745 <title>Memory Copy DMAC</title>
7746 <instance>
7747 <name>MDMAC</name>
7748 <address>0xb3030000</address>
7749 </instance>
7750 <node>
7751 <name>CH_SOURCE</name>
7752 <title>DMA source address</title>
7753 <instance>
7754 <name>CH_SOURCE</name>
7755 <range>
7756 <first>0</first>
7757 <count>2</count>
7758 <formula variable="n">(0x00 + (n) * 0x20)</formula>
7759 </range>
7760 </instance>
7761 <register/>
7762 </node>
7763 <node>
7764 <name>CH_TARGET</name>
7765 <title>DMA target address</title>
7766 <instance>
7767 <name>CH_TARGET</name>
7768 <range>
7769 <first>0</first>
7770 <count>2</count>
7771 <formula variable="n">(0x04 + (n) * 0x20)</formula>
7772 </range>
7773 </instance>
7774 <register/>
7775 </node>
7776 <node>
7777 <name>CH_COUNT</name>
7778 <title>DMA transfer count</title>
7779 <desc> </desc>
7780 <instance>
7781 <name>CH_COUNT</name>
7782 <range>
7783 <first>0</first>
7784 <count>2</count>
7785 <formula variable="n">(0x08 + (n) * 0x20)</formula>
7786 </range>
7787 </instance>
7788 <register/>
7789 </node>
7790 <node>
7791 <name>CH_REQUEST</name>
7792 <title>DMA request source</title>
7793 <instance>
7794 <name>CH_REQUEST</name>
7795 <range>
7796 <first>0</first>
7797 <count>2</count>
7798 <formula variable="n">(0x0c + (n) * 0x20)</formula>
7799 </range>
7800 </instance>
7801 <register/>
7802 </node>
7803 <node>
7804 <name>CH_CTRL</name>
7805 <title>DMA control/status</title>
7806 <instance>
7807 <name>CH_CTRL</name>
7808 <range>
7809 <first>0</first>
7810 <count>2</count>
7811 <formula variable="n">(0x10 + (n) * 0x20)</formula>
7812 </range>
7813 </instance>
7814 <register/>
7815 </node>
7816 <node>
7817 <name>CH_CMD</name>
7818 <title>DMA command</title>
7819 <instance>
7820 <name>CH_CMD</name>
7821 <range>
7822 <first>0</first>
7823 <count>2</count>
7824 <formula variable="n">(0x14 + (n) * 0x20)</formula>
7825 </range>
7826 </instance>
7827 <register/>
7828 </node>
7829 <node>
7830 <name>CH_DESC</name>
7831 <title>DMA descriptor address</title>
7832 <instance>
7833 <name>CH_DESC</name>
7834 <range>
7835 <first>0</first>
7836 <count>2</count>
7837 <formula variable="n">(0x18 + (n) * 0x20)</formula>
7838 </range>
7839 </instance>
7840 <register/>
7841 </node>
7842 <node>
7843 <name>CH_STRIDE</name>
7844 <title>DMA Stride Address</title>
7845 <instance>
7846 <name>CH_STRIDE</name>
7847 <range>
7848 <first>0</first>
7849 <count>2</count>
7850 <formula variable="n">(0xc0 + (n) * 0x04)</formula>
7851 </range>
7852 </instance>
7853 <register/>
7854 </node>
7855 <node>
7856 <name>CTRL</name>
7857 <title>DMA control register</title>
7858 <instance>
7859 <name>DMACR</name>
7860 <address>0x300</address>
7861 </instance>
7862 <register/>
7863 </node>
7864 <node>
7865 <name>IRQ</name>
7866 <title>DMA interrupt pending</title>
7867 <instance>
7868 <name>IRQ</name>
7869 <address>0x304</address>
7870 </instance>
7871 <register/>
7872 </node>
7873 <node>
7874 <name>DOORBELL</name>
7875 <title>DMA doorbell</title>
7876 <instance>
7877 <name>DOORBELL</name>
7878 <address>0x308</address>
7879 </instance>
7880 <register>
7881 <variant>
7882 <type>set</type>
7883 <offset>4</offset>
7884 </variant>
7885 </register>
7886 </node>
7887 <node>
7888 <name>CLOCK</name>
7889 <instance>
7890 <name>CLOCK</name>
7891 <address>0x310</address>
7892 </instance>
7893 <register>
7894 <variant>
7895 <type>set</type>
7896 <offset>4</offset>
7897 </variant>
7898 <variant>
7899 <type>clr</type>
7900 <offset>0</offset>
7901 </variant>
7902 </register>
7903 </node>
7904 </node>
7905 <node>
7906 <name>EPD</name>
7907 <title>EPD</title>
7908 <instance>
7909 <name>EPD</name>
7910 <address>0xb3050000</address>
7911 </instance>
7912 <node>
7913 <name>CTRL</name>
7914 <instance>
7915 <name>CTRL</name>
7916 <address>0x200</address>
7917 </instance>
7918 <register>
7919 <field>
7920 <name>PPL7_FRM_INTM</name>
7921 <position>31</position>
7922 </field>
7923 <field>
7924 <name>PPL6_FRM_INTM</name>
7925 <position>30</position>
7926 </field>
7927 <field>
7928 <name>PPL5_FRM_INTM</name>
7929 <position>29</position>
7930 </field>
7931 <field>
7932 <name>PPL4_FRM_INTM</name>
7933 <position>28</position>
7934 </field>
7935 <field>
7936 <name>PPL3_FRM_INTM</name>
7937 <position>27</position>
7938 </field>
7939 <field>
7940 <name>PPL2_FRM_INTM</name>
7941 <position>26</position>
7942 </field>
7943 <field>
7944 <name>PPL1_FRM_INTM</name>
7945 <position>25</position>
7946 </field>
7947 <field>
7948 <name>PPL0_FRM_INTM</name>
7949 <position>24</position>
7950 </field>
7951 <field>
7952 <name>FRM_VCOM_INTM</name>
7953 <position>22</position>
7954 </field>
7955 <field>
7956 <name>IMG_DONE_INTM</name>
7957 <position>21</position>
7958 </field>
7959 <field>
7960 <name>FRM_DONE_INTM</name>
7961 <position>20</position>
7962 </field>
7963 <field>
7964 <name>FRM_ABT_INTM</name>
7965 <position>19</position>
7966 </field>
7967 <field>
7968 <name>PWR_OFF_INTM</name>
7969 <position>18</position>
7970 </field>
7971 <field>
7972 <name>PWR_ON_INTM</name>
7973 <position>17</position>
7974 </field>
7975 <field>
7976 <name>DMA_DONE_INTM</name>
7977 <position>16</position>
7978 </field>
7979 <field>
7980 <name>PPL7_FRM_ENA</name>
7981 <position>15</position>
7982 </field>
7983 <field>
7984 <name>PPL6_FRM_ENA</name>
7985 <position>14</position>
7986 </field>
7987 <field>
7988 <name>PPL5_FRM_ENA</name>
7989 <position>13</position>
7990 </field>
7991 <field>
7992 <name>PPL4_FRM_ENA</name>
7993 <position>12</position>
7994 </field>
7995 <field>
7996 <name>PPL3_FRM_ENA</name>
7997 <position>11</position>
7998 </field>
7999 <field>
8000 <name>PPL2_FRM_ENA</name>
8001 <position>10</position>
8002 </field>
8003 <field>
8004 <name>PPL1_FRM_ENA</name>
8005 <position>9</position>
8006 </field>
8007 <field>
8008 <name>PPL0_FRM_ENA</name>
8009 <position>8</position>
8010 </field>
8011 <field>
8012 <name>IMG_REF_ABT</name>
8013 <position>7</position>
8014 </field>
8015 <field>
8016 <name>IMG_REF_ENA</name>
8017 <position>6</position>
8018 </field>
8019 <field>
8020 <name>PWROFF</name>
8021 <position>5</position>
8022 </field>
8023 <field>
8024 <name>PWRON</name>
8025 <position>4</position>
8026 </field>
8027 <field>
8028 <name>EPD_DMA_MODE</name>
8029 <position>1</position>
8030 </field>
8031 <field>
8032 <name>EPD_ENA</name>
8033 <position>0</position>
8034 </field>
8035 </register>
8036 </node>
8037 <node>
8038 <name>STA</name>
8039 <instance>
8040 <name>STA</name>
8041 <address>0x204</address>
8042 </instance>
8043 <register/>
8044 </node>
8045 <node>
8046 <name>ISR</name>
8047 <instance>
8048 <name>ISR</name>
8049 <address>0x208</address>
8050 </instance>
8051 <register>
8052 <field>
8053 <name>PPL7_FRM_INT</name>
8054 <position>15</position>
8055 </field>
8056 <field>
8057 <name>PPL6_FRM_INT</name>
8058 <position>14</position>
8059 </field>
8060 <field>
8061 <name>PPL5_FRM_INT</name>
8062 <position>13</position>
8063 </field>
8064 <field>
8065 <name>PPL4_FRM_INT</name>
8066 <position>12</position>
8067 </field>
8068 <field>
8069 <name>PPL3_FRM_INT</name>
8070 <position>11</position>
8071 </field>
8072 <field>
8073 <name>PPL2_FRM_INT</name>
8074 <position>10</position>
8075 </field>
8076 <field>
8077 <name>PPL1_FRM_INT</name>
8078 <position>9</position>
8079 </field>
8080 <field>
8081 <name>PPL0_FRM_INT</name>
8082 <position>8</position>
8083 </field>
8084 <field>
8085 <name>FRM_VCOM_INT</name>
8086 <position>6</position>
8087 </field>
8088 <field>
8089 <name>IMG_DONE_INT</name>
8090 <position>5</position>
8091 </field>
8092 <field>
8093 <name>FRM_DONE_INT</name>
8094 <position>4</position>
8095 </field>
8096 <field>
8097 <name>FRM_ABT_INT</name>
8098 <position>3</position>
8099 </field>
8100 <field>
8101 <name>PWR_OFF_INT</name>
8102 <position>2</position>
8103 </field>
8104 <field>
8105 <name>PWR_ON_INT</name>
8106 <position>1</position>
8107 </field>
8108 <field>
8109 <name>DMA_DONE_INT</name>
8110 <position>0</position>
8111 </field>
8112 </register>
8113 </node>
8114 <node>
8115 <name>CFG0</name>
8116 <instance>
8117 <name>CFG0</name>
8118 <address>0x20c</address>
8119 </instance>
8120 <register>
8121 <field>
8122 <name>DUAL_GATE</name>
8123 <position>31</position>
8124 </field>
8125 <field>
8126 <name>COLOR_MODE</name>
8127 <position>30</position>
8128 </field>
8129 <field>
8130 <name>COLOR_FORMAT</name>
8131 <position>27</position>
8132 <width>3</width>
8133 </field>
8134 <field>
8135 <name>SDSP_CAS</name>
8136 <position>26</position>
8137 </field>
8138 <field>
8139 <name>SDSP_MODE</name>
8140 <position>25</position>
8141 </field>
8142 <field>
8143 <name>GDCLK_MODE</name>
8144 <position>24</position>
8145 </field>
8146 <field>
8147 <name>GDOE_MODE</name>
8148 <position>22</position>
8149 <width>2</width>
8150 </field>
8151 <field>
8152 <name>GDUD</name>
8153 <position>21</position>
8154 </field>
8155 <field>
8156 <name>SDRL</name>
8157 <position>20</position>
8158 </field>
8159 <field>
8160 <name>GDCLK_POL</name>
8161 <position>19</position>
8162 </field>
8163 <field>
8164 <name>GDOE_POL</name>
8165 <position>18</position>
8166 </field>
8167 <field>
8168 <name>GDSP_POL</name>
8169 <position>17</position>
8170 </field>
8171 <field>
8172 <name>SDCLK_POL</name>
8173 <position>16</position>
8174 </field>
8175 <field>
8176 <name>SDOE_POL</name>
8177 <position>15</position>
8178 </field>
8179 <field>
8180 <name>SDSP_POL</name>
8181 <position>14</position>
8182 </field>
8183 <field>
8184 <name>SDCE_POL</name>
8185 <position>13</position>
8186 </field>
8187 <field>
8188 <name>SDLE_POL</name>
8189 <position>12</position>
8190 </field>
8191 <field>
8192 <name>GDSP_CAS</name>
8193 <position>9</position>
8194 </field>
8195 <field>
8196 <name>COMP_MODE</name>
8197 <position>8</position>
8198 </field>
8199 <field>
8200 <name>EPD_OBPP</name>
8201 <position>1</position>
8202 <width>3</width>
8203 </field>
8204 <field>
8205 <name>EPD_OMODE</name>
8206 <position>0</position>
8207 </field>
8208 </register>
8209 </node>
8210 <node>
8211 <name>CFG1</name>
8212 <instance>
8213 <name>CFG1</name>
8214 <address>0x210</address>
8215 </instance>
8216 <register>
8217 <field>
8218 <name>SDDO_REV</name>
8219 <position>30</position>
8220 </field>
8221 <field>
8222 <name>PDAT_SWAP</name>
8223 <position>29</position>
8224 </field>
8225 <field>
8226 <name>SDCE_REV</name>
8227 <position>28</position>
8228 </field>
8229 <field>
8230 <name>SDOS</name>
8231 <position>16</position>
8232 <width>8</width>
8233 </field>
8234 <field>
8235 <name>PADDING_DAT</name>
8236 <position>8</position>
8237 <width>8</width>
8238 </field>
8239 <field>
8240 <name>SDCE_STN</name>
8241 <position>4</position>
8242 <width>4</width>
8243 </field>
8244 <field>
8245 <name>SDCE_NUM</name>
8246 <position>0</position>
8247 <width>4</width>
8248 </field>
8249 </register>
8250 </node>
8251 <node>
8252 <name>PPL0</name>
8253 <instance>
8254 <name>PPL0</name>
8255 <address>0x214</address>
8256 </instance>
8257 <register>
8258 <field>
8259 <name>PPL3_FRM_NUM</name>
8260 <position>24</position>
8261 <width>8</width>
8262 </field>
8263 <field>
8264 <name>PPL2_FRM_NUM</name>
8265 <position>16</position>
8266 <width>8</width>
8267 </field>
8268 <field>
8269 <name>PPL1_FRM_NUM</name>
8270 <position>8</position>
8271 <width>8</width>
8272 </field>
8273 <field>
8274 <name>PPL0_FRM_NUM</name>
8275 <position>0</position>
8276 <width>8</width>
8277 </field>
8278 </register>
8279 </node>
8280 <node>
8281 <name>PPL1</name>
8282 <instance>
8283 <name>PPL1</name>
8284 <address>0x218</address>
8285 </instance>
8286 <register>
8287 <field>
8288 <name>PPL7_FRM_NUM</name>
8289 <position>24</position>
8290 <width>8</width>
8291 </field>
8292 <field>
8293 <name>PPL6_FRM_NUM</name>
8294 <position>16</position>
8295 <width>8</width>
8296 </field>
8297 <field>
8298 <name>PPL5_FRM_NUM</name>
8299 <position>8</position>
8300 <width>8</width>
8301 </field>
8302 <field>
8303 <name>PPL4_FRM_NUM</name>
8304 <position>0</position>
8305 <width>8</width>
8306 </field>
8307 </register>
8308 </node>
8309 <node>
8310 <name>VAT</name>
8311 <instance>
8312 <name>VAT</name>
8313 <address>0x21c</address>
8314 </instance>
8315 <register>
8316 <field>
8317 <name>VT</name>
8318 <position>16</position>
8319 <width>12</width>
8320 </field>
8321 <field>
8322 <name>HT</name>
8323 <position>0</position>
8324 <width>12</width>
8325 </field>
8326 </register>
8327 </node>
8328 <node>
8329 <name>DAV</name>
8330 <instance>
8331 <name>DAV</name>
8332 <address>0x220</address>
8333 </instance>
8334 <register>
8335 <field>
8336 <name>VDE</name>
8337 <position>16</position>
8338 <width>12</width>
8339 </field>
8340 <field>
8341 <name>VDS</name>
8342 <position>0</position>
8343 <width>12</width>
8344 </field>
8345 </register>
8346 </node>
8347 <node>
8348 <name>DAH</name>
8349 <instance>
8350 <name>DAH</name>
8351 <address>0x224</address>
8352 </instance>
8353 <register>
8354 <field>
8355 <name>HDE</name>
8356 <position>16</position>
8357 <width>12</width>
8358 </field>
8359 <field>
8360 <name>HDS</name>
8361 <position>0</position>
8362 <width>12</width>
8363 </field>
8364 </register>
8365 </node>
8366 <node>
8367 <name>VSYNC</name>
8368 <instance>
8369 <name>VSYNC</name>
8370 <address>0x228</address>
8371 </instance>
8372 <register>
8373 <field>
8374 <name>VPE</name>
8375 <position>16</position>
8376 <width>12</width>
8377 </field>
8378 <field>
8379 <name>VPS</name>
8380 <position>0</position>
8381 <width>12</width>
8382 </field>
8383 </register>
8384 </node>
8385 <node>
8386 <name>HSYNC</name>
8387 <instance>
8388 <name>HSYNC</name>
8389 <address>0x22c</address>
8390 </instance>
8391 <register>
8392 <field>
8393 <name>HPE</name>
8394 <position>16</position>
8395 <width>12</width>
8396 </field>
8397 <field>
8398 <name>HPS</name>
8399 <position>0</position>
8400 <width>12</width>
8401 </field>
8402 </register>
8403 </node>
8404 <node>
8405 <name>GDCLK</name>
8406 <instance>
8407 <name>GDCLK</name>
8408 <address>0x230</address>
8409 </instance>
8410 <register>
8411 <field>
8412 <name>DIS</name>
8413 <position>16</position>
8414 <width>12</width>
8415 </field>
8416 <field>
8417 <name>ENA</name>
8418 <position>0</position>
8419 <width>12</width>
8420 </field>
8421 </register>
8422 </node>
8423 <node>
8424 <name>GDOE</name>
8425 <instance>
8426 <name>GDOE</name>
8427 <address>0x234</address>
8428 </instance>
8429 <register>
8430 <field>
8431 <name>DIS</name>
8432 <position>16</position>
8433 <width>12</width>
8434 </field>
8435 <field>
8436 <name>ENA</name>
8437 <position>0</position>
8438 <width>12</width>
8439 </field>
8440 </register>
8441 </node>
8442 <node>
8443 <name>GDSP</name>
8444 <instance>
8445 <name>GDSP</name>
8446 <address>0x238</address>
8447 </instance>
8448 <register>
8449 <field>
8450 <name>DIS</name>
8451 <position>16</position>
8452 <width>12</width>
8453 </field>
8454 <field>
8455 <name>ENA</name>
8456 <position>0</position>
8457 <width>12</width>
8458 </field>
8459 </register>
8460 </node>
8461 <node>
8462 <name>SDOE</name>
8463 <instance>
8464 <name>SDOE</name>
8465 <address>0x23c</address>
8466 </instance>
8467 <register>
8468 <field>
8469 <name>DIS</name>
8470 <position>16</position>
8471 <width>12</width>
8472 </field>
8473 <field>
8474 <name>ENA</name>
8475 <position>0</position>
8476 <width>12</width>
8477 </field>
8478 </register>
8479 </node>
8480 <node>
8481 <name>SDSP</name>
8482 <instance>
8483 <name>SDSP</name>
8484 <address>0x240</address>
8485 </instance>
8486 <register>
8487 <field>
8488 <name>DIS</name>
8489 <position>16</position>
8490 <width>12</width>
8491 </field>
8492 <field>
8493 <name>ENA</name>
8494 <position>0</position>
8495 <width>12</width>
8496 </field>
8497 </register>
8498 </node>
8499 <node>
8500 <name>PMGR0</name>
8501 <instance>
8502 <name>PMGR0</name>
8503 <address>0x244</address>
8504 </instance>
8505 <register>
8506 <field>
8507 <name>PWR_DLY12</name>
8508 <position>16</position>
8509 <width>12</width>
8510 </field>
8511 <field>
8512 <name>PWR_DLY01</name>
8513 <position>0</position>
8514 <width>12</width>
8515 </field>
8516 </register>
8517 </node>
8518 <node>
8519 <name>PMGR1</name>
8520 <instance>
8521 <name>PMGR1</name>
8522 <address>0x248</address>
8523 </instance>
8524 <register>
8525 <field>
8526 <name>PWR_DLY34</name>
8527 <position>16</position>
8528 <width>12</width>
8529 </field>
8530 <field>
8531 <name>PWR_DLY23</name>
8532 <position>0</position>
8533 <width>12</width>
8534 </field>
8535 </register>
8536 </node>
8537 <node>
8538 <name>PMGR2</name>
8539 <instance>
8540 <name>PMGR2</name>
8541 <address>0x24c</address>
8542 </instance>
8543 <register>
8544 <field>
8545 <name>PWR_DLY56</name>
8546 <position>16</position>
8547 <width>12</width>
8548 </field>
8549 <field>
8550 <name>PWR_DLY45</name>
8551 <position>0</position>
8552 <width>12</width>
8553 </field>
8554 </register>
8555 </node>
8556 <node>
8557 <name>PMGR3</name>
8558 <instance>
8559 <name>PMGR3</name>
8560 <address>0x250</address>
8561 </instance>
8562 <register>
8563 <field>
8564 <name>VCOM_IDLE</name>
8565 <position>30</position>
8566 <width>2</width>
8567 </field>
8568 <field>
8569 <name>PWRCOM_POL</name>
8570 <position>29</position>
8571 </field>
8572 <field>
8573 <name>UNI_POL</name>
8574 <position>28</position>
8575 </field>
8576 <field>
8577 <name>PPL7_BDR_ENA</name>
8578 <position>27</position>
8579 </field>
8580 <field>
8581 <name>BDR_LEVEL</name>
8582 <position>26</position>
8583 </field>
8584 <field>
8585 <name>BDR_VALUE</name>
8586 <position>24</position>
8587 <width>2</width>
8588 </field>
8589 <field>
8590 <name>PWR_POL</name>
8591 <position>16</position>
8592 <width>8</width>
8593 </field>
8594 <field>
8595 <name>PWR_DLY67</name>
8596 <position>0</position>
8597 <width>12</width>
8598 </field>
8599 </register>
8600 </node>
8601 <node>
8602 <name>PMGR4</name>
8603 <instance>
8604 <name>PMGR4</name>
8605 <address>0x254</address>
8606 </instance>
8607 <register>
8608 <field>
8609 <name>PWR_VAL</name>
8610 <position>16</position>
8611 <width>8</width>
8612 </field>
8613 <field>
8614 <name>PWR_ENA</name>
8615 <position>0</position>
8616 <width>8</width>
8617 </field>
8618 </register>
8619 </node>
8620 <node>
8621 <name>VCOM0</name>
8622 <instance>
8623 <name>VCOM0</name>
8624 <address>0x258</address>
8625 </instance>
8626 <register/>
8627 </node>
8628 <node>
8629 <name>VCOM1</name>
8630 <instance>
8631 <name>VCOM1</name>
8632 <address>0x25c</address>
8633 </instance>
8634 <register/>
8635 </node>
8636 <node>
8637 <name>VCOM2</name>
8638 <instance>
8639 <name>VCOM2</name>
8640 <address>0x260</address>
8641 </instance>
8642 <register/>
8643 </node>
8644 <node>
8645 <name>VCOM3</name>
8646 <instance>
8647 <name>VCOM3</name>
8648 <address>0x264</address>
8649 </instance>
8650 <register/>
8651 </node>
8652 <node>
8653 <name>VCOM4</name>
8654 <instance>
8655 <name>VCOM4</name>
8656 <address>0x268</address>
8657 </instance>
8658 <register/>
8659 </node>
8660 <node>
8661 <name>VCOM5</name>
8662 <instance>
8663 <name>VCOM5</name>
8664 <address>0x26c</address>
8665 </instance>
8666 <register/>
8667 </node>
8668 <node>
8669 <name>BORDR</name>
8670 <instance>
8671 <name>BORDR</name>
8672 <address>0x270</address>
8673 </instance>
8674 <register/>
8675 </node>
8676 <node>
8677 <name>PPL_POS</name>
8678 <instance>
8679 <name>PPL_POS</name>
8680 <range>
8681 <first>0</first>
8682 <address>0x280</address>
8683 <address>0x288</address>
8684 <address>0x290</address>
8685 <address>0x298</address>
8686 <address>0x2a0</address>
8687 <address>0x2a8</address>
8688 <address>0x2b0</address>
8689 <address>0x2b8</address>
8690 </range>
8691 </instance>
8692 <register>
8693 <field>
8694 <name>PPL_YPOS</name>
8695 <position>16</position>
8696 <width>12</width>
8697 </field>
8698 <field>
8699 <name>PPL_XPOS</name>
8700 <position>0</position>
8701 <width>12</width>
8702 </field>
8703 </register>
8704 </node>
8705 <node>
8706 <name>PPL_SIZE</name>
8707 <instance>
8708 <name>PPL_SIZE</name>
8709 <range>
8710 <first>1</first>
8711 <address>0x28c</address>
8712 <address>0x294</address>
8713 <address>0x29c</address>
8714 <address>0x2a4</address>
8715 <address>0x2ac</address>
8716 <address>0x2b4</address>
8717 <address>0x2bc</address>
8718 </range>
8719 </instance>
8720 <register>
8721 <field>
8722 <name>PPL_HEIGHT</name>
8723 <position>16</position>
8724 <width>12</width>
8725 </field>
8726 <field>
8727 <name>PPL_WIDTH</name>
8728 <position>0</position>
8729 <width>12</width>
8730 </field>
8731 </register>
8732 </node>
8733 </node>
8734 <node>
8735 <name>LCD</name>
8736 <title>LCD (LCD Controller)</title>
8737 <instance>
8738 <name>LCD</name>
8739 <address>0xb3050000</address>
8740 </instance>
8741 <node>
8742 <name>CFG</name>
8743 <title>LCD Configure Register</title>
8744 <instance>
8745 <name>CFG</name>
8746 <address>0x0</address>
8747 </instance>
8748 <register>
8749 <field>
8750 <name>LCDPIN</name>
8751 <desc>LCD pins selection</desc>
8752 <position>31</position>
8753 <enum>
8754 <name>LCD</name>
8755 <value>0x0</value>
8756 </enum>
8757 <enum>
8758 <name>SLCD</name>
8759 <value>0x1</value>
8760 </enum>
8761 </field>
8762 <field>
8763 <name>TVEPEH</name>
8764 <desc>TVE PAL enable extra halfline signal</desc>
8765 <position>30</position>
8766 </field>
8767 <field>
8768 <name>FUHOLD</name>
8769 <desc>hold pixel clock when outFIFO underrun</desc>
8770 <position>29</position>
8771 </field>
8772 <field>
8773 <name>NEWDES</name>
8774 <desc>use new descripter. old: 4words, new:8words</desc>
8775 <position>28</position>
8776 </field>
8777 <field>
8778 <name>PALBP</name>
8779 <desc>bypass data format and alpha blending</desc>
8780 <position>27</position>
8781 </field>
8782 <field>
8783 <name>TVEN</name>
8784 <desc>indicate the terminal is lcd or tv</desc>
8785 <position>26</position>
8786 </field>
8787 <field>
8788 <name>RECOVER</name>
8789 <desc>Auto recover when output fifo underrun</desc>
8790 <position>25</position>
8791 </field>
8792 <field>
8793 <name>DITHER</name>
8794 <desc>Dither function</desc>
8795 <position>24</position>
8796 </field>
8797 <field>
8798 <name>PSM</name>
8799 <desc>PS signal mode</desc>
8800 <position>23</position>
8801 </field>
8802 <field>
8803 <name>CLSM</name>
8804 <desc>CLS signal mode</desc>
8805 <position>22</position>
8806 </field>
8807 <field>
8808 <name>SPLM</name>
8809 <desc>SPL signal mode</desc>
8810 <position>21</position>
8811 </field>
8812 <field>
8813 <name>REVM</name>
8814 <desc>REV signal mode</desc>
8815 <position>20</position>
8816 </field>
8817 <field>
8818 <name>HSYNM</name>
8819 <desc>HSYNC signal mode</desc>
8820 <position>19</position>
8821 </field>
8822 <field>
8823 <name>PCLKM</name>
8824 <desc>PCLK signal mode</desc>
8825 <position>18</position>
8826 </field>
8827 <field>
8828 <name>INVDAT</name>
8829 <desc>Inverse output data</desc>
8830 <position>17</position>
8831 </field>
8832 <field>
8833 <name>SYNDIR_IN</name>
8834 <desc>VSYNC&amp;HSYNC direction</desc>
8835 <position>16</position>
8836 </field>
8837 <field>
8838 <name>PSP</name>
8839 <desc>PS pin reset state</desc>
8840 <position>15</position>
8841 </field>
8842 <field>
8843 <name>CLSP</name>
8844 <desc>CLS pin reset state</desc>
8845 <position>14</position>
8846 </field>
8847 <field>
8848 <name>SPLP</name>
8849 <desc>SPL pin reset state</desc>
8850 <position>13</position>
8851 </field>
8852 <field>
8853 <name>REVP</name>
8854 <desc>REV pin reset state</desc>
8855 <position>12</position>
8856 </field>
8857 <field>
8858 <name>HSP</name>
8859 <desc>HSYNC polarity:0-active high,1-active low</desc>
8860 <position>11</position>
8861 </field>
8862 <field>
8863 <name>PCP</name>
8864 <desc>PCLK polarity:0-rising,1-falling</desc>
8865 <position>10</position>
8866 </field>
8867 <field>
8868 <name>DEP</name>
8869 <desc>DE polarity:0-active high,1-active low</desc>
8870 <position>9</position>
8871 </field>
8872 <field>
8873 <name>VSP</name>
8874 <desc>VSYNC polarity:0-rising,1-falling</desc>
8875 <position>8</position>
8876 </field>
8877 <field>
8878 <name>MODE_TFT_18BIT</name>
8879 <desc>18bit TFT</desc>
8880 <position>7</position>
8881 </field>
8882 <field>
8883 <name>MODE_TFT_24BIT</name>
8884 <desc>24bit TFT</desc>
8885 <position>6</position>
8886 </field>
8887 <field>
8888 <name>PDW</name>
8889 <desc>LCD_D[0:7]/LCD_D[8:15]</desc>
8890 <position>4</position>
8891 <width>2</width>
8892 <enum>
8893 <name>1</name>
8894 <value>0x0</value>
8895 </enum>
8896 <enum>
8897 <name>2</name>
8898 <value>0x1</value>
8899 </enum>
8900 <enum>
8901 <name>4</name>
8902 <value>0x2</value>
8903 </enum>
8904 <enum>
8905 <name>8</name>
8906 <value>0x3</value>
8907 </enum>
8908 </field>
8909 <field>
8910 <name>MODE</name>
8911 <desc>16,18 bit TFT</desc>
8912 <position>0</position>
8913 <width>4</width>
8914 <enum>
8915 <name>GENERIC_TFT</name>
8916 <value>0x0</value>
8917 </enum>
8918 <enum>
8919 <name>SPECIAL_TFT_1</name>
8920 <value>0x1</value>
8921 </enum>
8922 <enum>
8923 <name>SPECIAL_TFT_2</name>
8924 <value>0x2</value>
8925 </enum>
8926 <enum>
8927 <name>SPECIAL_TFT_3</name>
8928 <value>0x3</value>
8929 </enum>
8930 <enum>
8931 <name>NONINTER_CCIR656</name>
8932 <value>0x4</value>
8933 </enum>
8934 <enum>
8935 <name>INTER_CCIR656</name>
8936 <value>0x6</value>
8937 </enum>
8938 <enum>
8939 <name>SINGLE_CSTN</name>
8940 <value>0x8</value>
8941 </enum>
8942 <enum>
8943 <name>SINGLE_MSTN</name>
8944 <value>0x9</value>
8945 </enum>
8946 <enum>
8947 <name>DUAL_CSTN</name>
8948 <value>0xa</value>
8949 </enum>
8950 <enum>
8951 <name>DUAL_MSTN</name>
8952 <value>0xb</value>
8953 </enum>
8954 <enum>
8955 <name>SERIAL_TFT</name>
8956 <value>0xc</value>
8957 </enum>
8958 <enum>
8959 <name>LCM</name>
8960 <value>0xd</value>
8961 </enum>
8962 </field>
8963 </register>
8964 </node>
8965 <node>
8966 <name>VSYNC</name>
8967 <title>Vertical Synchronize Register</title>
8968 <instance>
8969 <name>VSYNC</name>
8970 <address>0x4</address>
8971 </instance>
8972 <register>
8973 <field>
8974 <name>VPS</name>
8975 <desc>VSYNC pulse start in line clock, fixed to 0</desc>
8976 <position>16</position>
8977 <width>16</width>
8978 </field>
8979 <field>
8980 <name>VPE</name>
8981 <desc>VSYNC pulse end in line clock</desc>
8982 <position>0</position>
8983 <width>16</width>
8984 </field>
8985 </register>
8986 </node>
8987 <node>
8988 <name>HSYNC</name>
8989 <title>Horizontal Synchronize Register</title>
8990 <instance>
8991 <name>HSYNC</name>
8992 <address>0x8</address>
8993 </instance>
8994 <register>
8995 <field>
8996 <name>HPS</name>
8997 <desc>HSYNC pulse start position in dot clock</desc>
8998 <position>16</position>
8999 <width>16</width>
9000 </field>
9001 <field>
9002 <name>HPE</name>
9003 <desc>HSYNC pulse end position in dot clock</desc>
9004 <position>0</position>
9005 <width>16</width>
9006 </field>
9007 </register>
9008 </node>
9009 <node>
9010 <name>VAT</name>
9011 <title>Virtual Area Setting Register</title>
9012 <instance>
9013 <name>VAT</name>
9014 <address>0xc</address>
9015 </instance>
9016 <register>
9017 <field>
9018 <name>HT</name>
9019 <desc>Horizontal Total size in dot clock</desc>
9020 <position>16</position>
9021 <width>16</width>
9022 </field>
9023 <field>
9024 <name>VT</name>
9025 <desc>Vertical Total size in dot clock</desc>
9026 <position>0</position>
9027 <width>16</width>
9028 </field>
9029 </register>
9030 </node>
9031 <node>
9032 <name>DAH</name>
9033 <title>Display Area Horizontal Start/End Point</title>
9034 <instance>
9035 <name>DAH</name>
9036 <address>0x10</address>
9037 </instance>
9038 <register>
9039 <field>
9040 <name>HDS</name>
9041 <desc>Horizontal display area start in dot clock</desc>
9042 <position>16</position>
9043 <width>16</width>
9044 </field>
9045 <field>
9046 <name>HDE</name>
9047 <desc>Horizontal display area end in dot clock</desc>
9048 <position>0</position>
9049 <width>16</width>
9050 </field>
9051 </register>
9052 </node>
9053 <node>
9054 <name>DAV</name>
9055 <title>Display Area Vertical Start/End Point</title>
9056 <instance>
9057 <name>DAV</name>
9058 <address>0x14</address>
9059 </instance>
9060 <register>
9061 <field>
9062 <name>VDS</name>
9063 <desc>Vertical display area start in line clock</desc>
9064 <position>16</position>
9065 <width>16</width>
9066 </field>
9067 <field>
9068 <name>VDE</name>
9069 <desc>Vertical display area end in line clock</desc>
9070 <position>0</position>
9071 <width>16</width>
9072 </field>
9073 </register>
9074 </node>
9075 <node>
9076 <name>PS</name>
9077 <title>PS Signal Setting</title>
9078 <instance>
9079 <name>PS</name>
9080 <address>0x18</address>
9081 </instance>
9082 <register>
9083 <field>
9084 <name>PSS</name>
9085 <desc>PS signal start position in dot clock</desc>
9086 <position>16</position>
9087 <width>16</width>
9088 </field>
9089 <field>
9090 <name>PSE</name>
9091 <desc>PS signal end position in dot clock</desc>
9092 <position>0</position>
9093 <width>16</width>
9094 </field>
9095 </register>
9096 </node>
9097 <node>
9098 <name>CLS</name>
9099 <title>CLS Signal Setting</title>
9100 <instance>
9101 <name>CLS</name>
9102 <address>0x1c</address>
9103 </instance>
9104 <register>
9105 <field>
9106 <name>CLSS</name>
9107 <desc>CLS signal start position in dot clock</desc>
9108 <position>16</position>
9109 <width>16</width>
9110 </field>
9111 <field>
9112 <name>CLSE</name>
9113 <desc>CLS signal end position in dot clock</desc>
9114 <position>0</position>
9115 <width>16</width>
9116 </field>
9117 </register>
9118 </node>
9119 <node>
9120 <name>SPL</name>
9121 <title>SPL Signal Setting</title>
9122 <instance>
9123 <name>SPL</name>
9124 <address>0x20</address>
9125 </instance>
9126 <register>
9127 <field>
9128 <name>SPLS</name>
9129 <desc>SPL signal start position in dot clock</desc>
9130 <position>16</position>
9131 <width>16</width>
9132 </field>
9133 <field>
9134 <name>SPLE</name>
9135 <desc>SPL signal end position in dot clock</desc>
9136 <position>0</position>
9137 <width>16</width>
9138 </field>
9139 </register>
9140 </node>
9141 <node>
9142 <name>REV</name>
9143 <title>REV Signal Setting</title>
9144 <instance>
9145 <name>REV</name>
9146 <address>0x24</address>
9147 </instance>
9148 <register>
9149 <field>
9150 <name>REVS</name>
9151 <desc>REV signal start position in dot clock</desc>
9152 <position>16</position>
9153 <width>16</width>
9154 </field>
9155 </register>
9156 </node>
9157 <node>
9158 <name>CTRL</name>
9159 <title>LCD Control Register</title>
9160 <instance>
9161 <name>CTRL</name>
9162 <address>0x30</address>
9163 </instance>
9164 <register>
9165 <field>
9166 <name>PINMD</name>
9167 <desc>This register set Pin distribution in 16-bit parallel mode, 0: 16-bit data correspond with LCD_D[15:0], 1: 16-bit data correspond with LCD_D[17:10], LCD_D[8:1]</desc>
9168 <position>31</position>
9169 </field>
9170 <field>
9171 <name>BST</name>
9172 <desc>16-word contiue</desc>
9173 <position>28</position>
9174 <width>3</width>
9175 <enum>
9176 <name>4</name>
9177 <value>0x0</value>
9178 </enum>
9179 <enum>
9180 <name>8</name>
9181 <value>0x1</value>
9182 </enum>
9183 <enum>
9184 <name>16</name>
9185 <value>0x2</value>
9186 </enum>
9187 <enum>
9188 <name>32</name>
9189 <value>0x3</value>
9190 </enum>
9191 <enum>
9192 <name>64</name>
9193 <value>0x4</value>
9194 </enum>
9195 <enum>
9196 <name>16_CTN</name>
9197 <value>0x5</value>
9198 </enum>
9199 <enum>
9200 <name>C16</name>
9201 <value>0x5</value>
9202 </enum>
9203 </field>
9204 <field>
9205 <name>RGB555</name>
9206 <desc>RGB555 mode(foreground 0 in OSD mode)</desc>
9207 <position>27</position>
9208 </field>
9209 <field>
9210 <name>OFUP</name>
9211 <desc>Output FIFO underrun protection enable</desc>
9212 <position>26</position>
9213 </field>
9214 <field>
9215 <name>FRC</name>
9216 <desc>2 grayscale</desc>
9217 <position>24</position>
9218 <width>2</width>
9219 <enum>
9220 <name>16</name>
9221 <value>0x0</value>
9222 </enum>
9223 <enum>
9224 <name>4</name>
9225 <value>0x1</value>
9226 </enum>
9227 <enum>
9228 <name>2</name>
9229 <value>0x2</value>
9230 </enum>
9231 </field>
9232 <field>
9233 <name>PDD</name>
9234 <desc>Load Palette Delay Counter</desc>
9235 <position>16</position>
9236 <width>8</width>
9237 </field>
9238 <field>
9239 <name>EOFM</name>
9240 <desc>EOF interrupt mask</desc>
9241 <position>13</position>
9242 </field>
9243 <field>
9244 <name>SOFM</name>
9245 <desc>SOF interrupt mask</desc>
9246 <position>12</position>
9247 </field>
9248 <field>
9249 <name>OFUM</name>
9250 <desc>Output FIFO underrun interrupt mask</desc>
9251 <position>11</position>
9252 </field>
9253 <field>
9254 <name>IFUM0</name>
9255 <desc>Input FIFO 0 underrun interrupt mask</desc>
9256 <position>10</position>
9257 </field>
9258 <field>
9259 <name>IFUM1</name>
9260 <desc>Input FIFO 1 underrun interrupt mask</desc>
9261 <position>9</position>
9262 </field>
9263 <field>
9264 <name>LDDM</name>
9265 <desc>LCD disable done interrupt mask</desc>
9266 <position>8</position>
9267 </field>
9268 <field>
9269 <name>QDM</name>
9270 <desc>LCD quick disable done interrupt mask</desc>
9271 <position>7</position>
9272 </field>
9273 <field>
9274 <name>BEDN</name>
9275 <desc>Endian selection</desc>
9276 <position>6</position>
9277 </field>
9278 <field>
9279 <name>PEDN</name>
9280 <desc>Endian in byte:0-msb first, 1-lsb first</desc>
9281 <position>5</position>
9282 </field>
9283 <field>
9284 <name>DIS</name>
9285 <desc>Disable indicate bit</desc>
9286 <position>4</position>
9287 </field>
9288 <field>
9289 <name>ENA</name>
9290 <desc>LCD enable bit</desc>
9291 <position>3</position>
9292 </field>
9293 <field>
9294 <name>BPP</name>
9295 <desc>30 bpp</desc>
9296 <position>0</position>
9297 <width>3</width>
9298 <enum>
9299 <name>1</name>
9300 <value>0x0</value>
9301 </enum>
9302 <enum>
9303 <name>2</name>
9304 <value>0x1</value>
9305 </enum>
9306 <enum>
9307 <name>4</name>
9308 <value>0x2</value>
9309 </enum>
9310 <enum>
9311 <name>8</name>
9312 <value>0x3</value>
9313 </enum>
9314 <enum>
9315 <name>16</name>
9316 <value>0x4</value>
9317 </enum>
9318 <enum>
9319 <name>18_24</name>
9320 <value>0x5</value>
9321 </enum>
9322 <enum>
9323 <name>CMPS_24</name>
9324 <value>0x6</value>
9325 </enum>
9326 <enum>
9327 <name>30</name>
9328 <value>0x7</value>
9329 </enum>
9330 </field>
9331 </register>
9332 </node>
9333 <node>
9334 <name>STATE</name>
9335 <title>LCD Status Register</title>
9336 <instance>
9337 <name>STATE</name>
9338 <address>0x34</address>
9339 </instance>
9340 <register>
9341 <field>
9342 <name>FEND</name>
9343 <position>22</position>
9344 </field>
9345 <field>
9346 <name>PWRUP</name>
9347 <position>20</position>
9348 </field>
9349 <field>
9350 <name>PWRDN</name>
9351 <position>19</position>
9352 </field>
9353 <field>
9354 <name>QD</name>
9355 <desc>Quick Disable Done</desc>
9356 <position>7</position>
9357 </field>
9358 <field>
9359 <name>EOF</name>
9360 <desc>EOF Flag</desc>
9361 <position>5</position>
9362 </field>
9363 <field>
9364 <name>SOF</name>
9365 <desc>SOF Flag</desc>
9366 <position>4</position>
9367 </field>
9368 <field>
9369 <name>OFU</name>
9370 <desc>Output FIFO Underrun</desc>
9371 <position>3</position>
9372 </field>
9373 <field>
9374 <name>IFU0</name>
9375 <desc>Input FIFO 0 Underrun</desc>
9376 <position>2</position>
9377 </field>
9378 <field>
9379 <name>IFU1</name>
9380 <desc>Input FIFO 1 Underrun</desc>
9381 <position>1</position>
9382 </field>
9383 <field>
9384 <name>LDD</name>
9385 <desc>LCD Disabled</desc>
9386 <position>0</position>
9387 </field>
9388 </register>
9389 </node>
9390 <node>
9391 <name>IID</name>
9392 <title>Interrupt ID Register</title>
9393 <instance>
9394 <name>IID</name>
9395 <address>0x38</address>
9396 </instance>
9397 <register/>
9398 </node>
9399 <node>
9400 <name>DA</name>
9401 <title>Descriptor Address Register 1</title>
9402 <instance>
9403 <name>DA</name>
9404 <range>
9405 <first>0</first>
9406 <address>0x40</address>
9407 <address>0x50</address>
9408 </range>
9409 </instance>
9410 <register/>
9411 </node>
9412 <node>
9413 <name>SA</name>
9414 <title>Source Address Register 1</title>
9415 <instance>
9416 <name>SA</name>
9417 <range>
9418 <first>0</first>
9419 <address>0x44</address>
9420 <address>0x54</address>
9421 </range>
9422 </instance>
9423 <register/>
9424 </node>
9425 <node>
9426 <name>FID</name>
9427 <title>Frame ID Register 1</title>
9428 <instance>
9429 <name>FID</name>
9430 <range>
9431 <first>0</first>
9432 <address>0x48</address>
9433 <address>0x58</address>
9434 </range>
9435 </instance>
9436 <register/>
9437 </node>
9438 <node>
9439 <name>CMD</name>
9440 <title>DMA Command Register 1</title>
9441 <instance>
9442 <name>CMD</name>
9443 <range>
9444 <first>0</first>
9445 <address>0x4c</address>
9446 <address>0x5c</address>
9447 </range>
9448 </instance>
9449 <register>
9450 <field>
9451 <name>SOFINT</name>
9452 <position>31</position>
9453 </field>
9454 <field>
9455 <name>EOFINT</name>
9456 <position>30</position>
9457 </field>
9458 <field>
9459 <name>CMD</name>
9460 <desc>indicate command in slcd mode</desc>
9461 <position>29</position>
9462 </field>
9463 <field>
9464 <name>PAL</name>
9465 <position>28</position>
9466 </field>
9467 <field>
9468 <name>LEN</name>
9469 <position>0</position>
9470 <width>24</width>
9471 </field>
9472 </register>
9473 </node>
9474 <node>
9475 <name>OFFS</name>
9476 <title>DMA Offsize Register 1</title>
9477 <instance>
9478 <name>OFFS</name>
9479 <range>
9480 <first>0</first>
9481 <address>0x60</address>
9482 <address>0x70</address>
9483 </range>
9484 </instance>
9485 <register/>
9486 </node>
9487 <node>
9488 <name>PW</name>
9489 <title>DMA Page Width Register 1</title>
9490 <instance>
9491 <name>PW</name>
9492 <range>
9493 <first>0</first>
9494 <address>0x64</address>
9495 <address>0x74</address>
9496 </range>
9497 </instance>
9498 <register/>
9499 </node>
9500 <node>
9501 <name>CNUM</name>
9502 <title>DMA Command Counter Register 1</title>
9503 <instance>
9504 <name>CNUM</name>
9505 <range>
9506 <first>0</first>
9507 <address>0x68</address>
9508 <address>0x78</address>
9509 </range>
9510 </instance>
9511 <register/>
9512 </node>
9513 <node>
9514 <name>DESSIZE</name>
9515 <title>Foreground Size in Descriptor 1 Register</title>
9516 <instance>
9517 <name>DESSIZE</name>
9518 <range>
9519 <first>0</first>
9520 <address>0x6c</address>
9521 <address>0x7c</address>
9522 </range>
9523 </instance>
9524 <register>
9525 <field>
9526 <name>HEIGHT</name>
9527 <desc>height of foreground 1</desc>
9528 <position>16</position>
9529 <width>16</width>
9530 </field>
9531 <field>
9532 <name>WIDTH</name>
9533 <desc>width of foreground 1</desc>
9534 <position>0</position>
9535 <width>16</width>
9536 </field>
9537 </register>
9538 </node>
9539 <node>
9540 <name>RGBC</name>
9541 <title>RGB Controll Register</title>
9542 <instance>
9543 <name>RGBC</name>
9544 <address>0x90</address>
9545 </instance>
9546 <register>
9547 <width>16</width>
9548 <field>
9549 <name>RGBDM</name>
9550 <desc>enable RGB Dummy data</desc>
9551 <position>15</position>
9552 </field>
9553 <field>
9554 <name>DMM</name>
9555 <desc>RGB Dummy mode</desc>
9556 <position>14</position>
9557 </field>
9558 <field>
9559 <name>YCC</name>
9560 <desc>RGB to YCC</desc>
9561 <position>8</position>
9562 </field>
9563 <field>
9564 <name>ODDRGB</name>
9565 <desc>odd line serial RGB data arrangement</desc>
9566 <position>4</position>
9567 <width>3</width>
9568 </field>
9569 <field>
9570 <name>EVENRGB</name>
9571 <desc>even line serial RGB data arrangement</desc>
9572 <position>0</position>
9573 <width>3</width>
9574 </field>
9575 </register>
9576 </node>
9577 <node>
9578 <name>OSDC</name>
9579 <title>LCD OSD Configure Register</title>
9580 <instance>
9581 <name>OSDC</name>
9582 <address>0x100</address>
9583 </instance>
9584 <register>
9585 <width>16</width>
9586 <field>
9587 <name>SOFM1</name>
9588 <desc>Start of frame interrupt mask for foreground 1</desc>
9589 <position>15</position>
9590 </field>
9591 <field>
9592 <name>EOFM1</name>
9593 <desc>End of frame interrupt mask for foreground 1</desc>
9594 <position>14</position>
9595 </field>
9596 <field>
9597 <name>SOFM0</name>
9598 <desc>Start of frame interrupt mask for foreground 0</desc>
9599 <position>11</position>
9600 </field>
9601 <field>
9602 <name>EOFM0</name>
9603 <desc>End of frame interrupt mask for foreground 0</desc>
9604 <position>10</position>
9605 </field>
9606 <field>
9607 <name>ENDM</name>
9608 <desc>End of frame interrupt mask for panel.</desc>
9609 <position>9</position>
9610 </field>
9611 <field>
9612 <name>F1EN</name>
9613 <desc>enable foreground 1</desc>
9614 <position>4</position>
9615 </field>
9616 <field>
9617 <name>F0EN</name>
9618 <desc>enable foreground 0</desc>
9619 <position>3</position>
9620 </field>
9621 <field>
9622 <name>ALPHAEN</name>
9623 <desc>enable alpha blending</desc>
9624 <position>2</position>
9625 </field>
9626 <field>
9627 <name>ALPHAMD</name>
9628 <desc>alpha blending mode</desc>
9629 <position>1</position>
9630 </field>
9631 <field>
9632 <name>OSDEN</name>
9633 <desc>OSD mode enable</desc>
9634 <position>0</position>
9635 </field>
9636 </register>
9637 </node>
9638 <node>
9639 <name>OSDCTRL</name>
9640 <title>LCD OSD Control Register</title>
9641 <instance>
9642 <name>OSDCTRL</name>
9643 <address>0x104</address>
9644 </instance>
9645 <register>
9646 <width>16</width>
9647 <field>
9648 <name>IPU</name>
9649 <desc>input data from IPU</desc>
9650 <position>15</position>
9651 </field>
9652 <field>
9653 <name>RGB555</name>
9654 <desc>foreground 1, 16bpp, 0-RGB565, 1-RGB555</desc>
9655 <position>4</position>
9656 </field>
9657 <field>
9658 <name>CHANGES</name>
9659 <desc>Change size flag</desc>
9660 <position>3</position>
9661 </field>
9662 <field>
9663 <name>OSDBPP</name>
9664 <desc>RGB 30 bit</desc>
9665 <position>0</position>
9666 <width>3</width>
9667 <enum>
9668 <name>2</name>
9669 <value>0x1</value>
9670 </enum>
9671 <enum>
9672 <name>4</name>
9673 <value>0x2</value>
9674 </enum>
9675 <enum>
9676 <name>15_16</name>
9677 <value>0x4</value>
9678 </enum>
9679 <enum>
9680 <name>16</name>
9681 <value>0x4</value>
9682 </enum>
9683 <enum>
9684 <name>18_24</name>
9685 <value>0x5</value>
9686 </enum>
9687 <enum>
9688 <name>CMPS_24</name>
9689 <value>0x6</value>
9690 </enum>
9691 <enum>
9692 <name>30</name>
9693 <value>0x7</value>
9694 </enum>
9695 </field>
9696 </register>
9697 </node>
9698 <node>
9699 <name>OSDS</name>
9700 <title>LCD OSD Status Register</title>
9701 <instance>
9702 <name>OSDS</name>
9703 <address>0x108</address>
9704 </instance>
9705 <register>
9706 <width>16</width>
9707 <field>
9708 <name>SOF1</name>
9709 <desc>Start of frame flag for foreground 1</desc>
9710 <position>15</position>
9711 </field>
9712 <field>
9713 <name>EOF1</name>
9714 <desc>End of frame flag for foreground 1</desc>
9715 <position>14</position>
9716 </field>
9717 <field>
9718 <name>SOF0</name>
9719 <desc>Start of frame flag for foreground 0</desc>
9720 <position>11</position>
9721 </field>
9722 <field>
9723 <name>EOF0</name>
9724 <desc>End of frame flag for foreground 0</desc>
9725 <position>10</position>
9726 </field>
9727 <field>
9728 <name>READY</name>
9729 <desc>Read for accept the change</desc>
9730 <position>0</position>
9731 </field>
9732 </register>
9733 </node>
9734 <node>
9735 <name>BGC</name>
9736 <title>LCD Background Color Register</title>
9737 <instance>
9738 <name>BGC</name>
9739 <address>0x10c</address>
9740 </instance>
9741 <register>
9742 <field>
9743 <name>RED</name>
9744 <desc>Red color offset</desc>
9745 <position>16</position>
9746 <width>8</width>
9747 </field>
9748 <field>
9749 <name>GREEN</name>
9750 <desc>Green color offset</desc>
9751 <position>8</position>
9752 <width>8</width>
9753 </field>
9754 <field>
9755 <name>BLUE</name>
9756 <desc>Blue color offset</desc>
9757 <position>0</position>
9758 <width>8</width>
9759 </field>
9760 </register>
9761 </node>
9762 <node>
9763 <name>KEY</name>
9764 <title>LCD Foreground Color Key Register 1</title>
9765 <instance>
9766 <name>KEY</name>
9767 <range>
9768 <first>0</first>
9769 <address>0x110</address>
9770 <address>0x114</address>
9771 </range>
9772 </instance>
9773 <register>
9774 <field>
9775 <name>KEYEN</name>
9776 <desc>enable color key</desc>
9777 <position>31</position>
9778 </field>
9779 <field>
9780 <name>KEYMD</name>
9781 <desc>color key mode</desc>
9782 <position>30</position>
9783 </field>
9784 <field>
9785 <name>RED</name>
9786 <desc>Red color offset</desc>
9787 <position>16</position>
9788 <width>8</width>
9789 </field>
9790 <field>
9791 <name>GREEN</name>
9792 <desc>Green color offset</desc>
9793 <position>8</position>
9794 <width>8</width>
9795 </field>
9796 <field>
9797 <name>BLUE</name>
9798 <desc>Blue color offset</desc>
9799 <position>0</position>
9800 <width>8</width>
9801 </field>
9802 </register>
9803 </node>
9804 <node>
9805 <name>ALPHA</name>
9806 <title>LCD ALPHA Register</title>
9807 <instance>
9808 <name>ALPHA</name>
9809 <address>0x118</address>
9810 </instance>
9811 <register>
9812 <width>8</width>
9813 </register>
9814 </node>
9815 <node>
9816 <name>IPUR</name>
9817 <title>LCD IPU Restart Register</title>
9818 <instance>
9819 <name>IPUR</name>
9820 <address>0x11c</address>
9821 </instance>
9822 <register>
9823 <field>
9824 <name>IPUREN</name>
9825 <desc>IPU restart function enable</desc>
9826 <position>31</position>
9827 </field>
9828 </register>
9829 </node>
9830 <node>
9831 <name>XYP</name>
9832 <title>Foreground 1 XY Position Register</title>
9833 <instance>
9834 <name>XYP</name>
9835 <range>
9836 <first>0</first>
9837 <address>0x120</address>
9838 <address>0x124</address>
9839 </range>
9840 </instance>
9841 <register>
9842 <field>
9843 <name>YPOS</name>
9844 <desc>Y position bit of foreground 0 or 1</desc>
9845 <position>16</position>
9846 <width>16</width>
9847 </field>
9848 <field>
9849 <name>XPOS</name>
9850 <desc>X position bit of foreground 0 or 1</desc>
9851 <position>0</position>
9852 <width>16</width>
9853 </field>
9854 </register>
9855 </node>
9856 <node>
9857 <name>SIZE</name>
9858 <title>Foreground 1 Size Register</title>
9859 <instance>
9860 <name>SIZE</name>
9861 <range>
9862 <first>0</first>
9863 <address>0x128</address>
9864 <address>0x12c</address>
9865 </range>
9866 </instance>
9867 <register/>
9868 </node>
9869 <node>
9870 <name>DA0_PART2</name>
9871 <title>Descriptor Address Register PART2</title>
9872 <instance>
9873 <name>DA0_PART2</name>
9874 <address>0x1c0</address>
9875 </instance>
9876 <register/>
9877 </node>
9878 <node>
9879 <name>SA0_PART2</name>
9880 <title>Source Address Register PART2</title>
9881 <instance>
9882 <name>SA0_PART2</name>
9883 <address>0x1c4</address>
9884 </instance>
9885 <register/>
9886 </node>
9887 <node>
9888 <name>FID0_PART2</name>
9889 <title>Frame ID Register PART2</title>
9890 <instance>
9891 <name>FID0_PART2</name>
9892 <address>0x1c8</address>
9893 </instance>
9894 <register/>
9895 </node>
9896 <node>
9897 <name>CMD0_PART2</name>
9898 <title>DMA Command Register PART2</title>
9899 <instance>
9900 <name>CMD0_PART2</name>
9901 <address>0x1cc</address>
9902 </instance>
9903 <register/>
9904 </node>
9905 <node>
9906 <name>OFFS0_PART2</name>
9907 <title>DMA Offsize Register PART2</title>
9908 <instance>
9909 <name>OFFS0_PART2</name>
9910 <address>0x1e0</address>
9911 </instance>
9912 <register/>
9913 </node>
9914 <node>
9915 <name>PW0_PART2</name>
9916 <title>DMA Command Counter Register PART2</title>
9917 <instance>
9918 <name>PW0_PART2</name>
9919 <address>0x1e4</address>
9920 </instance>
9921 <register/>
9922 </node>
9923 <node>
9924 <name>CNUM0_PART2</name>
9925 <title>Foreground Size in Descriptor PART2 Register</title>
9926 <instance>
9927 <name>CNUM0_PART2</name>
9928 <address>0x1e8</address>
9929 </instance>
9930 <register/>
9931 </node>
9932 <node>
9933 <name>DESSIZE0_PART2</name>
9934 <instance>
9935 <name>DESSIZE0_PART2</name>
9936 <address>0x1ec</address>
9937 </instance>
9938 <register/>
9939 </node>
9940 <node>
9941 <name>XYP0_PART2</name>
9942 <title>Foreground 0 PART2 XY Position Register</title>
9943 <instance>
9944 <name>XYP0_PART2</name>
9945 <address>0x1f0</address>
9946 </instance>
9947 <register/>
9948 </node>
9949 <node>
9950 <name>SIZE0_PART2</name>
9951 <title>Foreground 0 PART2 Size Register</title>
9952 <instance>
9953 <name>SIZE0_PART2</name>
9954 <address>0x1f4</address>
9955 </instance>
9956 <register/>
9957 </node>
9958 <node>
9959 <name>PCFG</name>
9960 <instance>
9961 <name>PCFG</name>
9962 <address>0x2c0</address>
9963 </instance>
9964 <register/>
9965 </node>
9966 </node>
9967 <node>
9968 <name>SLCD</name>
9969 <title>Smart LCD Controller</title>
9970 <instance>
9971 <name>SLCD</name>
9972 <address>0xb3050000</address>
9973 </instance>
9974 <node>
9975 <name>MCFG</name>
9976 <title>SLCD Configure Register</title>
9977 <instance>
9978 <name>SCFG</name>
9979 <address>0xa0</address>
9980 </instance>
9981 <register>
9982 <field>
9983 <name>DWIDTH</name>
9984 <position>10</position>
9985 <width>3</width>
9986 <enum>
9987 <name>18BIT</name>
9988 <value>0x0</value>
9989 </enum>
9990 <enum>
9991 <name>16BIT</name>
9992 <value>0x1</value>
9993 </enum>
9994 <enum>
9995 <name>8BIT_x3</name>
9996 <value>0x2</value>
9997 </enum>
9998 <enum>
9999 <name>8BIT_x2</name>
10000 <value>0x3</value>
10001 </enum>
10002 <enum>
10003 <name>8BIT_x1</name>
10004 <value>0x4</value>
10005 </enum>
10006 <enum>
10007 <name>24BIT</name>
10008 <value>0x5</value>
10009 </enum>
10010 <enum>
10011 <name>9BIT_x2</name>
10012 <value>0x7</value>
10013 </enum>
10014 </field>
10015 <field>
10016 <name>CWIDTH</name>
10017 <position>8</position>
10018 <width>2</width>
10019 <enum>
10020 <name>16BIT</name>
10021 <value>0x0</value>
10022 </enum>
10023 <enum>
10024 <name>8BIT</name>
10025 <value>0x1</value>
10026 </enum>
10027 <enum>
10028 <name>18BIT</name>
10029 <value>0x2</value>
10030 </enum>
10031 <enum>
10032 <name>24BIT</name>
10033 <value>0x3</value>
10034 </enum>
10035 </field>
10036 <field>
10037 <name>CS_ACTIVE_HIGH</name>
10038 <position>4</position>
10039 </field>
10040 <field>
10041 <name>RS_CMD_HIGH</name>
10042 <position>3</position>
10043 </field>
10044 <field>
10045 <name>CLK_ACTIVE_RISING</name>
10046 <position>1</position>
10047 </field>
10048 <field>
10049 <name>TYPE_SERIAL</name>
10050 <position>0</position>
10051 </field>
10052 </register>
10053 </node>
10054 <node>
10055 <name>MCTRL</name>
10056 <title>SLCD Control Register</title>
10057 <instance>
10058 <name>SCTRL</name>
10059 <address>0xa4</address>
10060 </instance>
10061 <register>
10062 <width>8</width>
10063 <field>
10064 <name>DMA_MODE</name>
10065 <position>2</position>
10066 </field>
10067 <field>
10068 <name>DMA_START</name>
10069 <position>1</position>
10070 </field>
10071 <field>
10072 <name>DMA_EN</name>
10073 <position>0</position>
10074 </field>
10075 </register>
10076 </node>
10077 <node>
10078 <name>MSTATE</name>
10079 <title>SLCD Status Register</title>
10080 <instance>
10081 <name>SSTATE</name>
10082 <address>0xa8</address>
10083 </instance>
10084 <register>
10085 <width>8</width>
10086 <field>
10087 <name>BUSY</name>
10088 <position>0</position>
10089 </field>
10090 </register>
10091 </node>
10092 <node>
10093 <name>MDATA</name>
10094 <title>SLCD Data Register</title>
10095 <instance>
10096 <name>MDATA</name>
10097 <address>0xac</address>
10098 </instance>
10099 <register>
10100 <field>
10101 <name>RS_COMMAND</name>
10102 <position>31</position>
10103 </field>
10104 </register>
10105 </node>
10106 </node>
10107 <node>
10108 <name>TVE</name>
10109 <title>TVE (TV Encoder Controller)</title>
10110 <instance>
10111 <name>TVE</name>
10112 <address>0xb3050100</address>
10113 </instance>
10114 <node>
10115 <name>CTRL</name>
10116 <title>TV Encoder Control register</title>
10117 <instance>
10118 <name>CTRL</name>
10119 <address>0x40</address>
10120 </instance>
10121 <register>
10122 <field>
10123 <name>EYCBCR</name>
10124 <desc>YCbCr_enable</desc>
10125 <position>25</position>
10126 </field>
10127 <field>
10128 <name>ECVBS</name>
10129 <desc>1: cvbs_enable 0: s-video</desc>
10130 <position>24</position>
10131 </field>
10132 <field>
10133 <name>DAPD3</name>
10134 <desc>DAC 3 power down</desc>
10135 <position>23</position>
10136 </field>
10137 <field>
10138 <name>DAPD2</name>
10139 <desc>DAC 2 power down</desc>
10140 <position>22</position>
10141 </field>
10142 <field>
10143 <name>DAPD1</name>
10144 <desc>DAC 1 power down</desc>
10145 <position>21</position>
10146 </field>
10147 <field>
10148 <name>DAPD</name>
10149 <desc>power down all DACs</desc>
10150 <position>20</position>
10151 </field>
10152 <field>
10153 <name>YCDLY</name>
10154 <position>16</position>
10155 <width>3</width>
10156 </field>
10157 <field>
10158 <name>CGAIN</name>
10159 <desc>gain = 3/4</desc>
10160 <position>14</position>
10161 <width>2</width>
10162 <enum>
10163 <name>FULL</name>
10164 <value>0x0</value>
10165 </enum>
10166 <enum>
10167 <name>QUTR</name>
10168 <value>0x1</value>
10169 </enum>
10170 <enum>
10171 <name>HALF</name>
10172 <value>0x2</value>
10173 </enum>
10174 <enum>
10175 <name>THREE_QURT</name>
10176 <value>0x3</value>
10177 </enum>
10178 </field>
10179 <field>
10180 <name>CBW</name>
10181 <desc>Ultra wide band</desc>
10182 <position>12</position>
10183 <width>2</width>
10184 <enum>
10185 <name>NARROW</name>
10186 <value>0x0</value>
10187 </enum>
10188 <enum>
10189 <name>WIDE</name>
10190 <value>0x1</value>
10191 </enum>
10192 <enum>
10193 <name>EXTRA</name>
10194 <value>0x2</value>
10195 </enum>
10196 <enum>
10197 <name>ULTRA</name>
10198 <value>0x3</value>
10199 </enum>
10200 </field>
10201 <field>
10202 <name>SYNCT</name>
10203 <position>9</position>
10204 </field>
10205 <field>
10206 <name>PAL</name>
10207 <desc>1: PAL, 0: NTSC</desc>
10208 <position>8</position>
10209 </field>
10210 <field>
10211 <name>FINV</name>
10212 <desc>invert_top:1-invert top and bottom fields.</desc>
10213 <position>7</position>
10214 </field>
10215 <field>
10216 <name>ZBLACK</name>
10217 <desc>bypass_yclamp:1-Black of luminance (Y) input is 0.</desc>
10218 <position>6</position>
10219 </field>
10220 <field>
10221 <name>CR1ST</name>
10222 <desc>uv_order:0-Cb before Cr,1-Cr before Cb</desc>
10223 <position>5</position>
10224 </field>
10225 <field>
10226 <name>CLBAR</name>
10227 <desc>Color bar mode:0-Output input video to TV,1-Output color bar to TV</desc>
10228 <position>4</position>
10229 </field>
10230 <field>
10231 <name>SWRST</name>
10232 <desc>Software reset:1-TVE is reset</desc>
10233 <position>0</position>
10234 </field>
10235 </register>
10236 </node>
10237 <node>
10238 <name>FRCFG</name>
10239 <title>Frame configure register</title>
10240 <instance>
10241 <name>FRCFG</name>
10242 <address>0x44</address>
10243 </instance>
10244 <register>
10245 <field>
10246 <name>L1ST</name>
10247 <position>16</position>
10248 <width>8</width>
10249 </field>
10250 <field>
10251 <name>NLINE</name>
10252 <position>0</position>
10253 <width>10</width>
10254 </field>
10255 </register>
10256 </node>
10257 <node>
10258 <name>SLCFG1</name>
10259 <title>TV signal level configure register 1</title>
10260 <instance>
10261 <name>SLCFG1</name>
10262 <address>0x50</address>
10263 </instance>
10264 <register>
10265 <field>
10266 <name>WHITEL</name>
10267 <position>16</position>
10268 <width>10</width>
10269 </field>
10270 <field>
10271 <name>BLACKL</name>
10272 <position>0</position>
10273 <width>10</width>
10274 </field>
10275 </register>
10276 </node>
10277 <node>
10278 <name>SLCFG2</name>
10279 <title>TV signal level configure register 2</title>
10280 <instance>
10281 <name>SLCFG2</name>
10282 <address>0x54</address>
10283 </instance>
10284 <register>
10285 <field>
10286 <name>VBLANKL</name>
10287 <position>16</position>
10288 <width>10</width>
10289 </field>
10290 <field>
10291 <name>BLANKL</name>
10292 <position>0</position>
10293 <width>10</width>
10294 </field>
10295 </register>
10296 </node>
10297 <node>
10298 <name>SLCFG3</name>
10299 <title>TV signal level configure register 3</title>
10300 <instance>
10301 <name>SLCFG3</name>
10302 <address>0x58</address>
10303 </instance>
10304 <register>
10305 <field>
10306 <name>SYNCL</name>
10307 <position>0</position>
10308 <width>8</width>
10309 </field>
10310 </register>
10311 </node>
10312 <node>
10313 <name>LTCFG1</name>
10314 <title>Line timing configure register 1</title>
10315 <instance>
10316 <name>LTCFG1</name>
10317 <address>0x60</address>
10318 </instance>
10319 <register>
10320 <field>
10321 <name>FRONTP</name>
10322 <position>16</position>
10323 <width>5</width>
10324 </field>
10325 <field>
10326 <name>HSYNCW</name>
10327 <position>8</position>
10328 <width>7</width>
10329 </field>
10330 <field>
10331 <name>BACKP</name>
10332 <position>0</position>
10333 <width>7</width>
10334 </field>
10335 </register>
10336 </node>
10337 <node>
10338 <name>LTCFG2</name>
10339 <title>Line timing configure register 2</title>
10340 <instance>
10341 <name>LTCFG2</name>
10342 <address>0x64</address>
10343 </instance>
10344 <register>
10345 <field>
10346 <name>ACTLIN</name>
10347 <position>16</position>
10348 <width>11</width>
10349 </field>
10350 <field>
10351 <name>PREBW</name>
10352 <position>8</position>
10353 <width>5</width>
10354 </field>
10355 <field>
10356 <name>BURSTW</name>
10357 <position>0</position>
10358 <width>6</width>
10359 </field>
10360 </register>
10361 </node>
10362 <node>
10363 <name>CFREQ</name>
10364 <title>Chrominance sub-carrier frequency configure register</title>
10365 <instance>
10366 <name>CFREQ</name>
10367 <address>0x70</address>
10368 </instance>
10369 <register/>
10370 </node>
10371 <node>
10372 <name>CPHASE</name>
10373 <title>Chrominance sub-carrier phase configure register</title>
10374 <instance>
10375 <name>CPHASE</name>
10376 <address>0x74</address>
10377 </instance>
10378 <register>
10379 <field>
10380 <name>INITPH</name>
10381 <position>24</position>
10382 <width>8</width>
10383 </field>
10384 <field>
10385 <name>ACTPH</name>
10386 <position>16</position>
10387 <width>8</width>
10388 </field>
10389 <field>
10390 <name>CCRSTP</name>
10391 <desc>Never</desc>
10392 <position>0</position>
10393 <width>2</width>
10394 <enum>
10395 <name>8</name>
10396 <value>0x0</value>
10397 </enum>
10398 <enum>
10399 <name>4</name>
10400 <value>0x1</value>
10401 </enum>
10402 <enum>
10403 <name>2</name>
10404 <value>0x2</value>
10405 </enum>
10406 <enum>
10407 <name>0</name>
10408 <value>0x3</value>
10409 </enum>
10410 </field>
10411 </register>
10412 </node>
10413 <node>
10414 <name>CBCRCFG</name>
10415 <title>Chrominance filter configure register</title>
10416 <instance>
10417 <name>CBCRCFG</name>
10418 <address>0x78</address>
10419 </instance>
10420 <register>
10421 <field>
10422 <name>CBBA</name>
10423 <position>24</position>
10424 <width>8</width>
10425 </field>
10426 <field>
10427 <name>CRBA</name>
10428 <position>16</position>
10429 <width>8</width>
10430 </field>
10431 <field>
10432 <name>CBGAIN</name>
10433 <position>8</position>
10434 <width>8</width>
10435 </field>
10436 <field>
10437 <name>CRGAIN</name>
10438 <position>0</position>
10439 <width>8</width>
10440 </field>
10441 </register>
10442 </node>
10443 <node>
10444 <name>WSSCR</name>
10445 <title>Wide screen signal control register</title>
10446 <instance>
10447 <name>WSSCR</name>
10448 <address>0x80</address>
10449 </instance>
10450 <register>
10451 <field>
10452 <name>NCHFREQ</name>
10453 <position>12</position>
10454 <width>3</width>
10455 </field>
10456 <field>
10457 <name>WSSEDGE</name>
10458 <position>4</position>
10459 <width>3</width>
10460 </field>
10461 </register>
10462 </node>
10463 <node>
10464 <name>WSSCFG1</name>
10465 <title>Wide screen signal configure register 1</title>
10466 <instance>
10467 <name>WSSCFG1</name>
10468 <address>0x84</address>
10469 </instance>
10470 <register/>
10471 </node>
10472 <node>
10473 <name>WSSCFG2</name>
10474 <title>Wide screen signal configure register 2</title>
10475 <instance>
10476 <name>WSSCFG2</name>
10477 <address>0x88</address>
10478 </instance>
10479 <register/>
10480 </node>
10481 <node>
10482 <name>WSSCFG3</name>
10483 <title>Wide screen signal configure register 3</title>
10484 <instance>
10485 <name>WSSCFG3</name>
10486 <address>0x8c</address>
10487 </instance>
10488 <register/>
10489 </node>
10490 </node>
10491 <node>
10492 <name>CIM</name>
10493 <instance>
10494 <name>CIM</name>
10495 <address>0xb3060000</address>
10496 </instance>
10497 <node>
10498 <name>CFG</name>
10499 <instance>
10500 <name>CFG</name>
10501 <address>0x0</address>
10502 </instance>
10503 <register>
10504 <field>
10505 <name>RXF_TRIG</name>
10506 <position>24</position>
10507 <width>6</width>
10508 </field>
10509 <field>
10510 <name>SEP</name>
10511 <position>20</position>
10512 </field>
10513 <field>
10514 <name>ORDER</name>
10515 <desc>CrY0CbY1; CrCbY</desc>
10516 <position>18</position>
10517 <width>2</width>
10518 <enum>
10519 <name>0</name>
10520 <value>0x0</value>
10521 </enum>
10522 <enum>
10523 <name>1</name>
10524 <value>0x1</value>
10525 </enum>
10526 <enum>
10527 <name>2</name>
10528 <value>0x2</value>
10529 </enum>
10530 <enum>
10531 <name>3</name>
10532 <value>0x3</value>
10533 </enum>
10534 </field>
10535 <field>
10536 <name>DF</name>
10537 <desc>ITU656 YCbCr422</desc>
10538 <position>16</position>
10539 <width>2</width>
10540 <enum>
10541 <name>YUV444</name>
10542 <value>0x1</value>
10543 </enum>
10544 <enum>
10545 <name>YUV422</name>
10546 <value>0x2</value>
10547 </enum>
10548 <enum>
10549 <name>ITU656</name>
10550 <value>0x3</value>
10551 </enum>
10552 </field>
10553 <field>
10554 <name>INV_DAT</name>
10555 <position>15</position>
10556 </field>
10557 <field>
10558 <name>VSP</name>
10559 <desc>VSYNC Polarity:0-rising edge active,1-falling edge active</desc>
10560 <position>14</position>
10561 </field>
10562 <field>
10563 <name>HSP</name>
10564 <desc>HSYNC Polarity:0-rising edge active,1-falling edge active</desc>
10565 <position>13</position>
10566 </field>
10567 <field>
10568 <name>PCP</name>
10569 <desc>PCLK working edge: 0-rising, 1-falling</desc>
10570 <position>12</position>
10571 </field>
10572 <field>
10573 <name>DMA</name>
10574 <desc>Suggested High speed AHB</desc>
10575 <position>10</position>
10576 <width>2</width>
10577 <enum>
10578 <name>BURST_INCR4</name>
10579 <value>0x0</value>
10580 </enum>
10581 <enum>
10582 <name>BURST_INCR8</name>
10583 <value>0x1</value>
10584 </enum>
10585 <enum>
10586 <name>BURST_INCR16</name>
10587 <value>0x2</value>
10588 </enum>
10589 <enum>
10590 <name>BURST_INCR32</name>
10591 <value>0x3</value>
10592 </enum>
10593 </field>
10594 <field>
10595 <name>DUMMY_ZERO</name>
10596 <position>9</position>
10597 </field>
10598 <field>
10599 <name>EXT_VSYNC</name>
10600 <desc>Only for ITU656 Progressive mode</desc>
10601 <position>8</position>
10602 </field>
10603 <field>
10604 <name>PACK</name>
10605 <desc>11 44 33 22 0xY0CrY1Cb</desc>
10606 <position>4</position>
10607 <width>3</width>
10608 <enum>
10609 <name>0</name>
10610 <value>0x0</value>
10611 </enum>
10612 <enum>
10613 <name>1</name>
10614 <value>0x1</value>
10615 </enum>
10616 <enum>
10617 <name>2</name>
10618 <value>0x2</value>
10619 </enum>
10620 <enum>
10621 <name>3</name>
10622 <value>0x3</value>
10623 </enum>
10624 <enum>
10625 <name>4</name>
10626 <value>0x4</value>
10627 </enum>
10628 <enum>
10629 <name>5</name>
10630 <value>0x5</value>
10631 </enum>
10632 <enum>
10633 <name>6</name>
10634 <value>0x6</value>
10635 </enum>
10636 <enum>
10637 <name>7</name>
10638 <value>0x7</value>
10639 </enum>
10640 </field>
10641 <field>
10642 <name>BYPASS</name>
10643 <position>2</position>
10644 </field>
10645 <field>
10646 <name>DSM</name>
10647 <desc>Gated Clock Mode</desc>
10648 <position>0</position>
10649 <width>2</width>
10650 <enum>
10651 <name>CPM</name>
10652 <value>0x0</value>
10653 </enum>
10654 <enum>
10655 <name>CIM</name>
10656 <value>0x1</value>
10657 </enum>
10658 <enum>
10659 <name>GCM</name>
10660 <value>0x2</value>
10661 </enum>
10662 </field>
10663 </register>
10664 </node>
10665 <node>
10666 <name>CTRL</name>
10667 <title>CIM Control Register</title>
10668 <instance>
10669 <name>CTRL</name>
10670 <address>0x4</address>
10671 </instance>
10672 <register>
10673 <field>
10674 <name>EEOF_LINE</name>
10675 <position>20</position>
10676 <width>12</width>
10677 </field>
10678 <field>
10679 <name>FRC</name>
10680 <desc>Sample 1/16 frame</desc>
10681 <position>16</position>
10682 <width>4</width>
10683 <enum>
10684 <name>1</name>
10685 <value>0x0</value>
10686 </enum>
10687 <enum>
10688 <name>2</name>
10689 <value>0x1</value>
10690 </enum>
10691 <enum>
10692 <name>3</name>
10693 <value>0x2</value>
10694 </enum>
10695 <enum>
10696 <name>4</name>
10697 <value>0x3</value>
10698 </enum>
10699 <enum>
10700 <name>5</name>
10701 <value>0x4</value>
10702 </enum>
10703 <enum>
10704 <name>6</name>
10705 <value>0x5</value>
10706 </enum>
10707 <enum>
10708 <name>7</name>
10709 <value>0x6</value>
10710 </enum>
10711 <enum>
10712 <name>8</name>
10713 <value>0x7</value>
10714 </enum>
10715 <enum>
10716 <name>9</name>
10717 <value>0x8</value>
10718 </enum>
10719 <enum>
10720 <name>10</name>
10721 <value>0x9</value>
10722 </enum>
10723 <enum>
10724 <name>11</name>
10725 <value>0xa</value>
10726 </enum>
10727 <enum>
10728 <name>12</name>
10729 <value>0xb</value>
10730 </enum>
10731 <enum>
10732 <name>13</name>
10733 <value>0xc</value>
10734 </enum>
10735 <enum>
10736 <name>14</name>
10737 <value>0xd</value>
10738 </enum>
10739 <enum>
10740 <name>15</name>
10741 <value>0xe</value>
10742 </enum>
10743 <enum>
10744 <name>16</name>
10745 <value>0xf</value>
10746 </enum>
10747 </field>
10748 <field>
10749 <name>DMA_EEOFM</name>
10750 <desc>Enable EEOF interrupt</desc>
10751 <position>15</position>
10752 </field>
10753 <field>
10754 <name>WIN_EN</name>
10755 <position>14</position>
10756 </field>
10757 <field>
10758 <name>VDDM</name>
10759 <desc>VDD interrupt enable</desc>
10760 <position>13</position>
10761 </field>
10762 <field>
10763 <name>DMA_SOFM</name>
10764 <position>12</position>
10765 </field>
10766 <field>
10767 <name>DMA_EOFM</name>
10768 <position>11</position>
10769 </field>
10770 <field>
10771 <name>DMA_STOPM</name>
10772 <position>10</position>
10773 </field>
10774 <field>
10775 <name>RXF_TRIGM</name>
10776 <position>9</position>
10777 </field>
10778 <field>
10779 <name>RXF_OFM</name>
10780 <position>8</position>
10781 </field>
10782 <field>
10783 <name>DMA_SYNC</name>
10784 <desc>when change DA, do frame sync</desc>
10785 <position>7</position>
10786 </field>
10787 <field>
10788 <name>RXF_TRIG</name>
10789 <desc>trigger value = (n+1)*burst_type</desc>
10790 <position>3</position>
10791 <width>4</width>
10792 </field>
10793 <field>
10794 <name>DMA_EN</name>
10795 <desc>Enable DMA</desc>
10796 <position>2</position>
10797 </field>
10798 <field>
10799 <name>RXF_RST</name>
10800 <desc>RxFIFO reset</desc>
10801 <position>1</position>
10802 </field>
10803 <field>
10804 <name>ENA</name>
10805 <desc>Enable CIM</desc>
10806 <position>0</position>
10807 </field>
10808 </register>
10809 </node>
10810 <node>
10811 <name>STATE</name>
10812 <title>CIM State Register</title>
10813 <instance>
10814 <name>STATE</name>
10815 <address>0x8</address>
10816 </instance>
10817 <register>
10818 <field>
10819 <name>CR_RF_OF</name>
10820 <position>27</position>
10821 </field>
10822 <field>
10823 <name>CR_RF_TRIG</name>
10824 <position>26</position>
10825 </field>
10826 <field>
10827 <name>CR_RF_EMPTY</name>
10828 <position>25</position>
10829 </field>
10830 <field>
10831 <name>CB_RF_OF</name>
10832 <position>19</position>
10833 </field>
10834 <field>
10835 <name>CB_RF_TRIG</name>
10836 <position>18</position>
10837 </field>
10838 <field>
10839 <name>CB_RF_EMPTY</name>
10840 <position>17</position>
10841 </field>
10842 <field>
10843 <name>Y_RF_OF</name>
10844 <position>11</position>
10845 </field>
10846 <field>
10847 <name>Y_RF_TRIG</name>
10848 <position>10</position>
10849 </field>
10850 <field>
10851 <name>Y_RF_EMPTY</name>
10852 <position>9</position>
10853 </field>
10854 <field>
10855 <name>DMA_EEOF</name>
10856 <desc>DMA Line EEOf irq</desc>
10857 <position>7</position>
10858 </field>
10859 <field>
10860 <name>DMA_SOF</name>
10861 <desc>DMA start irq</desc>
10862 <position>6</position>
10863 </field>
10864 <field>
10865 <name>DMA_EOF</name>
10866 <desc>DMA end irq</desc>
10867 <position>5</position>
10868 </field>
10869 <field>
10870 <name>DMA_STOP</name>
10871 <desc>DMA stop irq</desc>
10872 <position>4</position>
10873 </field>
10874 <field>
10875 <name>RXF_OF</name>
10876 <desc>RXFIFO over flow irq</desc>
10877 <position>3</position>
10878 </field>
10879 <field>
10880 <name>RXF_TRIG</name>
10881 <desc>RXFIFO triger meet irq</desc>
10882 <position>2</position>
10883 </field>
10884 <field>
10885 <name>RXF_EMPTY</name>
10886 <desc>RXFIFO empty irq</desc>
10887 <position>1</position>
10888 </field>
10889 <field>
10890 <name>VDD</name>
10891 <desc>CIM disabled irq</desc>
10892 <position>0</position>
10893 </field>
10894 </register>
10895 </node>
10896 <node>
10897 <name>IID</name>
10898 <instance>
10899 <name>IID</name>
10900 <address>0xc</address>
10901 </instance>
10902 <register/>
10903 </node>
10904 <node>
10905 <name>RXFIFO</name>
10906 <instance>
10907 <name>RXFIFO</name>
10908 <address>0x10</address>
10909 </instance>
10910 <register/>
10911 </node>
10912 <node>
10913 <name>DA</name>
10914 <instance>
10915 <name>DA</name>
10916 <address>0x20</address>
10917 </instance>
10918 <register/>
10919 </node>
10920 <node>
10921 <name>FA</name>
10922 <instance>
10923 <name>FA</name>
10924 <address>0x24</address>
10925 </instance>
10926 <register/>
10927 </node>
10928 <node>
10929 <name>FID</name>
10930 <instance>
10931 <name>FID</name>
10932 <address>0x28</address>
10933 </instance>
10934 <register/>
10935 </node>
10936 <node>
10937 <name>CMD</name>
10938 <title>CIM DMA Command Register</title>
10939 <instance>
10940 <name>CMD</name>
10941 <address>0x2c</address>
10942 </instance>
10943 <register>
10944 <field>
10945 <name>SOFINT</name>
10946 <desc>enable DMA start irq</desc>
10947 <position>31</position>
10948 </field>
10949 <field>
10950 <name>EOFINT</name>
10951 <desc>enable DMA end irq</desc>
10952 <position>30</position>
10953 </field>
10954 <field>
10955 <name>EEOFINT</name>
10956 <desc>enable DMA EEOF irq</desc>
10957 <position>29</position>
10958 </field>
10959 <field>
10960 <name>STOP</name>
10961 <desc>enable DMA stop irq</desc>
10962 <position>28</position>
10963 </field>
10964 <field>
10965 <name>OFRCV</name>
10966 <desc>enable recovery when TXFiFo overflow</desc>
10967 <position>27</position>
10968 </field>
10969 <field>
10970 <name>LEN</name>
10971 <position>0</position>
10972 <width>24</width>
10973 </field>
10974 </register>
10975 </node>
10976 <node>
10977 <name>SIZE</name>
10978 <title>CIM Window-Image Size Register</title>
10979 <instance>
10980 <name>SIZE</name>
10981 <address>0x30</address>
10982 </instance>
10983 <register>
10984 <field>
10985 <name>LPF</name>
10986 <desc>Lines per freame for csc output image</desc>
10987 <position>16</position>
10988 <width>13</width>
10989 </field>
10990 <field>
10991 <name>PPL</name>
10992 <desc>Pixels per line for csc output image, should be an even number</desc>
10993 <position>0</position>
10994 <width>13</width>
10995 </field>
10996 </register>
10997 </node>
10998 <node>
10999 <name>OFFSET</name>
11000 <title>CIM Image Offset Register</title>
11001 <instance>
11002 <name>OFFSET</name>
11003 <address>0x34</address>
11004 </instance>
11005 <register>
11006 <field>
11007 <name>V</name>
11008 <desc>Vertical offset</desc>
11009 <position>16</position>
11010 <width>12</width>
11011 </field>
11012 <field>
11013 <name>H</name>
11014 <desc>OFFSET_H should be even number</desc>
11015 <position>0</position>
11016 <width>12</width>
11017 </field>
11018 </register>
11019 </node>
11020 <node>
11021 <name>YFA</name>
11022 <instance>
11023 <name>YFA</name>
11024 <address>0x38</address>
11025 </instance>
11026 <register/>
11027 </node>
11028 <node>
11029 <name>YCMD</name>
11030 <instance>
11031 <name>YCMD</name>
11032 <address>0x3c</address>
11033 </instance>
11034 <register/>
11035 </node>
11036 <node>
11037 <name>CBFA</name>
11038 <instance>
11039 <name>CBFA</name>
11040 <address>0x40</address>
11041 </instance>
11042 <register/>
11043 </node>
11044 <node>
11045 <name>CBCMD</name>
11046 <instance>
11047 <name>CBCMD</name>
11048 <address>0x44</address>
11049 </instance>
11050 <register/>
11051 </node>
11052 <node>
11053 <name>CRFA</name>
11054 <instance>
11055 <name>CRFA</name>
11056 <address>0x48</address>
11057 </instance>
11058 <register/>
11059 </node>
11060 <node>
11061 <name>CRCMD</name>
11062 <instance>
11063 <name>CRCMD</name>
11064 <address>0x4c</address>
11065 </instance>
11066 <register/>
11067 </node>
11068 <node>
11069 <name>CTRL2</name>
11070 <instance>
11071 <name>CTRL2</name>
11072 <address>0x50</address>
11073 </instance>
11074 <register>
11075 <field>
11076 <name>OPG</name>
11077 <position>4</position>
11078 <width>2</width>
11079 </field>
11080 <field>
11081 <name>OPE</name>
11082 <position>2</position>
11083 </field>
11084 <field>
11085 <name>EME</name>
11086 <position>1</position>
11087 </field>
11088 <field>
11089 <name>APM</name>
11090 <position>0</position>
11091 </field>
11092 </register>
11093 </node>
11094 <node>
11095 <name>RAM_ADDR</name>
11096 <instance>
11097 <name>RAM_ADDR</name>
11098 <address>0x1000</address>
11099 </instance>
11100 <register/>
11101 </node>
11102 </node>
11103 <node>
11104 <name>IPU</name>
11105 <instance>
11106 <name>IPU</name>
11107 <address>0xb3080000</address>
11108 </instance>
11109 </node>
11110 <node>
11111 <name>IPU_V</name>
11112 <instance>
11113 <name>IPU_V</name>
11114 <address>0xb3080000</address>
11115 </instance>
11116 </node>
11117 <node>
11118 <name>HARB1</name>
11119 <title>AHB1 BUS Devices Base</title>
11120 <instance>
11121 <name>HARB1</name>
11122 <address>0xb3200000</address>
11123 </instance>
11124 </node>
11125 <node>
11126 <name>DMAGP0</name>
11127 <instance>
11128 <name>DMAGP0</name>
11129 <address>0xb3210000</address>
11130 </instance>
11131 </node>
11132 <node>
11133 <name>DMAGP1</name>
11134 <instance>
11135 <name>DMAGP1</name>
11136 <address>0xb3220000</address>
11137 </instance>
11138 </node>
11139 <node>
11140 <name>DMAGP2</name>
11141 <instance>
11142 <name>DMAGP2</name>
11143 <address>0xb3230000</address>
11144 </instance>
11145 </node>
11146 <node>
11147 <name>MC</name>
11148 <instance>
11149 <name>MC</name>
11150 <address>0xb3250000</address>
11151 </instance>
11152 <node>
11153 <name>MCCR</name>
11154 <title>MC Control Register</title>
11155 <instance>
11156 <name>MCCR</name>
11157 <address>0x0</address>
11158 </instance>
11159 <register/>
11160 </node>
11161 <node>
11162 <name>MCSR</name>
11163 <title>MC Status Register</title>
11164 <instance>
11165 <name>MCSR</name>
11166 <address>0x4</address>
11167 </instance>
11168 <register/>
11169 </node>
11170 <node>
11171 <name>MCRBAR</name>
11172 <instance>
11173 <name>MCRBAR</name>
11174 <address>0x8</address>
11175 </instance>
11176 <register/>
11177 </node>
11178 <node>
11179 <name>MCT1LFCR</name>
11180 <instance>
11181 <name>MCT1LFCR</name>
11182 <address>0xc</address>
11183 </instance>
11184 <register/>
11185 </node>
11186 <node>
11187 <name>MCT2LFCR</name>
11188 <instance>
11189 <name>MCT2LFCR</name>
11190 <address>0x10</address>
11191 </instance>
11192 <register/>
11193 </node>
11194 <node>
11195 <name>MCCBAR</name>
11196 <instance>
11197 <name>MCCBAR</name>
11198 <address>0x14</address>
11199 </instance>
11200 <register/>
11201 </node>
11202 <node>
11203 <name>MCIIR</name>
11204 <instance>
11205 <name>MCIIR</name>
11206 <address>0x18</address>
11207 </instance>
11208 <register/>
11209 </node>
11210 <node>
11211 <name>MCSIR</name>
11212 <instance>
11213 <name>MCSIR</name>
11214 <address>0x1c</address>
11215 </instance>
11216 <register/>
11217 </node>
11218 <node>
11219 <name>MCT1MFCR</name>
11220 <instance>
11221 <name>MCT1MFCR</name>
11222 <address>0x20</address>
11223 </instance>
11224 <register/>
11225 </node>
11226 <node>
11227 <name>MCT2MFCR</name>
11228 <instance>
11229 <name>MCT2MFCR</name>
11230 <address>0x24</address>
11231 </instance>
11232 <register/>
11233 </node>
11234 <node>
11235 <name>MCFGIR</name>
11236 <instance>
11237 <name>MCFGIR</name>
11238 <address>0x28</address>
11239 </instance>
11240 <register/>
11241 </node>
11242 <node>
11243 <name>MCFCIR</name>
11244 <instance>
11245 <name>MCFCIR</name>
11246 <address>0x2c</address>
11247 </instance>
11248 <register/>
11249 </node>
11250 <node>
11251 <name>MCRNDTR</name>
11252 <instance>
11253 <name>MCRNDTR</name>
11254 <address>0x40</address>
11255 </instance>
11256 <register/>
11257 </node>
11258 <node>
11259 <name>MC2CR</name>
11260 <instance>
11261 <name>MC2CR</name>
11262 <address>0x8000</address>
11263 </instance>
11264 <register/>
11265 </node>
11266 <node>
11267 <name>MC2SR</name>
11268 <instance>
11269 <name>MC2SR</name>
11270 <address>0x8004</address>
11271 </instance>
11272 <register/>
11273 </node>
11274 <node>
11275 <name>MC2RBAR</name>
11276 <instance>
11277 <name>MC2RBAR</name>
11278 <address>0x8008</address>
11279 </instance>
11280 <register/>
11281 </node>
11282 <node>
11283 <name>MC2CBAR</name>
11284 <instance>
11285 <name>MC2CBAR</name>
11286 <address>0x800c</address>
11287 </instance>
11288 <register/>
11289 </node>
11290 <node>
11291 <name>MC2IIR</name>
11292 <instance>
11293 <name>MC2IIR</name>
11294 <address>0x8010</address>
11295 </instance>
11296 <register/>
11297 </node>
11298 <node>
11299 <name>MC2TFCR</name>
11300 <instance>
11301 <name>MC2TFCR</name>
11302 <address>0x8014</address>
11303 </instance>
11304 <register/>
11305 </node>
11306 <node>
11307 <name>MC2SIR</name>
11308 <instance>
11309 <name>MC2SIR</name>
11310 <address>0x8018</address>
11311 </instance>
11312 <register/>
11313 </node>
11314 <node>
11315 <name>MC2FCIR</name>
11316 <instance>
11317 <name>MC2FCIR</name>
11318 <address>0x801c</address>
11319 </instance>
11320 <register/>
11321 </node>
11322 <node>
11323 <name>MC2RNDTR</name>
11324 <instance>
11325 <name>MC2RNDTR</name>
11326 <address>0x8040</address>
11327 </instance>
11328 <register/>
11329 </node>
11330 </node>
11331 <node>
11332 <name>ME</name>
11333 <instance>
11334 <name>ME</name>
11335 <address>0xb3260000</address>
11336 </instance>
11337 <node>
11338 <name>MECR</name>
11339 <title>ME control register</title>
11340 <instance>
11341 <name>MECR</name>
11342 <address>0x0</address>
11343 </instance>
11344 <register/>
11345 </node>
11346 <node>
11347 <name>MERBAR</name>
11348 <instance>
11349 <name>MERBAR</name>
11350 <address>0x4</address>
11351 </instance>
11352 <register/>
11353 </node>
11354 <node>
11355 <name>MECBAR</name>
11356 <instance>
11357 <name>MECBAR</name>
11358 <address>0x8</address>
11359 </instance>
11360 <register/>
11361 </node>
11362 <node>
11363 <name>MEDAR</name>
11364 <instance>
11365 <name>MEDAR</name>
11366 <address>0xc</address>
11367 </instance>
11368 <register/>
11369 </node>
11370 <node>
11371 <name>MERFSR</name>
11372 <instance>
11373 <name>MERFSR</name>
11374 <address>0x10</address>
11375 </instance>
11376 <register/>
11377 </node>
11378 <node>
11379 <name>MECFSR</name>
11380 <instance>
11381 <name>MECFSR</name>
11382 <address>0x14</address>
11383 </instance>
11384 <register/>
11385 </node>
11386 <node>
11387 <name>MEDFSR</name>
11388 <instance>
11389 <name>MEDFSR</name>
11390 <address>0x18</address>
11391 </instance>
11392 <register/>
11393 </node>
11394 <node>
11395 <name>MESR</name>
11396 <title>ME settings register</title>
11397 <instance>
11398 <name>MESR</name>
11399 <address>0x1c</address>
11400 </instance>
11401 <register/>
11402 </node>
11403 <node>
11404 <name>MEMR</name>
11405 <title>ME MVD register</title>
11406 <instance>
11407 <name>MEMR</name>
11408 <address>0x20</address>
11409 </instance>
11410 <register/>
11411 </node>
11412 <node>
11413 <name>MEFR</name>
11414 <title>ME flag register</title>
11415 <instance>
11416 <name>MEFR</name>
11417 <address>0x24</address>
11418 </instance>
11419 <register/>
11420 </node>
11421 </node>
11422 <node>
11423 <name>DEBLK</name>
11424 <instance>
11425 <name>DEBLK</name>
11426 <address>0xb3270000</address>
11427 </instance>
11428 </node>
11429 <node>
11430 <name>IDCT</name>
11431 <instance>
11432 <name>IDCT</name>
11433 <address>0xb3280000</address>
11434 </instance>
11435 </node>
11436 <node>
11437 <name>CABAC</name>
11438 <instance>
11439 <name>CABAC</name>
11440 <address>0xb3290000</address>
11441 </instance>
11442 </node>
11443 <node>
11444 <name>TCSM0</name>
11445 <instance>
11446 <name>TCSM0</name>
11447 <address>0xb32b0000</address>
11448 </instance>
11449 </node>
11450 <node>
11451 <name>TCSM1</name>
11452 <instance>
11453 <name>TCSM1</name>
11454 <address>0xb32c0000</address>
11455 </instance>
11456 </node>
11457 <node>
11458 <name>SRAM</name>
11459 <instance>
11460 <name>SRAM</name>
11461 <address>0xb32d0000</address>
11462 </instance>
11463 </node>
11464 <node>
11465 <name>HARB2</name>
11466 <title>AHB2 BUS Devices Base</title>
11467 <instance>
11468 <name>HARB2</name>
11469 <address>0xb3400000</address>
11470 </instance>
11471 </node>
11472 <node>
11473 <name>NEMC</name>
11474 <instance>
11475 <name>NEMC</name>
11476 <address>0xb3410000</address>
11477 </instance>
11478 <node>
11479 <name>SMC</name>
11480 <instance>
11481 <name>SMC</name>
11482 <range>
11483 <first>1</first>
11484 <address>0x14</address>
11485 <address>0x18</address>
11486 <address>0x1c</address>
11487 <address>0x20</address>
11488 <address>0x24</address>
11489 <address>0x28</address>
11490 </range>
11491 </instance>
11492 <register>
11493 <field>
11494 <name>STRV</name>
11495 <position>24</position>
11496 <width>5</width>
11497 </field>
11498 <field>
11499 <name>TAW</name>
11500 <position>20</position>
11501 <width>4</width>
11502 </field>
11503 <field>
11504 <name>TBP</name>
11505 <position>16</position>
11506 <width>4</width>
11507 </field>
11508 <field>
11509 <name>TAH</name>
11510 <position>12</position>
11511 <width>4</width>
11512 </field>
11513 <field>
11514 <name>TAS</name>
11515 <position>8</position>
11516 <width>4</width>
11517 </field>
11518 <field>
11519 <name>BW</name>
11520 <position>6</position>
11521 <width>2</width>
11522 <enum>
11523 <name>8BIT</name>
11524 <value>0x0</value>
11525 </enum>
11526 <enum>
11527 <name>16BIT</name>
11528 <value>0x1</value>
11529 </enum>
11530 </field>
11531 <field>
11532 <name>BL</name>
11533 <position>1</position>
11534 <width>2</width>
11535 <enum>
11536 <name>4</name>
11537 <value>0x0</value>
11538 </enum>
11539 <enum>
11540 <name>8</name>
11541 <value>0x1</value>
11542 </enum>
11543 <enum>
11544 <name>16</name>
11545 <value>0x2</value>
11546 </enum>
11547 <enum>
11548 <name>32</name>
11549 <value>0x3</value>
11550 </enum>
11551 </field>
11552 <field>
11553 <name>SMT</name>
11554 <position>0</position>
11555 </field>
11556 </register>
11557 </node>
11558 <node>
11559 <name>SMA</name>
11560 <instance>
11561 <name>SMA</name>
11562 <range>
11563 <first>1</first>
11564 <address>0x34</address>
11565 <address>0x38</address>
11566 <address>0x3c</address>
11567 <address>0x40</address>
11568 <address>0x44</address>
11569 <address>0x48</address>
11570 </range>
11571 </instance>
11572 <register>
11573 <field>
11574 <name>BASE</name>
11575 <position>8</position>
11576 <width>8</width>
11577 </field>
11578 <field>
11579 <name>MASK</name>
11580 <position>0</position>
11581 <width>8</width>
11582 </field>
11583 </register>
11584 </node>
11585 <node>
11586 <name>NFC</name>
11587 <title>NAND Flash Control/Status Register</title>
11588 <instance>
11589 <name>NFC</name>
11590 <address>0x50</address>
11591 </instance>
11592 <register>
11593 <field>
11594 <name>NFCE4</name>
11595 <desc>NAND Flash Enable</desc>
11596 <position>7</position>
11597 </field>
11598 <field>
11599 <name>NFE4</name>
11600 <desc>NAND Flash FCE# Assertion Enable</desc>
11601 <position>6</position>
11602 </field>
11603 <field>
11604 <name>NFCE3</name>
11605 <position>5</position>
11606 </field>
11607 <field>
11608 <name>NFE3</name>
11609 <position>4</position>
11610 </field>
11611 <field>
11612 <name>NFCE2</name>
11613 <position>3</position>
11614 </field>
11615 <field>
11616 <name>NFE2</name>
11617 <position>2</position>
11618 </field>
11619 <field>
11620 <name>NFCE1</name>
11621 <position>1</position>
11622 </field>
11623 <field>
11624 <name>NFE1</name>
11625 <position>0</position>
11626 </field>
11627 </register>
11628 </node>
11629 <node>
11630 <name>PNC</name>
11631 <instance>
11632 <name>PNC</name>
11633 <address>0x100</address>
11634 </instance>
11635 <register/>
11636 </node>
11637 <node>
11638 <name>PND</name>
11639 <instance>
11640 <name>PND</name>
11641 <address>0x104</address>
11642 </instance>
11643 <register/>
11644 </node>
11645 <node>
11646 <name>BITCNT</name>
11647 <instance>
11648 <name>BITCNT</name>
11649 <address>0x108</address>
11650 </instance>
11651 <register/>
11652 </node>
11653 </node>
11654 <node>
11655 <name>DMAC</name>
11656 <title>DMAC (DMA Controller)</title>
11657 <instance>
11658 <name>DMAC</name>
11659 <address>0xb3420000</address>
11660 </instance>
11661 <node>
11662 <name>DSAR</name>
11663 <title>DMA source address</title>
11664 <instance>
11665 <name>DSAR</name>
11666 <range>
11667 <first>0</first>
11668 <count>12</count>
11669 <formula variable="n">((n)/6*0x100 + 0x00 + ((n)-(n)/6*6) * 0x20)</formula>
11670 </range>
11671 </instance>
11672 <register/>
11673 </node>
11674 <node>
11675 <name>DTAR</name>
11676 <title>DMA target address</title>
11677 <instance>
11678 <name>DTAR</name>
11679 <range>
11680 <first>0</first>
11681 <count>12</count>
11682 <formula variable="n">((n)/6*0x100 + 0x04 + ((n)-(n)/6*6) * 0x20)</formula>
11683 </range>
11684 </instance>
11685 <register/>
11686 </node>
11687 <node>
11688 <name>DTCR</name>
11689 <title>DMA transfer count</title>
11690 <instance>
11691 <name>DTCR</name>
11692 <range>
11693 <first>0</first>
11694 <count>12</count>
11695 <formula variable="n">((n)/6*0x100 + 0x08 + ((n)-(n)/6*6) * 0x20)</formula>
11696 </range>
11697 </instance>
11698 <register/>
11699 </node>
11700 <node>
11701 <name>DRSR</name>
11702 <title>DMA request source</title>
11703 <instance>
11704 <name>DRSR</name>
11705 <range>
11706 <first>0</first>
11707 <count>12</count>
11708 <formula variable="n">((n)/6*0x100 + 0x0c + ((n)-(n)/6*6) * 0x20)</formula>
11709 </range>
11710 </instance>
11711 <register>
11712 <field>
11713 <name>RS</name>
11714 <position>0</position>
11715 <width>6</width>
11716 <enum>
11717 <name>AUTO</name>
11718 <value>0x8</value>
11719 </enum>
11720 <enum>
11721 <name>TSSIIN</name>
11722 <value>0x9</value>
11723 </enum>
11724 <enum>
11725 <name>EXTERN</name>
11726 <value>0xc</value>
11727 </enum>
11728 <enum>
11729 <name>UART3OUT</name>
11730 <value>0xe</value>
11731 </enum>
11732 <enum>
11733 <name>UART3IN</name>
11734 <value>0xf</value>
11735 </enum>
11736 <enum>
11737 <name>UART2OUT</name>
11738 <value>0x10</value>
11739 </enum>
11740 <enum>
11741 <name>UART2IN</name>
11742 <value>0x11</value>
11743 </enum>
11744 <enum>
11745 <name>UART1OUT</name>
11746 <value>0x12</value>
11747 </enum>
11748 <enum>
11749 <name>UART1IN</name>
11750 <value>0x13</value>
11751 </enum>
11752 <enum>
11753 <name>UART0OUT</name>
11754 <value>0x14</value>
11755 </enum>
11756 <enum>
11757 <name>UART0IN</name>
11758 <value>0x15</value>
11759 </enum>
11760 <enum>
11761 <name>SSI0OUT</name>
11762 <value>0x16</value>
11763 </enum>
11764 <enum>
11765 <name>SSI0IN</name>
11766 <value>0x17</value>
11767 </enum>
11768 <enum>
11769 <name>AICOUT</name>
11770 <value>0x18</value>
11771 </enum>
11772 <enum>
11773 <name>AICIN</name>
11774 <value>0x19</value>
11775 </enum>
11776 <enum>
11777 <name>MSC0OUT</name>
11778 <value>0x1a</value>
11779 </enum>
11780 <enum>
11781 <name>MSC0IN</name>
11782 <value>0x1b</value>
11783 </enum>
11784 <enum>
11785 <name>TCU</name>
11786 <value>0x1c</value>
11787 </enum>
11788 <enum>
11789 <name>SADC</name>
11790 <value>0x1d</value>
11791 </enum>
11792 <enum>
11793 <name>MSC1OUT</name>
11794 <value>0x1e</value>
11795 </enum>
11796 <enum>
11797 <name>MSC1IN</name>
11798 <value>0x1f</value>
11799 </enum>
11800 <enum>
11801 <name>SSI1OUT</name>
11802 <value>0x20</value>
11803 </enum>
11804 <enum>
11805 <name>SSI1IN</name>
11806 <value>0x21</value>
11807 </enum>
11808 <enum>
11809 <name>PMOUT</name>
11810 <value>0x22</value>
11811 </enum>
11812 <enum>
11813 <name>PMIN</name>
11814 <value>0x23</value>
11815 </enum>
11816 <enum>
11817 <name>MSC2OUT</name>
11818 <value>0x24</value>
11819 </enum>
11820 <enum>
11821 <name>MSC2IN</name>
11822 <value>0x25</value>
11823 </enum>
11824 </field>
11825 </register>
11826 </node>
11827 <node>
11828 <name>DCCSR</name>
11829 <title>DMA control/status</title>
11830 <instance>
11831 <name>DCCSR</name>
11832 <range>
11833 <first>0</first>
11834 <count>12</count>
11835 <formula variable="n">((n)/6*0x100 + 0x10 + ((n)-(n)/6*6) * 0x20)</formula>
11836 </range>
11837 </instance>
11838 <register>
11839 <field>
11840 <name>NDES</name>
11841 <desc>descriptor (0) or not (1) ?</desc>
11842 <position>31</position>
11843 </field>
11844 <field>
11845 <name>DES8</name>
11846 <desc>Descriptor 8 Word</desc>
11847 <position>30</position>
11848 </field>
11849 <field>
11850 <name>CDOA</name>
11851 <desc>copy of DMA offset address</desc>
11852 <position>16</position>
11853 <width>8</width>
11854 </field>
11855 <field>
11856 <name>AR</name>
11857 <desc>address error</desc>
11858 <position>4</position>
11859 </field>
11860 <field>
11861 <name>TT</name>
11862 <desc>transfer terminated</desc>
11863 <position>3</position>
11864 </field>
11865 <field>
11866 <name>HLT</name>
11867 <desc>DMA halted</desc>
11868 <position>2</position>
11869 </field>
11870 <field>
11871 <name>CT</name>
11872 <desc>count terminated</desc>
11873 <position>1</position>
11874 </field>
11875 <field>
11876 <name>EN</name>
11877 <desc>channel enable bit</desc>
11878 <position>0</position>
11879 </field>
11880 </register>
11881 </node>
11882 <node>
11883 <name>DCMD</name>
11884 <title>DMA command</title>
11885 <instance>
11886 <name>DCMD</name>
11887 <range>
11888 <first>0</first>
11889 <count>12</count>
11890 <formula variable="n">((n)/6*0x100 + 0x14 + ((n)-(n)/6*6) * 0x20)</formula>
11891 </range>
11892 </instance>
11893 <register>
11894 <field>
11895 <name>EACKS_LOW</name>
11896 <desc>External DACK Output Level Select, active low</desc>
11897 <position>31</position>
11898 </field>
11899 <field>
11900 <name>EACKM_WRITE</name>
11901 <desc>External DACK Output Mode Select, output in write cycle</desc>
11902 <position>30</position>
11903 </field>
11904 <field>
11905 <name>ERDM</name>
11906 <desc>External DREQ Detection Mode Select</desc>
11907 <position>28</position>
11908 <width>2</width>
11909 <enum>
11910 <name>LOW</name>
11911 <value>0x0</value>
11912 </enum>
11913 <enum>
11914 <name>FALL</name>
11915 <value>0x1</value>
11916 </enum>
11917 <enum>
11918 <name>HIGH</name>
11919 <value>0x2</value>
11920 </enum>
11921 <enum>
11922 <name>RISE</name>
11923 <value>0x3</value>
11924 </enum>
11925 </field>
11926 <field>
11927 <name>SAI</name>
11928 <desc>source address increment</desc>
11929 <position>23</position>
11930 </field>
11931 <field>
11932 <name>DAI</name>
11933 <desc>dest address increment</desc>
11934 <position>22</position>
11935 </field>
11936 <field>
11937 <name>RDIL</name>
11938 <desc>request detection interval length</desc>
11939 <position>16</position>
11940 <width>4</width>
11941 <enum>
11942 <name>IGN</name>
11943 <value>0x0</value>
11944 </enum>
11945 <enum>
11946 <name>2</name>
11947 <value>0x1</value>
11948 </enum>
11949 <enum>
11950 <name>4</name>
11951 <value>0x2</value>
11952 </enum>
11953 <enum>
11954 <name>8</name>
11955 <value>0x3</value>
11956 </enum>
11957 <enum>
11958 <name>12</name>
11959 <value>0x4</value>
11960 </enum>
11961 <enum>
11962 <name>16</name>
11963 <value>0x5</value>
11964 </enum>
11965 <enum>
11966 <name>20</name>
11967 <value>0x6</value>
11968 </enum>
11969 <enum>
11970 <name>24</name>
11971 <value>0x7</value>
11972 </enum>
11973 <enum>
11974 <name>28</name>
11975 <value>0x8</value>
11976 </enum>
11977 <enum>
11978 <name>32</name>
11979 <value>0x9</value>
11980 </enum>
11981 <enum>
11982 <name>48</name>
11983 <value>0xa</value>
11984 </enum>
11985 <enum>
11986 <name>60</name>
11987 <value>0xb</value>
11988 </enum>
11989 <enum>
11990 <name>64</name>
11991 <value>0xc</value>
11992 </enum>
11993 <enum>
11994 <name>124</name>
11995 <value>0xd</value>
11996 </enum>
11997 <enum>
11998 <name>128</name>
11999 <value>0xe</value>
12000 </enum>
12001 <enum>
12002 <name>200</name>
12003 <value>0xf</value>
12004 </enum>
12005 </field>
12006 <field>
12007 <name>SWDH</name>
12008 <desc>source port width</desc>
12009 <position>14</position>
12010 <width>2</width>
12011 <enum>
12012 <name>32</name>
12013 <value>0x0</value>
12014 </enum>
12015 <enum>
12016 <name>8</name>
12017 <value>0x1</value>
12018 </enum>
12019 <enum>
12020 <name>16</name>
12021 <value>0x2</value>
12022 </enum>
12023 </field>
12024 <field>
12025 <name>DWDH</name>
12026 <desc>dest port width</desc>
12027 <position>12</position>
12028 <width>2</width>
12029 <enum>
12030 <name>32</name>
12031 <value>0x0</value>
12032 </enum>
12033 <enum>
12034 <name>8</name>
12035 <value>0x1</value>
12036 </enum>
12037 <enum>
12038 <name>16</name>
12039 <value>0x2</value>
12040 </enum>
12041 </field>
12042 <field>
12043 <name>DS</name>
12044 <desc>transfer data size of a data unit</desc>
12045 <position>8</position>
12046 <width>3</width>
12047 <enum>
12048 <name>32BIT</name>
12049 <value>0x0</value>
12050 </enum>
12051 <enum>
12052 <name>8BIT</name>
12053 <value>0x1</value>
12054 </enum>
12055 <enum>
12056 <name>16BIT</name>
12057 <value>0x2</value>
12058 </enum>
12059 <enum>
12060 <name>16BYTE</name>
12061 <value>0x3</value>
12062 </enum>
12063 <enum>
12064 <name>32BYTE</name>
12065 <value>0x4</value>
12066 </enum>
12067 <enum>
12068 <name>64BYTE</name>
12069 <value>0x5</value>
12070 </enum>
12071 </field>
12072 <field>
12073 <name>STDE</name>
12074 <desc>Stride Disable/Enable</desc>
12075 <position>2</position>
12076 </field>
12077 <field>
12078 <name>TIE</name>
12079 <desc>DMA transfer interrupt enable</desc>
12080 <position>1</position>
12081 </field>
12082 <field>
12083 <name>LINK</name>
12084 <desc>descriptor link enable</desc>
12085 <position>0</position>
12086 </field>
12087 </register>
12088 </node>
12089 <node>
12090 <name>DDA</name>
12091 <title>DMA descriptor address</title>
12092 <instance>
12093 <name>DDA</name>
12094 <range>
12095 <first>0</first>
12096 <count>12</count>
12097 <formula variable="n">((n)/6*0x100 + 0x18 + ((n)-(n)/6*6) * 0x20)</formula>
12098 </range>
12099 </instance>
12100 <register>
12101 <field>
12102 <name>BASE</name>
12103 <desc>descriptor base address</desc>
12104 <position>12</position>
12105 <width>20</width>
12106 </field>
12107 <field>
12108 <name>OFFSET</name>
12109 <desc>descriptor offset address</desc>
12110 <position>4</position>
12111 <width>8</width>
12112 </field>
12113 </register>
12114 </node>
12115 <node>
12116 <name>DSD</name>
12117 <title>DMA Stride Address</title>
12118 <instance>
12119 <name>DSD</name>
12120 <range>
12121 <first>0</first>
12122 <count>12</count>
12123 <formula variable="n">((n)/6*0x100 + 0x1c + ((n)-(n)/6*6) * 0x04)</formula>
12124 </range>
12125 </instance>
12126 <register>
12127 <field>
12128 <name>TSD</name>
12129 <desc>target stride address</desc>
12130 <position>16</position>
12131 <width>16</width>
12132 </field>
12133 <field>
12134 <name>SSD</name>
12135 <desc>source stride address</desc>
12136 <position>0</position>
12137 <width>16</width>
12138 </field>
12139 </register>
12140 </node>
12141 <node>
12142 <name>DMACR</name>
12143 <title>DMA control register</title>
12144 <instance>
12145 <name>DMACR</name>
12146 <range>
12147 <first>0</first>
12148 <count>2</count>
12149 <formula variable="m">0x0300 + 0x100 * (m)</formula>
12150 </range>
12151 </instance>
12152 <register>
12153 <field>
12154 <name>FMSC</name>
12155 <desc>MSC Fast DMA mode</desc>
12156 <position>31</position>
12157 </field>
12158 <field>
12159 <name>FSSI</name>
12160 <desc>SSI Fast DMA mode</desc>
12161 <position>30</position>
12162 </field>
12163 <field>
12164 <name>FTSSI</name>
12165 <desc>TSSI Fast DMA mode</desc>
12166 <position>29</position>
12167 </field>
12168 <field>
12169 <name>FUART</name>
12170 <desc>UART Fast DMA mode</desc>
12171 <position>28</position>
12172 </field>
12173 <field>
12174 <name>FAIC</name>
12175 <desc>AIC Fast DMA mode</desc>
12176 <position>27</position>
12177 </field>
12178 <field>
12179 <name>PR</name>
12180 <desc>channel priority mode</desc>
12181 <position>8</position>
12182 <width>2</width>
12183 <enum>
12184 <name>012345</name>
12185 <value>0x0</value>
12186 </enum>
12187 <enum>
12188 <name>120345</name>
12189 <value>0x1</value>
12190 </enum>
12191 <enum>
12192 <name>230145</name>
12193 <value>0x2</value>
12194 </enum>
12195 <enum>
12196 <name>340125</name>
12197 <value>0x3</value>
12198 </enum>
12199 </field>
12200 <field>
12201 <name>HLT</name>
12202 <desc>DMA halt flag</desc>
12203 <position>3</position>
12204 </field>
12205 <field>
12206 <name>AR</name>
12207 <desc>address error flag</desc>
12208 <position>2</position>
12209 </field>
12210 <field>
12211 <name>DMAE</name>
12212 <desc>DMA enable bit</desc>
12213 <position>0</position>
12214 </field>
12215 </register>
12216 </node>
12217 <node>
12218 <name>DMAIPR</name>
12219 <title>DMA interrupt pending</title>
12220 <instance>
12221 <name>DMAIPR</name>
12222 <range>
12223 <first>0</first>
12224 <count>2</count>
12225 <formula variable="m">0x0304 + 0x100 * (m)</formula>
12226 </range>
12227 </instance>
12228 <register>
12229 <field>
12230 <name>CIRQ5</name>
12231 <desc>irq pending status for channel 5</desc>
12232 <position>5</position>
12233 </field>
12234 <field>
12235 <name>CIRQ4</name>
12236 <desc>irq pending status for channel 4</desc>
12237 <position>4</position>
12238 </field>
12239 <field>
12240 <name>CIRQ3</name>
12241 <desc>irq pending status for channel 3</desc>
12242 <position>3</position>
12243 </field>
12244 <field>
12245 <name>CIRQ2</name>
12246 <desc>irq pending status for channel 2</desc>
12247 <position>2</position>
12248 </field>
12249 <field>
12250 <name>CIRQ1</name>
12251 <desc>irq pending status for channel 1</desc>
12252 <position>1</position>
12253 </field>
12254 <field>
12255 <name>CIRQ0</name>
12256 <desc>irq pending status for channel 0</desc>
12257 <position>0</position>
12258 </field>
12259 </register>
12260 </node>
12261 <node>
12262 <name>DMADBR</name>
12263 <title>DMA doorbell</title>
12264 <instance>
12265 <name>DMADBR</name>
12266 <range>
12267 <first>0</first>
12268 <count>2</count>
12269 <formula variable="m">0x0308 + 0x100 * (m)</formula>
12270 </range>
12271 </instance>
12272 <register>
12273 <field>
12274 <name>DB5</name>
12275 <desc>doorbell for channel 5</desc>
12276 <position>5</position>
12277 </field>
12278 <field>
12279 <name>DB4</name>
12280 <desc>doorbell for channel 4</desc>
12281 <position>4</position>
12282 </field>
12283 <field>
12284 <name>DB3</name>
12285 <desc>doorbell for channel 3</desc>
12286 <position>3</position>
12287 </field>
12288 <field>
12289 <name>DB2</name>
12290 <desc>doorbell for channel 2</desc>
12291 <position>2</position>
12292 </field>
12293 <field>
12294 <name>DB1</name>
12295 <desc>doorbell for channel 1</desc>
12296 <position>1</position>
12297 </field>
12298 <field>
12299 <name>DB0</name>
12300 <desc>doorbell for channel 0</desc>
12301 <position>0</position>
12302 </field>
12303 </register>
12304 </node>
12305 <node>
12306 <name>DMADBSR</name>
12307 <title>DMA doorbell set</title>
12308 <instance>
12309 <name>DMADBSR</name>
12310 <range>
12311 <first>0</first>
12312 <count>2</count>
12313 <formula variable="m">0x030C + 0x100 * (m)</formula>
12314 </range>
12315 </instance>
12316 <register>
12317 <field>
12318 <name>DBS5</name>
12319 <desc>enable doorbell for channel 5</desc>
12320 <position>5</position>
12321 </field>
12322 <field>
12323 <name>DBS4</name>
12324 <desc>enable doorbell for channel 4</desc>
12325 <position>4</position>
12326 </field>
12327 <field>
12328 <name>DBS3</name>
12329 <desc>enable doorbell for channel 3</desc>
12330 <position>3</position>
12331 </field>
12332 <field>
12333 <name>DBS2</name>
12334 <desc>enable doorbell for channel 2</desc>
12335 <position>2</position>
12336 </field>
12337 <field>
12338 <name>DBS1</name>
12339 <desc>enable doorbell for channel 1</desc>
12340 <position>1</position>
12341 </field>
12342 <field>
12343 <name>DBS0</name>
12344 <desc>enable doorbell for channel 0</desc>
12345 <position>0</position>
12346 </field>
12347 </register>
12348 </node>
12349 <node>
12350 <name>DMACK</name>
12351 <instance>
12352 <name>DMACK</name>
12353 <range>
12354 <first>0</first>
12355 <count>2</count>
12356 <formula variable="m">0x0310 + 0x100 * (m)</formula>
12357 </range>
12358 </instance>
12359 <register/>
12360 </node>
12361 <node>
12362 <name>DMACKS</name>
12363 <instance>
12364 <name>DMACKS</name>
12365 <range>
12366 <first>0</first>
12367 <count>2</count>
12368 <formula variable="m">0x0314 + 0x100 * (m)</formula>
12369 </range>
12370 </instance>
12371 <register/>
12372 </node>
12373 <node>
12374 <name>DMACKC</name>
12375 <instance>
12376 <name>DMACKC</name>
12377 <range>
12378 <first>0</first>
12379 <count>2</count>
12380 <formula variable="m">0x0318 + 0x100 * (m)</formula>
12381 </range>
12382 </instance>
12383 <register/>
12384 </node>
12385 </node>
12386 <node>
12387 <name>UHC</name>
12388 <instance>
12389 <name>UHC</name>
12390 <address>0xb3430000</address>
12391 </instance>
12392 </node>
12393 <node>
12394 <name>USB</name>
12395 <instance>
12396 <name>USB</name>
12397 <address>0xb3440000</address>
12398 </instance>
12399 <node>
12400 <name>FADDR</name>
12401 <title>Function Address 8-bit</title>
12402 <instance>
12403 <name>FADDR</name>
12404 <address>0x0</address>
12405 </instance>
12406 <register/>
12407 </node>
12408 <node>
12409 <name>POWER</name>
12410 <title>Power register bit masks</title>
12411 <instance>
12412 <name>POWER</name>
12413 <address>0x1</address>
12414 </instance>
12415 <register>
12416 <field>
12417 <name>SOFTCONN</name>
12418 <position>6</position>
12419 </field>
12420 <field>
12421 <name>HSENAB</name>
12422 <position>5</position>
12423 </field>
12424 <field>
12425 <name>HSMODE</name>
12426 <position>4</position>
12427 </field>
12428 <field>
12429 <name>RESUME</name>
12430 <position>2</position>
12431 </field>
12432 <field>
12433 <name>SUSPENDM</name>
12434 <position>0</position>
12435 </field>
12436 </register>
12437 </node>
12438 <node>
12439 <name>INTRIN</name>
12440 <title>Interrupt IN 16-bit</title>
12441 <instance>
12442 <name>INTRIN</name>
12443 <address>0x2</address>
12444 </instance>
12445 <register/>
12446 </node>
12447 <node>
12448 <name>INTROUT</name>
12449 <title>Interrupt OUT 16-bit</title>
12450 <instance>
12451 <name>INTROUT</name>
12452 <address>0x4</address>
12453 </instance>
12454 <register/>
12455 </node>
12456 <node>
12457 <name>INTRINE</name>
12458 <title>Intr IN enable 16-bit</title>
12459 <instance>
12460 <name>INTRINE</name>
12461 <address>0x6</address>
12462 </instance>
12463 <register/>
12464 </node>
12465 <node>
12466 <name>INTROUTE</name>
12467 <title>Intr OUT enable 16-bit</title>
12468 <instance>
12469 <name>INTROUTE</name>
12470 <address>0x8</address>
12471 </instance>
12472 <register/>
12473 </node>
12474 <node>
12475 <name>INTRUSB</name>
12476 <title>Interrupt register bit masks</title>
12477 <instance>
12478 <name>INTRUSB</name>
12479 <address>0xa</address>
12480 </instance>
12481 <register>
12482 <field>
12483 <name>RESET</name>
12484 <position>2</position>
12485 </field>
12486 <field>
12487 <name>RESUME</name>
12488 <position>1</position>
12489 </field>
12490 <field>
12491 <name>SUSPEND</name>
12492 <position>0</position>
12493 </field>
12494 </register>
12495 </node>
12496 <node>
12497 <name>INTRUSBE</name>
12498 <title>Interrupt USB Enable 8-bit</title>
12499 <instance>
12500 <name>INTRUSBE</name>
12501 <address>0xb</address>
12502 </instance>
12503 <register/>
12504 </node>
12505 <node>
12506 <name>FRAME</name>
12507 <title>Frame number 16-bit</title>
12508 <instance>
12509 <name>FRAME</name>
12510 <address>0xc</address>
12511 </instance>
12512 <register/>
12513 </node>
12514 <node>
12515 <name>INDEX</name>
12516 <title>Index register 8-bit</title>
12517 <instance>
12518 <name>INDEX</name>
12519 <address>0xe</address>
12520 </instance>
12521 <register/>
12522 </node>
12523 <node>
12524 <name>TESTMODE</name>
12525 <title>Testmode register bits</title>
12526 <instance>
12527 <name>TESTMODE</name>
12528 <address>0xf</address>
12529 </instance>
12530 <register>
12531 <field>
12532 <name>PACKET</name>
12533 <position>3</position>
12534 </field>
12535 <field>
12536 <name>K</name>
12537 <position>2</position>
12538 </field>
12539 <field>
12540 <name>J</name>
12541 <position>1</position>
12542 </field>
12543 <field>
12544 <name>SE0NAK</name>
12545 <position>0</position>
12546 </field>
12547 </register>
12548 </node>
12549 <node>
12550 <name>INMAXP</name>
12551 <title>EP1-2 IN Max Pkt Size 16-bit</title>
12552 <instance>
12553 <name>INMAXP</name>
12554 <address>0x10</address>
12555 </instance>
12556 <register/>
12557 </node>
12558 <node>
12559 <name>CSR0</name>
12560 <title>CSR0 bit masks</title>
12561 <instance>
12562 <name>CSR0</name>
12563 <address>0x12</address>
12564 </instance>
12565 <register>
12566 <field>
12567 <name>SVDSETUPEND</name>
12568 <position>7</position>
12569 </field>
12570 <field>
12571 <name>SVDOUTPKTRDY</name>
12572 <position>6</position>
12573 </field>
12574 <field>
12575 <name>SENDSTALL</name>
12576 <position>5</position>
12577 </field>
12578 <field>
12579 <name>SETUPEND</name>
12580 <position>4</position>
12581 </field>
12582 <field>
12583 <name>DATAEND</name>
12584 <position>3</position>
12585 </field>
12586 <field>
12587 <name>SENTSTALL</name>
12588 <position>2</position>
12589 </field>
12590 <field>
12591 <name>INPKTRDY</name>
12592 <position>1</position>
12593 </field>
12594 <field>
12595 <name>OUTPKTRDY</name>
12596 <position>0</position>
12597 </field>
12598 </register>
12599 </node>
12600 <node>
12601 <name>INCSR</name>
12602 <title>EP1-2 IN CSR LSB 8/16bit</title>
12603 <instance>
12604 <name>INCSR</name>
12605 <address>0x12</address>
12606 </instance>
12607 <register>
12608 <field>
12609 <name>CDT</name>
12610 <position>6</position>
12611 </field>
12612 <field>
12613 <name>SENTSTALL</name>
12614 <position>5</position>
12615 </field>
12616 <field>
12617 <name>SENDSTALL</name>
12618 <position>4</position>
12619 </field>
12620 <field>
12621 <name>FF</name>
12622 <position>3</position>
12623 </field>
12624 <field>
12625 <name>UNDERRUN</name>
12626 <position>2</position>
12627 </field>
12628 <field>
12629 <name>FFNOTEMPT</name>
12630 <position>1</position>
12631 </field>
12632 <field>
12633 <name>INPKTRDY</name>
12634 <position>0</position>
12635 </field>
12636 </register>
12637 </node>
12638 <node>
12639 <name>INCSRH</name>
12640 <title>Endpoint CSR register bits</title>
12641 <instance>
12642 <name>INCSRH</name>
12643 <address>0x13</address>
12644 </instance>
12645 <register>
12646 <field>
12647 <name>AUTOSET</name>
12648 <position>7</position>
12649 </field>
12650 <field>
12651 <name>ISO</name>
12652 <position>6</position>
12653 </field>
12654 <field>
12655 <name>MODE</name>
12656 <position>5</position>
12657 </field>
12658 <field>
12659 <name>DMAREQENAB</name>
12660 <position>4</position>
12661 </field>
12662 <field>
12663 <name>DMAREQMODE</name>
12664 <position>2</position>
12665 </field>
12666 </register>
12667 </node>
12668 <node>
12669 <name>OUTMAXP</name>
12670 <title>EP1 OUT Max Pkt Size 16-bit</title>
12671 <instance>
12672 <name>OUTMAXP</name>
12673 <address>0x14</address>
12674 </instance>
12675 <register/>
12676 </node>
12677 <node>
12678 <name>OUTCSR</name>
12679 <title>EP1 OUT CSR LSB 8/16bit</title>
12680 <instance>
12681 <name>OUTCSR</name>
12682 <address>0x16</address>
12683 </instance>
12684 <register>
12685 <field>
12686 <name>CDT</name>
12687 <position>7</position>
12688 </field>
12689 <field>
12690 <name>SENTSTALL</name>
12691 <position>6</position>
12692 </field>
12693 <field>
12694 <name>SENDSTALL</name>
12695 <position>5</position>
12696 </field>
12697 <field>
12698 <name>FF</name>
12699 <position>4</position>
12700 </field>
12701 <field>
12702 <name>DATAERR</name>
12703 <position>3</position>
12704 </field>
12705 <field>
12706 <name>OVERRUN</name>
12707 <position>2</position>
12708 </field>
12709 <field>
12710 <name>FFFULL</name>
12711 <position>1</position>
12712 </field>
12713 <field>
12714 <name>OUTPKTRDY</name>
12715 <position>0</position>
12716 </field>
12717 </register>
12718 </node>
12719 <node>
12720 <name>OUTCSRH</name>
12721 <title>EP1 OUT CSR MSB 8-bit</title>
12722 <instance>
12723 <name>OUTCSRH</name>
12724 <address>0x17</address>
12725 </instance>
12726 <register>
12727 <field>
12728 <name>AUTOCLR</name>
12729 <position>7</position>
12730 </field>
12731 <field>
12732 <name>ISO</name>
12733 <position>6</position>
12734 </field>
12735 <field>
12736 <name>DMAREQENAB</name>
12737 <position>5</position>
12738 </field>
12739 <field>
12740 <name>DNYT</name>
12741 <position>4</position>
12742 </field>
12743 <field>
12744 <name>DMAREQMODE</name>
12745 <position>3</position>
12746 </field>
12747 </register>
12748 </node>
12749 <node>
12750 <name>OUTCOUNT</name>
12751 <title>bytes in EP0/1 OUT FIFO 16-bit</title>
12752 <instance>
12753 <name>OUTCOUNT</name>
12754 <address>0x18</address>
12755 </instance>
12756 <register/>
12757 </node>
12758 <node>
12759 <name>FIFO_EP0</name>
12760 <instance>
12761 <name>FIFO_EP0</name>
12762 <address>0x20</address>
12763 </instance>
12764 <register/>
12765 </node>
12766 <node>
12767 <name>FIFO_EP1</name>
12768 <instance>
12769 <name>FIFO_EP1</name>
12770 <address>0x24</address>
12771 </instance>
12772 <register/>
12773 </node>
12774 <node>
12775 <name>FIFO_EP2</name>
12776 <instance>
12777 <name>FIFO_EP2</name>
12778 <address>0x28</address>
12779 </instance>
12780 <register/>
12781 </node>
12782 <node>
12783 <name>EPINFO</name>
12784 <title>Endpoint information</title>
12785 <instance>
12786 <name>EPINFO</name>
12787 <address>0x78</address>
12788 </instance>
12789 <register/>
12790 </node>
12791 <node>
12792 <name>RAMINFO</name>
12793 <title>RAM information</title>
12794 <instance>
12795 <name>RAMINFO</name>
12796 <address>0x79</address>
12797 </instance>
12798 <register/>
12799 </node>
12800 <node>
12801 <name>INTR</name>
12802 <title>DMA pending interrupts</title>
12803 <instance>
12804 <name>INTR</name>
12805 <address>0x200</address>
12806 </instance>
12807 <register/>
12808 </node>
12809 <node>
12810 <name>CNTL</name>
12811 <title>DMA control bits</title>
12812 <instance>
12813 <name>CNTL</name>
12814 <range>
12815 <first>1</first>
12816 <address>0x204</address>
12817 <address>0x214</address>
12818 </range>
12819 </instance>
12820 <register>
12821 <field>
12822 <name>BURST</name>
12823 <position>9</position>
12824 <width>2</width>
12825 <enum>
12826 <name>0</name>
12827 <value>0x0</value>
12828 </enum>
12829 <enum>
12830 <name>4</name>
12831 <value>0x1</value>
12832 </enum>
12833 <enum>
12834 <name>8</name>
12835 <value>0x2</value>
12836 </enum>
12837 <enum>
12838 <name>16</name>
12839 <value>0x3</value>
12840 </enum>
12841 </field>
12842 <field>
12843 <name>INTR_EN</name>
12844 <position>3</position>
12845 </field>
12846 <field>
12847 <name>MODE_1</name>
12848 <position>2</position>
12849 </field>
12850 <field>
12851 <name>DIR_IN</name>
12852 <position>1</position>
12853 </field>
12854 <field>
12855 <name>ENA</name>
12856 <position>0</position>
12857 </field>
12858 </register>
12859 </node>
12860 <node>
12861 <name>ADDR</name>
12862 <title>DMA channel 2 AHB memory addr</title>
12863 <instance>
12864 <name>ADDR</name>
12865 <range>
12866 <first>1</first>
12867 <address>0x208</address>
12868 <address>0x218</address>
12869 </range>
12870 </instance>
12871 <register/>
12872 </node>
12873 <node>
12874 <name>COUNT</name>
12875 <title>DMA channel 2 byte count</title>
12876 <instance>
12877 <name>COUNT</name>
12878 <range>
12879 <first>1</first>
12880 <address>0x20c</address>
12881 <address>0x21c</address>
12882 </range>
12883 </instance>
12884 <register/>
12885 </node>
12886 </node>
12887 <node>
12888 <name>BDMAC</name>
12889 <title>BDMAC (BCH &amp; NAND DMA Controller)</title>
12890 <instance>
12891 <name>BDMAC</name>
12892 <address>0xb3450000</address>
12893 </instance>
12894 <node>
12895 <name>DSA</name>
12896 <title>DMA source address</title>
12897 <instance>
12898 <name>DSA</name>
12899 <range>
12900 <first>0</first>
12901 <count>3</count>
12902 <formula variable="n">(0x00 + (n) * 0x20)</formula>
12903 </range>
12904 </instance>
12905 <register/>
12906 </node>
12907 <node>
12908 <name>DTA</name>
12909 <title>DMA target address</title>
12910 <instance>
12911 <name>DTA</name>
12912 <range>
12913 <first>0</first>
12914 <count>3</count>
12915 <formula variable="n">(0x04 + (n) * 0x20)</formula>
12916 </range>
12917 </instance>
12918 <register/>
12919 </node>
12920 <node>
12921 <name>DTC</name>
12922 <title>DMA transfer count</title>
12923 <instance>
12924 <name>DTC</name>
12925 <range>
12926 <first>0</first>
12927 <count>3</count>
12928 <formula variable="n">(0x08 + (n) * 0x20)</formula>
12929 </range>
12930 </instance>
12931 <register/>
12932 </node>
12933 <node>
12934 <name>DRT</name>
12935 <title>BDMA request source register</title>
12936 <instance>
12937 <name>DRT</name>
12938 <range>
12939 <first>0</first>
12940 <count>3</count>
12941 <formula variable="n">(0x0c + (n) * 0x20)</formula>
12942 </range>
12943 </instance>
12944 <register>
12945 <field>
12946 <name>RS</name>
12947 <position>0</position>
12948 <width>6</width>
12949 <enum>
12950 <name>BCH_ENC</name>
12951 <value>0x2</value>
12952 </enum>
12953 <enum>
12954 <name>BCH_DEC</name>
12955 <value>0x3</value>
12956 </enum>
12957 <enum>
12958 <name>NAND0</name>
12959 <value>0x6</value>
12960 </enum>
12961 <enum>
12962 <name>NAND1</name>
12963 <value>0x7</value>
12964 </enum>
12965 <enum>
12966 <name>AUTO</name>
12967 <value>0x8</value>
12968 </enum>
12969 <enum>
12970 <name>EXT</name>
12971 <value>0xc</value>
12972 </enum>
12973 </field>
12974 </register>
12975 </node>
12976 <node>
12977 <name>DCS</name>
12978 <title>BDMA channel control/status register</title>
12979 <instance>
12980 <name>DCS</name>
12981 <range>
12982 <first>0</first>
12983 <count>3</count>
12984 <formula variable="n">(0x10 + (n) * 0x20)</formula>
12985 </range>
12986 </instance>
12987 <register>
12988 <field>
12989 <name>NDES</name>
12990 <desc>descriptor (0) or not (1) ?</desc>
12991 <position>31</position>
12992 </field>
12993 <field>
12994 <name>DES8</name>
12995 <desc>Descriptor 8 Word</desc>
12996 <position>30</position>
12997 </field>
12998 <field>
12999 <name>LASTMD1</name>
13000 <desc>BCH Decoding last mode 1, there's two descriptor for decoding blcok</desc>
13001 <position>28</position>
13002 </field>
13003 <field>
13004 <name>CDOA</name>
13005 <desc>copy of DMA offset address</desc>
13006 <position>16</position>
13007 <width>8</width>
13008 </field>
13009 <field>
13010 <name>BERR</name>
13011 <desc>BCH error within this transfer, Only for channel 0</desc>
13012 <position>7</position>
13013 <width>5</width>
13014 </field>
13015 <field>
13016 <name>BUERR</name>
13017 <desc>BCH uncorrectable error, only for channel 0</desc>
13018 <position>6</position>
13019 </field>
13020 <field>
13021 <name>NSERR</name>
13022 <desc>status error, only for channel 1</desc>
13023 <position>5</position>
13024 </field>
13025 <field>
13026 <name>AR</name>
13027 <desc>address error</desc>
13028 <position>4</position>
13029 </field>
13030 <field>
13031 <name>TT</name>
13032 <desc>transfer terminated</desc>
13033 <position>3</position>
13034 </field>
13035 <field>
13036 <name>HLT</name>
13037 <desc>DMA halted</desc>
13038 <position>2</position>
13039 </field>
13040 <field>
13041 <name>BAC</name>
13042 <desc>BCH auto correction</desc>
13043 <position>1</position>
13044 </field>
13045 <field>
13046 <name>EN</name>
13047 <desc>channel enable bit</desc>
13048 <position>0</position>
13049 </field>
13050 </register>
13051 </node>
13052 <node>
13053 <name>DCM</name>
13054 <title>BDMA channel command register</title>
13055 <instance>
13056 <name>DCM</name>
13057 <range>
13058 <first>0</first>
13059 <count>3</count>
13060 <formula variable="n">(0x14 + (n) * 0x20)</formula>
13061 </range>
13062 </instance>
13063 <register>
13064 <field>
13065 <name>EACKS_LOW</name>
13066 <desc>External DACK Output Level Select, active low</desc>
13067 <position>31</position>
13068 </field>
13069 <field>
13070 <name>EACKM_WRITE</name>
13071 <desc>External DACK Output Mode Select, output in write cycle</desc>
13072 <position>30</position>
13073 </field>
13074 <field>
13075 <name>ERDM</name>
13076 <desc>External DREQ Detection Mode Select</desc>
13077 <position>28</position>
13078 <width>2</width>
13079 <enum>
13080 <name>LOW</name>
13081 <value>0x0</value>
13082 </enum>
13083 <enum>
13084 <name>FALL</name>
13085 <value>0x1</value>
13086 </enum>
13087 <enum>
13088 <name>HIGH</name>
13089 <value>0x2</value>
13090 </enum>
13091 <enum>
13092 <name>RISE</name>
13093 <value>0x3</value>
13094 </enum>
13095 </field>
13096 <field>
13097 <name>BLAST</name>
13098 <desc>BCH last</desc>
13099 <position>25</position>
13100 </field>
13101 <field>
13102 <name>SAI</name>
13103 <desc>source address increment</desc>
13104 <position>23</position>
13105 </field>
13106 <field>
13107 <name>DAI</name>
13108 <desc>dest address increment</desc>
13109 <position>22</position>
13110 </field>
13111 <field>
13112 <name>SWDH</name>
13113 <desc>source port width</desc>
13114 <position>14</position>
13115 <width>2</width>
13116 <enum>
13117 <name>32</name>
13118 <value>0x0</value>
13119 </enum>
13120 <enum>
13121 <name>8</name>
13122 <value>0x1</value>
13123 </enum>
13124 <enum>
13125 <name>16</name>
13126 <value>0x2</value>
13127 </enum>
13128 </field>
13129 <field>
13130 <name>DWDH</name>
13131 <desc>dest port width</desc>
13132 <position>12</position>
13133 <width>2</width>
13134 <enum>
13135 <name>32</name>
13136 <value>0x0</value>
13137 </enum>
13138 <enum>
13139 <name>8</name>
13140 <value>0x1</value>
13141 </enum>
13142 <enum>
13143 <name>16</name>
13144 <value>0x2</value>
13145 </enum>
13146 </field>
13147 <field>
13148 <name>DS</name>
13149 <desc>transfer data size of a data unit</desc>
13150 <position>8</position>
13151 <width>3</width>
13152 <enum>
13153 <name>32BIT</name>
13154 <value>0x0</value>
13155 </enum>
13156 <enum>
13157 <name>8BIT</name>
13158 <value>0x1</value>
13159 </enum>
13160 <enum>
13161 <name>16BIT</name>
13162 <value>0x2</value>
13163 </enum>
13164 <enum>
13165 <name>16BYTE</name>
13166 <value>0x3</value>
13167 </enum>
13168 <enum>
13169 <name>32BYTE</name>
13170 <value>0x4</value>
13171 </enum>
13172 <enum>
13173 <name>64BYTE</name>
13174 <value>0x5</value>
13175 </enum>
13176 </field>
13177 <field>
13178 <name>NRD</name>
13179 <desc>NAND direct read</desc>
13180 <position>7</position>
13181 </field>
13182 <field>
13183 <name>NWR</name>
13184 <desc>NAND direct write</desc>
13185 <position>6</position>
13186 </field>
13187 <field>
13188 <name>NAC</name>
13189 <desc>NAND AL/CL enable</desc>
13190 <position>5</position>
13191 </field>
13192 <field>
13193 <name>STDE</name>
13194 <desc>Stride Disable/Enable</desc>
13195 <position>2</position>
13196 </field>
13197 <field>
13198 <name>TIE</name>
13199 <desc>DMA transfer interrupt enable</desc>
13200 <position>1</position>
13201 </field>
13202 <field>
13203 <name>LINK</name>
13204 <desc>descriptor link enable</desc>
13205 <position>0</position>
13206 </field>
13207 </register>
13208 </node>
13209 <node>
13210 <name>DDA</name>
13211 <title>BDMA descriptor address register</title>
13212 <instance>
13213 <name>DDA</name>
13214 <range>
13215 <first>0</first>
13216 <count>3</count>
13217 <formula variable="n">(0x18 + (n) * 0x20)</formula>
13218 </range>
13219 </instance>
13220 <register>
13221 <field>
13222 <name>BASE</name>
13223 <desc>descriptor base address</desc>
13224 <position>12</position>
13225 <width>20</width>
13226 </field>
13227 <field>
13228 <name>OFFSET</name>
13229 <desc>descriptor offset address</desc>
13230 <position>4</position>
13231 <width>8</width>
13232 </field>
13233 </register>
13234 </node>
13235 <node>
13236 <name>DSD</name>
13237 <title>BDMA stride address register</title>
13238 <instance>
13239 <name>DSD</name>
13240 <range>
13241 <first>0</first>
13242 <count>3</count>
13243 <formula variable="n">(0x1c + (n) * 0x20)</formula>
13244 </range>
13245 </instance>
13246 <register>
13247 <field>
13248 <name>TSD</name>
13249 <desc>target stride address</desc>
13250 <position>16</position>
13251 <width>16</width>
13252 </field>
13253 <field>
13254 <name>SSD</name>
13255 <desc>source stride address</desc>
13256 <position>0</position>
13257 <width>16</width>
13258 </field>
13259 </register>
13260 </node>
13261 <node>
13262 <name>DNT</name>
13263 <title>BDMA NAND Detect timer register</title>
13264 <instance>
13265 <name>DNT</name>
13266 <range>
13267 <first>0</first>
13268 <count>3</count>
13269 <formula variable="n">(0xc0 + (n) * 0x04)</formula>
13270 </range>
13271 </instance>
13272 <register>
13273 <field>
13274 <name>DTCT</name>
13275 <desc>tail counter</desc>
13276 <position>16</position>
13277 <width>7</width>
13278 </field>
13279 <field>
13280 <name>DNTE</name>
13281 <desc>enable detect timer</desc>
13282 <position>15</position>
13283 </field>
13284 <field>
13285 <name>DNT</name>
13286 <desc>detect counter</desc>
13287 <position>0</position>
13288 <width>6</width>
13289 </field>
13290 </register>
13291 </node>
13292 <node>
13293 <name>DMAC</name>
13294 <title>BDMA control register</title>
13295 <instance>
13296 <name>DMAC</name>
13297 <address>0x300</address>
13298 </instance>
13299 <register>
13300 <field>
13301 <name>PR</name>
13302 <desc>channel priority mode</desc>
13303 <position>8</position>
13304 <width>2</width>
13305 <enum>
13306 <name>01_2</name>
13307 <value>0x0</value>
13308 </enum>
13309 <enum>
13310 <name>12_0</name>
13311 <value>0x1</value>
13312 </enum>
13313 <enum>
13314 <name>20_1</name>
13315 <value>0x2</value>
13316 </enum>
13317 <enum>
13318 <name>012</name>
13319 <value>0x3</value>
13320 </enum>
13321 </field>
13322 <field>
13323 <name>HLT</name>
13324 <desc>DMA halt flag</desc>
13325 <position>3</position>
13326 </field>
13327 <field>
13328 <name>AR</name>
13329 <desc>address error flag</desc>
13330 <position>2</position>
13331 </field>
13332 <field>
13333 <name>DMAE</name>
13334 <desc>DMA enable bit</desc>
13335 <position>0</position>
13336 </field>
13337 </register>
13338 </node>
13339 <node>
13340 <name>DIRQP</name>
13341 <title>BDMA interrupt pending register</title>
13342 <instance>
13343 <name>DIRQP</name>
13344 <address>0x304</address>
13345 </instance>
13346 <register>
13347 <field>
13348 <name>CIRQ2</name>
13349 <desc>irq pending status for channel 2</desc>
13350 <position>2</position>
13351 </field>
13352 <field>
13353 <name>CIRQ1</name>
13354 <desc>irq pending status for channel 1</desc>
13355 <position>1</position>
13356 </field>
13357 <field>
13358 <name>CIRQ0</name>
13359 <desc>irq pending status for channel 0</desc>
13360 <position>0</position>
13361 </field>
13362 </register>
13363 </node>
13364 <node>
13365 <name>DDR</name>
13366 <title>BDMA doorbell register</title>
13367 <instance>
13368 <name>DDR</name>
13369 <address>0x308</address>
13370 </instance>
13371 <register>
13372 <field>
13373 <name>DB2</name>
13374 <desc>doorbell for channel 2</desc>
13375 <position>2</position>
13376 </field>
13377 <field>
13378 <name>DB1</name>
13379 <desc>doorbell for channel 1</desc>
13380 <position>1</position>
13381 </field>
13382 <field>
13383 <name>DB0</name>
13384 <desc>doorbell for channel 0</desc>
13385 <position>0</position>
13386 </field>
13387 </register>
13388 </node>
13389 <node>
13390 <name>DDRS</name>
13391 <title>BDMA doorbell set register</title>
13392 <instance>
13393 <name>DDRS</name>
13394 <address>0x30c</address>
13395 </instance>
13396 <register>
13397 <field>
13398 <name>DBS2</name>
13399 <desc>enable doorbell for channel 2</desc>
13400 <position>2</position>
13401 </field>
13402 <field>
13403 <name>DBS1</name>
13404 <desc>enable doorbell for channel 1</desc>
13405 <position>1</position>
13406 </field>
13407 <field>
13408 <name>DBS0</name>
13409 <desc>enable doorbell for channel 0</desc>
13410 <position>0</position>
13411 </field>
13412 </register>
13413 </node>
13414 <node>
13415 <name>DCKE</name>
13416 <title>DMA clock enable</title>
13417 <instance>
13418 <name>DCKE</name>
13419 <address>0x310</address>
13420 </instance>
13421 <register/>
13422 </node>
13423 <node>
13424 <name>DCKES</name>
13425 <instance>
13426 <name>DCKES</name>
13427 <address>0x314</address>
13428 </instance>
13429 <register/>
13430 </node>
13431 <node>
13432 <name>DCKEC</name>
13433 <instance>
13434 <name>DCKEC</name>
13435 <address>0x318</address>
13436 </instance>
13437 <register/>
13438 </node>
13439 </node>
13440 <node>
13441 <name>GPS</name>
13442 <instance>
13443 <name>GPS</name>
13444 <address>0xb3480000</address>
13445 </instance>
13446 </node>
13447 <node>
13448 <name>ETHC</name>
13449 <instance>
13450 <name>ETHC</name>
13451 <address>0xb34b0000</address>
13452 </instance>
13453 </node>
13454 <node>
13455 <name>BCH</name>
13456 <instance>
13457 <name>BCH</name>
13458 <address>0xb34d0000</address>
13459 </instance>
13460 <node>
13461 <name>CTRL</name>
13462 <title>BCH Control register</title>
13463 <instance>
13464 <name>CTRL</name>
13465 <address>0x0</address>
13466 </instance>
13467 <register>
13468 <field>
13469 <name>DMAE</name>
13470 <desc>BCH DMA Enable</desc>
13471 <position>7</position>
13472 </field>
13473 <field>
13474 <name>BSEL</name>
13475 <desc>24 Bit BCH Select</desc>
13476 <position>3</position>
13477 <width>3</width>
13478 <enum>
13479 <name>4</name>
13480 <value>0x0</value>
13481 </enum>
13482 <enum>
13483 <name>8</name>
13484 <value>0x1</value>
13485 </enum>
13486 <enum>
13487 <name>12</name>
13488 <value>0x2</value>
13489 </enum>
13490 <enum>
13491 <name>16</name>
13492 <value>0x3</value>
13493 </enum>
13494 <enum>
13495 <name>20</name>
13496 <value>0x4</value>
13497 </enum>
13498 <enum>
13499 <name>24</name>
13500 <value>0x5</value>
13501 </enum>
13502 </field>
13503 <field>
13504 <name>ENCE</name>
13505 <desc>BCH Encoding Select</desc>
13506 <position>2</position>
13507 </field>
13508 <field>
13509 <name>BRST</name>
13510 <desc>BCH Reset</desc>
13511 <position>1</position>
13512 </field>
13513 <field>
13514 <name>BCHE</name>
13515 <desc>BCH Enable</desc>
13516 <position>0</position>
13517 </field>
13518 <variant>
13519 <type>set</type>
13520 <offset>4</offset>
13521 </variant>
13522 <variant>
13523 <type>clr</type>
13524 <offset>8</offset>
13525 </variant>
13526 </register>
13527 </node>
13528 <node>
13529 <name>COUNT</name>
13530 <title>BCH ENC/DEC Count Register</title>
13531 <instance>
13532 <name>COUNT</name>
13533 <address>0xc</address>
13534 </instance>
13535 <register>
13536 <field>
13537 <name>DEC</name>
13538 <position>16</position>
13539 <width>11</width>
13540 </field>
13541 <field>
13542 <name>ENC</name>
13543 <position>0</position>
13544 <width>11</width>
13545 </field>
13546 </register>
13547 </node>
13548 <node>
13549 <name>DATA</name>
13550 <title>BCH data register</title>
13551 <instance>
13552 <name>DATA</name>
13553 <address>0x10</address>
13554 </instance>
13555 <register>
13556 <width>8</width>
13557 </register>
13558 </node>
13559 <node>
13560 <name>PARITY</name>
13561 <title>BCH Parity register</title>
13562 <instance>
13563 <name>PARITY</name>
13564 <range>
13565 <first>0</first>
13566 <count>12</count>
13567 <formula variable="n">0x14 + 4 *(n)</formula>
13568 </range>
13569 </instance>
13570 <register/>
13571 </node>
13572 <node>
13573 <name>ERROR</name>
13574 <title>BCH Error Report Register</title>
13575 <instance>
13576 <name>ERROR</name>
13577 <range>
13578 <first>0</first>
13579 <count>12</count>
13580 <formula variable="n">0x3C + 4*(n)</formula>
13581 </range>
13582 </instance>
13583 <register>
13584 <field>
13585 <name>INDEX_ODD</name>
13586 <position>16</position>
13587 <width>13</width>
13588 </field>
13589 <field>
13590 <name>INDEX_EVEN</name>
13591 <position>0</position>
13592 <width>13</width>
13593 </field>
13594 </register>
13595 </node>
13596 <node>
13597 <name>INTS</name>
13598 <title>BCH Interrupt Status Register</title>
13599 <instance>
13600 <name>INTS</name>
13601 <address>0x6c</address>
13602 </instance>
13603 <register>
13604 <field>
13605 <name>ERRC</name>
13606 <position>27</position>
13607 <width>5</width>
13608 </field>
13609 <field>
13610 <name>ALL0</name>
13611 <position>5</position>
13612 </field>
13613 <field>
13614 <name>ALLf</name>
13615 <position>4</position>
13616 </field>
13617 <field>
13618 <name>DECF</name>
13619 <position>3</position>
13620 </field>
13621 <field>
13622 <name>ENCF</name>
13623 <position>2</position>
13624 </field>
13625 <field>
13626 <name>UNCOR</name>
13627 <position>1</position>
13628 </field>
13629 <field>
13630 <name>ERR</name>
13631 <position>0</position>
13632 </field>
13633 </register>
13634 </node>
13635 <node>
13636 <name>INTE</name>
13637 <title>BCH Interrupt Enable register</title>
13638 <instance>
13639 <name>INTE</name>
13640 <address>0x70</address>
13641 </instance>
13642 <register/>
13643 </node>
13644 </node>
13645</soc>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-27 09:27:36 +0000