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1<?xml version="1.0"?>
2<soc version="2">
3 <name>vsoc2000</name>
4 <title>Virtual SOC 2000</title>
5 <desc>Virtual SoC 2000 is a nice chip. Its quad-core architecture with trustzone makes it super powerful.</desc>
6 <author>Amaury Pouly</author>
7 <isa>ARM</isa>
8 <version>0.5</version>
9 <node>
10 <name>int</name>
11 <title>Interrupt Collector</title>
12 <desc>The interrupt collector controls the routing of the interrupts to the processors. It has 32 interrupts sources, which can be routed as FIQ or IRQ to the either processor.</desc>
13 <instance>
14 <name>ICOLL</name>
15 <title>Interrupt collector</title>
16 <address>0x80000000</address>
17 </instance>
18 <node>
19 <name>ctrl</name>
20 <title>Control register</title>
21 <instance>
22 <name>CTRL</name>
23 <address>0x0</address>
24 </instance>
25 <register>
26 <width>8</width>
27 <field>
28 <name>CLKGATE</name>
29 <desc>Clock gating control. This bit can be protected by TZ lock.</desc>
30 <position>7</position>
31 </field>
32 <field>
33 <name>SFTRST</name>
34 <desc>Soft reset, the bit will automatically reset to 0 when reset is completed. This bit can be protected by TZ lock.</desc>
35 <position>6</position>
36 </field>
37 <field>
38 <name>TZ_LOCK</name>
39 <desc>Trust Zone lock</desc>
40 <position>5</position>
41 <enum>
42 <name>UNLOCKED</name>
43 <value>0x0</value>
44 </enum>
45 <enum>
46 <name>LOCKED</name>
47 <desc>When the interrupt collector is locked, only a secured processor can modify protected fields.</desc>
48 <value>0x1</value>
49 </enum>
50 </field>
51 <variant>
52 <type>set</type>
53 <offset>4</offset>
54 </variant>
55 <variant>
56 <type>clr</type>
57 <offset>8</offset>
58 </variant>
59 </register>
60 </node>
61 <node>
62 <name>status</name>
63 <title>Interrupt status register</title>
64 <instance>
65 <name>STATUS</name>
66 <address>0x10</address>
67 </instance>
68 <register>
69 <field>
70 <name>STATUS</name>
71 <desc>Bit is set to 1 is the interrupt is pending, write a 1 to the clear variant to clear it. Secured interrupts can only be cleared or polled by secured processors (non-secure will always read 0 for those).</desc>
72 <position>0</position>
73 <width>32</width>
74 </field>
75 <variant>
76 <type>clr</type>
77 <offset>8</offset>
78 </variant>
79 </register>
80 </node>
81 <node>
82 <name>enable</name>
83 <title>Interrupt enable register</title>
84 <instance>
85 <name>ENABLE</name>
86 <range>
87 <first>0</first>
88 <count>32</count>
89 <base>0x20</base>
90 <stride>0x10</stride>
91 </range>
92 </instance>
93 <register>
94 <width>16</width>
95 <desc>This register controls the routing of the interrupt</desc>
96 <field>
97 <name>CPU3_PRIO</name>
98 <desc>Interrupt priority</desc>
99 <position>14</position>
100 <width>2</width>
101 <enum>
102 <name>MASKED</name>
103 <desc>Interrupt is masked</desc>
104 <value>0x0</value>
105 </enum>
106 <enum>
107 <name>LOW</name>
108 <value>0x1</value>
109 </enum>
110 <enum>
111 <name>HIGH</name>
112 <value>0x2</value>
113 </enum>
114 <enum>
115 <name>NMI</name>
116 <desc>Interrupt is non maskable</desc>
117 <value>0x3</value>
118 </enum>
119 </field>
120 <field>
121 <name>CPU3_TYPE</name>
122 <desc>Interrupt type</desc>
123 <position>13</position>
124 <enum>
125 <name>IRQ</name>
126 <value>0x0</value>
127 </enum>
128 <enum>
129 <name>FIQ</name>
130 <value>0x1</value>
131 </enum>
132 </field>
133 <field>
134 <name>CPU3_TZ</name>
135 <desc>Trust Zone interrupt: when set, only a secured processor can modify the parameters for secured interrupts.</desc>
136 <position>12</position>
137 </field>
138 <field>
139 <name>CPU2_PRIO</name>
140 <position>10</position>
141 <width>2</width>
142 <enum>
143 <name>MASKED</name>
144 <desc>Interrupt is masked</desc>
145 <value>0x0</value>
146 </enum>
147 <enum>
148 <name>LOW</name>
149 <value>0x1</value>
150 </enum>
151 <enum>
152 <name>HIGH</name>
153 <value>0x2</value>
154 </enum>
155 <enum>
156 <name>NMI</name>
157 <desc>Interrupt is non maskable</desc>
158 <value>0x3</value>
159 </enum>
160 </field>
161 <field>
162 <name>CPU2_TYPE</name>
163 <desc>Interrupt type</desc>
164 <position>9</position>
165 <enum>
166 <name>IRQ</name>
167 <value>0x0</value>
168 </enum>
169 <enum>
170 <name>FIQ</name>
171 <value>0x1</value>
172 </enum>
173 </field>
174 <field>
175 <name>CPU2_TZ</name>
176 <desc>Trust Zone interrupt: when set, only a secured processor can modify the parameters for secured interrupts.</desc>
177 <position>8</position>
178 </field>
179 <field>
180 <name>CPU1_PRIO</name>
181 <desc>Interrupt priority</desc>
182 <position>6</position>
183 <width>2</width>
184 <enum>
185 <name>MASKED</name>
186 <desc>Interrupt is masked</desc>
187 <value>0x0</value>
188 </enum>
189 <enum>
190 <name>LOW</name>
191 <value>0x1</value>
192 </enum>
193 <enum>
194 <name>HIGH</name>
195 <value>0x2</value>
196 </enum>
197 <enum>
198 <name>NMI</name>
199 <desc>Interrupt is non maskable</desc>
200 <value>0x3</value>
201 </enum>
202 </field>
203 <field>
204 <name>CPU1_TYPE</name>
205 <desc>Interrupt type</desc>
206 <position>5</position>
207 <enum>
208 <name>IRQ</name>
209 <value>0x0</value>
210 </enum>
211 <enum>
212 <name>FIQ</name>
213 <value>0x1</value>
214 </enum>
215 </field>
216 <field>
217 <name>CPU1_TZ</name>
218 <desc>Trust Zone interrupt: when set, only a secured processor can modify the parameters for secured interrupts.</desc>
219 <position>4</position>
220 </field>
221 <field>
222 <name>CPU0_PRIO</name>
223 <desc>Interrupt priority</desc>
224 <position>2</position>
225 <width>2</width>
226 <enum>
227 <name>MASKED</name>
228 <desc>Interrupt will never be sent to the CPU</desc>
229 <value>0x0</value>
230 </enum>
231 <enum>
232 <name>LOW</name>
233 <value>0x1</value>
234 </enum>
235 <enum>
236 <name>HIGH</name>
237 <value>0x2</value>
238 </enum>
239 <enum>
240 <name>NMI</name>
241 <desc>Interrupt is non maskable</desc>
242 <value>0x3</value>
243 </enum>
244 </field>
245 <field>
246 <name>CPU0_TYPE</name>
247 <desc>Interrupt type</desc>
248 <position>1</position>
249 <enum>
250 <name>IRQ</name>
251 <value>0x0</value>
252 </enum>
253 <enum>
254 <name>FIQ</name>
255 <value>0x1</value>
256 </enum>
257 </field>
258 <field>
259 <name>CPU0_TZ</name>
260 <desc>Trust Zone interrupt: when set, only a secured processor can modify the parameters for secured interrupts.</desc>
261 <position>0</position>
262 </field>
263 <variant>
264 <type>set</type>
265 <offset>4</offset>
266 </variant>
267 <variant>
268 <type>clr</type>
269 <offset>8</offset>
270 </variant>
271 </register>
272 </node>
273 </node>
274 <node>
275 <name>gpio</name>
276 <title>GPIO controller</title>
277 <desc>A GPIO controller manages several ports.</desc>
278 <instance>
279 <name>CPU_GPIO</name>
280 <title>CPU GPIO controllers 1 through 7</title>
281 <range>
282 <first>1</first>
283 <count>8</count>
284 <formula variable="n">0x80001000+(n-1)*0x1000</formula>
285 </range>
286 </instance>
287 <node>
288 <name>port</name>
289 <title>GPIO port</title>
290 <instance>
291 <name>PORT</name>
292 <range>
293 <first>0</first>
294 <count>2</count>
295 <base>0x0</base>
296 <stride>0x100</stride>
297 </range>
298 </instance>
299 <node>
300 <name>input</name>
301 <title>Input register</title>
302 <instance>
303 <name>IN</name>
304 <address>0x0</address>
305 </instance>
306 <register>
307 <width>8</width>
308 <field>
309 <name>VALUE</name>
310 <position>0</position>
311 <width>8</width>
312 </field>
313 </register>
314 </node>
315 <node>
316 <name>output_enable</name>
317 <title>Output enable register</title>
318 <instance>
319 <name>OE</name>
320 <address>0x10</address>
321 </instance>
322 <register>
323 <width>8</width>
324 <field>
325 <name>ENABLE</name>
326 <position>0</position>
327 <width>8</width>
328 </field>
329 <variant>
330 <type>set</type>
331 <offset>4</offset>
332 </variant>
333 <variant>
334 <type>clr</type>
335 <offset>8</offset>
336 </variant>
337 <variant>
338 <type>mask</type>
339 <offset>12</offset>
340 </variant>
341 </register>
342 </node>
343 </node>
344 </node>
345 <node>
346 <name>tz</name>
347 <title>Trust Zone</title>
348 <instance>
349 <name>TZ</name>
350 <address>0xa0000000</address>
351 </instance>
352 <node>
353 <name>ctrl</name>
354 <title>Control Register</title>
355 <instance>
356 <name>CTRL</name>
357 <address>0x0</address>
358 </instance>
359 <register>
360 <width>8</width>
361 <field>
362 <name>SCRATCH</name>
363 <desc>TZ protected scratch value</desc>
364 <position>4</position>
365 <width>4</width>
366 </field>
367 <field>
368 <name>DISABLE</name>
369 <desc>One bit per CPU: set to 1 to prevent the processor from being able to enter TZ mode. Can only be set by a secured processor. By default all processors can enter TZ mode.</desc>
370 <position>0</position>
371 <width>4</width>
372 </field>
373 </register>
374 </node>
375 <node>
376 <name>debug</name>
377 <title>Debug register</title>
378 <instance>
379 <name>DEBUG</name>
380 <title>Debug register</title>
381 <desc>Don't touch it!</desc>
382 <range>
383 <first>42</first>
384 <address>0x50</address>
385 <address>0x60</address>
386 <address>0x90</address>
387 <address>0x110</address>
388 <address>0x130</address>
389 </range>
390 </instance>
391 <register>
392 <width>8</width>
393 </register>
394 </node>
395 </node>
396</soc>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-24 15:25:23 +0000