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Diffstat (limited to 'utils/hwstub/stub/jz4760b/jz4760b.h')
-rw-r--r-- | utils/hwstub/stub/jz4760b/jz4760b.h | 9613 |
1 files changed, 9613 insertions, 0 deletions
diff --git a/utils/hwstub/stub/jz4760b/jz4760b.h b/utils/hwstub/stub/jz4760b/jz4760b.h new file mode 100644 index 0000000000..97ef74a56c --- /dev/null +++ b/utils/hwstub/stub/jz4760b/jz4760b.h | |||
@@ -0,0 +1,9613 @@ | |||
1 | /* | ||
2 | * jz4760b.h | ||
3 | * | ||
4 | * JZ4760B common definition. | ||
5 | * | ||
6 | * Copyright (C) 2008 Ingenic Semiconductor Inc. | ||
7 | * | ||
8 | * Author: <cwjia@ingenic.cn> | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __JZ4760B_H__ | ||
16 | #define __JZ4760B_H__ | ||
17 | |||
18 | #if defined(__ASSEMBLY__) || defined(__LANGUAGE_ASSEMBLY) | ||
19 | #ifndef __MIPS_ASSEMBLER | ||
20 | #define __MIPS_ASSEMBLER | ||
21 | #endif | ||
22 | #define REG8(addr) (addr) | ||
23 | #define REG16(addr) (addr) | ||
24 | #define REG32(addr) (addr) | ||
25 | #else | ||
26 | typedef unsigned char u8; | ||
27 | typedef unsigned short u16; | ||
28 | typedef unsigned int u32; | ||
29 | |||
30 | #define REG8(addr) *((volatile unsigned char *)(addr)) | ||
31 | #define REG16(addr) *((volatile unsigned short *)(addr)) | ||
32 | #define REG32(addr) *((volatile unsigned int *)(addr)) | ||
33 | |||
34 | #define INREG8(x) ((unsigned char)(*(volatile unsigned char *)(x))) | ||
35 | #define OUTREG8(x, y) *(volatile unsigned char *)(x) = (y) | ||
36 | #define SETREG8(x, y) OUTREG8(x, INREG8(x)|(y)) | ||
37 | #define CLRREG8(x, y) OUTREG8(x, INREG8(x)&~(y)) | ||
38 | #define CMSREG8(x, y, m) OUTREG8(x, (INREG8(x)&~(m))|(y)) | ||
39 | |||
40 | #define INREG16(x) ((unsigned short)(*(volatile unsigned short *)(x))) | ||
41 | #define OUTREG16(x, y) *(volatile unsigned short *)(x) = (y) | ||
42 | #define SETREG16(x, y) OUTREG16(x, INREG16(x)|(y)) | ||
43 | #define CLRREG16(x, y) OUTREG16(x, INREG16(x)&~(y)) | ||
44 | #define CMSREG16(x, y, m) OUTREG16(x, (INREG16(x)&~(m))|(y)) | ||
45 | |||
46 | #define INREG32(x) ((unsigned int)(*(volatile unsigned int *)(x))) | ||
47 | #define OUTREG32(x, y) *(volatile unsigned int *)(x) = (y) | ||
48 | #define SETREG32(x, y) OUTREG32(x, INREG32(x)|(y)) | ||
49 | #define CLRREG32(x, y) OUTREG32(x, INREG32(x)&~(y)) | ||
50 | #define CMSREG32(x, y, m) OUTREG32(x, (INREG32(x)&~(m))|(y)) | ||
51 | #endif | ||
52 | |||
53 | /* | ||
54 | * Define the bit field macro to avoid the bit mistake | ||
55 | */ | ||
56 | #define BIT0 (1 << 0) | ||
57 | #define BIT1 (1 << 1) | ||
58 | #define BIT2 (1 << 2) | ||
59 | #define BIT3 (1 << 3) | ||
60 | #define BIT4 (1 << 4) | ||
61 | #define BIT5 (1 << 5) | ||
62 | #define BIT6 (1 << 6) | ||
63 | #define BIT7 (1 << 7) | ||
64 | #define BIT8 (1 << 8) | ||
65 | #define BIT9 (1 << 9) | ||
66 | #define BIT10 (1 << 10) | ||
67 | #define BIT11 (1 << 11) | ||
68 | #define BIT12 (1 << 12) | ||
69 | #define BIT13 (1 << 13) | ||
70 | #define BIT14 (1 << 14) | ||
71 | #define BIT15 (1 << 15) | ||
72 | #define BIT16 (1 << 16) | ||
73 | #define BIT17 (1 << 17) | ||
74 | #define BIT18 (1 << 18) | ||
75 | #define BIT19 (1 << 19) | ||
76 | #define BIT20 (1 << 20) | ||
77 | #define BIT21 (1 << 21) | ||
78 | #define BIT22 (1 << 22) | ||
79 | #define BIT23 (1 << 23) | ||
80 | #define BIT24 (1 << 24) | ||
81 | #define BIT25 (1 << 25) | ||
82 | #define BIT26 (1 << 26) | ||
83 | #define BIT27 (1 << 27) | ||
84 | #define BIT28 (1 << 28) | ||
85 | #define BIT29 (1 << 29) | ||
86 | #define BIT30 (1 << 30) | ||
87 | #define BIT31 (1 << 31) | ||
88 | |||
89 | /* Generate the bit field mask from msb to lsb */ | ||
90 | #define BITS_H2L(msb, lsb) ((0xFFFFFFFF >> (32-((msb)-(lsb)+1))) << (lsb)) | ||
91 | |||
92 | /* Get the bit field value from the data which is read from the register */ | ||
93 | #define get_bf_value(data, lsb, mask) (((data) & (mask)) >> (lsb)) | ||
94 | |||
95 | /* | ||
96 | * Define the module base addresses | ||
97 | */ | ||
98 | /* AHB0 BUS Devices Base */ | ||
99 | #define HARB0_BASE 0xB3000000 | ||
100 | /* AHB1 BUS Devices Base */ | ||
101 | #define HARB1_BASE 0xB3200000 | ||
102 | #define DMAGP0_BASE 0xB3210000 | ||
103 | #define DMAGP1_BASE 0xB3220000 | ||
104 | #define DMAGP2_BASE 0xB3230000 | ||
105 | #define DEBLK_BASE 0xB3270000 | ||
106 | #define IDCT_BASE 0xB3280000 | ||
107 | #define CABAC_BASE 0xB3290000 | ||
108 | #define TCSM0_BASE 0xB32B0000 | ||
109 | #define TCSM1_BASE 0xB32C0000 | ||
110 | #define SRAM_BASE 0xB32D0000 | ||
111 | /* AHB2 BUS Devices Base */ | ||
112 | #define HARB2_BASE 0xB3400000 | ||
113 | #define UHC_BASE 0xB3430000 | ||
114 | #define GPS_BASE 0xB3480000 | ||
115 | #define ETHC_BASE 0xB34B0000 | ||
116 | /* APB BUS Devices Base */ | ||
117 | #define PS2_BASE 0xB0060000 | ||
118 | |||
119 | /* | ||
120 | * General purpose I/O port module(GPIO) address definition | ||
121 | */ | ||
122 | #define GPIO_BASE 0xb0010000 | ||
123 | |||
124 | /* GPIO group offset */ | ||
125 | #define GPIO_GOS 0x100 | ||
126 | |||
127 | /* Each group address */ | ||
128 | #define GPIO_BASEA (GPIO_BASE + (0) * GPIO_GOS) | ||
129 | #define GPIO_BASEB (GPIO_BASE + (1) * GPIO_GOS) | ||
130 | #define GPIO_BASEC (GPIO_BASE + (2) * GPIO_GOS) | ||
131 | #define GPIO_BASED (GPIO_BASE + (3) * GPIO_GOS) | ||
132 | #define GPIO_BASEE (GPIO_BASE + (4) * GPIO_GOS) | ||
133 | #define GPIO_BASEF (GPIO_BASE + (5) * GPIO_GOS) | ||
134 | |||
135 | /* | ||
136 | * GPIO registers offset address definition | ||
137 | */ | ||
138 | #define GPIO_PXPIN_OFFSET (0x00) /* r, 32, 0x00000000 */ | ||
139 | #define GPIO_PXDAT_OFFSET (0x10) /* r, 32, 0x00000000 */ | ||
140 | #define GPIO_PXDATS_OFFSET (0x14) /* w, 32, 0x???????? */ | ||
141 | #define GPIO_PXDATC_OFFSET (0x18) /* w, 32, 0x???????? */ | ||
142 | #define GPIO_PXIM_OFFSET (0x20) /* r, 32, 0xffffffff */ | ||
143 | #define GPIO_PXIMS_OFFSET (0x24) /* w, 32, 0x???????? */ | ||
144 | #define GPIO_PXIMC_OFFSET (0x28) /* w, 32, 0x???????? */ | ||
145 | #define GPIO_PXPE_OFFSET (0x30) /* r, 32, 0x00000000 */ | ||
146 | #define GPIO_PXPES_OFFSET (0x34) /* w, 32, 0x???????? */ | ||
147 | #define GPIO_PXPEC_OFFSET (0x38) /* w, 32, 0x???????? */ | ||
148 | #define GPIO_PXFUN_OFFSET (0x40) /* r, 32, 0x00000000 */ | ||
149 | #define GPIO_PXFUNS_OFFSET (0x44) /* w, 32, 0x???????? */ | ||
150 | #define GPIO_PXFUNC_OFFSET (0x48) /* w, 32, 0x???????? */ | ||
151 | #define GPIO_PXSEL_OFFSET (0x50) /* r, 32, 0x00000000 */ | ||
152 | #define GPIO_PXSELS_OFFSET (0x54) /* w, 32, 0x???????? */ | ||
153 | #define GPIO_PXSELC_OFFSET (0x58) /* w, 32, 0x???????? */ | ||
154 | #define GPIO_PXDIR_OFFSET (0x60) /* r, 32, 0x00000000 */ | ||
155 | #define GPIO_PXDIRS_OFFSET (0x64) /* w, 32, 0x???????? */ | ||
156 | #define GPIO_PXDIRC_OFFSET (0x68) /* w, 32, 0x???????? */ | ||
157 | #define GPIO_PXTRG_OFFSET (0x70) /* r, 32, 0x00000000 */ | ||
158 | #define GPIO_PXTRGS_OFFSET (0x74) /* w, 32, 0x???????? */ | ||
159 | #define GPIO_PXTRGC_OFFSET (0x78) /* w, 32, 0x???????? */ | ||
160 | #define GPIO_PXFLG_OFFSET (0x80) /* r, 32, 0x00000000 */ | ||
161 | #define GPIO_PXFLGC_OFFSET (GPIO_PXDATS_OFFSET) /* w, 32, 0x???????? */ | ||
162 | #define GPIO_PXDS0_OFFSET (0xC0) /* r, 32, 0x00000000 */ | ||
163 | #define GPIO_PXDS0S_OFFSET (0xC4) /* w, 32, 0x00000000 */ | ||
164 | #define GPIO_PXDS0C_OFFSET (0xC8) /* w, 32, 0x00000000 */ | ||
165 | #define GPIO_PXDS1_OFFSET (0xD0) /* r, 32, 0x00000000 */ | ||
166 | #define GPIO_PXDS1S_OFFSET (0xD4) /* w, 32, 0x00000000 */ | ||
167 | #define GPIO_PXDS1C_OFFSET (0xD8) /* w, 32, 0x00000000 */ | ||
168 | #define GPIO_PXDS2_OFFSET (0xE0) /* r, 32, 0x00000000 */ | ||
169 | #define GPIO_PXDS2S_OFFSET (0xE4) /* w, 32, 0x00000000 */ | ||
170 | #define GPIO_PXDS2C_OFFSET (0xE8) /* w, 32, 0x00000000 */ | ||
171 | #define GPIO_PXSL_OFFSET (0xF0) /* r, 32, 0x00000000 */ | ||
172 | #define GPIO_PXSLS_OFFSET (0xF4) /* w, 32, 0x00000000 */ | ||
173 | #define GPIO_PXSLC_OFFSET (0xF8) /* w, 32, 0x00000000 */ | ||
174 | |||
175 | /* | ||
176 | * GPIO registers address definition | ||
177 | */ | ||
178 | #define GPIO_PXPIN(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXPIN_OFFSET) | ||
179 | #define GPIO_PXDAT(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDAT_OFFSET) | ||
180 | #define GPIO_PXDATS(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDATS_OFFSET) | ||
181 | #define GPIO_PXDATC(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDATC_OFFSET) | ||
182 | #define GPIO_PXIM(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXIM_OFFSET) | ||
183 | #define GPIO_PXIMS(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXIMS_OFFSET) | ||
184 | #define GPIO_PXIMC(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXIMC_OFFSET) | ||
185 | #define GPIO_PXPE(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXPE_OFFSET) | ||
186 | #define GPIO_PXPES(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXPES_OFFSET) | ||
187 | #define GPIO_PXPEC(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXPEC_OFFSET) | ||
188 | #define GPIO_PXFUN(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXFUN_OFFSET) | ||
189 | #define GPIO_PXFUNS(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXFUNS_OFFSET) | ||
190 | #define GPIO_PXFUNC(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXFUNC_OFFSET) | ||
191 | #define GPIO_PXSEL(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSEL_OFFSET) | ||
192 | #define GPIO_PXSELS(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSELS_OFFSET) | ||
193 | #define GPIO_PXSELC(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSELC_OFFSET) | ||
194 | #define GPIO_PXDIR(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDIR_OFFSET) | ||
195 | #define GPIO_PXDIRS(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDIRS_OFFSET) | ||
196 | #define GPIO_PXDIRC(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDIRC_OFFSET) | ||
197 | #define GPIO_PXTRG(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXTRG_OFFSET) | ||
198 | #define GPIO_PXTRGS(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXTRGS_OFFSET) | ||
199 | #define GPIO_PXTRGC(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXTRGC_OFFSET) | ||
200 | #define GPIO_PXFLG(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXFLG_OFFSET) | ||
201 | #define GPIO_PXFLGC(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXFLGC_OFFSET) | ||
202 | #define GPIO_PXDS0(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS0_OFFSET) | ||
203 | #define GPIO_PXDS0S(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS0S_OFFSET) | ||
204 | #define GPIO_PXDS0C(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS0C_OFFSET) | ||
205 | #define GPIO_PXDS1(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS1_OFFSET) | ||
206 | #define GPIO_PXDS1S(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS1S_OFFSET) | ||
207 | #define GPIO_PXDS1C(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS1C_OFFSET) | ||
208 | #define GPIO_PXDS2(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS2_OFFSET) | ||
209 | #define GPIO_PXDS2S(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS2S_OFFSET) | ||
210 | #define GPIO_PXDS2C(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXDS2C_OFFSET) | ||
211 | #define GPIO_PXSL(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSL_OFFSET) | ||
212 | #define GPIO_PXSLS(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSLS_OFFSET) | ||
213 | #define GPIO_PXSLC(n) (GPIO_BASE + (n)*GPIO_GOS + GPIO_PXSLC_OFFSET) | ||
214 | |||
215 | /* */ | ||
216 | #define GPIO_PORT_NUM 6 | ||
217 | #define MAX_GPIO_NUM 192 | ||
218 | #define GPIO_WAKEUP (30) | ||
219 | |||
220 | #ifndef __MIPS_ASSEMBLER | ||
221 | |||
222 | //n = 0,1,2,3,4,5 (PORTA, PORTB, PORTC, PORTD, PORTE, PORTF) | ||
223 | #define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN(n)) | ||
224 | #define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT(n)) | ||
225 | #define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS(n)) | ||
226 | #define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC(n)) | ||
227 | #define REG_GPIO_PXIM(n) REG32(GPIO_PXIM(n)) | ||
228 | #define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS(n)) | ||
229 | #define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC(n)) | ||
230 | #define REG_GPIO_PXPE(n) REG32(GPIO_PXPE(n)) | ||
231 | #define REG_GPIO_PXPES(n) REG32(GPIO_PXPES(n)) | ||
232 | #define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC(n)) | ||
233 | #define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN(n)) | ||
234 | #define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS(n)) | ||
235 | #define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC(n)) | ||
236 | #define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL(n)) | ||
237 | #define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS(n)) | ||
238 | #define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC(n)) | ||
239 | #define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR(n)) | ||
240 | #define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS(n)) | ||
241 | #define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC(n)) | ||
242 | #define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG(n)) | ||
243 | #define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS(n)) | ||
244 | #define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC(n)) | ||
245 | #define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG(n)) | ||
246 | #define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC(n)) | ||
247 | #define REG_GPIO_PXDS0(n) REG32(GPIO_PXDS0(n)) | ||
248 | #define REG_GPIO_PXDS0S(n) REG32(GPIO_PXDS0S(n)) | ||
249 | #define REG_GPIO_PXDS0C(n) REG32(GPIO_PXDS0C(n)) | ||
250 | #define REG_GPIO_PXDS1(n) REG32(GPIO_PXDS1(n)) | ||
251 | #define REG_GPIO_PXDS1S(n) REG32(GPIO_PXDS1S(n)) | ||
252 | #define REG_GPIO_PXDS1C(n) REG32(GPIO_PXDS1C(n)) | ||
253 | #define REG_GPIO_PXDS2(n) REG32(GPIO_PXDS2(n)) | ||
254 | #define REG_GPIO_PXDS2S(n) REG32(GPIO_PXDS2S(n)) | ||
255 | #define REG_GPIO_PXDS2C(n) REG32(GPIO_PXDS2C(n)) | ||
256 | #define REG_GPIO_PXSL(n) REG32(GPIO_PXSL(n)) | ||
257 | #define REG_GPIO_PXSLS(n) REG32(GPIO_PXSLS(n)) | ||
258 | #define REG_GPIO_PXSLC(n) REG32(GPIO_PXSLC(n)) | ||
259 | |||
260 | /*---------------------------------------------------------------- | ||
261 | * p is the port number (0,1,2,3,4,5) | ||
262 | * o is the pin offset (0-31) inside the port | ||
263 | * n is the absolute number of a pin (0-127), regardless of the port | ||
264 | */ | ||
265 | |||
266 | //---------------------------------------------------------------- | ||
267 | // Function Pins Mode | ||
268 | |||
269 | #define __gpio_as_func0(n) \ | ||
270 | do { \ | ||
271 | unsigned int p, o; \ | ||
272 | p = (n) / 32; \ | ||
273 | o = (n) % 32; \ | ||
274 | REG_GPIO_PXFUNS(p) = (1 << o); \ | ||
275 | REG_GPIO_PXTRGC(p) = (1 << o); \ | ||
276 | REG_GPIO_PXSELC(p) = (1 << o); \ | ||
277 | } while (0) | ||
278 | |||
279 | #define __gpio_as_func1(n) \ | ||
280 | do { \ | ||
281 | unsigned int p, o; \ | ||
282 | p = (n) / 32; \ | ||
283 | o = (n) % 32; \ | ||
284 | REG_GPIO_PXFUNS(p) = (1 << o); \ | ||
285 | REG_GPIO_PXTRGC(p) = (1 << o); \ | ||
286 | REG_GPIO_PXSELS(p) = (1 << o); \ | ||
287 | } while (0) | ||
288 | |||
289 | #define __gpio_as_func2(n) \ | ||
290 | do { \ | ||
291 | unsigned int p, o; \ | ||
292 | p = (n) / 32; \ | ||
293 | o = (n) % 32; \ | ||
294 | REG_GPIO_PXFUNS(p) = (1 << o); \ | ||
295 | REG_GPIO_PXTRGS(p) = (1 << o); \ | ||
296 | REG_GPIO_PXSELC(p) = (1 << o); \ | ||
297 | } while (0) | ||
298 | |||
299 | #define __gpio_as_func3(n) \ | ||
300 | do { \ | ||
301 | unsigned int p, o; \ | ||
302 | p = (n) / 32; \ | ||
303 | o = (n) % 32; \ | ||
304 | REG_GPIO_PXFUNS(p) = (1 << o); \ | ||
305 | REG_GPIO_PXTRGS(p) = (1 << o); \ | ||
306 | REG_GPIO_PXSELS(p) = (1 << o); \ | ||
307 | } while (0) | ||
308 | |||
309 | /* | ||
310 | * UART0_TxD, UART0_RxD | ||
311 | */ | ||
312 | #define __gpio_as_uart0() \ | ||
313 | do { \ | ||
314 | unsigned int bits = BIT3 | BIT0; \ | ||
315 | REG_GPIO_PXFUNS(5) = bits; \ | ||
316 | REG_GPIO_PXTRGC(5) = bits; \ | ||
317 | REG_GPIO_PXSELC(5) = bits; \ | ||
318 | REG_GPIO_PXPES(5) = bits; \ | ||
319 | } while (0) | ||
320 | |||
321 | /* | ||
322 | * UART0_TxD, UART0_RxD, UART0_CTS, UART0_RTS | ||
323 | */ | ||
324 | #define __gpio_as_uart0_ctsrts() \ | ||
325 | do { \ | ||
326 | unsigned int bits = BITS_H2L(3, 0); \ | ||
327 | REG_GPIO_PXFUNS(5) = bits; \ | ||
328 | REG_GPIO_PXTRGC(5) = bits; \ | ||
329 | REG_GPIO_PXSELC(5) = bits; \ | ||
330 | REG_GPIO_PXPES(5) = bits; \ | ||
331 | } while (0) | ||
332 | |||
333 | /* | ||
334 | * UART1_TxD, UART1_RxD | ||
335 | */ | ||
336 | #define __gpio_as_uart1() \ | ||
337 | do { \ | ||
338 | unsigned int bits = BIT28 | BIT26; \ | ||
339 | REG_GPIO_PXFUNS(3) = bits; \ | ||
340 | REG_GPIO_PXTRGC(3) = bits; \ | ||
341 | REG_GPIO_PXSELC(3) = bits; \ | ||
342 | REG_GPIO_PXPES(3) = bits; \ | ||
343 | } while (0) | ||
344 | |||
345 | /* | ||
346 | * UART1_TxD, UART1_RxD, UART1_CTS, UART1_RTS | ||
347 | */ | ||
348 | #define __gpio_as_uart1_ctsrts() \ | ||
349 | do { \ | ||
350 | unsigned int bits = BITS_H2L(29, 26); \ | ||
351 | REG_GPIO_PXFUNS(3) = bits; \ | ||
352 | REG_GPIO_PXTRGC(3) = bits; \ | ||
353 | REG_GPIO_PXSELC(3) = bits; \ | ||
354 | REG_GPIO_PXPES(3) = bits; \ | ||
355 | } while (0) | ||
356 | |||
357 | /* | ||
358 | * UART2_TxD, UART2_RxD | ||
359 | */ | ||
360 | #define __gpio_as_uart2() \ | ||
361 | do { \ | ||
362 | unsigned int bits = BIT30 | BIT28; \ | ||
363 | REG_GPIO_PXFUNS(2) = bits; \ | ||
364 | REG_GPIO_PXTRGC(2) = bits; \ | ||
365 | REG_GPIO_PXSELC(2) = bits; \ | ||
366 | REG_GPIO_PXPES(2) = bits; \ | ||
367 | } while (0) | ||
368 | |||
369 | /* | ||
370 | * UART2_TxD, UART2_RxD, UART2_CTS, UART2_RTS | ||
371 | */ | ||
372 | #define __gpio_as_uart2_ctsrts() \ | ||
373 | do { \ | ||
374 | unsigned int bits = BITS_H2L(31, 28); \ | ||
375 | REG_GPIO_PXFUNS(2) = bits; \ | ||
376 | REG_GPIO_PXTRGC(2) = bits; \ | ||
377 | REG_GPIO_PXSELC(2) = bits; \ | ||
378 | REG_GPIO_PXPES(2) = bits; \ | ||
379 | } while (0) | ||
380 | |||
381 | /* WARNING: the folloing macro do NOT check */ | ||
382 | /* | ||
383 | * UART3_TxD, UART3_RxD | ||
384 | */ | ||
385 | #define __gpio_as_uart3() \ | ||
386 | do { \ | ||
387 | unsigned int bits = BIT12; \ | ||
388 | REG_GPIO_PXFUNS(3) = bits; \ | ||
389 | REG_GPIO_PXTRGC(3) = bits; \ | ||
390 | REG_GPIO_PXSELS(3) = bits; \ | ||
391 | REG_GPIO_PXPES(3) = bits; \ | ||
392 | bits = BIT5; \ | ||
393 | REG_GPIO_PXFUNS(4) = bits; \ | ||
394 | REG_GPIO_PXTRGC(4) = bits; \ | ||
395 | REG_GPIO_PXSELS(4) = bits; \ | ||
396 | REG_GPIO_PXPES(4) = bits; \ | ||
397 | } while (0) | ||
398 | /* | ||
399 | * UART3_TxD, UART3_RxD, UART3_CTS, UART3_RTS | ||
400 | */ | ||
401 | #define __gpio_as_uart3_ctsrts() \ | ||
402 | do { \ | ||
403 | REG_GPIO_PXFUNS(3) = (1 << 12); \ | ||
404 | REG_GPIO_PXTRGC(3) = (1 << 12); \ | ||
405 | REG_GPIO_PXSELC(3) = (1 << 12); \ | ||
406 | REG_GPIO_PXPES(3) = (1 << 12); \ | ||
407 | REG_GPIO_PXFUNS(4) = 0x00000320; \ | ||
408 | REG_GPIO_PXTRGC(4) = 0x00000320; \ | ||
409 | REG_GPIO_PXSELS(4) = 0x00000020; \ | ||
410 | REG_GPIO_PXSELC(4) = 0x00000300; \ | ||
411 | REG_GPIO_PXPES(4) = 0x00000320; \ | ||
412 | } while (0) | ||
413 | |||
414 | /* | ||
415 | * SD0 ~ SD7, CS1#, CLE, ALE, FRE#, FWE#, FRB# | ||
416 | * @n: chip select number(1 ~ 6) | ||
417 | */ | ||
418 | #define __gpio_as_nand_8bit(n) \ | ||
419 | do { \ | ||
420 | \ | ||
421 | REG_GPIO_PXFUNS(0) = 0x000c00ff; /* SD0 ~ SD7, FRE#, FWE# */ \ | ||
422 | REG_GPIO_PXSELC(0) = 0x000c00ff; \ | ||
423 | REG_GPIO_PXTRGC(0) = 0x000c00ff; \ | ||
424 | REG_GPIO_PXPES(0) = 0x000c00ff; \ | ||
425 | REG_GPIO_PXFUNS(1) = 0x00000003; /* CLE(SA0_CL), ALE(SA1_AL) */ \ | ||
426 | REG_GPIO_PXSELC(1) = 0x00000003; \ | ||
427 | REG_GPIO_PXTRGC(1) = 0x00000003; \ | ||
428 | REG_GPIO_PXPES(1) = 0x00000003; \ | ||
429 | \ | ||
430 | REG_GPIO_PXFUNS(0) = 0x00200000 << ((n)-1); /* CSn */ \ | ||
431 | REG_GPIO_PXSELC(0) = 0x00200000 << ((n)-1); \ | ||
432 | REG_GPIO_PXTRGC(0) = 0x00200000 << ((n)-1); \ | ||
433 | REG_GPIO_PXPES(0) = 0x00200000 << ((n)-1); \ | ||
434 | \ | ||
435 | REG_GPIO_PXFUNC(0) = 0x00100000; /* FRB#(input) */ \ | ||
436 | REG_GPIO_PXSELC(0) = 0x00100000; \ | ||
437 | REG_GPIO_PXDIRC(0) = 0x00100000; \ | ||
438 | REG_GPIO_PXPES(0) = 0x00100000; \ | ||
439 | } while (0) | ||
440 | |||
441 | #define __gpio_as_nand_16bit(n) \ | ||
442 | do { \ | ||
443 | \ | ||
444 | REG_GPIO_PXFUNS(0) = 0x000cffff; /* SD0 ~ SD15, CS1#, FRE#, FWE# */ \ | ||
445 | REG_GPIO_PXSELC(0) = 0x000cffff; \ | ||
446 | REG_GPIO_PXTRGC(0) = 0x000cffff; \ | ||
447 | REG_GPIO_PXPES(0) = 0x000cffff; \ | ||
448 | REG_GPIO_PXFUNS(1) = 0x00000003; /* CLE(SA2), ALE(SA3) */ \ | ||
449 | REG_GPIO_PXSELC(1) = 0x00000003; \ | ||
450 | REG_GPIO_PXTRGC(1) = 0x00000003; \ | ||
451 | REG_GPIO_PXPES(1) = 0x00000003; \ | ||
452 | \ | ||
453 | REG_GPIO_PXFUNS(0) = 0x00200000 << ((n)-1); /* CSn */ \ | ||
454 | REG_GPIO_PXSELC(0) = 0x00200000 << ((n)-1); \ | ||
455 | REG_GPIO_PXTRGC(0) = 0x00200000 << ((n)-1); \ | ||
456 | REG_GPIO_PXPES(0) = 0x00200000 << ((n)-1); \ | ||
457 | \ | ||
458 | REG_GPIO_PXFUNC(0) = 0x00100000; /* FRB#(input) */ \ | ||
459 | REG_GPIO_PXSELC(0) = 0x00100000; \ | ||
460 | REG_GPIO_PXDIRC(0) = 0x00100000; \ | ||
461 | REG_GPIO_PXPES(0) = 0x00100000; \ | ||
462 | } while (0) | ||
463 | |||
464 | /* | ||
465 | * SLCD | ||
466 | */ | ||
467 | #define __gpio_as_slcd_16bit() \ | ||
468 | do { \ | ||
469 | REG_GPIO_PXFUNS(2) = 0x03cff0fc; \ | ||
470 | REG_GPIO_PXTRGC(2) = 0x03cff0fc; \ | ||
471 | REG_GPIO_PXSELC(2) = 0x03cff0fc; \ | ||
472 | REG_GPIO_PXPES(2) = 0x03cff0fc; \ | ||
473 | } while (0) | ||
474 | |||
475 | /* | ||
476 | * LCD_R3~LCD_R7, LCD_G2~LCD_G7, LCD_B3~LCD_B7, | ||
477 | * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE | ||
478 | */ | ||
479 | #define __gpio_as_lcd_16bit() \ | ||
480 | do { \ | ||
481 | REG_GPIO_PXFUNS(2) = 0x0f8ff3f8; \ | ||
482 | REG_GPIO_PXTRGC(2) = 0x0f8ff3f8; \ | ||
483 | REG_GPIO_PXSELC(2) = 0x0f8ff3f8; \ | ||
484 | REG_GPIO_PXPES(2) = 0x0f8ff3f8; \ | ||
485 | } while (0) | ||
486 | |||
487 | /* | ||
488 | * LCD_R2~LCD_R7, LCD_G2~LCD_G7, LCD_B2~LCD_B7, | ||
489 | * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE | ||
490 | */ | ||
491 | #define __gpio_as_lcd_18bit() \ | ||
492 | do { \ | ||
493 | REG_GPIO_PXFUNS(2) = 0x0fcff3fc; \ | ||
494 | REG_GPIO_PXTRGC(2) = 0x0fcff3fc; \ | ||
495 | REG_GPIO_PXSELC(2) = 0x0fcff3fc; \ | ||
496 | REG_GPIO_PXPES(2) = 0x0fcff3fc; \ | ||
497 | } while (0) | ||
498 | |||
499 | /* | ||
500 | * LCD_R0~LCD_R7, LCD_G0~LCD_G7, LCD_B0~LCD_B7, | ||
501 | * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE | ||
502 | */ | ||
503 | #define __gpio_as_lcd_24bit() \ | ||
504 | do { \ | ||
505 | REG_GPIO_PXFUNS(2) = 0x0fffffff; \ | ||
506 | REG_GPIO_PXTRGC(2) = 0x0fffffff; \ | ||
507 | REG_GPIO_PXSELC(2) = 0x0fffffff; \ | ||
508 | REG_GPIO_PXPES(2) = 0x0fffffff; \ | ||
509 | } while (0) | ||
510 | |||
511 | /* | ||
512 | * LCD_R0~LCD_R7, LCD_G0~LCD_G7, LCD_B0~LCD_B7, | ||
513 | * LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE | ||
514 | */ | ||
515 | #define __gpio_clear_lcd_24bit() \ | ||
516 | do { \ | ||
517 | REG_GPIO_PXFUNC(2) = 0x0fffffff; \ | ||
518 | REG_GPIO_PXTRGC(2) = 0x0fffffff; \ | ||
519 | REG_GPIO_PXSELC(2) = 0x0fffffff; \ | ||
520 | REG_GPIO_PXDIRS(2) = 0x0fffffff; \ | ||
521 | REG_GPIO_PXDATC(2) = 0x0fffffff; \ | ||
522 | REG_GPIO_PXPES(2) = 0x0fffffff; \ | ||
523 | } while (0) | ||
524 | |||
525 | /* Set data pin driver strength v: 0~7 */ | ||
526 | #define __gpio_set_lcd_data_driving_strength(v) \ | ||
527 | do { \ | ||
528 | unsigned int d; \ | ||
529 | d = v & 0x1; \ | ||
530 | if(d) REG_GPIO_PXDS0S(2) = 0x0ff3fcff; \ | ||
531 | else REG_GPIO_PXDS0C(2) = 0x0ff3fcff; \ | ||
532 | d = v & 0x2; \ | ||
533 | if(d) REG_GPIO_PXDS1S(2) = 0x0ff3fcff; \ | ||
534 | else REG_GPIO_PXDS1C(2) = 0x0ff3fcff; \ | ||
535 | d = v & 0x4; \ | ||
536 | if(d) REG_GPIO_PXDS2S(2) = 0x0ff3fcff; \ | ||
537 | else REG_GPIO_PXDS2C(2) = 0x0ff3fcff; \ | ||
538 | } while(0) | ||
539 | /* Set HSYNC VSYNC DE driver strength v: 0~7 */ | ||
540 | #define __gpio_set_lcd_sync_driving_strength(v) \ | ||
541 | do { \ | ||
542 | unsigned int d; \ | ||
543 | d = v & 0x1; \ | ||
544 | if(d) REG_GPIO_PXDS0S(2) = 0x000c0200; \ | ||
545 | else REG_GPIO_PXDS0C(2) = 0x000c0200; \ | ||
546 | d = v & 0x2; \ | ||
547 | if(d) REG_GPIO_PXDS1S(2) = 0x000c0200; \ | ||
548 | else REG_GPIO_PXDS1C(2) = 0x000c0200; \ | ||
549 | d = v & 0x4; \ | ||
550 | if(d) REG_GPIO_PXDS2S(2) = 0x000c0200; \ | ||
551 | else REG_GPIO_PXDS2C(2) = 0x000c0200; \ | ||
552 | } while(0) | ||
553 | /* Set PCLK driver strength v: 0~7 */ | ||
554 | #define __gpio_set_lcd_clk_driving_strength(v) \ | ||
555 | do { \ | ||
556 | unsigned int d; \ | ||
557 | d = v & 0x1; \ | ||
558 | if(d) REG_GPIO_PXDS0S(2) = (1 << 8); \ | ||
559 | else REG_GPIO_PXDS0C(2) = (1 << 8); \ | ||
560 | d = v & 0x2; \ | ||
561 | if(d) REG_GPIO_PXDS1S(2) = (1 << 8); \ | ||
562 | else REG_GPIO_PXDS1C(2) = (1 << 8); \ | ||
563 | d = v & 0x4; \ | ||
564 | if(d) REG_GPIO_PXDS2S(2) = (1 << 8); \ | ||
565 | else REG_GPIO_PXDS2C(2) = (1 << 8); \ | ||
566 | } while(0) | ||
567 | |||
568 | /* Set fast slew rate */ | ||
569 | #define __gpio_set_lcd_data_fslew(n) \ | ||
570 | do { \ | ||
571 | unsigned int p, o; \ | ||
572 | p = (n) / 32; \ | ||
573 | o = (n) % 32; \ | ||
574 | REG_GPIO_PXSLS(p) = 0x0ff3fcff; \ | ||
575 | } while(0) | ||
576 | |||
577 | /* Set slow slew rate */ | ||
578 | #define __gpio_set_lcd_data_sslew(n) \ | ||
579 | do { \ | ||
580 | unsigned int p, o; \ | ||
581 | p = (n) / 32; \ | ||
582 | o = (n) % 32; \ | ||
583 | REG_GPIO_PXSLC(p) = 0x0ff3fcff; \ | ||
584 | } while(0) | ||
585 | |||
586 | /* Set fast slew rate */ | ||
587 | #define __gpio_set_lcd_sync_fslew(n) \ | ||
588 | do { \ | ||
589 | unsigned int p, o; \ | ||
590 | p = (n) / 32; \ | ||
591 | o = (n) % 32; \ | ||
592 | REG_GPIO_PXSLS(p) = 0x000c0200; \ | ||
593 | } while(0) | ||
594 | |||
595 | /* Set slow slew rate */ | ||
596 | #define __gpio_set_lcd_sync_sslew(n) \ | ||
597 | do { \ | ||
598 | unsigned int p, o; \ | ||
599 | p = (n) / 32; \ | ||
600 | o = (n) % 32; \ | ||
601 | REG_GPIO_PXSLC(p) = 0x000c0200; \ | ||
602 | } while(0) | ||
603 | |||
604 | /* Set fast slew rate */ | ||
605 | #define __gpio_set_lcd_pclk_fslew(n) \ | ||
606 | do { \ | ||
607 | unsigned int p, o; \ | ||
608 | p = (n) / 32; \ | ||
609 | o = (n) % 32; \ | ||
610 | REG_GPIO_PXSLS(p) = (1 << 8); \ | ||
611 | } while(0) | ||
612 | |||
613 | /* Set slow slew rate */ | ||
614 | #define __gpio_set_lcd_pclk_sslew(n) \ | ||
615 | do { \ | ||
616 | unsigned int p, o; \ | ||
617 | p = (n) / 32; \ | ||
618 | o = (n) % 32; \ | ||
619 | REG_GPIO_PXSLC(p) = (1 << 8); \ | ||
620 | } while(0) | ||
621 | |||
622 | /* | ||
623 | * LCD_CLS, LCD_SPL, LCD_PS, LCD_REV | ||
624 | */ | ||
625 | #define __gpio_as_lcd_special() \ | ||
626 | do { \ | ||
627 | REG_GPIO_PXFUNS(2) = 0x0fffffff; \ | ||
628 | REG_GPIO_PXTRGC(2) = 0x0fffffff; \ | ||
629 | REG_GPIO_PXSELC(2) = 0x0feffbfc; \ | ||
630 | REG_GPIO_PXSELS(2) = 0x00100403; \ | ||
631 | REG_GPIO_PXPES(2) = 0x0fffffff; \ | ||
632 | } while (0) | ||
633 | |||
634 | #define __gpio_as_epd() \ | ||
635 | do { \ | ||
636 | REG_GPIO_PXFUNS(1) = 0x00011e00; \ | ||
637 | REG_GPIO_PXTRGS(1) = 0x00011e00; \ | ||
638 | REG_GPIO_PXSELS(1) = 0x00011e00; \ | ||
639 | REG_GPIO_PXPES(1) = 0x00011e00; \ | ||
640 | } while (0) | ||
641 | /* | ||
642 | * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC | ||
643 | */ | ||
644 | #define __gpio_as_cim() \ | ||
645 | do { \ | ||
646 | REG_GPIO_PXFUNS(1) = 0x0003ffc0; \ | ||
647 | REG_GPIO_PXTRGC(1) = 0x0003ffc0; \ | ||
648 | REG_GPIO_PXSELC(1) = 0x0003ffc0; \ | ||
649 | REG_GPIO_PXPES(1) = 0x0003ffc0; \ | ||
650 | } while (0) | ||
651 | |||
652 | /* | ||
653 | * SDATO, SDATI, BCLK, SYNC, SCLK_RSTN(gpio sepc) or | ||
654 | * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET(aic spec) | ||
655 | */ | ||
656 | #define __gpio_as_aic() \ | ||
657 | do { \ | ||
658 | REG_GPIO_PXFUNS(3) = 0x00003000; \ | ||
659 | REG_GPIO_PXTRGC(3) = 0x00003000; \ | ||
660 | REG_GPIO_PXSELS(3) = 0x00001000; \ | ||
661 | REG_GPIO_PXSELC(3) = 0x00002000; \ | ||
662 | REG_GPIO_PXPES(3) = 0x00003000; \ | ||
663 | REG_GPIO_PXFUNS(4) = 0x000000e0; \ | ||
664 | REG_GPIO_PXTRGS(4) = 0x00000020; \ | ||
665 | REG_GPIO_PXTRGC(4) = 0x000000c0; \ | ||
666 | REG_GPIO_PXSELC(4) = 0x000000e0; \ | ||
667 | REG_GPIO_PXPES(4) = 0x000000e0; \ | ||
668 | } while (0) | ||
669 | |||
670 | #define __gpio_as_spdif() \ | ||
671 | do { \ | ||
672 | REG_GPIO_PXFUNS(3) = 0x00003000; \ | ||
673 | REG_GPIO_PXTRGC(3) = 0x00003000; \ | ||
674 | REG_GPIO_PXSELS(3) = 0x00001000; \ | ||
675 | REG_GPIO_PXSELC(3) = 0x00002000; \ | ||
676 | REG_GPIO_PXPES(3) = 0x00003000; \ | ||
677 | REG_GPIO_PXFUNS(4) = 0x000038e0; \ | ||
678 | REG_GPIO_PXTRGC(4) = 0x000038c0; \ | ||
679 | REG_GPIO_PXTRGS(4) = 0x00000020; \ | ||
680 | REG_GPIO_PXSELC(4) = 0x000038e0; \ | ||
681 | REG_GPIO_PXPES(4) = 0x000038e0; \ | ||
682 | } while (0) | ||
683 | |||
684 | /* | ||
685 | * MSC0_CMD, MSC0_CLK, MSC0_D0 ~ MSC0_D3 | ||
686 | */ | ||
687 | #define __gpio_as_msc0_pa_4bit() \ | ||
688 | do { \ | ||
689 | REG_GPIO_PXFUNS(0) = 0x00fc0000; \ | ||
690 | REG_GPIO_PXTRGC(0) = 0x00fc0000; \ | ||
691 | REG_GPIO_PXSELS(0) = 0x00ec0000; \ | ||
692 | REG_GPIO_PXSELC(0) = 0x00100000; \ | ||
693 | REG_GPIO_PXPES(0) = 0x00fc0000; \ | ||
694 | } while (0) | ||
695 | |||
696 | /* | ||
697 | * MSC0_CMD, MSC0_CLK, MSC0_D0 ~ MSC0_D7 | ||
698 | */ | ||
699 | #define __gpio_as_msc0_pe_8bit() \ | ||
700 | do { \ | ||
701 | REG_GPIO_PXFUNS(4) = 0x3ff00000; \ | ||
702 | REG_GPIO_PXTRGC(4) = 0x3ff00000; \ | ||
703 | REG_GPIO_PXSELC(4) = 0x3ff00000; \ | ||
704 | REG_GPIO_PXPES(4) = 0x3ff00000; \ | ||
705 | REG_GPIO_PXDS0S(4) = 0x3ff00000; \ | ||
706 | } while (0) | ||
707 | /* | ||
708 | * MSC0_CMD, MSC0_CLK, MSC0_D0 ~ MSC0_D3 | ||
709 | */ | ||
710 | #define __gpio_as_msc0_pe_4bit() \ | ||
711 | do { \ | ||
712 | REG_GPIO_PXFUNS(4) = 0x30f00000; \ | ||
713 | REG_GPIO_PXTRGC(4) = 0x30f00000; \ | ||
714 | REG_GPIO_PXSELC(4) = 0x30f00000; \ | ||
715 | REG_GPIO_PXPES(4) = 0x30f00000; \ | ||
716 | REG_GPIO_PXDS0S(4) = 0x30f00000; \ | ||
717 | } while (0) | ||
718 | |||
719 | #define __gpio_as_msc0_boot() \ | ||
720 | do { \ | ||
721 | REG_GPIO_PXFUNS(0) = 0x00ec0000; \ | ||
722 | REG_GPIO_PXTRGC(0) = 0x00ec0000; \ | ||
723 | REG_GPIO_PXSELS(0) = 0x00ec0000; \ | ||
724 | REG_GPIO_PXPES(0) = 0x00ec0000; \ | ||
725 | REG_GPIO_PXFUNS(0) = 0x00100000; \ | ||
726 | REG_GPIO_PXTRGC(0) = 0x00100000; \ | ||
727 | REG_GPIO_PXSELC(0) = 0x00100000; \ | ||
728 | REG_GPIO_PXPES(0) = 0x00100000; \ | ||
729 | \ | ||
730 | } while (0) | ||
731 | |||
732 | /* | ||
733 | * MSC1_CMD, MSC1_CLK, MSC1_D0 ~ MSC1_D7 | ||
734 | */ | ||
735 | #define __gpio_as_msc1_pe_8bit() \ | ||
736 | do { \ | ||
737 | REG_GPIO_PXFUNS(4) = 0x3ff00000; \ | ||
738 | REG_GPIO_PXTRGC(4) = 0x3ff00000; \ | ||
739 | REG_GPIO_PXSELS(4) = 0x3ff00000; \ | ||
740 | REG_GPIO_PXPES(4) = 0x3ff00000; \ | ||
741 | REG_GPIO_PXDS0S(4) = 0x3ff00000; \ | ||
742 | } while (0) | ||
743 | /* | ||
744 | * MSC1_CMD, MSC1_CLK, MSC1_D0 ~ MSC1_D3 | ||
745 | */ | ||
746 | #define __gpio_as_msc1_pe_4bit() \ | ||
747 | do { \ | ||
748 | REG_GPIO_PXFUNS(4) = 0x30f00000; \ | ||
749 | REG_GPIO_PXTRGC(4) = 0x30f00000; \ | ||
750 | REG_GPIO_PXSELS(4) = 0x30f00000; \ | ||
751 | REG_GPIO_PXPES(4) = 0x30f00000; \ | ||
752 | REG_GPIO_PXDS0S(4) = 0x30f00000; \ | ||
753 | } while (0) | ||
754 | |||
755 | /* | ||
756 | * MSC1_CMD, MSC1_CLK, MSC1_D0 ~ MSC1_D3 | ||
757 | */ | ||
758 | #define __gpio_as_msc1_pd_4bit() \ | ||
759 | do { \ | ||
760 | REG_GPIO_PXFUNS(3) = 0x03f00000; \ | ||
761 | REG_GPIO_PXTRGC(3) = 0x03f00000; \ | ||
762 | REG_GPIO_PXSELC(3) = 0x03f00000; \ | ||
763 | REG_GPIO_PXPES(3) = 0x03f00000; \ | ||
764 | REG_GPIO_PXDS0S(3) = 0x03f00000; \ | ||
765 | } while (0) | ||
766 | |||
767 | /* Port B | ||
768 | * MSC2_CMD, MSC2_CLK, MSC2_D0 ~ MSC2_D3 | ||
769 | */ | ||
770 | #define __gpio_as_msc2_pb_4bit() \ | ||
771 | do { \ | ||
772 | REG_GPIO_PXFUNS(1) = 0xf0300000; \ | ||
773 | REG_GPIO_PXTRGC(1) = 0xf0300000; \ | ||
774 | REG_GPIO_PXSELC(1) = 0xf0300000; \ | ||
775 | REG_GPIO_PXPES(1) = 0xf0300000; \ | ||
776 | REG_GPIO_PXDS0S(1) = 0xf0300000; \ | ||
777 | } while (0) | ||
778 | |||
779 | /* | ||
780 | * MSC2_CMD, MSC2_CLK, MSC2_D0 ~ MSC2_D7 | ||
781 | */ | ||
782 | #define __gpio_as_msc2_pe_8bit() \ | ||
783 | do { \ | ||
784 | REG_GPIO_PXFUNS(4) = 0x3ff00000; \ | ||
785 | REG_GPIO_PXTRGS(4) = 0x3ff00000; \ | ||
786 | REG_GPIO_PXSELC(4) = 0x3ff00000; \ | ||
787 | REG_GPIO_PXPES(4) = 0x3ff00000; \ | ||
788 | REG_GPIO_PXDS0S(4) = 0x3ff00000; \ | ||
789 | } while (0) | ||
790 | /* | ||
791 | * MSC2_CMD, MSC2_CLK, MSC2_D0 ~ MSC2_D3 | ||
792 | */ | ||
793 | #define __gpio_as_msc2_pe_4bit() \ | ||
794 | do { \ | ||
795 | REG_GPIO_PXFUNS(4) = 0x30f00000; \ | ||
796 | REG_GPIO_PXTRGS(4) = 0x30f00000; \ | ||
797 | REG_GPIO_PXSELC(4) = 0x30f00000; \ | ||
798 | REG_GPIO_PXPES(4) = 0x30f00000; \ | ||
799 | REG_GPIO_PXDS0S(4)= 0x30f00000; \ | ||
800 | } while (0) | ||
801 | #define __gpio_as_msc0_4bit __gpio_as_msc0_pe_4bit /* default as msc0 4bit */ | ||
802 | #define __gpio_as_msc1_4bit __gpio_as_msc1_pd_4bit /* msc1 only support 4bit */ | ||
803 | #define __gpio_as_msc __gpio_as_msc0_4bit /* default as msc0 4bit */ | ||
804 | #define __gpio_as_msc0 __gpio_as_msc0_4bit /* msc0 default as 4bit */ | ||
805 | #define __gpio_as_msc1 __gpio_as_msc1_4bit /* msc1 only support 4bit */ | ||
806 | #define __gpio_as_msc0_8bit __gpio_as_msc0_pe_8bit /* default as msc0 8bit */ | ||
807 | #define __gpio_as_msc1_8bit __gpio_as_msc1_pd_8bit /* msc1 only support 8bit */ | ||
808 | /* | ||
809 | * TSCLK, TSSTR, TSFRM, TSFAIL, TSDI0~7 | ||
810 | */ | ||
811 | #define __gpio_as_tssi_1() \ | ||
812 | do { \ | ||
813 | REG_GPIO_PXFUNS(1) = 0x0003ffc0; \ | ||
814 | REG_GPIO_PXTRGC(1) = 0x0003ffc0; \ | ||
815 | REG_GPIO_PXSELS(1) = 0x0003ffc0; \ | ||
816 | REG_GPIO_PXPES(1) = 0x0003ffc0; \ | ||
817 | } while (0) | ||
818 | |||
819 | /* | ||
820 | * TSCLK, TSSTR, TSFRM, TSFAIL, TSDI0~7 | ||
821 | */ | ||
822 | #define __gpio_as_tssi_2() \ | ||
823 | do { \ | ||
824 | REG_GPIO_PXFUNS(1) = 0xfff00000; \ | ||
825 | REG_GPIO_PXTRGC(1) = 0x0fc00000; \ | ||
826 | REG_GPIO_PXTRGS(1) = 0xf0300000; \ | ||
827 | REG_GPIO_PXSELC(1) = 0xfff00000; \ | ||
828 | REG_GPIO_PXPES(1) = 0xfff00000; \ | ||
829 | } while (0) | ||
830 | |||
831 | /* | ||
832 | * SSI_CE0, SSI_CE1, SSI_GPC, SSI_CLK, SSI_DT, SSI_DR | ||
833 | */ | ||
834 | #define __gpio_as_ssi() \ | ||
835 | do { \ | ||
836 | REG_GPIO_PXFUNS(0) = 0x002c0000; /* SSI0_CE0, SSI0_CLK, SSI0_DT */ \ | ||
837 | REG_GPIO_PXTRGS(0) = 0x002c0000; \ | ||
838 | REG_GPIO_PXSELC(0) = 0x002c0000; \ | ||
839 | REG_GPIO_PXPES(0) = 0x002c0000; \ | ||
840 | \ | ||
841 | REG_GPIO_PXFUNS(0) = 0x00100000; /* SSI0_DR */ \ | ||
842 | REG_GPIO_PXTRGC(0) = 0x00100000; \ | ||
843 | REG_GPIO_PXSELS(0) = 0x00100000; \ | ||
844 | REG_GPIO_PXPES(0) = 0x00100000; \ | ||
845 | } while (0) | ||
846 | |||
847 | /* | ||
848 | * SSI_CE0, SSI_CE2, SSI_GPC, SSI_CLK, SSI_DT, SSI1_DR | ||
849 | */ | ||
850 | #define __gpio_as_ssi_1() \ | ||
851 | do { \ | ||
852 | REG_GPIO_PXFUNS(5) = 0x0000fc00; \ | ||
853 | REG_GPIO_PXTRGC(5) = 0x0000fc00; \ | ||
854 | REG_GPIO_PXSELC(5) = 0x0000fc00; \ | ||
855 | REG_GPIO_PXPES(5) = 0x0000fc00; \ | ||
856 | } while (0) | ||
857 | |||
858 | /* Port B | ||
859 | * SSI2_CE0, SSI2_CE2, SSI2_GPC, SSI2_CLK, SSI2_DT, SSI12_DR | ||
860 | */ | ||
861 | #define __gpio_as_ssi2_1() \ | ||
862 | do { \ | ||
863 | REG_GPIO_PXFUNS(5) = 0xf0300000; \ | ||
864 | REG_GPIO_PXTRGC(5) = 0xf0300000; \ | ||
865 | REG_GPIO_PXSELS(5) = 0xf0300000; \ | ||
866 | REG_GPIO_PXPES(5) = 0xf0300000; \ | ||
867 | } while (0) | ||
868 | |||
869 | #define __gpio_as_pcm0() \ | ||
870 | do { \ | ||
871 | REG_GPIO_PXFUNS(3) = 0xf; \ | ||
872 | REG_GPIO_PXTRGC(3) = 0xf; \ | ||
873 | REG_GPIO_PXSELC(3) = 0xf; \ | ||
874 | REG_GPIO_PXPES(3) = 0xf; \ | ||
875 | } while (0) | ||
876 | |||
877 | #define __gpio_as_pcm1() \ | ||
878 | do { \ | ||
879 | REG_GPIO_PXFUNS(3) = 0x1000; \ | ||
880 | REG_GPIO_PXTRGS(3) = 0x1000; \ | ||
881 | REG_GPIO_PXSELC(3) = 0x1000; \ | ||
882 | REG_GPIO_PXPES(3) = 0x1000; \ | ||
883 | REG_GPIO_PXFUNS(4) = 0x1000; \ | ||
884 | REG_GPIO_PXTRGC(4) = 0x300; \ | ||
885 | REG_GPIO_PXTRGS(4) = 0x20; \ | ||
886 | REG_GPIO_PXSELS(4) = 0x320; \ | ||
887 | REG_GPIO_PXPES(4) = 0x320; \ | ||
888 | } while (0) | ||
889 | /* | ||
890 | * I2C_SCK, I2C_SDA | ||
891 | */ | ||
892 | #define __gpio_as_i2c(n) \ | ||
893 | do { \ | ||
894 | REG_GPIO_PXFUNS(3+(n)) = 0xc0000000; \ | ||
895 | REG_GPIO_PXTRGC(3+(n)) = 0xc0000000; \ | ||
896 | REG_GPIO_PXSELC(3+(n)) = 0xc0000000; \ | ||
897 | REG_GPIO_PXPES(3+(n)) = 0xc0000000; \ | ||
898 | } while (0) | ||
899 | |||
900 | /* | ||
901 | * PWM0 | ||
902 | */ | ||
903 | #define __gpio_as_pwm0() \ | ||
904 | do { \ | ||
905 | REG_GPIO_PXFUNS(4) = 0x1; \ | ||
906 | REG_GPIO_PXTRGC(4) = 0x1; \ | ||
907 | REG_GPIO_PXSELC(4) = 0x1; \ | ||
908 | REG_GPIO_PXPES(4) = 0x1; \ | ||
909 | } while (0) | ||
910 | |||
911 | /* | ||
912 | * PWM1 | ||
913 | */ | ||
914 | #define __gpio_as_pwm1() \ | ||
915 | do { \ | ||
916 | REG_GPIO_PXFUNS(4) = 0x2; \ | ||
917 | REG_GPIO_PXTRGC(4) = 0x2; \ | ||
918 | REG_GPIO_PXSELC(4) = 0x2; \ | ||
919 | REG_GPIO_PXPEC(4) = 0x2; \ | ||
920 | } while (0) | ||
921 | |||
922 | /* | ||
923 | * PWM2 | ||
924 | */ | ||
925 | #define __gpio_as_pwm2() \ | ||
926 | do { \ | ||
927 | REG_GPIO_PXFUNS(4) = 0x4; \ | ||
928 | REG_GPIO_PXTRGC(4) = 0x4; \ | ||
929 | REG_GPIO_PXSELC(4) = 0x4; \ | ||
930 | REG_GPIO_PXPES(4) = 0x4; \ | ||
931 | } while (0) | ||
932 | |||
933 | /* | ||
934 | * PWM3 | ||
935 | */ | ||
936 | #define __gpio_as_pwm3() \ | ||
937 | do { \ | ||
938 | REG_GPIO_PXFUNS(4) = 0x8; \ | ||
939 | REG_GPIO_PXTRGC(4) = 0x8; \ | ||
940 | REG_GPIO_PXSELC(4) = 0x8; \ | ||
941 | REG_GPIO_PXPES(4) = 0x8; \ | ||
942 | } while (0) | ||
943 | |||
944 | /* | ||
945 | * PWM4 | ||
946 | */ | ||
947 | #define __gpio_as_pwm4() \ | ||
948 | do { \ | ||
949 | REG_GPIO_PXFUNS(4) = 0x10; \ | ||
950 | REG_GPIO_PXTRGC(4) = 0x10; \ | ||
951 | REG_GPIO_PXSELC(4) = 0x10; \ | ||
952 | REG_GPIO_PXPES(4) = 0x10; \ | ||
953 | } while (0) | ||
954 | |||
955 | /* | ||
956 | * PWM5 | ||
957 | */ | ||
958 | #define __gpio_as_pwm5() \ | ||
959 | do { \ | ||
960 | REG_GPIO_PXFUNS(4) = 0x20; \ | ||
961 | REG_GPIO_PXTRGC(4) = 0x20; \ | ||
962 | REG_GPIO_PXSELC(4) = 0x20; \ | ||
963 | REG_GPIO_PXPES(4) = 0x20; \ | ||
964 | } while (0) | ||
965 | |||
966 | /* | ||
967 | * n = 0 ~ 5 | ||
968 | */ | ||
969 | #define __gpio_as_pwm(n) __gpio_as_pwm##n() | ||
970 | |||
971 | /* | ||
972 | * OWI - PA29 function 1 | ||
973 | */ | ||
974 | #define __gpio_as_owi() \ | ||
975 | do { \ | ||
976 | REG_GPIO_PXFUNS(0) = 0x20000000; \ | ||
977 | REG_GPIO_PXTRGC(0) = 0x20000000; \ | ||
978 | REG_GPIO_PXSELS(0) = 0x20000000; \ | ||
979 | } while (0) | ||
980 | |||
981 | /* | ||
982 | * SCC - PD08 function 0 | ||
983 | * PD09 function 0 | ||
984 | */ | ||
985 | #define __gpio_as_scc() \ | ||
986 | do { \ | ||
987 | REG_GPIO_PXFUNS(3) = 0xc0000300; \ | ||
988 | REG_GPIO_PXTRGC(3) = 0xc0000300; \ | ||
989 | REG_GPIO_PXSELC(3) = 0xc0000300; \ | ||
990 | } while (0) | ||
991 | |||
992 | #define __gpio_as_otg_drvvbus() \ | ||
993 | do { \ | ||
994 | REG_GPIO_PXDATC(4) = (1 << 10); \ | ||
995 | REG_GPIO_PXPEC(4) = (1 << 10); \ | ||
996 | REG_GPIO_PXSELC(4) = (1 << 10); \ | ||
997 | REG_GPIO_PXTRGC(4) = (1 << 10); \ | ||
998 | REG_GPIO_PXFUNS(4) = (1 << 10); \ | ||
999 | } while (0) | ||
1000 | |||
1001 | //------------------------------------------- | ||
1002 | // GPIO or Interrupt Mode | ||
1003 | |||
1004 | #define __gpio_get_port(p) (REG_GPIO_PXPIN(p)) | ||
1005 | |||
1006 | #define __gpio_port_as_output(p, o) \ | ||
1007 | do { \ | ||
1008 | REG_GPIO_PXFUNC(p) = (1 << (o)); \ | ||
1009 | REG_GPIO_PXSELC(p) = (1 << (o)); \ | ||
1010 | REG_GPIO_PXDIRS(p) = (1 << (o)); \ | ||
1011 | REG_GPIO_PXPES(p) = (1 << (o)); \ | ||
1012 | } while (0) | ||
1013 | |||
1014 | #define __gpio_port_as_input(p, o) \ | ||
1015 | do { \ | ||
1016 | REG_GPIO_PXFUNC(p) = (1 << (o)); \ | ||
1017 | REG_GPIO_PXSELC(p) = (1 << (o)); \ | ||
1018 | REG_GPIO_PXDIRC(p) = (1 << (o)); \ | ||
1019 | } while (0) | ||
1020 | |||
1021 | #define __gpio_as_output(n) \ | ||
1022 | do { \ | ||
1023 | unsigned int p, o; \ | ||
1024 | p = (n) / 32; \ | ||
1025 | o = (n) % 32; \ | ||
1026 | __gpio_port_as_output(p, o); \ | ||
1027 | } while (0) | ||
1028 | |||
1029 | #define __gpio_as_input(n) \ | ||
1030 | do { \ | ||
1031 | unsigned int p, o; \ | ||
1032 | p = (n) / 32; \ | ||
1033 | o = (n) % 32; \ | ||
1034 | __gpio_port_as_input(p, o); \ | ||
1035 | } while (0) | ||
1036 | |||
1037 | #define __gpio_set_pin(n) \ | ||
1038 | do { \ | ||
1039 | unsigned int p, o; \ | ||
1040 | p = (n) / 32; \ | ||
1041 | o = (n) % 32; \ | ||
1042 | REG_GPIO_PXDATS(p) = (1 << o); \ | ||
1043 | } while (0) | ||
1044 | |||
1045 | #define __gpio_clear_pin(n) \ | ||
1046 | do { \ | ||
1047 | unsigned int p, o; \ | ||
1048 | p = (n) / 32; \ | ||
1049 | o = (n) % 32; \ | ||
1050 | REG_GPIO_PXDATC(p) = (1 << o); \ | ||
1051 | } while (0) | ||
1052 | |||
1053 | #define __gpio_get_pin(n) \ | ||
1054 | ({ \ | ||
1055 | unsigned int p, o, v; \ | ||
1056 | p = (n) / 32; \ | ||
1057 | o = (n) % 32; \ | ||
1058 | if (__gpio_get_port(p) & (1 << o)) \ | ||
1059 | v = 1; \ | ||
1060 | else \ | ||
1061 | v = 0; \ | ||
1062 | v; \ | ||
1063 | }) | ||
1064 | |||
1065 | #define __gpio_as_irq_high_level(n) \ | ||
1066 | do { \ | ||
1067 | unsigned int p, o; \ | ||
1068 | p = (n) / 32; \ | ||
1069 | o = (n) % 32; \ | ||
1070 | REG_GPIO_PXIMS(p) = (1 << o); \ | ||
1071 | REG_GPIO_PXTRGC(p) = (1 << o); \ | ||
1072 | REG_GPIO_PXFUNC(p) = (1 << o); \ | ||
1073 | REG_GPIO_PXSELS(p) = (1 << o); \ | ||
1074 | REG_GPIO_PXDIRS(p) = (1 << o); \ | ||
1075 | REG_GPIO_PXFLGC(p) = (1 << o); \ | ||
1076 | REG_GPIO_PXIMC(p) = (1 << o); \ | ||
1077 | } while (0) | ||
1078 | |||
1079 | #define __gpio_as_irq_low_level(n) \ | ||
1080 | do { \ | ||
1081 | unsigned int p, o; \ | ||
1082 | p = (n) / 32; \ | ||
1083 | o = (n) % 32; \ | ||
1084 | REG_GPIO_PXIMS(p) = (1 << o); \ | ||
1085 | REG_GPIO_PXTRGC(p) = (1 << o); \ | ||
1086 | REG_GPIO_PXFUNC(p) = (1 << o); \ | ||
1087 | REG_GPIO_PXSELS(p) = (1 << o); \ | ||
1088 | REG_GPIO_PXDIRC(p) = (1 << o); \ | ||
1089 | REG_GPIO_PXFLGC(p) = (1 << o); \ | ||
1090 | REG_GPIO_PXIMC(p) = (1 << o); \ | ||
1091 | } while (0) | ||
1092 | |||
1093 | #define __gpio_as_irq_rise_edge(n) \ | ||
1094 | do { \ | ||
1095 | unsigned int p, o; \ | ||
1096 | p = (n) / 32; \ | ||
1097 | o = (n) % 32; \ | ||
1098 | REG_GPIO_PXIMS(p) = (1 << o); \ | ||
1099 | REG_GPIO_PXTRGS(p) = (1 << o); \ | ||
1100 | REG_GPIO_PXFUNC(p) = (1 << o); \ | ||
1101 | REG_GPIO_PXSELS(p) = (1 << o); \ | ||
1102 | REG_GPIO_PXDIRS(p) = (1 << o); \ | ||
1103 | REG_GPIO_PXFLGC(p) = (1 << o); \ | ||
1104 | REG_GPIO_PXIMC(p) = (1 << o); \ | ||
1105 | } while (0) | ||
1106 | |||
1107 | #define __gpio_as_irq_fall_edge(n) \ | ||
1108 | do { \ | ||
1109 | unsigned int p, o; \ | ||
1110 | p = (n) / 32; \ | ||
1111 | o = (n) % 32; \ | ||
1112 | REG_GPIO_PXIMS(p) = (1 << o); \ | ||
1113 | REG_GPIO_PXTRGS(p) = (1 << o); \ | ||
1114 | REG_GPIO_PXFUNC(p) = (1 << o); \ | ||
1115 | REG_GPIO_PXSELS(p) = (1 << o); \ | ||
1116 | REG_GPIO_PXDIRC(p) = (1 << o); \ | ||
1117 | REG_GPIO_PXFLGC(p) = (1 << o); \ | ||
1118 | REG_GPIO_PXIMC(p) = (1 << o); \ | ||
1119 | } while (0) | ||
1120 | |||
1121 | #define __gpio_mask_irq(n) \ | ||
1122 | do { \ | ||
1123 | unsigned int p, o; \ | ||
1124 | p = (n) / 32; \ | ||
1125 | o = (n) % 32; \ | ||
1126 | REG_GPIO_PXIMS(p) = (1 << o); \ | ||
1127 | } while (0) | ||
1128 | |||
1129 | #define __gpio_unmask_irq(n) \ | ||
1130 | do { \ | ||
1131 | unsigned int p, o; \ | ||
1132 | p = (n) / 32; \ | ||
1133 | o = (n) % 32; \ | ||
1134 | REG_GPIO_PXIMC(p) = (1 << o); \ | ||
1135 | } while (0) | ||
1136 | |||
1137 | #define __gpio_ack_irq(n) \ | ||
1138 | do { \ | ||
1139 | unsigned int p, o; \ | ||
1140 | p = (n) / 32; \ | ||
1141 | o = (n) % 32; \ | ||
1142 | REG_GPIO_PXFLGC(p) = (1 << o); \ | ||
1143 | } while (0) | ||
1144 | |||
1145 | #define __gpio_get_irq() \ | ||
1146 | ({ \ | ||
1147 | unsigned int tmp, v = 0; \ | ||
1148 | for (int p = 5; p >= 0; p--) { \ | ||
1149 | tmp = REG_GPIO_PXFLG(p); \ | ||
1150 | for (int i = 0; i < 32; i++) \ | ||
1151 | if (tmp & (1 << i)) \ | ||
1152 | v = (32*p + i); \ | ||
1153 | } \ | ||
1154 | v; \ | ||
1155 | }) | ||
1156 | |||
1157 | #define __gpio_group_irq(n) \ | ||
1158 | ({ \ | ||
1159 | register int tmp, i; \ | ||
1160 | tmp = REG_GPIO_PXFLG(n) & (~REG_GPIO_PXIM(n)); \ | ||
1161 | for (i=31;i>=0;i--) \ | ||
1162 | if (tmp & (1 << i)) \ | ||
1163 | break; \ | ||
1164 | i; \ | ||
1165 | }) | ||
1166 | |||
1167 | #define __gpio_enable_pull(n) \ | ||
1168 | do { \ | ||
1169 | unsigned int p, o; \ | ||
1170 | p = (n) / 32; \ | ||
1171 | o = (n) % 32; \ | ||
1172 | REG_GPIO_PXPEC(p) = (1 << o); \ | ||
1173 | } while (0) | ||
1174 | |||
1175 | #define __gpio_disable_pull(n) \ | ||
1176 | do { \ | ||
1177 | unsigned int p, o; \ | ||
1178 | p = (n) / 32; \ | ||
1179 | o = (n) % 32; \ | ||
1180 | REG_GPIO_PXPES(p) = (1 << o); \ | ||
1181 | } while (0) | ||
1182 | |||
1183 | /* Set pin driver strength v: 0~7 */ | ||
1184 | #define __gpio_set_driving_strength(n, v) \ | ||
1185 | do { \ | ||
1186 | unsigned int p, o, d; \ | ||
1187 | p = (n) / 32; \ | ||
1188 | o = (n) % 32; \ | ||
1189 | d = v & 0x1; \ | ||
1190 | if(d) REG_GPIO_PXDS0S(p) = (1 << o); \ | ||
1191 | else REG_GPIO_PXDS0C(p) = (1 << o); \ | ||
1192 | d = v & 0x2; \ | ||
1193 | if(d) REG_GPIO_PXDS1S(p) = (1 << o); \ | ||
1194 | else REG_GPIO_PXDS1C(p) = (1 << o); \ | ||
1195 | d = v & 0x4; \ | ||
1196 | if(d) REG_GPIO_PXDS2S(p) = (1 << o); \ | ||
1197 | else REG_GPIO_PXDS2C(p) = (1 << o); \ | ||
1198 | } while(0) | ||
1199 | |||
1200 | /* Set fast slew rate */ | ||
1201 | #define __gpio_set_fslew(n) \ | ||
1202 | do { \ | ||
1203 | unsigned int p, o; \ | ||
1204 | p = (n) / 32; \ | ||
1205 | o = (n) % 32; \ | ||
1206 | REG_GPIO_PXSLS(p) = (1 << o); \ | ||
1207 | } while(0) | ||
1208 | |||
1209 | /* Set slow slew rate */ | ||
1210 | #define __gpio_set_sslew(n) \ | ||
1211 | do { \ | ||
1212 | unsigned int p, o; \ | ||
1213 | p = (n) / 32; \ | ||
1214 | o = (n) % 32; \ | ||
1215 | REG_GPIO_PXSLC(p) = (1 << o); \ | ||
1216 | } while(0) | ||
1217 | |||
1218 | #endif /* __MIPS_ASSEMBLER */ | ||
1219 | |||
1220 | #define DMAC_BASE 0xB3420000 | ||
1221 | |||
1222 | /************************************************************************* | ||
1223 | * DMAC (DMA Controller) | ||
1224 | *************************************************************************/ | ||
1225 | |||
1226 | #define MAX_DMA_NUM 12 /* max 12 channels */ | ||
1227 | #define MAX_MDMA_NUM 3 /* max 3 channels */ | ||
1228 | #define MAX_BDMA_NUM 3 /* max 3 channels */ | ||
1229 | #define HALF_DMA_NUM 6 /* the number of one dma controller's channels */ | ||
1230 | |||
1231 | /* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */ | ||
1232 | |||
1233 | #define DMAC_DSAR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x00 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA source address */ | ||
1234 | #define DMAC_DTAR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x04 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA target address */ | ||
1235 | #define DMAC_DTCR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x08 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA transfer count */ | ||
1236 | #define DMAC_DRSR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x0c + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA request source */ | ||
1237 | #define DMAC_DCCSR(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x10 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA control/status */ | ||
1238 | #define DMAC_DCMD(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x14 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA command */ | ||
1239 | #define DMAC_DDA(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0x18 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x20)) /* DMA descriptor address */ | ||
1240 | #define DMAC_DSD(n) (DMAC_BASE + ((n)/HALF_DMA_NUM*0x100 + 0xc0 + ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM) * 0x04)) /* DMA Stride Address */ | ||
1241 | |||
1242 | #define DMAC_DMACR(m) (DMAC_BASE + 0x0300 + 0x100 * (m)) /* DMA control register */ | ||
1243 | #define DMAC_DMAIPR(m) (DMAC_BASE + 0x0304 + 0x100 * (m)) /* DMA interrupt pending */ | ||
1244 | #define DMAC_DMADBR(m) (DMAC_BASE + 0x0308 + 0x100 * (m)) /* DMA doorbell */ | ||
1245 | #define DMAC_DMADBSR(m) (DMAC_BASE + 0x030C + 0x100 * (m)) /* DMA doorbell set */ | ||
1246 | #define DMAC_DMACKE(m) (DMAC_BASE + 0x0310 + 0x100 * (m)) | ||
1247 | #define DMAC_DMACKES(m) (DMAC_BASE + 0x0314 + 0x100 * (m)) | ||
1248 | #define DMAC_DMACKEC(m) (DMAC_BASE + 0x0318 + 0x100 * (m)) | ||
1249 | |||
1250 | #define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n))) | ||
1251 | #define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n))) | ||
1252 | #define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n))) | ||
1253 | #define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n))) | ||
1254 | #define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n))) | ||
1255 | #define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n))) | ||
1256 | #define REG_DMAC_DDA(n) REG32(DMAC_DDA((n))) | ||
1257 | #define REG_DMAC_DSD(n) REG32(DMAC_DSD(n)) | ||
1258 | #define REG_DMAC_DMACR(m) REG32(DMAC_DMACR(m)) | ||
1259 | #define REG_DMAC_DMAIPR(m) REG32(DMAC_DMAIPR(m)) | ||
1260 | #define REG_DMAC_DMADBR(m) REG32(DMAC_DMADBR(m)) | ||
1261 | #define REG_DMAC_DMADBSR(m) REG32(DMAC_DMADBSR(m)) | ||
1262 | #define REG_DMAC_DMACKE(m) REG32(DMAC_DMACKE(m)) | ||
1263 | #define REG_DMAC_DMACKES(m) REG32(DMAC_DMACKES(m)) | ||
1264 | #define REG_DMAC_DMACKEC(m) REG32(DMAC_DMACKEC(m)) | ||
1265 | |||
1266 | // DMA request source register | ||
1267 | #define DMAC_DRSR_RS_BIT 0 | ||
1268 | #define DMAC_DRSR_RS_MASK (0x3f << DMAC_DRSR_RS_BIT) | ||
1269 | #define DMAC_DRSR_RS_NAND (1 << DMAC_DRSR_RS_BIT) | ||
1270 | #define DMAC_DRSR_RS_BCH_ENC (2 << DMAC_DRSR_RS_BIT) | ||
1271 | #define DMAC_DRSR_RS_BCH_DEC (3 << DMAC_DRSR_RS_BIT) | ||
1272 | #define DMAC_DRSR_RS_AUTO (0x08 << DMAC_DRSR_RS_BIT) | ||
1273 | #define DMAC_DRSR_RS_TSSIIN (0x09 << DMAC_DRSR_RS_BIT) | ||
1274 | #define DMAC_DRSR_RS_EXT (0x0c << DMAC_DRSR_RS_BIT) | ||
1275 | #define DMAC_DRSR_RS_UART3OUT (0x0e << DMAC_DRSR_RS_BIT) | ||
1276 | #define DMAC_DRSR_RS_UART3IN (0x0f << DMAC_DRSR_RS_BIT) | ||
1277 | #define DMAC_DRSR_RS_UART2OUT (0x10 << DMAC_DRSR_RS_BIT) | ||
1278 | #define DMAC_DRSR_RS_UART2IN (0x11 << DMAC_DRSR_RS_BIT) | ||
1279 | #define DMAC_DRSR_RS_UART1OUT (0x12 << DMAC_DRSR_RS_BIT) | ||
1280 | #define DMAC_DRSR_RS_UART1IN (0x13 << DMAC_DRSR_RS_BIT) | ||
1281 | #define DMAC_DRSR_RS_UART0OUT (0x14 << DMAC_DRSR_RS_BIT) | ||
1282 | #define DMAC_DRSR_RS_UART0IN (0x15 << DMAC_DRSR_RS_BIT) | ||
1283 | #define DMAC_DRSR_RS_SSI0OUT (0x16 << DMAC_DRSR_RS_BIT) | ||
1284 | #define DMAC_DRSR_RS_SSI0IN (0x17 << DMAC_DRSR_RS_BIT) | ||
1285 | #define DMAC_DRSR_RS_AICOUT (0x18 << DMAC_DRSR_RS_BIT) | ||
1286 | #define DMAC_DRSR_RS_AICIN (0x19 << DMAC_DRSR_RS_BIT) | ||
1287 | #define DMAC_DRSR_RS_MSC0OUT (0x1a << DMAC_DRSR_RS_BIT) | ||
1288 | #define DMAC_DRSR_RS_MSC0IN (0x1b << DMAC_DRSR_RS_BIT) | ||
1289 | #define DMAC_DRSR_RS_TCU (0x1c << DMAC_DRSR_RS_BIT) | ||
1290 | #define DMAC_DRSR_RS_SADC (0x1d << DMAC_DRSR_RS_BIT) | ||
1291 | #define DMAC_DRSR_RS_MSC1OUT (0x1e << DMAC_DRSR_RS_BIT) | ||
1292 | #define DMAC_DRSR_RS_MSC1IN (0x1f << DMAC_DRSR_RS_BIT) | ||
1293 | #define DMAC_DRSR_RS_SSI1OUT (0x20 << DMAC_DRSR_RS_BIT) | ||
1294 | #define DMAC_DRSR_RS_SSI1IN (0x21 << DMAC_DRSR_RS_BIT) | ||
1295 | #define DMAC_DRSR_RS_PMOUT (0x22 << DMAC_DRSR_RS_BIT) | ||
1296 | #define DMAC_DRSR_RS_PMIN (0x23 << DMAC_DRSR_RS_BIT) | ||
1297 | #define DMAC_DRSR_RS_MSC2OUT (0x24 << DMAC_DRSR_RS_BIT) | ||
1298 | #define DMAC_DRSR_RS_MSC2IN (0x25 << DMAC_DRSR_RS_BIT) | ||
1299 | |||
1300 | // DMA channel control/status register | ||
1301 | #define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */ | ||
1302 | #define DMAC_DCCSR_DES8 (1 << 30) /* Descriptor 8 Word */ | ||
1303 | #define DMAC_DCCSR_DES4 (0 << 30) /* Descriptor 4 Word */ | ||
1304 | #define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */ | ||
1305 | #define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT) | ||
1306 | |||
1307 | #define DMAC_DCCSR_AR (1 << 4) /* address error */ | ||
1308 | #define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */ | ||
1309 | #define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */ | ||
1310 | #define DMAC_DCCSR_CT (1 << 1) /* count terminated */ | ||
1311 | #define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */ | ||
1312 | |||
1313 | // DMA channel command register | ||
1314 | #define DMAC_DCMD_EACKS_LOW (1 << 31) /* External DACK Output Level Select, active low */ | ||
1315 | #define DMAC_DCMD_EACKS_HIGH (0 << 31) /* External DACK Output Level Select, active high */ | ||
1316 | #define DMAC_DCMD_EACKM_WRITE (1 << 30) /* External DACK Output Mode Select, output in write cycle */ | ||
1317 | #define DMAC_DCMD_EACKM_READ (0 << 30) /* External DACK Output Mode Select, output in read cycle */ | ||
1318 | #define DMAC_DCMD_ERDM_BIT 28 /* External DREQ Detection Mode Select */ | ||
1319 | #define DMAC_DCMD_ERDM_MASK (0x03 << DMAC_DCMD_ERDM_BIT) | ||
1320 | #define DMAC_DCMD_ERDM_LOW (0 << DMAC_DCMD_ERDM_BIT) | ||
1321 | #define DMAC_DCMD_ERDM_FALL (1 << DMAC_DCMD_ERDM_BIT) | ||
1322 | #define DMAC_DCMD_ERDM_HIGH (2 << DMAC_DCMD_ERDM_BIT) | ||
1323 | #define DMAC_DCMD_ERDM_RISE (3 << DMAC_DCMD_ERDM_BIT) | ||
1324 | #define DMAC_DCMD_BLAST (1 << 25) /* BCH last */ | ||
1325 | #define DMAC_DCMD_SAI (1 << 23) /* source address increment */ | ||
1326 | #define DMAC_DCMD_DAI (1 << 22) /* dest address increment */ | ||
1327 | #define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */ | ||
1328 | #define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT) | ||
1329 | #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT) | ||
1330 | #define DMAC_DCMD_RDIL_2 (0x01 << DMAC_DCMD_RDIL_BIT) | ||
1331 | #define DMAC_DCMD_RDIL_4 (0x02 << DMAC_DCMD_RDIL_BIT) | ||
1332 | #define DMAC_DCMD_RDIL_8 (0x03 << DMAC_DCMD_RDIL_BIT) | ||
1333 | #define DMAC_DCMD_RDIL_12 (0x04 << DMAC_DCMD_RDIL_BIT) | ||
1334 | #define DMAC_DCMD_RDIL_16 (0x05 << DMAC_DCMD_RDIL_BIT) | ||
1335 | #define DMAC_DCMD_RDIL_20 (0x06 << DMAC_DCMD_RDIL_BIT) | ||
1336 | #define DMAC_DCMD_RDIL_24 (0x07 << DMAC_DCMD_RDIL_BIT) | ||
1337 | #define DMAC_DCMD_RDIL_28 (0x08 << DMAC_DCMD_RDIL_BIT) | ||
1338 | #define DMAC_DCMD_RDIL_32 (0x09 << DMAC_DCMD_RDIL_BIT) | ||
1339 | #define DMAC_DCMD_RDIL_48 (0x0a << DMAC_DCMD_RDIL_BIT) | ||
1340 | #define DMAC_DCMD_RDIL_60 (0x0b << DMAC_DCMD_RDIL_BIT) | ||
1341 | #define DMAC_DCMD_RDIL_64 (0x0c << DMAC_DCMD_RDIL_BIT) | ||
1342 | #define DMAC_DCMD_RDIL_124 (0x0d << DMAC_DCMD_RDIL_BIT) | ||
1343 | #define DMAC_DCMD_RDIL_128 (0x0e << DMAC_DCMD_RDIL_BIT) | ||
1344 | #define DMAC_DCMD_RDIL_200 (0x0f << DMAC_DCMD_RDIL_BIT) | ||
1345 | #define DMAC_DCMD_SWDH_BIT 14 /* source port width */ | ||
1346 | #define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT) | ||
1347 | #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT) | ||
1348 | #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT) | ||
1349 | #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT) | ||
1350 | #define DMAC_DCMD_DWDH_BIT 12 /* dest port width */ | ||
1351 | #define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT) | ||
1352 | #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT) | ||
1353 | #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT) | ||
1354 | #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT) | ||
1355 | #define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */ | ||
1356 | #define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT) | ||
1357 | #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT) | ||
1358 | #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT) | ||
1359 | #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT) | ||
1360 | #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT) | ||
1361 | #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT) | ||
1362 | #define DMAC_DCMD_DS_64BYTE (5 << DMAC_DCMD_DS_BIT) | ||
1363 | |||
1364 | #define DMAC_DCMD_STDE (1 << 2) /* Stride enable */ | ||
1365 | #define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */ | ||
1366 | #define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */ | ||
1367 | |||
1368 | // DMA descriptor address register | ||
1369 | #define DMAC_DDA_BASE_BIT 12 /* descriptor base address */ | ||
1370 | #define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT) | ||
1371 | #define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */ | ||
1372 | #define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT) | ||
1373 | |||
1374 | // DMA stride address register | ||
1375 | #define DMAC_DSD_TSD_BIT 16 /* target stride address */ | ||
1376 | #define DMAC_DSD_TSD_MASK (0xffff << DMAC_DSD_TSD_BIT) | ||
1377 | #define DMAC_DSD_SSD_BIT 0 /* source stride address */ | ||
1378 | #define DMAC_DSD_SSD_MASK (0xffff << DMAC_DSD_SSD_BIT) | ||
1379 | |||
1380 | // DMA control register | ||
1381 | #define DMAC_DMACR_FMSC (1 << 31) /* MSC Fast DMA mode */ | ||
1382 | #define DMAC_DMACR_FSSI (1 << 30) /* SSI Fast DMA mode */ | ||
1383 | #define DMAC_DMACR_FTSSI (1 << 29) /* TSSI Fast DMA mode */ | ||
1384 | #define DMAC_DMACR_FUART (1 << 28) /* UART Fast DMA mode */ | ||
1385 | #define DMAC_DMACR_FAIC (1 << 27) /* AIC Fast DMA mode */ | ||
1386 | #define DMAC_DMACR_PR_BIT 8 /* channel priority mode */ | ||
1387 | #define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT) | ||
1388 | #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT) | ||
1389 | #define DMAC_DMACR_PR_120345 (1 << DMAC_DMACR_PR_BIT) | ||
1390 | #define DMAC_DMACR_PR_230145 (2 << DMAC_DMACR_PR_BIT) | ||
1391 | #define DMAC_DMACR_PR_340125 (3 << DMAC_DMACR_PR_BIT) | ||
1392 | #define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */ | ||
1393 | #define DMAC_DMACR_AR (1 << 2) /* address error flag */ | ||
1394 | #define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */ | ||
1395 | |||
1396 | // DMA doorbell register | ||
1397 | #define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */ | ||
1398 | #define DMAC_DMADBR_DB4 (1 << 4) /* doorbell for channel 4 */ | ||
1399 | #define DMAC_DMADBR_DB3 (1 << 3) /* doorbell for channel 3 */ | ||
1400 | #define DMAC_DMADBR_DB2 (1 << 2) /* doorbell for channel 2 */ | ||
1401 | #define DMAC_DMADBR_DB1 (1 << 1) /* doorbell for channel 1 */ | ||
1402 | #define DMAC_DMADBR_DB0 (1 << 0) /* doorbell for channel 0 */ | ||
1403 | |||
1404 | // DMA doorbell set register | ||
1405 | #define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */ | ||
1406 | #define DMAC_DMADBSR_DBS4 (1 << 4) /* enable doorbell for channel 4 */ | ||
1407 | #define DMAC_DMADBSR_DBS3 (1 << 3) /* enable doorbell for channel 3 */ | ||
1408 | #define DMAC_DMADBSR_DBS2 (1 << 2) /* enable doorbell for channel 2 */ | ||
1409 | #define DMAC_DMADBSR_DBS1 (1 << 1) /* enable doorbell for channel 1 */ | ||
1410 | #define DMAC_DMADBSR_DBS0 (1 << 0) /* enable doorbell for channel 0 */ | ||
1411 | |||
1412 | // DMA interrupt pending register | ||
1413 | #define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */ | ||
1414 | #define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */ | ||
1415 | #define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */ | ||
1416 | #define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */ | ||
1417 | #define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */ | ||
1418 | #define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */ | ||
1419 | |||
1420 | #ifndef __MIPS_ASSEMBLER | ||
1421 | |||
1422 | /*************************************************************************** | ||
1423 | * DMAC | ||
1424 | ***************************************************************************/ | ||
1425 | |||
1426 | /* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */ | ||
1427 | |||
1428 | #define __dmac_enable_module(m) \ | ||
1429 | ( REG_DMAC_DMACR(m) |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_012345 ) | ||
1430 | #define __dmac_disable_module(m) \ | ||
1431 | ( REG_DMAC_DMACR(m) &= ~DMAC_DMACR_DMAE ) | ||
1432 | |||
1433 | /* p=0,1,2,3 */ | ||
1434 | #define __dmac_set_priority(m,p) \ | ||
1435 | do { \ | ||
1436 | REG_DMAC_DMACR(m) &= ~DMAC_DMACR_PR_MASK; \ | ||
1437 | REG_DMAC_DMACR(m) |= ((p) << DMAC_DMACR_PR_BIT); \ | ||
1438 | } while (0) | ||
1439 | |||
1440 | #define __dmac_test_halt_error(m) ( REG_DMAC_DMACR(m) & DMAC_DMACR_HLT ) | ||
1441 | #define __dmac_test_addr_error(m) ( REG_DMAC_DMACR(m) & DMAC_DMACR_AR ) | ||
1442 | |||
1443 | #define __dmac_channel_enable_clk(n) \ | ||
1444 | REG_DMAC_DMACKES((n)/HALF_DMA_NUM) = 1 << ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM); | ||
1445 | |||
1446 | #define __dmac_channel_disable_clk(n) \ | ||
1447 | REG_DMAC_DMACKEC((n)/HALF_DMA_NUM) = 1 << ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM); | ||
1448 | |||
1449 | #define __dmac_enable_descriptor(n) \ | ||
1450 | ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES ) | ||
1451 | #define __dmac_disable_descriptor(n) \ | ||
1452 | ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES ) | ||
1453 | |||
1454 | #define __dmac_enable_channel(n) \ | ||
1455 | do { \ | ||
1456 | REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN; \ | ||
1457 | } while (0) | ||
1458 | #define __dmac_disable_channel(n) \ | ||
1459 | do { \ | ||
1460 | REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN; \ | ||
1461 | } while (0) | ||
1462 | #define __dmac_channel_enabled(n) \ | ||
1463 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN ) | ||
1464 | |||
1465 | #define __dmac_channel_enable_irq(n) \ | ||
1466 | ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE ) | ||
1467 | #define __dmac_channel_disable_irq(n) \ | ||
1468 | ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE ) | ||
1469 | |||
1470 | #define __dmac_channel_transmit_halt_detected(n) \ | ||
1471 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT ) | ||
1472 | #define __dmac_channel_transmit_end_detected(n) \ | ||
1473 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT ) | ||
1474 | #define __dmac_channel_address_error_detected(n) \ | ||
1475 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR ) | ||
1476 | |||
1477 | #define __dmac_channel_count_terminated_detected(n) \ | ||
1478 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT ) | ||
1479 | #define __dmac_channel_descriptor_invalid_detected(n) \ | ||
1480 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV ) | ||
1481 | |||
1482 | #define __dmac_channel_clear_transmit_halt(n) \ | ||
1483 | do { \ | ||
1484 | /* clear both channel halt error and globle halt error */ \ | ||
1485 | REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT; \ | ||
1486 | REG_DMAC_DMACR(n/HALF_DMA_NUM) &= ~DMAC_DMACR_HLT; \ | ||
1487 | } while (0) | ||
1488 | #define __dmac_channel_clear_transmit_end(n) \ | ||
1489 | ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT ) | ||
1490 | #define __dmac_channel_clear_address_error(n) \ | ||
1491 | do { \ | ||
1492 | REG_DMAC_DDA(n) = 0; /* clear descriptor address register */ \ | ||
1493 | REG_DMAC_DSAR(n) = 0; /* clear source address register */ \ | ||
1494 | REG_DMAC_DTAR(n) = 0; /* clear target address register */ \ | ||
1495 | /* clear both channel addr error and globle address error */ \ | ||
1496 | REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR; \ | ||
1497 | REG_DMAC_DMACR(n/HALF_DMA_NUM) &= ~DMAC_DMACR_AR; \ | ||
1498 | } while (0) | ||
1499 | |||
1500 | #define __dmac_channel_clear_count_terminated(n) \ | ||
1501 | ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT ) | ||
1502 | #define __dmac_channel_clear_descriptor_invalid(n) \ | ||
1503 | ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV ) | ||
1504 | |||
1505 | #define __dmac_channel_set_transfer_unit_32bit(n) \ | ||
1506 | do { \ | ||
1507 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ | ||
1508 | REG_DMAC_DCMD((n)) |= MAC_DCMD_DS_32BIT; \ | ||
1509 | } while (0) | ||
1510 | |||
1511 | #define __dmac_channel_set_transfer_unit_16bit(n) \ | ||
1512 | do { \ | ||
1513 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ | ||
1514 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \ | ||
1515 | } while (0) | ||
1516 | |||
1517 | #define __dmac_channel_set_transfer_unit_8bit(n) \ | ||
1518 | do { \ | ||
1519 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ | ||
1520 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \ | ||
1521 | } while (0) | ||
1522 | |||
1523 | #define __dmac_channel_set_transfer_unit_16byte(n) \ | ||
1524 | do { \ | ||
1525 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ | ||
1526 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \ | ||
1527 | } while (0) | ||
1528 | |||
1529 | #define __dmac_channel_set_transfer_unit_32byte(n) \ | ||
1530 | do { \ | ||
1531 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ | ||
1532 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \ | ||
1533 | } while (0) | ||
1534 | |||
1535 | /* w=8,16,32 */ | ||
1536 | #define __dmac_channel_set_dest_port_width(n,w) \ | ||
1537 | do { \ | ||
1538 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \ | ||
1539 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \ | ||
1540 | } while (0) | ||
1541 | |||
1542 | /* w=8,16,32 */ | ||
1543 | #define __dmac_channel_set_src_port_width(n,w) \ | ||
1544 | do { \ | ||
1545 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \ | ||
1546 | REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \ | ||
1547 | } while (0) | ||
1548 | |||
1549 | /* v=0-15 */ | ||
1550 | #define __dmac_channel_set_rdil(n,v) \ | ||
1551 | do { \ | ||
1552 | REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \ | ||
1553 | REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \ | ||
1554 | } while (0) | ||
1555 | |||
1556 | #define __dmac_channel_dest_addr_fixed(n) \ | ||
1557 | ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI ) | ||
1558 | #define __dmac_channel_dest_addr_increment(n) \ | ||
1559 | ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI ) | ||
1560 | |||
1561 | #define __dmac_channel_src_addr_fixed(n) \ | ||
1562 | ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI ) | ||
1563 | #define __dmac_channel_src_addr_increment(n) \ | ||
1564 | ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI ) | ||
1565 | |||
1566 | #define __dmac_channel_set_doorbell(n) \ | ||
1567 | ( REG_DMAC_DMADBSR((n)/HALF_DMA_NUM) = (1 << ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM)) ) | ||
1568 | |||
1569 | #define __dmac_channel_irq_detected(n) ( REG_DMAC_DMAIPR((n)/HALF_DMA_NUM) & (1 << ((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM)) ) | ||
1570 | #define __dmac_channel_ack_irq(n) ( REG_DMAC_DMAIPR((n)/HALF_DMA_NUM) &= ~(1 <<((n)-(n)/HALF_DMA_NUM*HALF_DMA_NUM)) ) | ||
1571 | |||
1572 | static __inline__ int __dmac_get_irq(void) | ||
1573 | { | ||
1574 | int i; | ||
1575 | for (i = 0; i < MAX_DMA_NUM; i++) | ||
1576 | if (__dmac_channel_irq_detected(i)) | ||
1577 | return i; | ||
1578 | return -1; | ||
1579 | } | ||
1580 | |||
1581 | #endif /* __MIPS_ASSEMBLER */ | ||
1582 | |||
1583 | /* | ||
1584 | * Interrupt controller module(INTC) address definition | ||
1585 | */ | ||
1586 | #define INTC_BASE 0xB0001000 | ||
1587 | |||
1588 | /* | ||
1589 | * INTC registers offset address definition | ||
1590 | */ | ||
1591 | #define INTC_ICSR_OFFSET (0x00) /* 32, r, 0x00000000 */ | ||
1592 | #define INTC_ICMR_OFFSET (0x04) /* 32, rw, 0xffffffff */ | ||
1593 | #define INTC_ICMSR_OFFSET (0x08) /* 32, w, 0x???????? */ | ||
1594 | #define INTC_ICMCR_OFFSET (0x0c) /* 32, w, 0x???????? */ | ||
1595 | #define INTC_ICPR_OFFSET (0x10) /* 32, r, 0x00000000 */ | ||
1596 | |||
1597 | /* INTC groups offset */ | ||
1598 | #define INTC_GOS 0x20 | ||
1599 | |||
1600 | /* | ||
1601 | * INTC registers address definition | ||
1602 | */ | ||
1603 | #define INTC_ICSR(n) (INTC_BASE + (n) * INTC_GOS + INTC_ICSR_OFFSET) | ||
1604 | #define INTC_ICMR(n) (INTC_BASE + (n) * INTC_GOS + INTC_ICMR_OFFSET) | ||
1605 | #define INTC_ICMSR(n) (INTC_BASE + (n) * INTC_GOS + INTC_ICMSR_OFFSET) | ||
1606 | #define INTC_ICMCR(n) (INTC_BASE + (n) * INTC_GOS + INTC_ICMCR_OFFSET) | ||
1607 | #define INTC_ICPR(n) (INTC_BASE + (n) * INTC_GOS + INTC_ICPR_OFFSET) | ||
1608 | |||
1609 | /* | ||
1610 | * INTC registers common define | ||
1611 | */ | ||
1612 | |||
1613 | /* 1st-level interrupts */ | ||
1614 | #define IRQ_I2C1 0 | ||
1615 | #define IRQ_I2C0 1 | ||
1616 | #define IRQ_UART3 2 | ||
1617 | #define IRQ_UART2 3 | ||
1618 | #define IRQ_UART1 4 | ||
1619 | #define IRQ_UART0 5 | ||
1620 | #define IRQ_GPU 6 | ||
1621 | #define IRQ_SSI1 7 | ||
1622 | #define IRQ_SSI0 8 | ||
1623 | #define IRQ_TSSI 9 | ||
1624 | #define IRQ_BDMA 10 | ||
1625 | #define IRQ_KBC 11 | ||
1626 | #define IRQ_GPIO5 12 | ||
1627 | #define IRQ_GPIO4 13 | ||
1628 | #define IRQ_GPIO3 14 | ||
1629 | #define IRQ_GPIO2 15 | ||
1630 | #define IRQ_GPIO1 16 | ||
1631 | #define IRQ_GPIO0 17 | ||
1632 | #define IRQ_SADC 18 | ||
1633 | #define IRQ_ETH 19 | ||
1634 | #define IRQ_UHC 20 | ||
1635 | #define IRQ_OTG 21 | ||
1636 | #define IRQ_MDMA 22 | ||
1637 | #define IRQ_DMAC1 23 | ||
1638 | #define IRQ_DMAC0 24 | ||
1639 | #define IRQ_TCU2 25 | ||
1640 | #define IRQ_TCU1 26 | ||
1641 | #define IRQ_TCU0 27 | ||
1642 | #define IRQ_GPS 28 | ||
1643 | #define IRQ_IPU 29 | ||
1644 | #define IRQ_CIM 30 | ||
1645 | #define IRQ_LCD 31 | ||
1646 | |||
1647 | #define IRQ_RTC 32 /* 32 + 0 */ | ||
1648 | #define IRQ_OWI 33 /* 32 + 1 */ | ||
1649 | #define IRQ_AIC 34 /* 32 + 2 */ | ||
1650 | #define IRQ_MSC2 35 /* 32 + 3 */ | ||
1651 | #define IRQ_MSC1 36 /* 32 + 4 */ | ||
1652 | #define IRQ_MSC0 37 /* 32 + 5 */ | ||
1653 | #define IRQ_SCC 38 /* 32 + 6 */ | ||
1654 | #define IRQ_BCH 39 /* 32 + 7 */ | ||
1655 | #define IRQ_PCM 40 /* 32 + 8 */ | ||
1656 | #define IRQ_HARB0 41 /* 32 + 9 */ | ||
1657 | #define IRQ_HARB2 42 /* 32 + 10 */ | ||
1658 | #define IRQ_AOSD 43 /* 32 + 11 */ | ||
1659 | #define IRQ_CPM 44 /* 32 + 12 */ | ||
1660 | |||
1661 | #define IRQ_INTC_MAX 45 | ||
1662 | |||
1663 | /* 2nd-level interrupts */ | ||
1664 | #define IRQ_DMA_BASE (IRQ_INTC_MAX) | ||
1665 | #define IRQ_DMA_MAX (IRQ_DMA_BASE + NUM_DMA) | ||
1666 | |||
1667 | #define IRQ_MDMA_BASE (IRQ_DMA_MAX) | ||
1668 | #define IRQ_MDMA_MAX (IRQ_MDMA_BASE + NUM_MDMA) | ||
1669 | |||
1670 | #define IRQ_BDMA_BASE (IRQ_MDMA_MAX) | ||
1671 | #define IRQ_BDMA_MAX (IRQ_BDMA_BASE + NUM_BDMA) | ||
1672 | |||
1673 | /* To be cleanup begin */ | ||
1674 | #define IRQ_DMA_0 46 | ||
1675 | #define IRQ_DMA_1 (IRQ_DMA_0 + HALF_DMA_NUM) /* 46 + 6 = 52 */ | ||
1676 | #define IRQ_MDMA_0 (IRQ_DMA_0 + MAX_DMA_NUM) /* 46 + 12 = 58 */ | ||
1677 | #define IRQ_BDMA_0 (IRQ_DMA_0 + MAX_DMA_NUM + MAX_MDMA_NUM) /* 46 + 12 + 2 = 60 */ | ||
1678 | |||
1679 | #define IRQ_GPIO_0 64 /* 64 to (64+MAX_GPIO_NUM-1) for GPIO pin 0 to MAX_GPIO_NUM-1 */ | ||
1680 | |||
1681 | #define NUM_INTC 45 | ||
1682 | #define NUM_DMA MAX_DMA_NUM | ||
1683 | #define NUM_MDMA MAX_MDMA_NUM | ||
1684 | #define NUM_BDMA MAX_BDMA_NUM | ||
1685 | #define NUM_GPIO MAX_GPIO_NUM | ||
1686 | /* To be cleanup end */ | ||
1687 | |||
1688 | #ifndef __MIPS_ASSEMBLER | ||
1689 | |||
1690 | #define REG_INTC_ICMR(n) REG32(INTC_ICMR(n)) | ||
1691 | #define REG_INTC_ICMSR(n) REG32(INTC_ICMSR(n)) | ||
1692 | #define REG_INTC_ICMCR(n) REG32(INTC_ICMCR(n)) | ||
1693 | #define REG_INTC_ICPR(n) REG32(INTC_ICPR(n)) | ||
1694 | |||
1695 | #define __intc_unmask_irq(n) (REG_INTC_ICMCR((n)/32) = (1 << ((n)%32))) | ||
1696 | #define __intc_mask_irq(n) (REG_INTC_ICMSR((n)/32) = (1 << ((n)%32))) | ||
1697 | |||
1698 | #endif /* __MIPS_ASSEMBLER */ | ||
1699 | |||
1700 | /* | ||
1701 | * AC97 and I2S controller module(AIC) address definition | ||
1702 | */ | ||
1703 | #define AIC_BASE 0xb0020000 | ||
1704 | |||
1705 | /* | ||
1706 | * AIC registers offset address definition | ||
1707 | */ | ||
1708 | #define AIC_FR_OFFSET (0x00) | ||
1709 | #define AIC_CR_OFFSET (0x04) | ||
1710 | #define AIC_ACCR1_OFFSET (0x08) | ||
1711 | #define AIC_ACCR2_OFFSET (0x0c) | ||
1712 | #define AIC_I2SCR_OFFSET (0x10) | ||
1713 | #define AIC_SR_OFFSET (0x14) | ||
1714 | #define AIC_ACSR_OFFSET (0x18) | ||
1715 | #define AIC_I2SSR_OFFSET (0x1c) | ||
1716 | #define AIC_ACCAR_OFFSET (0x20) | ||
1717 | #define AIC_ACCDR_OFFSET (0x24) | ||
1718 | #define AIC_ACSAR_OFFSET (0x28) | ||
1719 | #define AIC_ACSDR_OFFSET (0x2c) | ||
1720 | #define AIC_I2SDIV_OFFSET (0x30) | ||
1721 | #define AIC_DR_OFFSET (0x34) | ||
1722 | |||
1723 | #define SPDIF_ENA_OFFSET (0x80) | ||
1724 | #define SPDIF_CTRL_OFFSET (0x84) | ||
1725 | #define SPDIF_STATE_OFFSET (0x88) | ||
1726 | #define SPDIF_CFG1_OFFSET (0x8c) | ||
1727 | #define SPDIF_CFG2_OFFSET (0x90) | ||
1728 | #define SPDIF_FIFO_OFFSET (0x94) | ||
1729 | |||
1730 | #define ICDC_RGADW_OFFSET (0xa4) | ||
1731 | #define ICDC_RGDATA_OFFSET (0xa8) | ||
1732 | |||
1733 | /* | ||
1734 | * AIC registers address definition | ||
1735 | */ | ||
1736 | #define AIC_FR (AIC_BASE + AIC_FR_OFFSET) | ||
1737 | #define AIC_CR (AIC_BASE + AIC_CR_OFFSET) | ||
1738 | #define AIC_ACCR1 (AIC_BASE + AIC_ACCR1_OFFSET) | ||
1739 | #define AIC_ACCR2 (AIC_BASE + AIC_ACCR2_OFFSET) | ||
1740 | #define AIC_I2SCR (AIC_BASE + AIC_I2SCR_OFFSET) | ||
1741 | #define AIC_SR (AIC_BASE + AIC_SR_OFFSET) | ||
1742 | #define AIC_ACSR (AIC_BASE + AIC_ACSR_OFFSET) | ||
1743 | #define AIC_I2SSR (AIC_BASE + AIC_I2SSR_OFFSET) | ||
1744 | #define AIC_ACCAR (AIC_BASE + AIC_ACCAR_OFFSET) | ||
1745 | #define AIC_ACCDR (AIC_BASE + AIC_ACCDR_OFFSET) | ||
1746 | #define AIC_ACSAR (AIC_BASE + AIC_ACSAR_OFFSET) | ||
1747 | #define AIC_ACSDR (AIC_BASE + AIC_ACSDR_OFFSET) | ||
1748 | #define AIC_I2SDIV (AIC_BASE + AIC_I2SDIV_OFFSET) | ||
1749 | #define AIC_DR (AIC_BASE + AIC_DR_OFFSET) | ||
1750 | |||
1751 | #define SPDIF_ENA (AIC_BASE + SPDIF_ENA_OFFSET) | ||
1752 | #define SPDIF_CTRL (AIC_BASE + SPDIF_CTRL_OFFSET) | ||
1753 | #define SPDIF_STATE (AIC_BASE + SPDIF_STATE_OFFSET) | ||
1754 | #define SPDIF_CFG1 (AIC_BASE + SPDIF_CFG1_OFFSET) | ||
1755 | #define SPDIF_CFG2 (AIC_BASE + SPDIF_CFG2_OFFSET) | ||
1756 | #define SPDIF_FIFO (AIC_BASE + SPDIF_FIFO_OFFSET) | ||
1757 | |||
1758 | #define ICDC_RGADW (AIC_BASE + ICDC_RGADW_OFFSET) | ||
1759 | #define ICDC_RGDATA (AIC_BASE + ICDC_RGDATA_OFFSET) | ||
1760 | |||
1761 | /* | ||
1762 | * AIC registers common define | ||
1763 | */ | ||
1764 | |||
1765 | /* AIC controller configuration register(AICFR) */ | ||
1766 | #define AIC_FR_LSMP BIT6 | ||
1767 | #define AIC_FR_ICDC BIT5 | ||
1768 | #define AIC_FR_AUSEL BIT4 | ||
1769 | #define AIC_FR_RST BIT3 | ||
1770 | #define AIC_FR_BCKD BIT2 | ||
1771 | #define AIC_FR_SYNCD BIT1 | ||
1772 | #define AIC_FR_ENB BIT0 | ||
1773 | |||
1774 | #define AIC_FR_RFTH_LSB 24 | ||
1775 | #define AIC_FR_RFTH_MASK BITS_H2L(27, AIC_FR_RFTH_LSB) | ||
1776 | |||
1777 | #define AIC_FR_TFTH_LSB 16 | ||
1778 | #define AIC_FR_TFTH_MASK BITS_H2L(20, AIC_FR_TFTH_LSB) | ||
1779 | |||
1780 | /* AIC controller common control register(AICCR) */ | ||
1781 | #define AIC_CR_PACK16 BIT28 | ||
1782 | #define AIC_CR_RDMS BIT15 | ||
1783 | #define AIC_CR_TDMS BIT14 | ||
1784 | #define AIC_CR_M2S BIT11 | ||
1785 | #define AIC_CR_ENDSW BIT10 | ||
1786 | #define AIC_CR_AVSTSU BIT9 | ||
1787 | #define AIC_CR_TFLUSH BIT8 | ||
1788 | #define AIC_CR_RFLUSH BIT7 | ||
1789 | #define AIC_CR_EROR BIT6 | ||
1790 | #define AIC_CR_ETUR BIT5 | ||
1791 | #define AIC_CR_ERFS BIT4 | ||
1792 | #define AIC_CR_ETFS BIT3 | ||
1793 | #define AIC_CR_ENLBF BIT2 | ||
1794 | #define AIC_CR_ERPL BIT1 | ||
1795 | #define AIC_CR_EREC BIT0 | ||
1796 | |||
1797 | #define AIC_CR_CHANNEL_LSB 24 | ||
1798 | #define AIC_CR_CHANNEL_MASK BITS_H2L(26, AIC_CR_CHANNEL_LSB) | ||
1799 | |||
1800 | #define AIC_CR_OSS_LSB 19 | ||
1801 | #define AIC_CR_OSS_MASK BITS_H2L(21, AIC_CR_OSS_LSB) | ||
1802 | #define AIC_CR_OSS(n) (((n) > 18 ? (n)/6 : (n)/9) << AIC_CR_OSS_LSB) /* n = 8, 16, 18, 20, 24 */ | ||
1803 | |||
1804 | #define AIC_CR_ISS_LSB 16 | ||
1805 | #define AIC_CR_ISS_MASK BITS_H2L(18, AIC_CR_ISS_LSB) | ||
1806 | #define AIC_CR_ISS(n) (((n) > 18 ? (n)/6 : (n)/9) << AIC_CR_ISS_LSB) /* n = 8, 16, 18, 20, 24 */ | ||
1807 | |||
1808 | /* AIC controller AC-link control register 1(ACCR1) */ | ||
1809 | #define AIC_ACCR1_RS_LSB 16 | ||
1810 | #define AIC_ACCR1_RS_MASK BITS_H2L(25, AIC_ACCR1_RS_LSB) | ||
1811 | #define AIC_ACCR1_RS_SLOT(n) ((1 << ((n) - 3)) << AIC_ACCR1_RS_LSB) /* n = 3 .. 12 */ | ||
1812 | |||
1813 | #define AIC_ACCR1_XS_LSB 0 | ||
1814 | #define AIC_ACCR1_XS_MASK BITS_H2L(9, AIC_ACCR1_XS_LSB) | ||
1815 | #define AIC_ACCR1_XS_SLOT(n) ((1 << ((n) - 3)) << AIC_ACCR1_XS_LSB) /* n = 3 .. 12 */ | ||
1816 | |||
1817 | /* AIC controller AC-link control register 2 (ACCR2) */ | ||
1818 | #define AIC_ACCR2_ERSTO BIT18 | ||
1819 | #define AIC_ACCR2_ESADR BIT17 | ||
1820 | #define AIC_ACCR2_ECADT BIT16 | ||
1821 | #define AIC_ACCR2_SO BIT3 | ||
1822 | #define AIC_ACCR2_SR BIT2 | ||
1823 | #define AIC_ACCR2_SS BIT1 | ||
1824 | #define AIC_ACCR2_SA BIT0 | ||
1825 | |||
1826 | /* AIC controller i2s/msb-justified control register (I2SCR) */ | ||
1827 | #define AIC_I2SCR_RFIRST BIT17 | ||
1828 | #define AIC_I2SCR_SWLH BIT16 | ||
1829 | #define AIC_I2SCR_STPBK BIT12 | ||
1830 | #define AIC_I2SCR_ESCLK BIT4 | ||
1831 | #define AIC_I2SCR_AMSL BIT0 | ||
1832 | |||
1833 | /* AIC controller FIFO status register (AICSR) */ | ||
1834 | #define AIC_SR_ROR BIT6 | ||
1835 | #define AIC_SR_TUR BIT5 | ||
1836 | #define AIC_SR_RFS BIT4 | ||
1837 | #define AIC_SR_TFS BIT3 | ||
1838 | |||
1839 | #define AIC_SR_RFL_LSB 24 | ||
1840 | #define AIC_SR_RFL_MASK BITS_H2L(29, AIC_SR_RFL_LSB) | ||
1841 | |||
1842 | #define AIC_SR_TFL_LSB 8 | ||
1843 | #define AIC_SR_TFL_MASK BITS_H2L(13, AIC_SR_TFL_LSB) | ||
1844 | |||
1845 | /* AIC controller AC-link status register (ACSR) */ | ||
1846 | #define AIC_ACSR_SLTERR BIT21 | ||
1847 | #define AIC_ACSR_CRDY BIT20 | ||
1848 | #define AIC_ACSR_CLPM BIT19 | ||
1849 | #define AIC_ACSR_RSTO BIT18 | ||
1850 | #define AIC_ACSR_SADR BIT17 | ||
1851 | #define AIC_ACSR_CADT BIT16 | ||
1852 | |||
1853 | /* AIC controller I2S/MSB-justified status register (I2SSR) */ | ||
1854 | #define AIC_I2SSR_CHBSY BIT5 | ||
1855 | #define AIC_I2SSR_TBSY BIT4 | ||
1856 | #define AIC_I2SSR_RBSY BIT3 | ||
1857 | #define AIC_I2SSR_BSY BIT2 | ||
1858 | |||
1859 | /* AIC controller AC97 codec command address register (ACCAR) */ | ||
1860 | #define AIC_ACCAR_CAR_LSB 0 | ||
1861 | #define AIC_ACCAR_CAR_MASK BITS_H2L(19, AIC_ACCAR_CAR_LSB) | ||
1862 | |||
1863 | /* AIC controller AC97 codec command data register (ACCDR) */ | ||
1864 | #define AIC_ACCDR_CDR_LSB 0 | ||
1865 | #define AIC_ACCDR_CDR_MASK BITS_H2L(19, AIC_ACCDR_CDR_LSB) | ||
1866 | |||
1867 | /* AC97 read and write macro based on ACCAR and ACCDR */ | ||
1868 | #define AC97_READ_CMD BIT19 | ||
1869 | #define AC97_WRITE_CMD (BIT19 & ~BIT19) | ||
1870 | |||
1871 | #define AC97_INDEX_LSB 12 | ||
1872 | #define AC97_INDEX_MASK BITS_H2L(18, AC97_INDEX_LSB) | ||
1873 | |||
1874 | #define AC97_DATA_LSB 4 | ||
1875 | #define AC97_DATA_MASK BITS_H2L(19, AC97_DATA_LSB) | ||
1876 | |||
1877 | /* AIC controller AC97 codec status address register (ACSAR) */ | ||
1878 | #define AIC_ACSAR_SAR_LSB 0 | ||
1879 | #define AIC_ACSAR_SAR_MASK BITS_H2L(19, AIC_ACSAR_SAR_LSB) | ||
1880 | |||
1881 | /* AIC controller AC97 codec status data register (ACSDR) */ | ||
1882 | #define AIC_ACSDR_SDR_LSB 0 | ||
1883 | #define AIC_ACSDR_SDR_MASK BITS_H2L(19, AIC_ACSDR_SDR_LSB) | ||
1884 | |||
1885 | /* AIC controller I2S/MSB-justified clock divider register (I2SDIV) */ | ||
1886 | #define AIC_I2SDIV_DIV_LSB 0 | ||
1887 | #define AIC_I2SDIV_DIV_MASK BITS_H2L(3, AIC_I2SDIV_DIV_LSB) | ||
1888 | |||
1889 | /* SPDIF enable register (SPDIF_ENA) */ | ||
1890 | #define SPDIF_ENA_SPEN BIT0 | ||
1891 | |||
1892 | /* SPDIF control register (SPDIF_CTRL) */ | ||
1893 | #define SPDIF_CTRL_DMAEN BIT15 | ||
1894 | #define SPDIF_CTRL_DTYPE BIT14 | ||
1895 | #define SPDIF_CTRL_SIGN BIT13 | ||
1896 | #define SPDIF_CTRL_INVALID BIT12 | ||
1897 | #define SPDIF_CTRL_RST BIT11 | ||
1898 | #define SPDIF_CTRL_SPDIFI2S BIT10 | ||
1899 | #define SPDIF_CTRL_MTRIG BIT1 | ||
1900 | #define SPDIF_CTRL_MFFUR BIT0 | ||
1901 | |||
1902 | /* SPDIF state register (SPDIF_STAT) */ | ||
1903 | #define SPDIF_STAT_BUSY BIT7 | ||
1904 | #define SPDIF_STAT_FTRIG BIT1 | ||
1905 | #define SPDIF_STAT_FUR BIT0 | ||
1906 | |||
1907 | #define SPDIF_STAT_FLVL_LSB 8 | ||
1908 | #define SPDIF_STAT_FLVL_MASK BITS_H2L(14, SPDIF_STAT_FLVL_LSB) | ||
1909 | |||
1910 | /* SPDIF configure 1 register (SPDIF_CFG1) */ | ||
1911 | #define SPDIF_CFG1_INITLVL BIT17 | ||
1912 | #define SPDIF_CFG1_ZROVLD BIT16 | ||
1913 | |||
1914 | #define SPDIF_CFG1_TRIG_LSB 12 | ||
1915 | #define SPDIF_CFG1_TRIG_MASK BITS_H2L(13, SPDIF_CFG1_TRIG_LSB) | ||
1916 | #define SPDIF_CFG1_TRIG(n) (((n) > 16 ? 3 : (n)/8) << SPDIF_CFG1_TRIG_LSB) /* n = 4, 8, 16, 32 */ | ||
1917 | |||
1918 | #define SPDIF_CFG1_SRCNUM_LSB 8 | ||
1919 | #define SPDIF_CFG1_SRCNUM_MASK BITS_H2L(11, SPDIF_CFG1_SRCNUM_LSB) | ||
1920 | |||
1921 | #define SPDIF_CFG1_CH1NUM_LSB 4 | ||
1922 | #define SPDIF_CFG1_CH1NUM_MASK BITS_H2L(7, SPDIF_CFG1_CH1NUM_LSB) | ||
1923 | |||
1924 | #define SPDIF_CFG1_CH2NUM_LSB 0 | ||
1925 | #define SPDIF_CFG1_CH2NUM_MASK BITS_H2L(3, SPDIF_CFG1_CH2NUM_LSB) | ||
1926 | |||
1927 | /* SPDIF configure 2 register (SPDIF_CFG2) */ | ||
1928 | #define SPDIF_CFG2_MAXWL BIT18 | ||
1929 | #define SPDIF_CFG2_PRE BIT3 | ||
1930 | #define SPDIF_CFG2_COPYN BIT2 | ||
1931 | #define SPDIF_CFG2_AUDION BIT1 | ||
1932 | #define SPDIF_CFG2_CONPRO BIT0 | ||
1933 | |||
1934 | #define SPDIF_CFG2_FS_LSB 26 | ||
1935 | #define SPDIF_CFG2_FS_MASK BITS_H2L(29, SPDIF_CFG2_FS_LSB) | ||
1936 | |||
1937 | #define SPDIF_CFG2_ORGFRQ_LSB 22 | ||
1938 | #define SPDIF_CFG2_ORGFRQ_MASK BITS_H2L(25, SPDIF_CFG2_ORGFRQ_LSB) | ||
1939 | |||
1940 | #define SPDIF_CFG2_SAMWL_LSB 19 | ||
1941 | #define SPDIF_CFG2_SAMWL_MASK BITS_H2L(21, SPDIF_CFG2_SAMWL_LSB) | ||
1942 | |||
1943 | #define SPDIF_CFG2_CLKACU_LSB 16 | ||
1944 | #define SPDIF_CFG2_CLKACU_MASK BITS_H2L(17, SPDIF_CFG2_CLKACU_LSB) | ||
1945 | |||
1946 | #define SPDIF_CFG2_CATCODE_LSB 8 | ||
1947 | #define SPDIF_CFG2_CATCODE_MASK BITS_H2L(15, SPDIF_CFG2_CATCODE_LSB) | ||
1948 | |||
1949 | #define SPDIF_CFG2_CHMD_LSB 6 | ||
1950 | #define SPDIF_CFG2_CHMD_MASK BITS_H2L(7, SPDIF_CFG2_CHMD_LSB) | ||
1951 | |||
1952 | /* ICDC internal register access control register(RGADW) */ | ||
1953 | #define ICDC_RGADW_RGWR BIT16 | ||
1954 | |||
1955 | #define ICDC_RGADW_RGADDR_LSB 8 | ||
1956 | #define ICDC_RGADW_RGADDR_MASK BITS_H2L(14, ICDC_RGADW_RGADDR_LSB) | ||
1957 | |||
1958 | #define ICDC_RGADW_RGDIN_LSB 0 | ||
1959 | #define ICDC_RGADW_RGDIN_MASK BITS_H2L(7, ICDC_RGADW_RGDIN_LSB) | ||
1960 | |||
1961 | /* ICDC internal register data output register (RGDATA)*/ | ||
1962 | #define ICDC_RGDATA_IRQ BIT8 | ||
1963 | |||
1964 | #define ICDC_RGDATA_RGDOUT_LSB 0 | ||
1965 | #define ICDC_RGDATA_RGDOUT_MASK BITS_H2L(7, ICDC_RGDATA_RGDOUT_LSB) | ||
1966 | |||
1967 | #ifndef __MIPS_ASSEMBLER | ||
1968 | |||
1969 | #define REG_AIC_FR REG32(AIC_FR) | ||
1970 | #define REG_AIC_CR REG32(AIC_CR) | ||
1971 | #define REG_AIC_ACCR1 REG32(AIC_ACCR1) | ||
1972 | #define REG_AIC_ACCR2 REG32(AIC_ACCR2) | ||
1973 | #define REG_AIC_I2SCR REG32(AIC_I2SCR) | ||
1974 | #define REG_AIC_SR REG32(AIC_SR) | ||
1975 | #define REG_AIC_ACSR REG32(AIC_ACSR) | ||
1976 | #define REG_AIC_I2SSR REG32(AIC_I2SSR) | ||
1977 | #define REG_AIC_ACCAR REG32(AIC_ACCAR) | ||
1978 | #define REG_AIC_ACCDR REG32(AIC_ACCDR) | ||
1979 | #define REG_AIC_ACSAR REG32(AIC_ACSAR) | ||
1980 | #define REG_AIC_ACSDR REG32(AIC_ACSDR) | ||
1981 | #define REG_AIC_I2SDIV REG32(AIC_I2SDIV) | ||
1982 | #define REG_AIC_DR REG32(AIC_DR) | ||
1983 | |||
1984 | #define REG_SPDIF_ENA REG32(SPDIF_ENA) | ||
1985 | #define REG_SPDIF_CTRL REG32(SPDIF_CTRL) | ||
1986 | #define REG_SPDIF_STATE REG32(SPDIF_STATE) | ||
1987 | #define REG_SPDIF_CFG1 REG32(SPDIF_CFG1) | ||
1988 | #define REG_SPDIF_CFG2 REG32(SPDIF_CFG2) | ||
1989 | #define REG_SPDIF_FIFO REG32(SPDIF_FIFO) | ||
1990 | |||
1991 | #define REG_ICDC_RGADW REG32(ICDC_RGADW) | ||
1992 | #define REG_ICDC_RGDATA REG32(ICDC_RGDATA) | ||
1993 | |||
1994 | #define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB ) | ||
1995 | #define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB ) | ||
1996 | |||
1997 | #define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL ) | ||
1998 | #define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL ) | ||
1999 | |||
2000 | #define __aic_play_zero() ( REG_AIC_FR &= ~AIC_FR_LSMP ) | ||
2001 | #define __aic_play_lastsample() ( REG_AIC_FR |= AIC_FR_LSMP ) | ||
2002 | |||
2003 | #define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD ) | ||
2004 | #define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) ) | ||
2005 | #define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST ) | ||
2006 | |||
2007 | #define __i2s_enable_sclk() ( REG_AIC_I2SCR |= AIC_I2SCR_ESCLK ) | ||
2008 | #define __i2s_disable_sclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_ESCLK ) | ||
2009 | |||
2010 | #define __aic_reset() \ | ||
2011 | do { \ | ||
2012 | REG_AIC_FR |= AIC_FR_RST; \ | ||
2013 | } while(0) | ||
2014 | |||
2015 | #define __aic_set_transmit_trigger(n) \ | ||
2016 | do { \ | ||
2017 | REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \ | ||
2018 | REG_AIC_FR |= ((n) << AIC_FR_TFTH_LSB); \ | ||
2019 | } while(0) | ||
2020 | |||
2021 | #define __aic_set_receive_trigger(n) \ | ||
2022 | do { \ | ||
2023 | REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \ | ||
2024 | REG_AIC_FR |= ((n) << AIC_FR_RFTH_LSB); \ | ||
2025 | } while(0) | ||
2026 | |||
2027 | #define __aic_enable_oldstyle() | ||
2028 | #define __aic_enable_newstyle() | ||
2029 | #define __aic_enable_pack16() ( REG_AIC_CR |= AIC_CR_PACK16 ) | ||
2030 | #define __aic_enable_unpack16() ( REG_AIC_CR &= ~AIC_CR_PACK16) | ||
2031 | |||
2032 | /* n = AIC_CR_CHANNEL_MONO,AIC_CR_CHANNEL_STEREO ... */ | ||
2033 | #define __aic_out_channel_select(n) \ | ||
2034 | do { \ | ||
2035 | REG_AIC_CR &= ~AIC_CR_CHANNEL_MASK; \ | ||
2036 | REG_AIC_CR |= ((n) << AIC_CR_CHANNEL_LSB ); \ | ||
2037 | } while(0) | ||
2038 | |||
2039 | #define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC ) | ||
2040 | #define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC ) | ||
2041 | #define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL ) | ||
2042 | #define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL ) | ||
2043 | #define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF ) | ||
2044 | #define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF ) | ||
2045 | |||
2046 | #define __aic_flush_tfifo() ( REG_AIC_CR |= AIC_CR_TFLUSH ) | ||
2047 | #define __aic_unflush_tfifo() ( REG_AIC_CR &= ~AIC_CR_TFLUSH ) | ||
2048 | #define __aic_flush_rfifo() ( REG_AIC_CR |= AIC_CR_RFLUSH ) | ||
2049 | #define __aic_unflush_rfifo() ( REG_AIC_CR &= ~AIC_CR_RFLUSH ) | ||
2050 | |||
2051 | #define __aic_enable_transmit_intr() \ | ||
2052 | ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) ) | ||
2053 | #define __aic_disable_transmit_intr() \ | ||
2054 | ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) ) | ||
2055 | #define __aic_enable_receive_intr() \ | ||
2056 | ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) ) | ||
2057 | #define __aic_disable_receive_intr() \ | ||
2058 | ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) ) | ||
2059 | |||
2060 | #define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS ) | ||
2061 | #define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS ) | ||
2062 | #define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS ) | ||
2063 | #define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS ) | ||
2064 | |||
2065 | #define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S ) | ||
2066 | #define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S ) | ||
2067 | #define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW ) | ||
2068 | #define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW ) | ||
2069 | #define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU ) | ||
2070 | #define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU ) | ||
2071 | |||
2072 | #define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT(3) | ||
2073 | #define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT(4) | ||
2074 | #define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT(6) | ||
2075 | #define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT(7) | ||
2076 | #define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT(8) | ||
2077 | #define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT(9) | ||
2078 | |||
2079 | #define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT(3) | ||
2080 | #define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT(4) | ||
2081 | #define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT(6) | ||
2082 | #define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT(7) | ||
2083 | #define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT(8) | ||
2084 | #define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT(9) | ||
2085 | |||
2086 | #define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK ) | ||
2087 | #define __ac97_set_xs_mono() \ | ||
2088 | do { \ | ||
2089 | REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ | ||
2090 | REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \ | ||
2091 | } while(0) | ||
2092 | #define __ac97_set_xs_stereo() \ | ||
2093 | do { \ | ||
2094 | REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ | ||
2095 | REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \ | ||
2096 | } while(0) | ||
2097 | |||
2098 | /* In fact, only stereo is support now. */ | ||
2099 | #define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK ) | ||
2100 | #define __ac97_set_rs_mono() \ | ||
2101 | do { \ | ||
2102 | REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ | ||
2103 | REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \ | ||
2104 | } while(0) | ||
2105 | #define __ac97_set_rs_stereo() \ | ||
2106 | do { \ | ||
2107 | REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ | ||
2108 | REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \ | ||
2109 | } while(0) | ||
2110 | |||
2111 | #define __ac97_warm_reset_codec() \ | ||
2112 | do { \ | ||
2113 | REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ | ||
2114 | REG_AIC_ACCR2 |= AIC_ACCR2_SS; \ | ||
2115 | udelay(2); \ | ||
2116 | REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ | ||
2117 | REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ | ||
2118 | } while (0) | ||
2119 | |||
2120 | #define __ac97_cold_reset_codec() \ | ||
2121 | do { \ | ||
2122 | REG_AIC_ACCR2 |= AIC_ACCR2_SR; \ | ||
2123 | udelay(2); \ | ||
2124 | REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \ | ||
2125 | } while (0) | ||
2126 | |||
2127 | /* n=8,16,18,20 */ | ||
2128 | #define __ac97_set_iass(n) \ | ||
2129 | ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT ) | ||
2130 | #define __ac97_set_oass(n) \ | ||
2131 | ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT ) | ||
2132 | |||
2133 | /* This bit should only be set in 2 channels configuration */ | ||
2134 | #define __i2s_send_rfirst() ( REG_AIC_I2SCR |= AIC_I2SCR_RFIRST ) /* RL */ | ||
2135 | #define __i2s_send_lfirst() ( REG_AIC_I2SCR &= ~AIC_I2SCR_RFIRST ) /* LR */ | ||
2136 | |||
2137 | /* This bit should only be set in 2 channels configuration and 16bit-packed mode */ | ||
2138 | #define __i2s_switch_lr() ( REG_AIC_I2SCR |= AIC_I2SCR_SWLH ) | ||
2139 | #define __i2s_unswitch_lr() ( REG_AIC_I2SCR &= ~AIC_I2SCR_SWLH ) | ||
2140 | |||
2141 | #define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL ) | ||
2142 | #define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL ) | ||
2143 | |||
2144 | /* n=8,16,18,20,24 */ | ||
2145 | /*#define __i2s_set_sample_size(n) \ | ||
2146 | ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/ | ||
2147 | |||
2148 | #define __i2s_out_channel_select(n) __aic_out_channel_select(n) | ||
2149 | |||
2150 | #define __i2s_set_oss_sample_size(n) \ | ||
2151 | ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS(n)) | ||
2152 | #define __i2s_set_iss_sample_size(n) \ | ||
2153 | ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS(n)) | ||
2154 | |||
2155 | #define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK ) | ||
2156 | #define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK ) | ||
2157 | |||
2158 | #define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS ) | ||
2159 | #define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS ) | ||
2160 | #define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR ) | ||
2161 | #define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR ) | ||
2162 | |||
2163 | #define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) ) | ||
2164 | |||
2165 | #define __aic_get_transmit_resident() \ | ||
2166 | ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_LSB ) | ||
2167 | #define __aic_get_receive_count() \ | ||
2168 | ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_LSB ) | ||
2169 | |||
2170 | #define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT ) | ||
2171 | #define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR ) | ||
2172 | #define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO ) | ||
2173 | #define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM ) | ||
2174 | #define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY ) | ||
2175 | #define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR ) | ||
2176 | #define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR ) | ||
2177 | |||
2178 | #define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY ) | ||
2179 | |||
2180 | #define __ac97_out_rcmd_addr(reg) \ | ||
2181 | do { \ | ||
2182 | REG_AIC_ACCAR = AC97_READ_CMD | ((reg) << AC97_INDEX_LSB); \ | ||
2183 | } while (0) | ||
2184 | |||
2185 | #define __ac97_out_wcmd_addr(reg) \ | ||
2186 | do { \ | ||
2187 | REG_AIC_ACCAR = AC97_WRITE_CMD | ((reg) << AC97_INDEX_LSB); \ | ||
2188 | } while (0) | ||
2189 | |||
2190 | #define __ac97_out_data(value) \ | ||
2191 | do { \ | ||
2192 | REG_AIC_ACCDR = ((value) << AC97_DATA_LSB); \ | ||
2193 | } while (0) | ||
2194 | |||
2195 | #define __ac97_in_data() \ | ||
2196 | ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> AC97_DATA_LSB ) | ||
2197 | |||
2198 | #define __ac97_in_status_addr() \ | ||
2199 | ( (REG_AIC_ACSAR & AC97_INDEX_MASK) >> AC97_INDEX_LSB ) | ||
2200 | |||
2201 | #define __i2s_set_sample_rate(i2sclk, sync) \ | ||
2202 | ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) | ||
2203 | |||
2204 | #define __i2s_set_i2sdiv(n) \ | ||
2205 | ( REG_AIC_I2SDIV = (n) ) | ||
2206 | |||
2207 | #define __aic_write_tfifo(v) ( REG_AIC_DR = (v) ) | ||
2208 | #define __aic_read_rfifo() ( REG_AIC_DR ) | ||
2209 | |||
2210 | #define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC ) | ||
2211 | #define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC ) | ||
2212 | |||
2213 | // | ||
2214 | // Define next ops for AC97 compatible | ||
2215 | // | ||
2216 | |||
2217 | #define AC97_ACSR AIC_ACSR | ||
2218 | |||
2219 | #define __ac97_enable() __aic_enable(); __aic_select_ac97() | ||
2220 | #define __ac97_disable() __aic_disable() | ||
2221 | #define __ac97_reset() __aic_reset() | ||
2222 | |||
2223 | #define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n) | ||
2224 | #define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n) | ||
2225 | |||
2226 | #define __ac97_enable_record() __aic_enable_record() | ||
2227 | #define __ac97_disable_record() __aic_disable_record() | ||
2228 | #define __ac97_enable_replay() __aic_enable_replay() | ||
2229 | #define __ac97_disable_replay() __aic_disable_replay() | ||
2230 | #define __ac97_enable_loopback() __aic_enable_loopback() | ||
2231 | #define __ac97_disable_loopback() __aic_disable_loopback() | ||
2232 | |||
2233 | #define __ac97_enable_transmit_dma() __aic_enable_transmit_dma() | ||
2234 | #define __ac97_disable_transmit_dma() __aic_disable_transmit_dma() | ||
2235 | #define __ac97_enable_receive_dma() __aic_enable_receive_dma() | ||
2236 | #define __ac97_disable_receive_dma() __aic_disable_receive_dma() | ||
2237 | |||
2238 | #define __ac97_transmit_request() __aic_transmit_request() | ||
2239 | #define __ac97_receive_request() __aic_receive_request() | ||
2240 | #define __ac97_transmit_underrun() __aic_transmit_underrun() | ||
2241 | #define __ac97_receive_overrun() __aic_receive_overrun() | ||
2242 | |||
2243 | #define __ac97_clear_errors() __aic_clear_errors() | ||
2244 | |||
2245 | #define __ac97_get_transmit_resident() __aic_get_transmit_resident() | ||
2246 | #define __ac97_get_receive_count() __aic_get_receive_count() | ||
2247 | |||
2248 | #define __ac97_enable_transmit_intr() __aic_enable_transmit_intr() | ||
2249 | #define __ac97_disable_transmit_intr() __aic_disable_transmit_intr() | ||
2250 | #define __ac97_enable_receive_intr() __aic_enable_receive_intr() | ||
2251 | #define __ac97_disable_receive_intr() __aic_disable_receive_intr() | ||
2252 | |||
2253 | #define __ac97_write_tfifo(v) __aic_write_tfifo(v) | ||
2254 | #define __ac97_read_rfifo() __aic_read_rfifo() | ||
2255 | |||
2256 | // | ||
2257 | // Define next ops for I2S compatible | ||
2258 | // | ||
2259 | |||
2260 | #define I2S_ACSR AIC_I2SSR | ||
2261 | |||
2262 | #define __i2s_enable() __aic_enable(); __aic_select_i2s() | ||
2263 | #define __i2s_disable() __aic_disable() | ||
2264 | #define __i2s_reset() __aic_reset() | ||
2265 | |||
2266 | #define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n) | ||
2267 | #define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n) | ||
2268 | |||
2269 | #define __i2s_enable_record() __aic_enable_record() | ||
2270 | #define __i2s_disable_record() __aic_disable_record() | ||
2271 | #define __i2s_enable_replay() __aic_enable_replay() | ||
2272 | #define __i2s_disable_replay() __aic_disable_replay() | ||
2273 | #define __i2s_enable_loopback() __aic_enable_loopback() | ||
2274 | #define __i2s_disable_loopback() __aic_disable_loopback() | ||
2275 | |||
2276 | #define __i2s_enable_transmit_dma() __aic_enable_transmit_dma() | ||
2277 | #define __i2s_disable_transmit_dma() __aic_disable_transmit_dma() | ||
2278 | #define __i2s_enable_receive_dma() __aic_enable_receive_dma() | ||
2279 | #define __i2s_disable_receive_dma() __aic_disable_receive_dma() | ||
2280 | |||
2281 | #define __i2s_transmit_request() __aic_transmit_request() | ||
2282 | #define __i2s_receive_request() __aic_receive_request() | ||
2283 | #define __i2s_transmit_underrun() __aic_transmit_underrun() | ||
2284 | #define __i2s_receive_overrun() __aic_receive_overrun() | ||
2285 | |||
2286 | #define __i2s_clear_errors() __aic_clear_errors() | ||
2287 | |||
2288 | #define __i2s_get_transmit_resident() __aic_get_transmit_resident() | ||
2289 | #define __i2s_get_receive_count() __aic_get_receive_count() | ||
2290 | |||
2291 | #define __i2s_enable_transmit_intr() __aic_enable_transmit_intr() | ||
2292 | #define __i2s_disable_transmit_intr() __aic_disable_transmit_intr() | ||
2293 | #define __i2s_enable_receive_intr() __aic_enable_receive_intr() | ||
2294 | #define __i2s_disable_receive_intr() __aic_disable_receive_intr() | ||
2295 | |||
2296 | #define __i2s_write_tfifo(v) __aic_write_tfifo(v) | ||
2297 | #define __i2s_read_rfifo() __aic_read_rfifo() | ||
2298 | |||
2299 | #define __i2s_enable_pack16() __aic_enable_pack16() | ||
2300 | #define __i2s_enable_unpack16() __aic_enable_unpack16() | ||
2301 | |||
2302 | #define __i2s_reset_codec() \ | ||
2303 | do { \ | ||
2304 | } while (0) | ||
2305 | |||
2306 | /************************************************************************* | ||
2307 | * SPDIF INTERFACE in AIC Controller | ||
2308 | *************************************************************************/ | ||
2309 | |||
2310 | #define __spdif_enable() ( REG_SPDIF_ENA |= SPDIF_ENA_SPEN ) | ||
2311 | #define __spdif_disable() ( REG_SPDIF_ENA &= ~SPDIF_ENA_SPEN ) | ||
2312 | |||
2313 | #define __spdif_enable_transmit_dma() ( REG_SPDIF_CTRL |= SPDIF_CTRL_DMAEN ) | ||
2314 | #define __spdif_disable_transmit_dma() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_DMAEN ) | ||
2315 | #define __spdif_enable_dtype() ( REG_SPDIF_CTRL |= SPDIF_CTRL_DTYPE ) | ||
2316 | #define __spdif_disable_dtype() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_DTYPE ) | ||
2317 | #define __spdif_enable_sign() ( REG_SPDIF_CTRL |= SPDIF_CTRL_SIGN ) | ||
2318 | #define __spdif_disable_sign() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_SIGN ) | ||
2319 | #define __spdif_enable_invalid() ( REG_SPDIF_CTRL |= SPDIF_CTRL_INVALID ) | ||
2320 | #define __spdif_disable_invalid() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_INVALID ) | ||
2321 | #define __spdif_enable_reset() ( REG_SPDIF_CTRL |= SPDIF_CTRL_RST ) | ||
2322 | #define __spdif_select_spdif() ( REG_SPDIF_CTRL |= SPDIF_CTRL_SPDIFI2S ) | ||
2323 | #define __spdif_select_i2s() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_SPDIFI2S ) | ||
2324 | #define __spdif_enable_MTRIGmask() ( REG_SPDIF_CTRL |= SPDIF_CTRL_MTRIG ) | ||
2325 | #define __spdif_disable_MTRIGmask() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_MTRIG ) | ||
2326 | #define __spdif_enable_MFFURmask() ( REG_SPDIF_CTRL |= SPDIF_CTRL_MFFUR ) | ||
2327 | #define __spdif_disable_MFFURmask() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_MFFUR ) | ||
2328 | |||
2329 | #define __spdif_enable_initlvl_high() ( REG_SPDIF_CFG1 |= SPDIF_CFG1_INITLVL ) | ||
2330 | #define __spdif_enable_initlvl_low() ( REG_SPDIF_CFG1 &= ~SPDIF_CFG1_INITLVL ) | ||
2331 | #define __spdif_enable_zrovld_invald() ( REG_SPDIF_CFG1 |= SPDIF_CFG1_ZROVLD ) | ||
2332 | #define __spdif_enable_zrovld_vald() ( REG_SPDIF_CFG1 &= ~SPDIF_CFG1_ZROVLD ) | ||
2333 | |||
2334 | /* 0, 1, 2, 3 */ | ||
2335 | #define __spdif_set_transmit_trigger(n) \ | ||
2336 | do { \ | ||
2337 | REG_SPDIF_CFG1 &= ~SPDIF_CFG1_TRIG_MASK; \ | ||
2338 | REG_SPDIF_CFG1 |= SPDIF_CFG1_TRIG(n); \ | ||
2339 | } while(0) | ||
2340 | |||
2341 | /* 1 ~ 15 */ | ||
2342 | #define __spdif_set_srcnum(n) \ | ||
2343 | do { \ | ||
2344 | REG_SPDIF_CFG1 &= ~SPDIF_CFG1_SRCNUM_MASK; \ | ||
2345 | REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_SRCNUM_LSB); \ | ||
2346 | } while(0) | ||
2347 | |||
2348 | /* 1 ~ 15 */ | ||
2349 | #define __spdif_set_ch1num(n) \ | ||
2350 | do { \ | ||
2351 | REG_SPDIF_CFG1 &= ~SPDIF_CFG1_CH1NUM_MASK; \ | ||
2352 | REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH1NUM_LSB); \ | ||
2353 | } while(0) | ||
2354 | |||
2355 | /* 1 ~ 15 */ | ||
2356 | #define __spdif_set_ch2num(n) \ | ||
2357 | do { \ | ||
2358 | REG_SPDIF_CFG1 &= ~SPDIF_CFG1_CH2NUM_MASK; \ | ||
2359 | REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH2NUM_LSB); \ | ||
2360 | } while(0) | ||
2361 | |||
2362 | /* 0x0, 0x2, 0x3, 0xa, 0xe */ | ||
2363 | #define __spdif_set_fs(n) \ | ||
2364 | do { \ | ||
2365 | REG_SPDIF_CFG2 &= ~SPDIF_CFG2_FS_MASK; \ | ||
2366 | REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_FS_LSB); \ | ||
2367 | } while(0) | ||
2368 | |||
2369 | /* 0xd, 0xc, 0x5, 0x1 */ | ||
2370 | #define __spdif_set_orgfrq(n) \ | ||
2371 | do { \ | ||
2372 | REG_SPDIF_CFG2 &= ~SPDIF_CFG2_ORGFRQ_MASK; \ | ||
2373 | REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_ORGFRQ_LSB); \ | ||
2374 | } while(0) | ||
2375 | |||
2376 | /* 0x1, 0x6, 0x2, 0x4, 0x5 */ | ||
2377 | #define __spdif_set_samwl(n) \ | ||
2378 | do { \ | ||
2379 | REG_SPDIF_CFG2 &= ~SPDIF_CFG2_SAMWL_MASK; \ | ||
2380 | REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_SAMWL_LSB); \ | ||
2381 | } while(0) | ||
2382 | |||
2383 | #define __spdif_enable_samwl_24() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_MAXWL ) | ||
2384 | #define __spdif_enable_samwl_20() ( REG_SPDIF_CFG1 &= ~SPDIF_CFG2_MAXWL ) | ||
2385 | |||
2386 | /* 0x1, 0x1, 0x2, 0x3 */ | ||
2387 | #define __spdif_set_clkacu(n) \ | ||
2388 | do { \ | ||
2389 | REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CLKACU_MASK; \ | ||
2390 | REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CLKACU_LSB); \ | ||
2391 | } while(0) | ||
2392 | |||
2393 | /* see IEC60958-3 */ | ||
2394 | #define __spdif_set_catcode(n) \ | ||
2395 | do { \ | ||
2396 | REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CATCODE_MASK; \ | ||
2397 | REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CATCODE_LSB); \ | ||
2398 | } while(0) | ||
2399 | |||
2400 | /* n = 0x0, */ | ||
2401 | #define __spdif_set_chmode(n) \ | ||
2402 | do { \ | ||
2403 | REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CHMD_MASK; \ | ||
2404 | REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CHMD_LSB); \ | ||
2405 | } while(0) | ||
2406 | |||
2407 | #define __spdif_enable_pre() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_PRE ) | ||
2408 | #define __spdif_disable_pre() ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_PRE ) | ||
2409 | #define __spdif_enable_copyn() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_COPYN ) | ||
2410 | #define __spdif_disable_copyn() ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_COPYN ) | ||
2411 | /* audio sample word represents linear PCM samples */ | ||
2412 | #define __spdif_enable_audion() ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_AUDION ) | ||
2413 | /* udio sample word used for other purpose */ | ||
2414 | #define __spdif_disable_audion() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_AUDION ) | ||
2415 | #define __spdif_enable_conpro() ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CONPRO ) | ||
2416 | #define __spdif_disable_conpro() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_CONPRO ) | ||
2417 | |||
2418 | /*************************************************************************** | ||
2419 | * ICDC | ||
2420 | ***************************************************************************/ | ||
2421 | #define __i2s_internal_codec() __aic_internal_codec() | ||
2422 | #define __i2s_external_codec() __aic_external_codec() | ||
2423 | |||
2424 | #define __icdc_clk_ready() ( REG_ICDC_CKCFG & ICDC_CKCFG_CKRDY ) | ||
2425 | #define __icdc_sel_adc() ( REG_ICDC_CKCFG |= ICDC_CKCFG_SELAD ) | ||
2426 | #define __icdc_sel_dac() ( REG_ICDC_CKCFG &= ~ICDC_CKCFG_SELAD ) | ||
2427 | |||
2428 | #define __icdc_set_rgwr() ( REG_ICDC_RGADW |= ICDC_RGADW_RGWR ) | ||
2429 | #define __icdc_clear_rgwr() ( REG_ICDC_RGADW &= ~ICDC_RGADW_RGWR ) | ||
2430 | #define __icdc_rgwr_ready() ( REG_ICDC_RGADW & ICDC_RGADW_RGWR ) | ||
2431 | |||
2432 | #define __icdc_set_addr(n) \ | ||
2433 | do { \ | ||
2434 | REG_ICDC_RGADW &= ~ICDC_RGADW_RGADDR_MASK; \ | ||
2435 | REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGADDR_LSB; \ | ||
2436 | } while(0) | ||
2437 | |||
2438 | #define __icdc_set_cmd(n) \ | ||
2439 | do { \ | ||
2440 | REG_ICDC_RGADW &= ~ICDC_RGADW_RGDIN_MASK; \ | ||
2441 | REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGDIN_LSB; \ | ||
2442 | } while(0) | ||
2443 | |||
2444 | #define __icdc_irq_pending() ( REG_ICDC_RGDATA & ICDC_RGDATA_IRQ ) | ||
2445 | #define __icdc_get_value() ( REG_ICDC_RGDATA & ICDC_RGDATA_RGDOUT_MASK ) | ||
2446 | |||
2447 | #endif /* __MIPS_ASSEMBLER */ | ||
2448 | |||
2449 | /* | ||
2450 | * Bose-Chaudhuri-Hocquenghem controller module(BCH) address definition | ||
2451 | */ | ||
2452 | #define BCH_BASE 0xb34d0000 | ||
2453 | |||
2454 | /* | ||
2455 | * BCH registers offset addresses definition | ||
2456 | */ | ||
2457 | #define BCH_BHCR_OFFSET (0x00) /* r, 32, 0x00000000 */ | ||
2458 | #define BCH_BHCSR_OFFSET (0x04) /* w, 32, 0x???????? */ | ||
2459 | #define BCH_BHCCR_OFFSET (0x08) /* w, 32, 0x???????? */ | ||
2460 | #define BCH_BHCNT_OFFSET (0x0c) /* rw, 32, 0x00000000 */ | ||
2461 | #define BCH_BHDR_OFFSET (0x10) /* w, 8, 0x???????? */ | ||
2462 | #define BCH_BHPAR0_OFFSET (0x14) /* rw, 32, 0x00000000 */ | ||
2463 | #define BCH_BHPAR1_OFFSET (0x18) /* rw, 32, 0x00000000 */ | ||
2464 | #define BCH_BHPAR2_OFFSET (0x1c) /* rw, 32, 0x00000000 */ | ||
2465 | #define BCH_BHPAR3_OFFSET (0x20) /* rw, 32, 0x00000000 */ | ||
2466 | #define BCH_BHPAR4_OFFSET (0x24) /* rw, 32, 0x00000000 */ | ||
2467 | #define BCH_BHPAR5_OFFSET (0x28) /* rw, 32, 0x00000000 */ | ||
2468 | #define BCH_BHPAR6_OFFSET (0x2c) /* rw, 32, 0x00000000 */ | ||
2469 | #define BCH_BHPAR7_OFFSET (0x30) /* rw, 32, 0x00000000 */ | ||
2470 | #define BCH_BHPAR8_OFFSET (0x34) /* rw, 32, 0x00000000 */ | ||
2471 | #define BCH_BHPAR9_OFFSET (0x38) /* rw, 32, 0x00000000 */ | ||
2472 | #define BCH_BHERR0_OFFSET (0x3c) /* r, 32, 0x00000000 */ | ||
2473 | #define BCH_BHERR1_OFFSET (0x40) /* r, 32, 0x00000000 */ | ||
2474 | #define BCH_BHERR2_OFFSET (0x44) /* r, 32, 0x00000000 */ | ||
2475 | #define BCH_BHERR3_OFFSET (0x48) /* r, 32, 0x00000000 */ | ||
2476 | #define BCH_BHERR4_OFFSET (0x4c) /* r, 32, 0x00000000 */ | ||
2477 | #define BCH_BHERR5_OFFSET (0x50) /* r, 32, 0x00000000 */ | ||
2478 | #define BCH_BHERR6_OFFSET (0x54) /* r, 32, 0x00000000 */ | ||
2479 | #define BCH_BHERR7_OFFSET (0x58) /* r, 32, 0x00000000 */ | ||
2480 | #define BCH_BHERR8_OFFSET (0x5c) /* r, 32, 0x00000000 */ | ||
2481 | #define BCH_BHERR9_OFFSET (0x60) /* r, 32, 0x00000000 */ | ||
2482 | #define BCH_BHERR10_OFFSET (0x64) /* r, 32, 0x00000000 */ | ||
2483 | #define BCH_BHERR11_OFFSET (0x68) /* r, 32, 0x00000000 */ | ||
2484 | #define BCH_BHINT_OFFSET (0x6c) /* r, 32, 0x00000000 */ | ||
2485 | #define BCH_BHINTE_OFFSET (0x70) /* rw, 32, 0x00000000 */ | ||
2486 | #define BCH_BHINTES_OFFSET (0x74) /* w, 32, 0x???????? */ | ||
2487 | #define BCH_BHINTEC_OFFSET (0x78) /* w, 32, 0x???????? */ | ||
2488 | |||
2489 | /* | ||
2490 | * BCH registers addresses definition | ||
2491 | */ | ||
2492 | #define BCH_BHCR (BCH_BASE + BCH_BHCR_OFFSET) | ||
2493 | #define BCH_BHCSR (BCH_BASE + BCH_BHCSR_OFFSET) | ||
2494 | #define BCH_BHCCR (BCH_BASE + BCH_BHCCR_OFFSET) | ||
2495 | #define BCH_BHCNT (BCH_BASE + BCH_BHCNT_OFFSET) | ||
2496 | #define BCH_BHDR (BCH_BASE + BCH_BHDR_OFFSET) | ||
2497 | #define BCH_BHPAR0 (BCH_BASE + BCH_BHPAR0_OFFSET) | ||
2498 | #define BCH_BHPAR1 (BCH_BASE + BCH_BHPAR1_OFFSET) | ||
2499 | #define BCH_BHPAR2 (BCH_BASE + BCH_BHPAR2_OFFSET) | ||
2500 | #define BCH_BHPAR3 (BCH_BASE + BCH_BHPAR3_OFFSET) | ||
2501 | #define BCH_BHPAR4 (BCH_BASE + BCH_BHPAR4_OFFSET) | ||
2502 | #define BCH_BHPAR5 (BCH_BASE + BCH_BHPAR5_OFFSET) | ||
2503 | #define BCH_BHPAR6 (BCH_BASE + BCH_BHPAR6_OFFSET) | ||
2504 | #define BCH_BHPAR7 (BCH_BASE + BCH_BHPAR7_OFFSET) | ||
2505 | #define BCH_BHPAR8 (BCH_BASE + BCH_BHPAR8_OFFSET) | ||
2506 | #define BCH_BHPAR9 (BCH_BASE + BCH_BHPAR9_OFFSET) | ||
2507 | #define BCH_BHERR0 (BCH_BASE + BCH_BHERR0_OFFSET) | ||
2508 | #define BCH_BHERR1 (BCH_BASE + BCH_BHERR1_OFFSET) | ||
2509 | #define BCH_BHERR2 (BCH_BASE + BCH_BHERR2_OFFSET) | ||
2510 | #define BCH_BHERR3 (BCH_BASE + BCH_BHERR3_OFFSET) | ||
2511 | #define BCH_BHERR4 (BCH_BASE + BCH_BHERR4_OFFSET) | ||
2512 | #define BCH_BHERR5 (BCH_BASE + BCH_BHERR5_OFFSET) | ||
2513 | #define BCH_BHERR6 (BCH_BASE + BCH_BHERR6_OFFSET) | ||
2514 | #define BCH_BHERR7 (BCH_BASE + BCH_BHERR7_OFFSET) | ||
2515 | #define BCH_BHERR8 (BCH_BASE + BCH_BHERR8_OFFSET) | ||
2516 | #define BCH_BHERR9 (BCH_BASE + BCH_BHERR9_OFFSET) | ||
2517 | #define BCH_BHERR10 (BCH_BASE + BCH_BHERR10_OFFSET) | ||
2518 | #define BCH_BHERR11 (BCH_BASE + BCH_BHERR11_OFFSET) | ||
2519 | #define BCH_BHINT (BCH_BASE + BCH_BHINT_OFFSET) | ||
2520 | #define BCH_BHINTES (BCH_BASE + BCH_BHINTES_OFFSET) | ||
2521 | #define BCH_BHINTEC (BCH_BASE + BCH_BHINTEC_OFFSET) | ||
2522 | #define BCH_BHINTE (BCH_BASE + BCH_BHINTE_OFFSET) | ||
2523 | |||
2524 | /* | ||
2525 | * BCH registers common define | ||
2526 | */ | ||
2527 | |||
2528 | /* BCH control register (BHCR) */ | ||
2529 | #define BHCR_DMAE BIT7 /* BCH DMA enable */ | ||
2530 | #define BHCR_ENCE BIT2 | ||
2531 | #define BHCR_BRST BIT1 /* BCH reset */ | ||
2532 | #define BHCR_BCHE BIT0 /* BCH enable */ | ||
2533 | |||
2534 | #define BHCR_BSEL_LSB 3 | ||
2535 | #define BHCR_BSEL_MASK BITS_H2L(5, BHCR_BSEL_LSB) | ||
2536 | #define BHCR_BSEL(n) (((n)/4 - 1) << BHCR_BSEL_LSB) /* n = 4, 8, 12, 16, 20, 24 */ | ||
2537 | |||
2538 | /* BCH interrupt status register (BHINT) */ | ||
2539 | #define BHINT_ALL_F BIT4 | ||
2540 | #define BHINT_DECF BIT3 | ||
2541 | #define BHINT_ENCF BIT2 | ||
2542 | #define BHINT_UNCOR BIT1 | ||
2543 | #define BHINT_ERR BIT0 | ||
2544 | |||
2545 | #define BHINT_ERRC_LSB 27 | ||
2546 | #define BHINT_ERRC_MASK BITS_H2L(31, BHINT_ERRC_LSB) | ||
2547 | |||
2548 | /* BCH ENC/DEC count register (BHCNT) */ | ||
2549 | #define BHCNT_DEC_LSB 16 | ||
2550 | #define BHCNT_DEC_MASK BITS_H2L(26, BHCNT_DEC_LSB) | ||
2551 | |||
2552 | #define BHCNT_ENC_LSB 0 | ||
2553 | #define BHCNT_ENC_MASK BITS_H2L(10, BHCNT_ENC_LSB) | ||
2554 | |||
2555 | /* BCH error report register (BCHERR)*/ | ||
2556 | #define BCH_ERR_INDEX_LSB 0 | ||
2557 | #define BCH_ERR_INDEX_MASK BITS_H2L(12, BCH_ERR_INDEX_LSB) | ||
2558 | |||
2559 | /* BCH common macro define */ | ||
2560 | #define BCH_ENCODE 1 | ||
2561 | #define BCH_DECODE 0 | ||
2562 | |||
2563 | #ifndef __MIPS_ASSEMBLER | ||
2564 | |||
2565 | #define REG_BCH_BHCR REG32(BCH_BHCR) | ||
2566 | #define REG_BCH_BHCSR REG32(BCH_BHCSR) | ||
2567 | #define REG_BCH_BHCCR REG32(BCH_BHCCR) | ||
2568 | #define REG_BCH_BHCNT REG32(BCH_BHCNT) | ||
2569 | #define REG_BCH_BHDR REG8(BCH_BHDR) | ||
2570 | #define REG_BCH_BHPAR0 REG32(BCH_BHPAR0) | ||
2571 | #define REG_BCH_BHPAR1 REG32(BCH_BHPAR1) | ||
2572 | #define REG_BCH_BHPAR2 REG32(BCH_BHPAR2) | ||
2573 | #define REG_BCH_BHPAR3 REG32(BCH_BHPAR3) | ||
2574 | #define REG_BCH_BHPAR4 REG32(BCH_BHPAR4) | ||
2575 | #define REG_BCH_BHPAR5 REG32(BCH_BHPAR5) | ||
2576 | #define REG_BCH_BHPAR6 REG32(BCH_BHPAR6) | ||
2577 | #define REG_BCH_BHPAR7 REG32(BCH_BHPAR7) | ||
2578 | #define REG_BCH_BHPAR8 REG32(BCH_BHPAR8) | ||
2579 | #define REG_BCH_BHPAR9 REG32(BCH_BHPAR9) | ||
2580 | #define REG_BCH_BHERR0 REG32(BCH_BHERR0) | ||
2581 | #define REG_BCH_BHERR1 REG32(BCH_BHERR1) | ||
2582 | #define REG_BCH_BHERR2 REG32(BCH_BHERR2) | ||
2583 | #define REG_BCH_BHERR3 REG32(BCH_BHERR3) | ||
2584 | #define REG_BCH_BHERR4 REG32(BCH_BHERR4) | ||
2585 | #define REG_BCH_BHERR5 REG32(BCH_BHERR5) | ||
2586 | #define REG_BCH_BHERR6 REG32(BCH_BHERR6) | ||
2587 | #define REG_BCH_BHERR7 REG32(BCH_BHERR7) | ||
2588 | #define REG_BCH_BHERR8 REG32(BCH_BHERR8) | ||
2589 | #define REG_BCH_BHERR9 REG32(BCH_BHERR9) | ||
2590 | #define REG_BCH_BHERR10 REG32(BCH_BHERR10) | ||
2591 | #define REG_BCH_BHERR11 REG32(BCH_BHERR11) | ||
2592 | #define REG_BCH_BHINT REG32(BCH_BHINT) | ||
2593 | #define REG_BCH_BHINTE REG32(BCH_BHINTE) | ||
2594 | #define REG_BCH_BHINTEC REG32(BCH_BHINTEC) | ||
2595 | #define REG_BCH_BHINTES REG32(BCH_BHINTES) | ||
2596 | |||
2597 | #define __ecc_enable(encode, bit) \ | ||
2598 | do { \ | ||
2599 | unsigned int tmp = BHCR_BRST | BHCR_BCHE; \ | ||
2600 | if (encode) \ | ||
2601 | tmp |= BHCR_ENCE; \ | ||
2602 | tmp |= BHCR_BSEL(bit); \ | ||
2603 | REG_BCH_BHCSR = tmp; \ | ||
2604 | REG_BCH_BHCCR = ~tmp; \ | ||
2605 | } while (0) | ||
2606 | #define __ecc_disable() (REG_BCH_BHCCR = BHCR_BCHE) | ||
2607 | |||
2608 | #define __ecc_dma_enable() (REG_BCH_BHCSR = BHCR_DMAE) | ||
2609 | #define __ecc_dma_disable() (REG_BCH_BHCCR = BHCR_DMAE) | ||
2610 | |||
2611 | #define __ecc_cnt_enc(n) CMSREG32(BCH_BHCNT, (n) << BHCNT_ENC_LSB, BHCNT_ENC_MASK) | ||
2612 | #define __ecc_cnt_dec(n) CMSREG32(BCH_BHCNT, (n) << BHCNT_DEC_LSB, BHCNT_DEC_MASK) | ||
2613 | |||
2614 | #define __ecc_encode_sync() \ | ||
2615 | do { \ | ||
2616 | unsigned int i = 1; \ | ||
2617 | while (!(REG_BCH_BHINT & BHINT_ENCF) && i++); \ | ||
2618 | } while (0) | ||
2619 | |||
2620 | #define __ecc_decode_sync() \ | ||
2621 | do { \ | ||
2622 | unsigned int i = 1; \ | ||
2623 | while (!(REG_BCH_BHINT & BHINT_DECF) && i++); \ | ||
2624 | } while (0) | ||
2625 | |||
2626 | #endif /* __MIPS_ASSEMBLER */ | ||
2627 | |||
2628 | #define BDMAC_BASE 0xB3450000 | ||
2629 | |||
2630 | /************************************************************************* | ||
2631 | * BDMAC (BCH & NAND DMA Controller) | ||
2632 | *************************************************************************/ | ||
2633 | |||
2634 | /* n is the DMA channel index (0 - 2) */ | ||
2635 | #define BDMAC_DSAR(n) (BDMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */ | ||
2636 | #define BDMAC_DTAR(n) (BDMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */ | ||
2637 | #define BDMAC_DTCR(n) (BDMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */ | ||
2638 | #define BDMAC_DRSR(n) (BDMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */ | ||
2639 | #define BDMAC_DCCSR(n) (BDMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */ | ||
2640 | #define BDMAC_DCMD(n) (BDMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */ | ||
2641 | #define BDMAC_DDA(n) (BDMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */ | ||
2642 | #define BDMAC_DSD(n) (BDMAC_BASE + (0x1c + (n) * 0x20)) /* DMA Stride Address */ | ||
2643 | #define BDMAC_DNT(n) (BDMAC_BASE + (0xc0 + (n) * 0x04)) /* NAND Detect Timer */ | ||
2644 | |||
2645 | #define BDMAC_DMACR (BDMAC_BASE + 0x0300) /* DMA control register */ | ||
2646 | #define BDMAC_DMAIPR (BDMAC_BASE + 0x0304) /* DMA interrupt pending */ | ||
2647 | #define BDMAC_DMADBR (BDMAC_BASE + 0x0308) /* DMA doorbell */ | ||
2648 | #define BDMAC_DMADBSR (BDMAC_BASE + 0x030C) /* DMA doorbell set */ | ||
2649 | #define BDMAC_DMACKE (BDMAC_BASE + 0x0310) | ||
2650 | #define BDMAC_DMACKES (BDMAC_BASE + 0x0314) | ||
2651 | #define BDMAC_DMACKEC (BDMAC_BASE + 0x0318) | ||
2652 | |||
2653 | #define REG_BDMAC_DSAR(n) REG32(BDMAC_DSAR((n))) | ||
2654 | #define REG_BDMAC_DTAR(n) REG32(BDMAC_DTAR((n))) | ||
2655 | #define REG_BDMAC_DTCR(n) REG32(BDMAC_DTCR((n))) | ||
2656 | #define REG_BDMAC_DRSR(n) REG32(BDMAC_DRSR((n))) | ||
2657 | #define REG_BDMAC_DCCSR(n) REG32(BDMAC_DCCSR((n))) | ||
2658 | #define REG_BDMAC_DCMD(n) REG32(BDMAC_DCMD((n))) | ||
2659 | #define REG_BDMAC_DDA(n) REG32(BDMAC_DDA((n))) | ||
2660 | #define REG_BDMAC_DSD(n) REG32(BDMAC_DSD(n)) | ||
2661 | #define REG_BDMAC_DNT(n) REG32(BDMAC_DNT(n)) | ||
2662 | |||
2663 | #define REG_BDMAC_DMACR REG32(BDMAC_DMACR) | ||
2664 | #define REG_BDMAC_DMAIPR REG32(BDMAC_DMAIPR) | ||
2665 | #define REG_BDMAC_DMADBR REG32(BDMAC_DMADBR) | ||
2666 | #define REG_BDMAC_DMADBSR REG32(BDMAC_DMADBSR) | ||
2667 | #define REG_BDMAC_DMACKE REG32(BDMAC_DMACKE) | ||
2668 | #define REG_BDMAC_DMACKES REG32(BDMAC_DMACKES) | ||
2669 | #define REG_BDMAC_DMACKEC REG32(BDMAC_DMACKEC) | ||
2670 | |||
2671 | // BDMA request source register | ||
2672 | #define BDMAC_DRSR_RS_BIT 0 | ||
2673 | #define BDMAC_DRSR_RS_MASK (0x3f << DMAC_DRSR_RS_BIT) | ||
2674 | #define BDMAC_DRSR_RS_BCH_ENC (2 << DMAC_DRSR_RS_BIT) | ||
2675 | #define BDMAC_DRSR_RS_BCH_DEC (3 << DMAC_DRSR_RS_BIT) | ||
2676 | #define BDMAC_DRSR_RS_NAND0 (6 << DMAC_DRSR_RS_BIT) | ||
2677 | #define BDMAC_DRSR_RS_NAND1 (7 << DMAC_DRSR_RS_BIT) | ||
2678 | #define BDMAC_DRSR_RS_NAND (BDMAC_DRSR_RS_NAND0) | ||
2679 | #define BDMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT) | ||
2680 | #define BDMAC_DRSR_RS_EXT (12 << DMAC_DRSR_RS_BIT) | ||
2681 | |||
2682 | // BDMA channel control/status register | ||
2683 | #define BDMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */ | ||
2684 | #define BDMAC_DCCSR_DES8 (1 << 30) /* Descriptor 8 Word */ | ||
2685 | #define BDMAC_DCCSR_DES4 (0 << 30) /* Descriptor 4 Word */ | ||
2686 | #define BDMAC_DCCSR_LASTMD_BIT 28 | ||
2687 | #define BDMAC_DCCSR_LASTMD_MASK (0x3 << BDMAC_DCCSR_LASTMD_BIT) | ||
2688 | #define BDMAC_DCCSR_LASTMD0 (0 << 28) /* BCH Decoding last mode 0, there's one descriptor for decoding blcok*/ | ||
2689 | #define BDMAC_DCCSR_LASTMD1 (1 << 28) /* BCH Decoding last mode 1, there's two descriptor for decoding blcok*/ | ||
2690 | #define BDMAC_DCCSR_LASTMD2 (2 << 28) /* BCH Decoding last mode 2, there's three descriptor for decoding blcok*/ | ||
2691 | #define BDMAC_DCCSR_FRBS(n) ((n) << 24) | ||
2692 | #define BDMAC_DCCSR_FRBS_BIT 24 | ||
2693 | #define BDMAC_DCCSR_FRBS_MASK (0x7 << BDMAC_DCCSR_FRBS_BIT) | ||
2694 | #define BDMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */ | ||
2695 | #define BDMAC_DCCSR_CDOA_MASK (0xff << BDMACC_DCCSR_CDOA_BIT) | ||
2696 | #define BDMAC_DCCSR_BERR_BIT 7 | ||
2697 | #define BDMAC_DCCSR_BERR_MASK (0x1f << BDMAC_DCCSR_BERR_BIT) | ||
2698 | #define BDMAC_DCCSR_BUERR (1 << 5) | ||
2699 | #define BDMAC_DCCSR_AR (1 << 4) /* address error */ | ||
2700 | #define BDMAC_DCCSR_TT (1 << 3) /* transfer terminated */ | ||
2701 | #define BDMAC_DCCSR_HLT (1 << 2) /* DMA halted */ | ||
2702 | #define BDMAC_DCCSR_BAC (1 << 1) | ||
2703 | #define BDMAC_DCCSR_EN (1 << 0) /* channel enable bit */ | ||
2704 | |||
2705 | // BDMA channel command register | ||
2706 | #define BDMAC_DCMD_EACKS_LOW (1 << 31) /* External DACK Output Level Select, active low */ | ||
2707 | #define BDMAC_DCMD_EACKS_HIGH (0 << 31) /* External DACK Output Level Select, active high */ | ||
2708 | #define BDMAC_DCMD_EACKM_WRITE (1 << 30) /* External DACK Output Mode Select, output in write cycle */ | ||
2709 | #define BDMAC_DCMD_EACKM_READ (0 << 30) /* External DACK Output Mode Select, output in read cycle */ | ||
2710 | #define BDMAC_DCMD_ERDM_BIT 28 /* External DREQ Detection Mode Select */ | ||
2711 | #define BDMAC_DCMD_ERDM_MASK (0x03 << BDMAC_DCMD_ERDM_BIT) | ||
2712 | #define BDMAC_DCMD_ERDM_LOW (0 << BDMAC_DCMD_ERDM_BIT) | ||
2713 | #define BDMAC_DCMD_ERDM_FALL (1 << BDMAC_DCMD_ERDM_BIT) | ||
2714 | #define BDMAC_DCMD_ERDM_HIGH (2 << BDMAC_DCMD_ERDM_BIT) | ||
2715 | #define BDMAC_DCMD_ERDM_RISE (3 << BDMAC_DCMD_ERDM_BIT) | ||
2716 | #define BDMAC_DCMD_BLAST (1 << 25) /* BCH last */ | ||
2717 | #define BDMAC_DCMD_SAI (1 << 23) /* source address increment */ | ||
2718 | #define BDMAC_DCMD_DAI (1 << 22) /* dest address increment */ | ||
2719 | #define BDMAC_DCMD_SWDH_BIT 14 /* source port width */ | ||
2720 | #define BDMAC_DCMD_SWDH_MASK (0x03 << BDMAC_DCMD_SWDH_BIT) | ||
2721 | #define BDMAC_DCMD_SWDH_32 (0 << BDMAC_DCMD_SWDH_BIT) | ||
2722 | #define BDMAC_DCMD_SWDH_8 (1 << BDMAC_DCMD_SWDH_BIT) | ||
2723 | #define BDMAC_DCMD_SWDH_16 (2 << BDMAC_DCMD_SWDH_BIT) | ||
2724 | #define BDMAC_DCMD_DWDH_BIT 12 /* dest port width */ | ||
2725 | #define BDMAC_DCMD_DWDH_MASK (0x03 << BDMAC_DCMD_DWDH_BIT) | ||
2726 | #define BDMAC_DCMD_DWDH_32 (0 << BDMAC_DCMD_DWDH_BIT) | ||
2727 | #define BDMAC_DCMD_DWDH_8 (1 << BDMAC_DCMD_DWDH_BIT) | ||
2728 | #define BDMAC_DCMD_DWDH_16 (2 << BDMAC_DCMD_DWDH_BIT) | ||
2729 | #define BDMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */ | ||
2730 | #define BDMAC_DCMD_DS_MASK (0x07 << BDMAC_DCMD_DS_BIT) | ||
2731 | #define BDMAC_DCMD_DS_32BIT (0 << BDMAC_DCMD_DS_BIT) | ||
2732 | #define BDMAC_DCMD_DS_8BIT (1 << BDMAC_DCMD_DS_BIT) | ||
2733 | #define BDMAC_DCMD_DS_16BIT (2 << BDMAC_DCMD_DS_BIT) | ||
2734 | #define BDMAC_DCMD_DS_16BYTE (3 << BDMAC_DCMD_DS_BIT) | ||
2735 | #define BDMAC_DCMD_DS_32BYTE (4 << BDMAC_DCMD_DS_BIT) | ||
2736 | #define BDMAC_DCMD_DS_64BYTE (5 << BDMAC_DCMD_DS_BIT) | ||
2737 | #define BDMAC_DCMD_NRD (1 << 7) /* NAND direct read */ | ||
2738 | #define BDMAC_DCMD_NWR (1 << 6) /* NAND direct write */ | ||
2739 | #define BDMAC_DCMD_NAC (1 << 5) /* NAND AL/CL enable */ | ||
2740 | #define BDMAC_DCMD_NSTA (1 << 4) | ||
2741 | #define BDMAC_DCMD_STDE (1 << 2) /* Stride Disable/Enable */ | ||
2742 | #define BDMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */ | ||
2743 | #define BDMAC_DCMD_LINK (1 << 0) /* descriptor link enable */ | ||
2744 | |||
2745 | // BDMA descriptor address register | ||
2746 | #define BDMAC_DDA_BASE_BIT 12 /* descriptor base address */ | ||
2747 | #define BDMAC_DDA_BASE_MASK (0x0fffff << BDMAC_DDA_BASE_BIT) | ||
2748 | #define BDMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */ | ||
2749 | #define BDMAC_DDA_OFFSET_MASK (0x0ff << BDMAC_DDA_OFFSET_BIT) | ||
2750 | |||
2751 | // BDMA stride address register | ||
2752 | #define BDMAC_DSD_TSD_BIT 16 /* target stride address */ | ||
2753 | #define BDMAC_DSD_TSD_MASK (0xffff << BDMAC_DSD_TSD_BIT) | ||
2754 | #define BDMAC_DSD_SSD_BIT 0 /* source stride address */ | ||
2755 | #define BDMAC_DSD_SSD_MASK (0xffff << BDMAC_DSD_SSD_BIT) | ||
2756 | |||
2757 | // BDMA NAND Detect timer register | ||
2758 | #define BDMAC_NDTCTIMER_EN (1 << 15) /* enable detect timer */ | ||
2759 | #define BDMAC_TAILCNT_BIT 16 | ||
2760 | |||
2761 | // BDMA control register | ||
2762 | #define BDMAC_DMACR_PR_BIT 8 /* channel priority mode */ | ||
2763 | #define BDMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT) | ||
2764 | #define BDMAC_DMACR_PR_01_2 (0 << BDMAC_DMACR_PR_BIT) | ||
2765 | #define BDMAC_DMACR_PR_12_0 (1 << BDMAC_DMACR_PR_BIT) | ||
2766 | #define BDMAC_DMACR_PR_20_1 (2 << BDMAC_DMACR_PR_BIT) | ||
2767 | #define BDMAC_DMACR_PR_012 (3 << BDMAC_DMACR_PR_BIT) | ||
2768 | #define BDMAC_DMACR_HLT (1 << 3) /* DMA halt flag */ | ||
2769 | #define BDMAC_DMACR_AR (1 << 2) /* address error flag */ | ||
2770 | #define BDMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */ | ||
2771 | |||
2772 | // BDMA interrupt pending register | ||
2773 | #define BDMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */ | ||
2774 | #define BDMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */ | ||
2775 | #define BDMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */ | ||
2776 | |||
2777 | // BDMA doorbell register | ||
2778 | #define BDMAC_DMADBR_DB2 (1 << 2) /* doorbell for channel 2 */ | ||
2779 | #define BDMAC_DMADBR_DB1 (1 << 1) /* doorbell for channel 1 */ | ||
2780 | #define BDMAC_DMADBR_DB0 (1 << 0) /* doorbell for channel 0 */ | ||
2781 | |||
2782 | // BDMA doorbell set register | ||
2783 | #define BDMAC_DMADBSR_DBS2 (1 << 2) /* enable doorbell for channel 2 */ | ||
2784 | #define BDMAC_DMADBSR_DBS1 (1 << 1) /* enable doorbell for channel 1 */ | ||
2785 | #define BDMAC_DMADBSR_DBS0 (1 << 0) /* enable doorbell for channel 0 */ | ||
2786 | |||
2787 | #ifndef __MIPS_ASSEMBLER | ||
2788 | |||
2789 | /*************************************************************************** | ||
2790 | * BCH & NAND DMAC | ||
2791 | ***************************************************************************/ | ||
2792 | |||
2793 | #define __bdmac_enable_module() \ | ||
2794 | ( REG_BDMAC_DMACR |= BDMAC_DMACR_DMAE ) | ||
2795 | #define __bdmac_disable_module() \ | ||
2796 | ( REG_BDMAC_DMACR &= ~BDMAC_DMACR_DMAE ) | ||
2797 | |||
2798 | /* n is the DMA channel index (0 - 2) */ | ||
2799 | |||
2800 | #define __bdmac_test_halt_error ( REG_BDMAC_DMACR & BDMAC_DMACR_HLT ) | ||
2801 | #define __bdmac_test_addr_error ( REG_BDMAC_DMACR & BDMAC_DMACR_AR ) | ||
2802 | |||
2803 | #define __bdmac_channel_enable_clk(n) \ | ||
2804 | REG_BDMAC_DMACKES = 1 << (n); | ||
2805 | |||
2806 | #define __bdmac_enable_descriptor(n) \ | ||
2807 | ( REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_NDES ) | ||
2808 | #define __bdmac_disable_descriptor(n) \ | ||
2809 | ( REG_BDMAC_DCCSR((n)) |= BDMAC_DCCSR_NDES ) | ||
2810 | |||
2811 | #define __bdmac_enable_channel(n) \ | ||
2812 | do { \ | ||
2813 | REG_BDMAC_DCCSR((n)) |= BDMAC_DCCSR_EN; \ | ||
2814 | } while (0) | ||
2815 | #define __bdmac_disable_channel(n) \ | ||
2816 | do { \ | ||
2817 | REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_EN; \ | ||
2818 | } while (0) | ||
2819 | |||
2820 | #define __bdmac_channel_enable_irq(n) \ | ||
2821 | ( REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_TIE ) | ||
2822 | #define __bdmac_channel_disable_irq(n) \ | ||
2823 | ( REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_TIE ) | ||
2824 | |||
2825 | #define __bdmac_channel_transmit_halt_detected(n) \ | ||
2826 | ( REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_HLT ) | ||
2827 | #define __bdmac_channel_transmit_end_detected(n) \ | ||
2828 | ( REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_TT ) | ||
2829 | /* Nand ops status error, only for channel 1 */ | ||
2830 | #define __bdmac_channel_status_error_detected() \ | ||
2831 | ( REG_BDMAC_DCCSR(1) & BDMAC_DCCSR_NSERR ) | ||
2832 | #define __bdmac_channel_address_error_detected(n) \ | ||
2833 | ( REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_AR ) | ||
2834 | #define __bdmac_channel_count_terminated_detected(n) \ | ||
2835 | ( REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_CT ) | ||
2836 | #define __bdmac_channel_descriptor_invalid_detected(n) \ | ||
2837 | ( REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_INV ) | ||
2838 | #define __bdmac_BCH_error_detected(n) \ | ||
2839 | ( REG_BDMAC_DCCSR((n)) & BDMAC_DCCSR_BERR ) | ||
2840 | |||
2841 | #define __bdmac_channel_clear_transmit_halt(n) \ | ||
2842 | do { \ | ||
2843 | /* clear both channel halt error and globle halt error */ \ | ||
2844 | REG_BDMAC_DCCSR(n) &= ~BDMAC_DCCSR_HLT; \ | ||
2845 | REG_BDMAC_DMACR &= ~BDMAC_DMACR_HLT; \ | ||
2846 | } while (0) | ||
2847 | #define __bdmac_channel_clear_transmit_end(n) \ | ||
2848 | ( REG_BDMAC_DCCSR(n) &= ~BDMAC_DCCSR_TT ) | ||
2849 | /* Nand ops status error, only for channel 1 */ | ||
2850 | #define __bdmac_channel_clear_status_error() \ | ||
2851 | ( REG_BDMAC_DCCSR(1) &= ~BDMAC_DCCSR_NSERR ) | ||
2852 | #define __bdmac_channel_clear_address_error(n) \ | ||
2853 | do { \ | ||
2854 | REG_BDMAC_DDA(n) = 0; /* clear descriptor address register */ \ | ||
2855 | REG_BDMAC_DSAR(n) = 0; /* clear source address register */ \ | ||
2856 | REG_BDMAC_DTAR(n) = 0; /* clear target address register */ \ | ||
2857 | /* clear both channel addr error and globle address error */ \ | ||
2858 | REG_BDMAC_DCCSR(n) &= ~BDMAC_DCCSR_AR; \ | ||
2859 | REG_BDMAC_DMACR &= ~BDMAC_DMACR_AR; \ | ||
2860 | } while (0) | ||
2861 | #define __bdmac_channel_clear_count_terminated(n) \ | ||
2862 | ( REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_CT ) | ||
2863 | #define __bdmac_channel_clear_descriptor_invalid(n) \ | ||
2864 | ( REG_BDMAC_DCCSR((n)) &= ~BDMAC_DCCSR_INV ) | ||
2865 | |||
2866 | #define __bdmac_channel_set_transfer_unit_32bit(n) \ | ||
2867 | do { \ | ||
2868 | REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK; \ | ||
2869 | REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_32BIT; \ | ||
2870 | } while (0) | ||
2871 | |||
2872 | #define __bdmac_channel_set_transfer_unit_16bit(n) \ | ||
2873 | do { \ | ||
2874 | REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK; \ | ||
2875 | REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_16BIT; \ | ||
2876 | } while (0) | ||
2877 | |||
2878 | #define __bdmac_channel_set_transfer_unit_8bit(n) \ | ||
2879 | do { \ | ||
2880 | REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK; \ | ||
2881 | REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_8BIT; \ | ||
2882 | } while (0) | ||
2883 | |||
2884 | #define __bdmac_channel_set_transfer_unit_16byte(n) \ | ||
2885 | do { \ | ||
2886 | REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK; \ | ||
2887 | REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_16BYTE; \ | ||
2888 | } while (0) | ||
2889 | |||
2890 | #define __bdmac_channel_set_transfer_unit_32byte(n) \ | ||
2891 | do { \ | ||
2892 | REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DS_MASK; \ | ||
2893 | REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DS_32BYTE; \ | ||
2894 | } while (0) | ||
2895 | |||
2896 | /* w=8,16,32 */ | ||
2897 | #define __bdmac_channel_set_dest_port_width(n,w) \ | ||
2898 | do { \ | ||
2899 | REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DWDH_MASK; \ | ||
2900 | REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DWDH_##w; \ | ||
2901 | } while (0) | ||
2902 | |||
2903 | /* w=8,16,32 */ | ||
2904 | #define __bdmac_channel_set_src_port_width(n,w) \ | ||
2905 | do { \ | ||
2906 | REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_SWDH_MASK; \ | ||
2907 | REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_SWDH_##w; \ | ||
2908 | } while (0) | ||
2909 | |||
2910 | #define __bdmac_channel_dest_addr_fixed(n) \ | ||
2911 | (REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_DAI) | ||
2912 | #define __bdmac_channel_dest_addr_increment(n) \ | ||
2913 | (REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_DAI) | ||
2914 | |||
2915 | #define __bdmac_channel_src_addr_fixed(n) \ | ||
2916 | (REG_BDMAC_DCMD((n)) &= ~BDMAC_DCMD_SAI) | ||
2917 | #define __bdmac_channel_src_addr_increment(n) \ | ||
2918 | (REG_BDMAC_DCMD((n)) |= BDMAC_DCMD_SAI) | ||
2919 | |||
2920 | #define __bdmac_channel_set_doorbell(n) \ | ||
2921 | (REG_BDMAC_DMADBSR = (1 << (n))) | ||
2922 | |||
2923 | #define __bdmac_channel_irq_detected(n) (REG_BDMAC_DMAIPR & (1 << (n))) | ||
2924 | #define __bdmac_channel_ack_irq(n) (REG_BDMAC_DMAIPR &= ~(1 <<(n))) | ||
2925 | |||
2926 | static __inline__ int __bdmac_get_irq(void) | ||
2927 | { | ||
2928 | int i; | ||
2929 | for (i = 0; i < MAX_BDMA_NUM; i++) | ||
2930 | if (__bdmac_channel_irq_detected(i)) | ||
2931 | return i; | ||
2932 | return -1; | ||
2933 | } | ||
2934 | |||
2935 | #endif /* __MIPS_ASSEMBLER */ | ||
2936 | |||
2937 | #define CIM_BASE 0xB3060000 | ||
2938 | |||
2939 | /************************************************************************* | ||
2940 | * CIM | ||
2941 | *************************************************************************/ | ||
2942 | #define CIM_CFG (CIM_BASE + 0x0000) | ||
2943 | #define CIM_CTRL (CIM_BASE + 0x0004) | ||
2944 | #define CIM_STATE (CIM_BASE + 0x0008) | ||
2945 | #define CIM_IID (CIM_BASE + 0x000C) | ||
2946 | #define CIM_DA (CIM_BASE + 0x0020) | ||
2947 | #define CIM_FA (CIM_BASE + 0x0024) | ||
2948 | #define CIM_FID (CIM_BASE + 0x0028) | ||
2949 | #define CIM_CMD (CIM_BASE + 0x002C) | ||
2950 | #define CIM_SIZE (CIM_BASE + 0x0030) | ||
2951 | #define CIM_OFFSET (CIM_BASE + 0x0034) | ||
2952 | #define CIM_YFA (CIM_BASE + 0x0038) | ||
2953 | #define CIM_YCMD (CIM_BASE + 0x003C) | ||
2954 | #define CIM_CBFA (CIM_BASE + 0x0040) | ||
2955 | #define CIM_CBCMD (CIM_BASE + 0x0044) | ||
2956 | #define CIM_CRFA (CIM_BASE + 0x0048) | ||
2957 | #define CIM_CRCMD (CIM_BASE + 0x004C) | ||
2958 | #define CIM_CTRL2 (CIM_BASE + 0x0050) | ||
2959 | |||
2960 | #define CIM_RAM_ADDR (CIM_BASE + 0x1000) | ||
2961 | |||
2962 | #define REG_CIM_CFG REG32(CIM_CFG) | ||
2963 | #define REG_CIM_CTRL REG32(CIM_CTRL) | ||
2964 | #define REG_CIM_STATE REG32(CIM_STATE) | ||
2965 | #define REG_CIM_IID REG32(CIM_IID) | ||
2966 | #define REG_CIM_DA REG32(CIM_DA) | ||
2967 | #define REG_CIM_FA REG32(CIM_FA) | ||
2968 | #define REG_CIM_FID REG32(CIM_FID) | ||
2969 | #define REG_CIM_CMD REG32(CIM_CMD) | ||
2970 | #define REG_CIM_SIZE REG32(CIM_SIZE) | ||
2971 | #define REG_CIM_OFFSET REG32(CIM_OFFSET) | ||
2972 | #define REG_CIM_YFA REG32(CIM_YFA) | ||
2973 | #define REG_CIM_YCMD REG32(CIM_YCMD) | ||
2974 | #define REG_CIM_CBFA REG32(CIM_CBFA) | ||
2975 | #define REG_CIM_CBCMD REG32(CIM_CBCMD) | ||
2976 | #define REG_CIM_CRFA REG32(CIM_CRFA) | ||
2977 | #define REG_CIM_CRCMD REG32(CIM_CRCMD) | ||
2978 | #define REG_CIM_CTRL2 REG32(CIM_CTRL2) | ||
2979 | |||
2980 | #define CIM_CFG_EEOFEN (1 << 31) | ||
2981 | #define CIM_CFG_EXP (1 << 30) | ||
2982 | |||
2983 | #define CIM_CFG_RXF_TRIG_BIT 24 | ||
2984 | #define CIM_CFG_RXF_TRIG_MASK (0x3f << CIM_CFG_RXF_TRIG_BIT) | ||
2985 | |||
2986 | #define CIM_CFG_BW_BIT 22 | ||
2987 | #define CIM_CFG_BW_MASK (0x3 << CIM_CFG_BW_BIT) | ||
2988 | |||
2989 | #define CIM_CFG_SEP (1 << 20) | ||
2990 | |||
2991 | #define CIM_CFG_ORDER_BIT 18 | ||
2992 | #define CIM_CFG_ORDER_MASK (0x3 << CIM_CFG_ORDER_BIT) | ||
2993 | #define CIM_CFG_ORDER_0 (0x0 << CIM_CFG_ORDER_BIT) /* Y0CbY1Cr; YCbCr */ | ||
2994 | #define CIM_CFG_ORDER_1 (0x1 << CIM_CFG_ORDER_BIT) /* Y0CrY1Cb; YCrCb */ | ||
2995 | #define CIM_CFG_ORDER_2 (0x2 << CIM_CFG_ORDER_BIT) /* CbY0CrY1; CbCrY */ | ||
2996 | #define CIM_CFG_ORDER_3 (0x3 << CIM_CFG_ORDER_BIT) /* CrY0CbY1; CrCbY */ | ||
2997 | |||
2998 | #define CIM_CFG_DF_BIT 16 | ||
2999 | #define CIM_CFG_DF_MASK (0x3 << CIM_CFG_DF_BIT) | ||
3000 | #define CIM_CFG_DF_YUV444 (0x1 << CIM_CFG_DF_BIT) /* YCbCr444 */ | ||
3001 | #define CIM_CFG_DF_YUV422 (0x2 << CIM_CFG_DF_BIT) /* YCbCr422 */ | ||
3002 | #define CIM_CFG_DF_ITU656 (0x3 << CIM_CFG_DF_BIT) /* ITU656 YCbCr422 */ | ||
3003 | |||
3004 | #define CIM_CFG_INV_DAT (1 << 15) | ||
3005 | #define CIM_CFG_VSP (1 << 14) /* VSYNC Polarity:0-rising edge active,1-falling edge active */ | ||
3006 | #define CIM_CFG_HSP (1 << 13) /* HSYNC Polarity:0-rising edge active,1-falling edge active */ | ||
3007 | #define CIM_CFG_PCP (1 << 12) /* PCLK working edge: 0-rising, 1-falling */ | ||
3008 | |||
3009 | #define CIM_CFG_DMA_BURST_TYPE_BIT 10 | ||
3010 | #define CIM_CFG_DMA_BURST_TYPE_MASK (0x3 << CIM_CFG_DMA_BURST_TYPE_BIT) | ||
3011 | #define CIM_CFG_DMA_BURST_INCR4 (0 << CIM_CFG_DMA_BURST_TYPE_BIT) | ||
3012 | #define CIM_CFG_DMA_BURST_INCR8 (1 << CIM_CFG_DMA_BURST_TYPE_BIT) /* Suggested */ | ||
3013 | #define CIM_CFG_DMA_BURST_INCR16 (2 << CIM_CFG_DMA_BURST_TYPE_BIT) /* Suggested High speed AHB*/ | ||
3014 | #define CIM_CFG_DMA_BURST_INCR32 (3 << CIM_CFG_DMA_BURST_TYPE_BIT) /* Suggested High speed AHB*/ | ||
3015 | |||
3016 | #define CIM_CFG_DUMMY_ZERO (1 << 9) | ||
3017 | #define CIM_CFG_EXT_VSYNC (1 << 8) /* Only for ITU656 Progressive mode */ | ||
3018 | #define CIM_CFG_LM (1 << 7) /* Only for ITU656 Progressive mode */ | ||
3019 | #define CIM_CFG_PACK_BIT 4 | ||
3020 | #define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT) | ||
3021 | #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT) /* 11 22 33 44 0xY0CbY1Cr */ | ||
3022 | #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT) /* 22 33 44 11 0xCbY1CrY0 */ | ||
3023 | #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT) /* 33 44 11 22 0xY1CrY0Cb */ | ||
3024 | #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT) /* 44 11 22 33 0xCrY0CbY1 */ | ||
3025 | #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT) /* 44 33 22 11 0xCrY1CbY0 */ | ||
3026 | #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT) /* 33 22 11 44 0xY1CbY0Cr */ | ||
3027 | #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT) /* 22 11 44 33 0xCbY0CrY1 */ | ||
3028 | #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT) /* 11 44 33 22 0xY0CrY1Cb */ | ||
3029 | #define CIM_CFG_FP (1 << 3) /* Only for ITU656 Progressive mode */ | ||
3030 | #define CIM_CFG_BYPASS_BIT 2 | ||
3031 | #define CIM_CFG_BYPASS_MASK (1 << CIM_CFG_BYPASS_BIT) | ||
3032 | #define CIM_CFG_BYPASS (1 << CIM_CFG_BYPASS_BIT) | ||
3033 | #define CIM_CFG_DSM_BIT 0 | ||
3034 | #define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT) | ||
3035 | #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */ | ||
3036 | #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */ | ||
3037 | #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */ | ||
3038 | |||
3039 | /* CIM Control Register (CIM_CTRL) */ | ||
3040 | #define CIM_CTRL_EEOF_LINE_BIT 20 | ||
3041 | #define CIM_CTRL_EEOF_LINE_MASK (0xfff << CIM_CTRL_EEOF_LINE_BIT) | ||
3042 | |||
3043 | #define CIM_CTRL_FRC_BIT 16 | ||
3044 | #define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT) | ||
3045 | #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */ | ||
3046 | #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */ | ||
3047 | #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */ | ||
3048 | #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */ | ||
3049 | #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */ | ||
3050 | #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */ | ||
3051 | #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */ | ||
3052 | #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */ | ||
3053 | #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */ | ||
3054 | #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */ | ||
3055 | #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */ | ||
3056 | #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */ | ||
3057 | #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */ | ||
3058 | #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */ | ||
3059 | #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */ | ||
3060 | #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */ | ||
3061 | |||
3062 | #define CIM_CTRL_DMA_EEOF (1 << 15) /* Enable EEOF interrupt */ | ||
3063 | #define CIM_CTRL_WIN_EN (1 << 14) | ||
3064 | #define CIM_CTRL_VDDM (1 << 13) /* VDD interrupt enable */ | ||
3065 | #define CIM_CTRL_DMA_SOFM (1 << 12) | ||
3066 | #define CIM_CTRL_DMA_EOFM (1 << 11) | ||
3067 | #define CIM_CTRL_DMA_STOPM (1 << 10) | ||
3068 | #define CIM_CTRL_RXF_TRIGM (1 << 9) | ||
3069 | #define CIM_CTRL_RXF_OFM (1 << 8) | ||
3070 | #define CIM_CTRL_DMA_SYNC (1 << 7) /*when change DA, do frame sync */ | ||
3071 | #define CIM_CTRL_H_SYNC (1 << 6) /*Enable horizental sync when CIMCFG.SEP is 1*/ | ||
3072 | |||
3073 | #define CIM_CTRL_PPW_BIT 3 | ||
3074 | #define CIM_CTRL_PPW_MASK (0x3 << CIM_CTRL_PPW_BIT) | ||
3075 | |||
3076 | #define CIM_CTRL_DMA_EN (1 << 2) /* Enable DMA */ | ||
3077 | #define CIM_CTRL_RXF_RST (1 << 1) /* RxFIFO reset */ | ||
3078 | #define CIM_CTRL_ENA (1 << 0) /* Enable CIM */ | ||
3079 | |||
3080 | /* cim control2 */ | ||
3081 | #define CIM_CTRL2_OPG_BIT 4 | ||
3082 | #define CIM_CTRL2_OPG_MASK (0x3 << CIM_CTRL2_OPG_BIT) | ||
3083 | #define CIM_CTRL2_OPE (1 << 2) | ||
3084 | #define CIM_CTRL2_EME (1 << 1) | ||
3085 | #define CIM_CTRL2_APM (1 << 0) | ||
3086 | |||
3087 | /* CIM State Register (CIM_STATE) */ | ||
3088 | #define CIM_STATE_CR_RF_OF (1 << 27) | ||
3089 | #define CIM_STATE_CR_RF_TRIG (1 << 26) | ||
3090 | #define CIM_STATE_CR_RF_EMPTY (1 << 25) | ||
3091 | #define CIM_STATE_CB_RF_OF (1 << 19) | ||
3092 | #define CIM_STATE_CB_RF_TRIG (1 << 18) | ||
3093 | #define CIM_STATE_CB_RF_EMPTY (1 << 17) | ||
3094 | #define CIM_STATE_Y_RF_OF (1 << 11) | ||
3095 | #define CIM_STATE_Y_RF_TRIG (1 << 10) | ||
3096 | #define CIM_STATE_Y_RF_EMPTY (1 << 9) | ||
3097 | #define CIM_STATE_DMA_EEOF (1 << 7) /* DMA Line EEOf irq */ | ||
3098 | #define CIM_STATE_DMA_SOF (1 << 6) /* DMA start irq */ | ||
3099 | #define CIM_STATE_DMA_EOF (1 << 5) /* DMA end irq */ | ||
3100 | #define CIM_STATE_DMA_STOP (1 << 4) /* DMA stop irq */ | ||
3101 | #define CIM_STATE_RXF_OF (1 << 3) /* RXFIFO over flow irq */ | ||
3102 | #define CIM_STATE_RXF_TRIG (1 << 2) /* RXFIFO triger meet irq */ | ||
3103 | #define CIM_STATE_RXF_EMPTY (1 << 1) /* RXFIFO empty irq */ | ||
3104 | #define CIM_STATE_VDD (1 << 0) /* CIM disabled irq */ | ||
3105 | |||
3106 | /* CIM DMA Command Register (CIM_CMD) */ | ||
3107 | |||
3108 | #define CIM_CMD_SOFINT (1 << 31) /* enable DMA start irq */ | ||
3109 | #define CIM_CMD_EOFINT (1 << 30) /* enable DMA end irq */ | ||
3110 | #define CIM_CMD_EEOFINT (1 << 29) /* enable DMA EEOF irq */ | ||
3111 | #define CIM_CMD_STOP (1 << 28) /* enable DMA stop irq */ | ||
3112 | #define CIM_CMD_OFRCV (1 << 27) /* enable recovery when TXFiFo overflow */ | ||
3113 | #define CIM_CMD_LEN_BIT 0 | ||
3114 | #define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT) | ||
3115 | |||
3116 | /* CIM Window-Image Size Register (CIM_SIZE) */ | ||
3117 | #define CIM_SIZE_LPF_BIT 16 /* Lines per freame for csc output image */ | ||
3118 | #define CIM_SIZE_LPF_MASK (0x1fff << CIM_SIZE_LPF_BIT) | ||
3119 | #define CIM_SIZE_PPL_BIT 0 /* Pixels per line for csc output image, should be an even number */ | ||
3120 | #define CIM_SIZE_PPL_MASK (0x1fff << CIM_SIZE_PPL_BIT) | ||
3121 | |||
3122 | /* CIM Image Offset Register (CIM_OFFSET) */ | ||
3123 | #define CIM_OFFSET_V_BIT 16 /* Vertical offset */ | ||
3124 | #define CIM_OFFSET_V_MASK (0xfff << CIM_OFFSET_V_BIT) | ||
3125 | #define CIM_OFFSET_H_BIT 0 /* Horizontal offset, should be an enen number */ | ||
3126 | #define CIM_OFFSET_H_MASK (0xfff << CIM_OFFSET_H_BIT) /*OFFSET_H should be even number*/ | ||
3127 | |||
3128 | #define CIM_YCMD_SOFINT (1 << 31) /* enable DMA start irq */ | ||
3129 | #define CIM_YCMD_EOFINT (1 << 30) /* enable DMA end irq */ | ||
3130 | #define CIM_YCMD_EEOFINT (1 << 29) /* enable DMA EEOF irq */ | ||
3131 | #define CIM_YCMD_STOP (1 << 28) /* enable DMA stop irq */ | ||
3132 | #define CIM_YCMD_OFRCV (1 << 27) /* enable recovery when TXFiFo overflow */ | ||
3133 | #define CIM_YCMD_LEN_BIT 0 | ||
3134 | #define CIM_YCMD_LEN_MASK (0xffffff << CIM_YCMD_LEN_BIT) | ||
3135 | |||
3136 | #define CIM_CBCMD_LEN_BIT 0 | ||
3137 | #define CIM_CBCMD_LEN_MASK (0xffffff << CIM_CBCMD_LEN_BIT) | ||
3138 | |||
3139 | #define CIM_CRCMD_LEN_BIT 0 | ||
3140 | #define CIM_CRCMD_LEN_MASK (0xffffff << CIM_CRCMD_LEN_BIT) | ||
3141 | |||
3142 | #ifndef __MIPS_ASSEMBLER | ||
3143 | |||
3144 | /*************************************************************************** | ||
3145 | * CIM | ||
3146 | ***************************************************************************/ | ||
3147 | |||
3148 | #define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA ) | ||
3149 | #define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA ) | ||
3150 | |||
3151 | #define __cim_enable_sep() (REG_CIM_CFG |= CIM_CFG_SEP) | ||
3152 | #define __cim_disable_sep() (REG_CIM_CFG &= ~CIM_CFG_SEP) | ||
3153 | |||
3154 | /* n = 0, 1, 2, 3 */ | ||
3155 | #define __cim_set_input_data_stream_order(n) \ | ||
3156 | do { \ | ||
3157 | REG_CIM_CFG &= ~CIM_CFG_ORDER_MASK; \ | ||
3158 | REG_CIM_CFG |= ((n)<<CIM_CFG_ORDER_BIT)&CIM_CFG_ORDER_MASK; \ | ||
3159 | } while (0) | ||
3160 | |||
3161 | #define __cim_input_data_format_select_YUV444() \ | ||
3162 | do { \ | ||
3163 | REG_CIM_CFG &= ~CIM_CFG_DF_MASK; \ | ||
3164 | REG_CIM_CFG |= CIM_CFG_DF_YUV444; \ | ||
3165 | } while (0) | ||
3166 | |||
3167 | #define __cim_input_data_format_select_YUV422() \ | ||
3168 | do { \ | ||
3169 | REG_CIM_CFG &= ~CIM_CFG_DF_MASK; \ | ||
3170 | REG_CIM_CFG |= CIM_CFG_DF_YUV422; \ | ||
3171 | } while (0) | ||
3172 | |||
3173 | #define __cim_input_data_format_select_ITU656() \ | ||
3174 | do { \ | ||
3175 | REG_CIM_CFG &= ~CIM_CFG_DF_MASK; \ | ||
3176 | REG_CIM_CFG |= CIM_CFG_DF_ITU656; \ | ||
3177 | } while (0) | ||
3178 | |||
3179 | #define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT ) | ||
3180 | #define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT ) | ||
3181 | |||
3182 | #define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP ) | ||
3183 | #define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP ) | ||
3184 | |||
3185 | #define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP ) | ||
3186 | #define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP ) | ||
3187 | |||
3188 | #define __cim_sample_data_at_pclk_falling_edge() \ | ||
3189 | ( REG_CIM_CFG |= CIM_CFG_PCP ) | ||
3190 | #define __cim_sample_data_at_pclk_rising_edge() \ | ||
3191 | ( REG_CIM_CFG &= ~CIM_CFG_PCP ) | ||
3192 | |||
3193 | #define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO ) | ||
3194 | #define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO ) | ||
3195 | |||
3196 | #define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC ) | ||
3197 | #define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC ) | ||
3198 | |||
3199 | /* n=0-7 */ | ||
3200 | #define __cim_set_data_packing_mode(n) \ | ||
3201 | do { \ | ||
3202 | REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \ | ||
3203 | REG_CIM_CFG |= (CIM_CFG_PACK_##n); \ | ||
3204 | } while (0) | ||
3205 | |||
3206 | #define __cim_enable_bypass_func() (REG_CIM_CFG &= ~CIM_CFG_BYPASS) | ||
3207 | #define __cim_disable_bypass_func() (REG_CIM_CFG |= CIM_CFG_BYPASS) | ||
3208 | |||
3209 | #define __cim_enable_ccir656_progressive_mode() \ | ||
3210 | do { \ | ||
3211 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ | ||
3212 | REG_CIM_CFG |= CIM_CFG_DSM_CPM; \ | ||
3213 | } while (0) | ||
3214 | |||
3215 | #define __cim_enable_ccir656_interlace_mode() \ | ||
3216 | do { \ | ||
3217 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ | ||
3218 | REG_CIM_CFG |= CIM_CFG_DSM_CIM; \ | ||
3219 | } while (0) | ||
3220 | |||
3221 | #define __cim_enable_gated_clock_mode() \ | ||
3222 | do { \ | ||
3223 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ | ||
3224 | REG_CIM_CFG |= CIM_CFG_DSM_GCM; \ | ||
3225 | } while (0) | ||
3226 | |||
3227 | #define __cim_enable_nongated_clock_mode() \ | ||
3228 | do { \ | ||
3229 | REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ | ||
3230 | REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \ | ||
3231 | } while (0) | ||
3232 | |||
3233 | /* n=1-16 */ | ||
3234 | #define __cim_set_frame_rate(n) \ | ||
3235 | do { \ | ||
3236 | REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \ | ||
3237 | REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \ | ||
3238 | } while (0) | ||
3239 | |||
3240 | #define __cim_enable_size_func() \ | ||
3241 | ( REG_CIM_CTRL |= CIM_CTRL_WIN_EN) | ||
3242 | #define __cim_disable_size_func() \ | ||
3243 | ( REG_CIM_CTRL &= ~CIM_CTRL_WIN_EN ) | ||
3244 | |||
3245 | #define __cim_enable_vdd_intr() \ | ||
3246 | ( REG_CIM_CTRL |= CIM_CTRL_VDDM ) | ||
3247 | #define __cim_disable_vdd_intr() \ | ||
3248 | ( REG_CIM_CTRL &= ~CIM_CTRL_VDDM ) | ||
3249 | |||
3250 | #define __cim_enable_sof_intr() \ | ||
3251 | ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM ) | ||
3252 | #define __cim_disable_sof_intr() \ | ||
3253 | ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM ) | ||
3254 | |||
3255 | #define __cim_enable_eof_intr() \ | ||
3256 | ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM ) | ||
3257 | #define __cim_disable_eof_intr() \ | ||
3258 | ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM ) | ||
3259 | |||
3260 | #define __cim_enable_eeof_intr() \ | ||
3261 | ( REG_CIM_CTRL |= CIM_CTRL_DMA_EEOFM ) | ||
3262 | #define __cim_disable_eeof_intr() \ | ||
3263 | ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EEOFM ) | ||
3264 | |||
3265 | #define __cim_enable_stop_intr() \ | ||
3266 | ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM ) | ||
3267 | #define __cim_disable_stop_intr() \ | ||
3268 | ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM ) | ||
3269 | |||
3270 | #define __cim_enable_trig_intr() \ | ||
3271 | ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM ) | ||
3272 | #define __cim_disable_trig_intr() \ | ||
3273 | ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM ) | ||
3274 | |||
3275 | #define __cim_enable_rxfifo_overflow_intr() \ | ||
3276 | ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM ) | ||
3277 | #define __cim_disable_rxfifo_overflow_intr() \ | ||
3278 | ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM ) | ||
3279 | |||
3280 | #define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN ) | ||
3281 | #define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN ) | ||
3282 | #define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST ) | ||
3283 | #define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST ) | ||
3284 | |||
3285 | /* cim control2 */ | ||
3286 | #define __cim_enable_priority_control() ( REG_CIM_CTRL2 |= CIM_CTRL2_OPE) | ||
3287 | #define __cim_disable_priority_control() ( REG_CIM_CTRL2 &= ~CIM_CTRL2_OPE) | ||
3288 | #define __cim_enable_auto_priority() ( REG_CIM_CTRL2 |= CIM_CTRL2_APM) | ||
3289 | #define __cim_disable_auto_priority() ( REG_CIM_CTRL2 &= ~CIM_CTRL2_APM) | ||
3290 | #define __cim_enable_emergency() ( REG_CIM_CTRL2 |= CIM_CTRL2_EME) | ||
3291 | #define __cim_disable_emergency() ( REG_CIM_CTRL2 &= ~CIM_CTRL2_EME); | ||
3292 | /* 0, 1, 2, 3 | ||
3293 | ** 0: highest priority | ||
3294 | ** 3: lowest priority | ||
3295 | ** 1 maybe best for SEP=1 | ||
3296 | ** 3 maybe best for SEP=0 | ||
3297 | **/ | ||
3298 | #define __cim_set_opg(n) \ | ||
3299 | do { \ | ||
3300 | REG_CIM_CTRL2 &= ~CIM_CTRL2_OPG_MASK; \ | ||
3301 | REG_CIM_CTRL2 |= ((n) << CIM_CTRL2_OPG_BIT) & CIM_CTRL2_OPG_MASK; \ | ||
3302 | } while (0) | ||
3303 | |||
3304 | #define __cim_clear_state() ( REG_CIM_STATE = 0 ) | ||
3305 | |||
3306 | #define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD ) | ||
3307 | #define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY ) | ||
3308 | #define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG ) | ||
3309 | #define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF ) | ||
3310 | #define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF ) | ||
3311 | #define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP ) | ||
3312 | #define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF ) | ||
3313 | #define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF ) | ||
3314 | |||
3315 | #define __cim_get_iid() ( REG_CIM_IID ) | ||
3316 | #define __cim_get_fid() ( REG_CIM_FID ) | ||
3317 | //#define __cim_get_image_data() ( REG_CIM_RXFIFO ) | ||
3318 | #define __cim_get_dma_cmd() ( REG_CIM_CMD ) | ||
3319 | |||
3320 | #define __cim_set_da(a) ( REG_CIM_DA = (a) ) | ||
3321 | |||
3322 | #define __cim_set_line(a) ( REG_CIM_SIZE = (REG_CIM_SIZE&(~CIM_SIZE_LPF_MASK))|((a)<<CIM_SIZE_LPF_BIT) ) | ||
3323 | #define __cim_set_pixel(a) ( REG_CIM_SIZE = (REG_CIM_SIZE&(~CIM_SIZE_PPL_MASK))|((a)<<CIM_SIZE_PPL_BIT) ) | ||
3324 | #define __cim_get_line() ((REG_CIM_SIZE&CIM_SIZE_LPF_MASK)>>CIM_SIZE_LPF_BIT) | ||
3325 | #define __cim_get_pixel() ((REG_CIM_SIZE&CIM_SIZE_PPL_MASK)>>CIM_SIZE_PPL_BIT) | ||
3326 | |||
3327 | #define __cim_set_v_offset(a) ( REG_CIM_OFFSET = (REG_CIM_OFFSET&(~CIM_OFFSET_V_MASK)) | ((a)<<CIM_OFFSET_V_BIT) ) | ||
3328 | #define __cim_set_h_offset(a) ( REG_CIM_OFFSET = (REG_CIM_OFFSET&(~CIM_OFFSET_H_MASK)) | ((a)<<CIM_OFFSET_H_BIT) ) | ||
3329 | #define __cim_get_v_offset() ((REG_CIM_OFFSET&CIM_OFFSET_V_MASK)>>CIM_OFFSET_V_BIT) | ||
3330 | #define __cim_get_h_offset() ((REG_CIM_OFFSET&CIM_OFFSET_H_MASK)>>CIM_OFFSET_H_BIT) | ||
3331 | |||
3332 | #endif /* __MIPS_ASSEMBLER */ | ||
3333 | |||
3334 | /* | ||
3335 | * Clock reset and power controller module(CPM) address definition | ||
3336 | */ | ||
3337 | #define CPM_BASE 0xb0000000 | ||
3338 | |||
3339 | /* | ||
3340 | * CPM registers offset address definition | ||
3341 | */ | ||
3342 | #define CPM_CPCCR_OFFSET (0x00) /* rw, 32, 0x01011100 */ | ||
3343 | #define CPM_LCR_OFFSET (0x04) /* rw, 32, 0x000000f8 */ | ||
3344 | #define CPM_RSR_OFFSET (0x08) /* rw, 32, 0x???????? */ | ||
3345 | #define CPM_CPPCR0_OFFSET (0x10) /* rw, 32, 0x28080011 */ | ||
3346 | #define CPM_CPPSR_OFFSET (0x14) /* rw, 32, 0x80000000 */ | ||
3347 | #define CPM_CLKGR0_OFFSET (0x20) /* rw, 32, 0x3fffffe0 */ | ||
3348 | #define CPM_OPCR_OFFSET (0x24) /* rw, 32, 0x00001570 */ | ||
3349 | #define CPM_CLKGR1_OFFSET (0x28) /* rw, 32, 0x0000017f */ | ||
3350 | #define CPM_CPPCR1_OFFSET (0x30) /* rw, 32, 0x28080002 */ | ||
3351 | #define CPM_CPSPR_OFFSET (0x34) /* rw, 32, 0x???????? */ | ||
3352 | #define CPM_CPSPPR_OFFSET (0x38) /* rw, 32, 0x0000a5a5 */ | ||
3353 | #define CPM_USBPCR_OFFSET (0x3c) /* rw, 32, 0x42992198 */ | ||
3354 | #define CPM_USBRDT_OFFSET (0x40) /* rw, 32, 0x00000096 */ | ||
3355 | #define CPM_USBVBFIL_OFFSET (0x44) /* rw, 32, 0x00000080 */ | ||
3356 | #define CPM_USBCDR_OFFSET (0x50) /* rw, 32, 0x00000000 */ | ||
3357 | #define CPM_I2SCDR_OFFSET (0x60) /* rw, 32, 0x00000000 */ | ||
3358 | #define CPM_LPCDR_OFFSET (0x64) /* rw, 32, 0x00000000 */ | ||
3359 | #define CPM_MSCCDR_OFFSET (0x68) /* rw, 32, 0x00000000 */ | ||
3360 | #define CPM_UHCCDR_OFFSET (0x6c) /* rw, 32, 0x00000000 */ | ||
3361 | #define CPM_SSICDR_OFFSET (0x74) /* rw, 32, 0x00000000 */ | ||
3362 | #define CPM_CIMCDR_OFFSET (0x7c) /* rw, 32, 0x00000000 */ | ||
3363 | #define CPM_GPSCDR_OFFSET (0x80) /* rw, 32, 0x00000000 */ | ||
3364 | #define CPM_PCMCDR_OFFSET (0x84) /* rw, 32, 0x00000000 */ | ||
3365 | #define CPM_GPUCDR_OFFSET (0x88) /* rw, 32, 0x00000000 */ | ||
3366 | #define CPM_PSWC0ST_OFFSET (0x90) /* rw, 32, 0x00000000 */ | ||
3367 | #define CPM_PSWC1ST_OFFSET (0x94) /* rw, 32, 0x00000000 */ | ||
3368 | #define CPM_PSWC2ST_OFFSET (0x98) /* rw, 32, 0x00000000 */ | ||
3369 | #define CPM_PSWC3ST_OFFSET (0x9c) /* rw, 32, 0x00000000 */ | ||
3370 | |||
3371 | /* | ||
3372 | * CPM registers address definition | ||
3373 | */ | ||
3374 | #define CPM_CPCCR (CPM_BASE + CPM_CPCCR_OFFSET) | ||
3375 | #define CPM_LCR (CPM_BASE + CPM_LCR_OFFSET) | ||
3376 | #define CPM_RSR (CPM_BASE + CPM_RSR_OFFSET) | ||
3377 | #define CPM_CPPCR0 (CPM_BASE + CPM_CPPCR0_OFFSET) | ||
3378 | #define CPM_CPPSR (CPM_BASE + CPM_CPPSR_OFFSET) | ||
3379 | #define CPM_CLKGR0 (CPM_BASE + CPM_CLKGR0_OFFSET) | ||
3380 | #define CPM_OPCR (CPM_BASE + CPM_OPCR_OFFSET) | ||
3381 | #define CPM_CLKGR1 (CPM_BASE + CPM_CLKGR1_OFFSET) | ||
3382 | #define CPM_CPPCR1 (CPM_BASE + CPM_CPPCR1_OFFSET) | ||
3383 | #define CPM_CPSPR (CPM_BASE + CPM_CPSPR_OFFSET) | ||
3384 | #define CPM_CPSPPR (CPM_BASE + CPM_CPSPPR_OFFSET) | ||
3385 | #define CPM_USBPCR (CPM_BASE + CPM_USBPCR_OFFSET) | ||
3386 | #define CPM_USBRDT (CPM_BASE + CPM_USBRDT_OFFSET) | ||
3387 | #define CPM_USBVBFIL (CPM_BASE + CPM_USBVBFIL_OFFSET) | ||
3388 | #define CPM_USBCDR (CPM_BASE + CPM_USBCDR_OFFSET) | ||
3389 | #define CPM_I2SCDR (CPM_BASE + CPM_I2SCDR_OFFSET) | ||
3390 | #define CPM_LPCDR (CPM_BASE + CPM_LPCDR_OFFSET) | ||
3391 | #define CPM_MSCCDR (CPM_BASE + CPM_MSCCDR_OFFSET) | ||
3392 | #define CPM_UHCCDR (CPM_BASE + CPM_UHCCDR_OFFSET) | ||
3393 | #define CPM_SSICDR (CPM_BASE + CPM_SSICDR_OFFSET) | ||
3394 | #define CPM_CIMCDR (CPM_BASE + CPM_CIMCDR_OFFSET) | ||
3395 | #define CPM_GPSCDR (CPM_BASE + CPM_GPSCDR_OFFSET) | ||
3396 | #define CPM_PCMCDR (CPM_BASE + CPM_PCMCDR_OFFSET) | ||
3397 | #define CPM_GPUCDR (CPM_BASE + CPM_GPUCDR_OFFSET) | ||
3398 | #define CPM_PSWC0ST (CPM_BASE + CPM_PSWC0ST_OFFSET) | ||
3399 | #define CPM_PSWC1ST (CPM_BASE + CPM_PSWC1ST_OFFSET) | ||
3400 | #define CPM_PSWC2ST (CPM_BASE + CPM_PSWC2ST_OFFSET) | ||
3401 | #define CPM_PSWC3ST (CPM_BASE + CPM_PSWC3ST_OFFSET) | ||
3402 | |||
3403 | /* | ||
3404 | * CPM registers common define | ||
3405 | */ | ||
3406 | |||
3407 | /* Clock control register(CPCCR) */ | ||
3408 | #define CPCCR_ECS BIT31 | ||
3409 | #define CPCCR_MEM BIT30 | ||
3410 | #define CPCCR_CE BIT22 | ||
3411 | #define CPCCR_PCS BIT21 | ||
3412 | |||
3413 | #define CPCCR_SDIV_LSB 24 | ||
3414 | #define CPCCR_SDIV_MASK BITS_H2L(27, CPCCR_SDIV_LSB) | ||
3415 | |||
3416 | #define CPCCR_H2DIV_LSB 16 | ||
3417 | #define CPCCR_H2DIV_MASK BITS_H2L(19, CPCCR_H2DIV_LSB) | ||
3418 | |||
3419 | #define CPCCR_MDIV_LSB 12 | ||
3420 | #define CPCCR_MDIV_MASK BITS_H2L(15, CPCCR_MDIV_LSB) | ||
3421 | |||
3422 | #define CPCCR_PDIV_LSB 8 | ||
3423 | #define CPCCR_PDIV_MASK BITS_H2L(11, CPCCR_PDIV_LSB) | ||
3424 | |||
3425 | #define CPCCR_HDIV_LSB 4 | ||
3426 | #define CPCCR_HDIV_MASK BITS_H2L(7, CPCCR_HDIV_LSB) | ||
3427 | |||
3428 | #define CPCCR_CDIV_LSB 0 | ||
3429 | #define CPCCR_CDIV_MASK BITS_H2L(3, CPCCR_CDIV_LSB) | ||
3430 | |||
3431 | /* Low power control register(LCR) */ | ||
3432 | #define LCR_PDAHB1 BIT30 | ||
3433 | #define LCR_PDAHB1S BIT26 | ||
3434 | #define LCR_DOZE BIT2 | ||
3435 | |||
3436 | #define LCR_PST_LSB 8 | ||
3437 | #define LCR_PST_MASK BITS_H2L(19, LCR_PST_LSB) | ||
3438 | |||
3439 | #define LCR_DUTY_LSB 3 | ||
3440 | #define LCR_DUTY_MASK BITS_H2L(7, LCR_DUTY_LSB) | ||
3441 | |||
3442 | #define LCR_LPM_LSB 0 | ||
3443 | #define LCR_LPM_MASK BITS_H2L(1, LCR_LPM_LSB) | ||
3444 | #define LCR_LPM_IDLE (0x0 << LCR_LPM_LSB) | ||
3445 | #define LCR_LPM_SLEEP (0x1 << LCR_LPM_LSB) | ||
3446 | |||
3447 | /* Reset status register(RSR) */ | ||
3448 | #define RSR_P0R BIT2 | ||
3449 | #define RSR_WR BIT1 | ||
3450 | #define RSR_PR BIT0 | ||
3451 | |||
3452 | /* PLL control register 0(CPPCR0) */ | ||
3453 | #define CPPCR0_LOCK BIT15 /* LOCK0 bit */ | ||
3454 | #define CPPCR0_PLLS BIT10 | ||
3455 | #define CPPCR0_PLLBP BIT9 | ||
3456 | #define CPPCR0_PLLEN BIT8 | ||
3457 | |||
3458 | #define CPPCR0_PLLM_LSB 24 | ||
3459 | #define CPPCR0_PLLM_MASK BITS_H2L(30, CPPCR0_PLLM_LSB) | ||
3460 | |||
3461 | #define CPPCR0_PLLN_LSB 18 | ||
3462 | #define CPPCR0_PLLN_MASK BITS_H2L(21, CPPCR0_PLLN_LSB) | ||
3463 | |||
3464 | #define CPPCR0_PLLOD_LSB 16 | ||
3465 | #define CPPCR0_PLLOD_MASK BITS_H2L(17, CPPCR0_PLLOD_LSB) | ||
3466 | |||
3467 | #define CPPCR0_PLLST_LSB 0 | ||
3468 | #define CPPCR0_PLLST_MASK BITS_H2L(7, CPPCR0_PLLST_LSB) | ||
3469 | |||
3470 | /* PLL switch and status register(CPPSR) */ | ||
3471 | #define CPPSR_PLLOFF BIT31 | ||
3472 | #define CPPSR_PLLBP BIT30 | ||
3473 | #define CPPSR_PLLON BIT29 | ||
3474 | #define CPPSR_PS BIT28 | ||
3475 | #define CPPSR_FS BIT27 | ||
3476 | #define CPPSR_CS BIT26 | ||
3477 | #define CPPSR_SM BIT2 | ||
3478 | #define CPPSR_PM BIT1 | ||
3479 | #define CPPSR_FM BIT0 | ||
3480 | |||
3481 | /* Clock gate register 0(CGR0) */ | ||
3482 | #define CLKGR0_AHB_MON BIT31 | ||
3483 | #define CLKGR0_DDR BIT30 | ||
3484 | #define CLKGR0_IPU BIT29 | ||
3485 | #define CLKGR0_LCD BIT28 | ||
3486 | #define CLKGR0_TVE BIT27 | ||
3487 | #define CLKGR0_CIM BIT26 | ||
3488 | #define CLKGR0_MDMA BIT25 | ||
3489 | #define CLKGR0_UHC BIT24 | ||
3490 | #define CLKGR0_MAC BIT23 | ||
3491 | #define CLKGR0_GPS BIT22 | ||
3492 | #define CLKGR0_DMAC BIT21 | ||
3493 | #define CLKGR0_SSI2 BIT20 | ||
3494 | #define CLKGR0_SSI1 BIT19 | ||
3495 | #define CLKGR0_UART3 BIT18 | ||
3496 | #define CLKGR0_UART2 BIT17 | ||
3497 | #define CLKGR0_UART1 BIT16 | ||
3498 | #define CLKGR0_UART0 BIT15 | ||
3499 | #define CLKGR0_SADC BIT14 | ||
3500 | #define CLKGR0_KBC BIT13 | ||
3501 | #define CLKGR0_MSC2 BIT12 | ||
3502 | #define CLKGR0_MSC1 BIT11 | ||
3503 | #define CLKGR0_OWI BIT10 | ||
3504 | #define CLKGR0_TSSI BIT9 | ||
3505 | #define CLKGR0_AIC BIT8 | ||
3506 | #define CLKGR0_SCC BIT7 | ||
3507 | #define CLKGR0_I2C1 BIT6 | ||
3508 | #define CLKGR0_I2C0 BIT5 | ||
3509 | #define CLKGR0_SSI0 BIT4 | ||
3510 | #define CLKGR0_MSC0 BIT3 | ||
3511 | #define CLKGR0_OTG BIT2 | ||
3512 | #define CLKGR0_BCH BIT1 | ||
3513 | #define CLKGR0_NEMC BIT0 | ||
3514 | |||
3515 | /* Oscillator and power control register(OPCR) */ | ||
3516 | #define OPCR_OTGPHY_ENABLE BIT7 /* SPENDN bit */ | ||
3517 | #define OPCR_GPSEN BIT6 | ||
3518 | #define OPCR_UHCPHY_DISABLE BIT5 /* SPENDH bit */ | ||
3519 | #define OPCR_O1SE BIT4 | ||
3520 | #define OPCR_PD BIT3 | ||
3521 | #define OPCR_ERCS BIT2 | ||
3522 | |||
3523 | #define OPCR_O1ST_LSB 8 | ||
3524 | #define OPCR_O1ST_MASK BITS_H2L(15, OPCR_O1ST_LSB) | ||
3525 | |||
3526 | /* Clock gate register 1(CGR1) */ | ||
3527 | #define CLKGR1_AUX BIT11 | ||
3528 | #define CLKGR1_OSD BIT10 | ||
3529 | #define CLKGR1_GPU BIT9 | ||
3530 | #define CLKGR1_PCM BIT8 | ||
3531 | #define CLKGR1_AHB1 BIT7 | ||
3532 | #define CLKGR1_CABAC BIT6 | ||
3533 | #define CLKGR1_SRAM BIT5 | ||
3534 | #define CLKGR1_DCT BIT4 | ||
3535 | #define CLKGR1_ME BIT3 | ||
3536 | #define CLKGR1_DBLK BIT2 | ||
3537 | #define CLKGR1_MC BIT1 | ||
3538 | #define CLKGR1_BDMA BIT0 | ||
3539 | |||
3540 | /* PLL control register 1(CPPCR1) */ | ||
3541 | #define CPPCR1_P1SCS BIT15 | ||
3542 | #define CPPCR1_PLL1EN BIT7 | ||
3543 | #define CPPCR1_PLL1S BIT6 | ||
3544 | #define CPPCR1_LOCK BIT2 /* LOCK1 bit */ | ||
3545 | #define CPPCR1_PLL1OFF BIT1 | ||
3546 | #define CPPCR1_PLL1ON BIT0 | ||
3547 | |||
3548 | #define CPPCR1_PLL1M_LSB 24 | ||
3549 | #define CPPCR1_PLL1M_MASK BITS_H2L(30, CPPCR1_PLL1M_LSB) | ||
3550 | |||
3551 | #define CPPCR1_PLL1N_LSB 18 | ||
3552 | #define CPPCR1_PLL1N_MASK BITS_H2L(21, CPPCR1_PLL1N_LSB) | ||
3553 | |||
3554 | #define CPPCR1_PLL1OD_LSB 16 | ||
3555 | #define CPPCR1_PLL1OD_MASK BITS_H2L(17, CPPCR1_PLL1OD_LSB) | ||
3556 | |||
3557 | #define CPPCR1_P1SDIV_LSB 9 | ||
3558 | #define CPPCR1_P1SDIV_MASK BITS_H2L(14, CPPCR1_P1SDIV_LSB) | ||
3559 | |||
3560 | /* CPM scratch pad protected register(CPSPPR) */ | ||
3561 | #define CPSPPR_CPSPR_WRITABLE (0x00005a5a) | ||
3562 | |||
3563 | /* OTG parameter control register(USBPCR) */ | ||
3564 | #define USBPCR_USB_MODE BIT31 | ||
3565 | #define USBPCR_AVLD_REG BIT30 | ||
3566 | #define USBPCR_INCRM BIT27 /* INCR_MASK bit */ | ||
3567 | #define USBPCR_CLK12_EN BIT26 | ||
3568 | #define USBPCR_COMMONONN BIT25 | ||
3569 | #define USBPCR_VBUSVLDEXT BIT24 | ||
3570 | #define USBPCR_VBUSVLDEXTSEL BIT23 | ||
3571 | #define USBPCR_POR BIT22 | ||
3572 | #define USBPCR_SIDDQ BIT21 | ||
3573 | #define USBPCR_OTG_DISABLE BIT20 | ||
3574 | #define USBPCR_TXPREEMPHTUNE BIT6 | ||
3575 | |||
3576 | #define USBPCR_IDPULLUP_LSB 28 /* IDPULLUP_MASK bit */ | ||
3577 | #define USBPCR_IDPULLUP_MASK BITS_H2L(29, USBPCR_USBPCR_IDPULLUP_LSB) | ||
3578 | |||
3579 | #define USBPCR_COMPDISTUNE_LSB 17 | ||
3580 | #define USBPCR_COMPDISTUNE_MASK BITS_H2L(19, USBPCR_COMPDISTUNE_LSB) | ||
3581 | |||
3582 | #define USBPCR_OTGTUNE_LSB 14 | ||
3583 | #define USBPCR_OTGTUNE_MASK BITS_H2L(16, USBPCR_OTGTUNE_LSB) | ||
3584 | |||
3585 | #define USBPCR_SQRXTUNE_LSB 11 | ||
3586 | #define USBPCR_SQRXTUNE_MASK BITS_H2L(13, USBPCR_SQRXTUNE_LSB) | ||
3587 | |||
3588 | #define USBPCR_TXFSLSTUNE_LSB 7 | ||
3589 | #define USBPCR_TXFSLSTUNE_MASK BITS_H2L(10, USBPCR_TXFSLSTUNE_LSB) | ||
3590 | |||
3591 | #define USBPCR_TXRISETUNE_LSB 4 | ||
3592 | #define USBPCR_TXRISETUNE_MASK BITS_H2L(5, USBPCR_TXRISETUNE_LSB) | ||
3593 | |||
3594 | #define USBPCR_TXVREFTUNE_LSB 0 | ||
3595 | #define USBPCR_TXVREFTUNE_MASK BITS_H2L(3, USBPCR_TXVREFTUNE_LSB) | ||
3596 | |||
3597 | /* OTG reset detect timer register(USBRDT) */ | ||
3598 | #define USBRDT_HB_MASK BIT26 | ||
3599 | #define USBRDT_VBFIL_LD_EN BIT25 | ||
3600 | #define USBRDT_IDDIG_EN BIT24 | ||
3601 | #define USBRDT_IDDIG_REG BIT23 | ||
3602 | |||
3603 | #define USBRDT_USBRDT_LSB 0 | ||
3604 | #define USBRDT_USBRDT_MASK BITS_H2L(22, USBRDT_USBRDT_LSB) | ||
3605 | |||
3606 | /* OTG PHY clock divider register(USBCDR) */ | ||
3607 | #define USBCDR_UCS BIT31 | ||
3608 | #define USBCDR_UPCS BIT30 | ||
3609 | |||
3610 | #define USBCDR_OTGDIV_LSB 0 /* USBCDR bit */ | ||
3611 | #define USBCDR_OTGDIV_MASK BITS_H2L(5, USBCDR_OTGDIV_LSB) | ||
3612 | |||
3613 | /* I2S device clock divider register(I2SCDR) */ | ||
3614 | #define I2SCDR_I2CS BIT31 | ||
3615 | #define I2SCDR_I2PCS BIT30 | ||
3616 | |||
3617 | #define I2SCDR_I2SDIV_LSB 0 /* I2SCDR bit */ | ||
3618 | #define I2SCDR_I2SDIV_MASK BITS_H2L(8, I2SCDR_I2SDIV_LSB) | ||
3619 | |||
3620 | /* LCD pix clock divider register(LPCDR) */ | ||
3621 | //#define LPCDR_LSCS BIT31 | ||
3622 | #define LPCDR_LTCS BIT30 | ||
3623 | #define LPCDR_LPCS BIT29 | ||
3624 | |||
3625 | #define LPCDR_PIXDIV_LSB 0 /* LPCDR bit */ | ||
3626 | #define LPCDR_PIXDIV_MASK BITS_H2L(10, LPCDR_PIXDIV_LSB) | ||
3627 | |||
3628 | /* MSC clock divider register(MSCCDR) */ | ||
3629 | #define MSCCDR_MCS BIT31 | ||
3630 | |||
3631 | #define MSCCDR_MSCDIV_LSB 0 /* MSCCDR bit */ | ||
3632 | #define MSCCDR_MSCDIV_MASK BITS_H2L(4, MSCCDR_MSCDIV_LSB) | ||
3633 | |||
3634 | /* UHC device clock divider register(UHCCDR) */ | ||
3635 | #define UHCCDR_UHPCS BIT31 | ||
3636 | |||
3637 | #define UHCCDR_UHCDIV_LSB 0 /* UHCCDR bit */ | ||
3638 | #define UHCCDR_UHCDIV_MASK BITS_H2L(3, UHCCDR_UHCDIV_LSB) | ||
3639 | |||
3640 | /* SSI clock divider register(SSICDR) */ | ||
3641 | #define SSICDR_SCS BIT31 | ||
3642 | |||
3643 | #define SSICDR_SSIDIV_LSB 0 /* SSICDR bit */ | ||
3644 | #define SSICDR_SSIDIV_MASK BITS_H2L(3, SSICDR_SSIDIV_LSB) | ||
3645 | |||
3646 | /* CIM mclk clock divider register(CIMCDR) */ | ||
3647 | #define CIMCDR_CIMDIV_LSB 0 /* CIMCDR bit */ | ||
3648 | #define CIMCDR_CIMDIV_MASK BITS_H2L(7, CIMCDR_CIMDIV_LSB) | ||
3649 | |||
3650 | /* GPS clock divider register(GPSCDR) */ | ||
3651 | #define GPSCDR_GPCS BIT31 | ||
3652 | |||
3653 | #define GPSCDR_GPSDIV_LSB 0 /* GPSCDR bit */ | ||
3654 | #define GSPCDR_GPSDIV_MASK BITS_H2L(3, GPSCDR_GPSDIV_LSB) | ||
3655 | |||
3656 | /* PCM device clock divider register(PCMCDR) */ | ||
3657 | #define PCMCDR_PCMS BIT31 | ||
3658 | #define PCMCDR_PCMPCS BIT30 | ||
3659 | |||
3660 | #define PCMCDR_PCMDIV_LSB 0 /* PCMCDR bit */ | ||
3661 | #define PCMCDR_PCMDIV_MASK BITS_H2L(8, PCMCDR_PCMDIV_LSB) | ||
3662 | |||
3663 | /* GPU clock divider register */ | ||
3664 | #define GPUCDR_GPCS BIT31 | ||
3665 | #define GPUCDR_GPUDIV_LSB 0 /* GPUCDR bit */ | ||
3666 | #define GPUCDR_GPUDIV_MASK BITS_H2L(2, GPUCDR_GPUDIV_LSB) | ||
3667 | |||
3668 | #ifndef __MIPS_ASSEMBLER | ||
3669 | |||
3670 | #define REG_CPM_CPCCR REG32(CPM_CPCCR) | ||
3671 | #define REG_CPM_RSR REG32(CPM_RSR) | ||
3672 | #define REG_CPM_CPPCR0 REG32(CPM_CPPCR0) | ||
3673 | #define REG_CPM_CPPSR REG32(CPM_CPPSR) | ||
3674 | #define REG_CPM_CPPCR1 REG32(CPM_CPPCR1) | ||
3675 | #define REG_CPM_CPSPR REG32(CPM_CPSPR) | ||
3676 | #define REG_CPM_CPSPPR REG32(CPM_CPSPPR) | ||
3677 | #define REG_CPM_USBPCR REG32(CPM_USBPCR) | ||
3678 | #define REG_CPM_USBRDT REG32(CPM_USBRDT) | ||
3679 | #define REG_CPM_USBVBFIL REG32(CPM_USBVBFIL) | ||
3680 | #define REG_CPM_USBCDR REG32(CPM_USBCDR) | ||
3681 | #define REG_CPM_I2SCDR REG32(CPM_I2SCDR) | ||
3682 | #define REG_CPM_LPCDR REG32(CPM_LPCDR) | ||
3683 | #define REG_CPM_MSCCDR REG32(CPM_MSCCDR) | ||
3684 | #define REG_CPM_UHCCDR REG32(CPM_UHCCDR) | ||
3685 | #define REG_CPM_SSICDR REG32(CPM_SSICDR) | ||
3686 | #define REG_CPM_CIMCDR REG32(CPM_CIMCDR) | ||
3687 | #define REG_CPM_GPSCDR REG32(CPM_GPSCDR) | ||
3688 | #define REG_CPM_PCMCDR REG32(CPM_PCMCDR) | ||
3689 | #define REG_CPM_GPUCDR REG32(CPM_GPUCDR) | ||
3690 | |||
3691 | #define REG_CPM_PSWC0ST REG32(CPM_PSWC0ST) | ||
3692 | #define REG_CPM_PSWC1ST REG32(CPM_PSWC1ST) | ||
3693 | #define REG_CPM_PSWC2ST REG32(CPM_PSWC2ST) | ||
3694 | #define REG_CPM_PSWC3ST REG32(CPM_PSWC3ST) | ||
3695 | |||
3696 | #define REG_CPM_LCR REG32(CPM_LCR) | ||
3697 | #define REG_CPM_CLKGR0 REG32(CPM_CLKGR0) | ||
3698 | #define REG_CPM_OPCR REG32(CPM_OPCR) | ||
3699 | #define REG_CPM_CLKGR1 REG32(CPM_CLKGR1) | ||
3700 | #define REG_CPM_CLKGR REG32(CPM_CLKGR0) | ||
3701 | |||
3702 | #define cpm_get_scrpad() INREG32(CPM_CPSPR) | ||
3703 | #define cpm_set_scrpad(data) \ | ||
3704 | do { \ | ||
3705 | OUTREG32(CPM_CPSPPR, CPSPPR_CPSPR_WRITABLE); \ | ||
3706 | OUTREG32(CPM_CPSPR, data); \ | ||
3707 | OUTREG32(CPM_CPSPPR, ~CPSPPR_CPSPR_WRITABLE); \ | ||
3708 | } while (0) | ||
3709 | |||
3710 | #define CPM_POWER_ON 1 | ||
3711 | #define CPM_POWER_OFF 0 | ||
3712 | |||
3713 | /*************************************************************************** | ||
3714 | * CPM * | ||
3715 | ***************************************************************************/ | ||
3716 | #define __cpm_get_pllm() \ | ||
3717 | ((REG_CPM_CPPCR0 & CPPCR0_PLLM_MASK) >> CPPCR0_PLLM_LSB) | ||
3718 | #define __cpm_get_plln() \ | ||
3719 | ((REG_CPM_CPPCR0 & CPPCR0_PLLN_MASK) >> CPPCR0_PLLN_LSB) | ||
3720 | #define __cpm_get_pllod() \ | ||
3721 | ((REG_CPM_CPPCR0 & CPPCR0_PLLOD_MASK) >> CPPCR0_PLLOD_LSB) | ||
3722 | |||
3723 | #define __cpm_get_pll1m() \ | ||
3724 | ((REG_CPM_CPPCR1 & CPPCR1_PLL1M_MASK) >> CPPCR1_PLL1M_LSB) | ||
3725 | #define __cpm_get_pll1n() \ | ||
3726 | ((REG_CPM_CPPCR1 & CPPCR1_PLL1N_MASK) >> CPPCR1_PLL1N_LSB) | ||
3727 | #define __cpm_get_pll1od() \ | ||
3728 | ((REG_CPM_CPPCR1 & CPPCR1_PLL1OD_MASK) >> CPPCR1_PLL1OD_LSB) | ||
3729 | |||
3730 | #define __cpm_get_cdiv() \ | ||
3731 | ((REG_CPM_CPCCR & CPCCR_CDIV_MASK) >> CPCCR_CDIV_LSB) | ||
3732 | #define __cpm_get_hdiv() \ | ||
3733 | ((REG_CPM_CPCCR & CPCCR_HDIV_MASK) >> CPCCR_HDIV_LSB) | ||
3734 | #define __cpm_get_h2div() \ | ||
3735 | ((REG_CPM_CPCCR & CPCCR_H2DIV_MASK) >> CPCCR_H2DIV_LSB) | ||
3736 | #define __cpm_get_pdiv() \ | ||
3737 | ((REG_CPM_CPCCR & CPCCR_PDIV_MASK) >> CPCCR_PDIV_LSB) | ||
3738 | #define __cpm_get_mdiv() \ | ||
3739 | ((REG_CPM_CPCCR & CPCCR_MDIV_MASK) >> CPCCR_MDIV_LSB) | ||
3740 | #define __cpm_get_sdiv() \ | ||
3741 | ((REG_CPM_CPCCR & CPCCR_SDIV_MASK) >> CPCCR_SDIV_LSB) | ||
3742 | #define __cpm_get_i2sdiv() \ | ||
3743 | ((REG_CPM_I2SCDR & I2SCDR_I2SDIV_MASK) >> I2SCDR_I2SDIV_LSB) | ||
3744 | #define __cpm_get_pixdiv() \ | ||
3745 | ((REG_CPM_LPCDR & LPCDR_PIXDIV_MASK) >> LPCDR_PIXDIV_LSB) | ||
3746 | #define __cpm_get_mscdiv() \ | ||
3747 | ((REG_CPM_MSCCDR & MSCCDR_MSCDIV_MASK) >> MSCCDR_MSCDIV_LSB) | ||
3748 | #define __cpm_get_ssidiv() \ | ||
3749 | ((REG_CPM_SSICCDR & SSICDR_SSICDIV_MASK) >> SSICDR_SSIDIV_LSB) | ||
3750 | #define __cpm_get_pcmdiv() \ | ||
3751 | ((REG_CPM_PCMCDR & PCMCDR_PCMCD_MASK) >> PCMCDR_PCMCD_LSB) | ||
3752 | #define __cpm_get_pll1div() \ | ||
3753 | ((REG_CPM_CPPCR1 & CPCCR1_P1SDIV_MASK) >> CPCCR1_P1SDIV_LSB) | ||
3754 | |||
3755 | #define __cpm_set_cdiv(v) \ | ||
3756 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPCCR_CDIV_MASK) | ((v) << (CPCCR_CDIV_LSB))) | ||
3757 | #define __cpm_set_hdiv(v) \ | ||
3758 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPCCR_HDIV_MASK) | ((v) << (CPCCR_HDIV_LSB))) | ||
3759 | #define __cpm_set_pdiv(v) \ | ||
3760 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPCCR_PDIV_MASK) | ((v) << (CPCCR_PDIV_LSB))) | ||
3761 | #define __cpm_set_mdiv(v) \ | ||
3762 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPCCR_MDIV_MASK) | ((v) << (CPCCR_MDIV_LSB))) | ||
3763 | #define __cpm_set_h1div(v) \ | ||
3764 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPCCR_H1DIV_MASK) | ((v) << (CPCCR_H1DIV_LSB))) | ||
3765 | #define __cpm_set_udiv(v) \ | ||
3766 | (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPCCR_UDIV_MASK) | ((v) << (CPCCR_UDIV_LSB))) | ||
3767 | #define __cpm_set_i2sdiv(v) \ | ||
3768 | (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~I2SCDR_I2SDIV_MASK) | ((v) << (I2SCDR_I2SDIV_LSB))) | ||
3769 | #define __cpm_set_pixdiv(v) \ | ||
3770 | (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~LPCDR_PIXDIV_MASK) | ((v) << (LPCDR_PIXDIV_LSB))) | ||
3771 | #define __cpm_set_mscdiv(v) \ | ||
3772 | (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~MSCCDR_MSCDIV_MASK) | ((v) << (MSCCDR_MSCDIV_LSB))) | ||
3773 | #define __cpm_set_ssidiv(v) \ | ||
3774 | (REG_CPM_SSICDR = (REG_CPM_SSICDR & ~SSICDR_SSIDIV_MASK) | ((v) << (SSICDR_SSIDIV_LSB))) | ||
3775 | #define __cpm_set_pcmdiv(v) \ | ||
3776 | (REG_CPM_PCMCDR = (REG_CPM_PCMCDR & ~PCMCDR_PCMCD_MASK) | ((v) << (PCMCDR_PCMCD_LSB))) | ||
3777 | #define __cpm_set_pll1div(v) \ | ||
3778 | (REG_CPM_CPPCR1 = (REG_CPM_CPPCR1 & ~CPCCR1_P1SDIV_MASK) | ((v) << (CPCCR1_P1SDIV_LSB))) | ||
3779 | |||
3780 | #define __cpm_select_i2sclk_pll1() (REG_CPM_I2SCDR |= I2SCDR_I2PCS) | ||
3781 | #define __cpm_select_i2sclk_pll0() (REG_CPM_I2SCDR &= ~I2SCDR_I2PCS) | ||
3782 | #define __cpm_select_otgclk_pll1() (REG_CPM_USBCDR |= USBCDR_UPCS) | ||
3783 | #define __cpm_select_otgclk_pll0() (REG_CPM_USBCDR &= ~USBCDR_UPCS) | ||
3784 | #define __cpm_select_lcdpclk_pll1() (REG_CPM_LPCDR |= LPCDR_LPCS) | ||
3785 | #define __cpm_select_lcdpclk_pll0() (REG_CPM_LPCDR &= ~LPCDR_LPCS) | ||
3786 | #define __cpm_select_uhcclk_pll1() (REG_CPM_UHCCDR |= UHCCDR_UHPCS) | ||
3787 | #define __cpm_select_uhcclk_pll0() (REG_CPM_UHCCDR &= ~UHCCDR_UHPCS) | ||
3788 | #define __cpm_select_gpsclk_pll1() (REG_CPM_GPSCDR |= GPSCDR_GPCS) | ||
3789 | #define __cpm_select_gpsclk_pll0() (REG_CPM_GPSCDR &= ~GPSCDR_GPCS) | ||
3790 | #define __cpm_select_pcmclk_pll1() (REG_CPM_PCMCDR |= PCMCDR_PCMPCS) | ||
3791 | #define __cpm_select_pcmclk_pll0() (REG_CPM_PCMCDR &= ~PCMCDR_PCMPCS) | ||
3792 | #define __cpm_select_gpuclk_pll1() (REG_CPM_GPUCDR |= GPUCDR_GPCS) | ||
3793 | #define __cpm_select_gpuclk_pll0() (REG_CPM_GPUCDR &= ~GPUCDR_GPCS) | ||
3794 | #define __cpm_select_clk_pll1() (REG_CPM_CDR |= CDR_PCS) | ||
3795 | #define __cpm_select_clk_pll0() (REG_CPM_CDR &= ~CDR_PCS) | ||
3796 | |||
3797 | |||
3798 | #define __cpm_select_pcmclk_pll() (REG_CPM_PCMCDR |= PCMCDR_PCMS) | ||
3799 | #define __cpm_select_pcmclk_exclk() (REG_CPM_PCMCDR &= ~PCMCDR_PCMS) | ||
3800 | #define __cpm_select_pixclk_ext() (REG_CPM_LPCDR |= LPCDR_LPCS) | ||
3801 | #define __cpm_select_pixclk_pll() (REG_CPM_LPCDR &= ~LPCDR_LPCS) | ||
3802 | #define __cpm_select_tveclk_exclk() (REG_CPM_LPCDR |= CPCCR_LSCS) | ||
3803 | #define __cpm_select_tveclk_pll() (REG_CPM_LPCDR &= ~LPCDR_LSCS) | ||
3804 | #define __cpm_select_pixclk_lcd() (REG_CPM_LPCDR &= ~LPCDR_LTCS) | ||
3805 | #define __cpm_select_pixclk_tve() (REG_CPM_LPCDR |= LPCDR_LTCS) | ||
3806 | #define __cpm_select_i2sclk_exclk() (REG_CPM_I2SCDR &= ~I2SCDR_I2CS) | ||
3807 | #define __cpm_select_i2sclk_pll() (REG_CPM_I2SCDR |= I2SCDR_I2CS) | ||
3808 | //#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPCCR_UCS) | ||
3809 | //#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPCCR_UCS) | ||
3810 | |||
3811 | #define __cpm_enable_cko() | ||
3812 | #define __cpm_exclk_direct() (REG_CPM_CPCCR &= ~CPCCR_ECS) | ||
3813 | #define __cpm_exclk_div2() (REG_CPM_CPCCR |= CPCCR_ECS) | ||
3814 | #define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPCCR_CE) | ||
3815 | |||
3816 | #define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPCCR_PCS) | ||
3817 | #define __cpm_pll_enable() (REG_CPM_CPPCR0 |= CPPCR0_PLLEN) | ||
3818 | |||
3819 | #define __cpm_pll1_enable() (REG_CPM_CPPCR1 |= CPPCR1_PLL1EN) | ||
3820 | |||
3821 | #define __cpm_pll_is_off() (REG_CPM_CPPSR & CPPSR_PLLOFF) | ||
3822 | #define __cpm_pll_is_on() (REG_CPM_CPPSR & CPPSR_PLLON) | ||
3823 | #define __cpm_pll_bypass() (REG_CPM_CPPSR |= CPPSR_PLLBP) | ||
3824 | |||
3825 | #define __cpm_get_cclk_doze_duty() \ | ||
3826 | ((REG_CPM_LCR & LCR_DOZE_DUTY_MASK) >> LCR_DOZE_DUTY_LSB) | ||
3827 | #define __cpm_set_cclk_doze_duty(v) \ | ||
3828 | (REG_CPM_LCR = (REG_CPM_LCR & ~LCR_DOZE_DUTY_MASK) | ((v) << (LCR_DOZE_DUTY_LSB))) | ||
3829 | |||
3830 | #define __cpm_doze_mode() (REG_CPM_LCR |= LCR_DOZE_ON) | ||
3831 | #define __cpm_idle_mode() \ | ||
3832 | (REG_CPM_LCR = (REG_CPM_LCR & ~LCR_LPM_MASK) | LCR_LPM_IDLE) | ||
3833 | #define __cpm_sleep_mode() \ | ||
3834 | (REG_CPM_LCR = (REG_CPM_LCR & ~LCR_LPM_MASK) | LCR_LPM_SLEEP) | ||
3835 | |||
3836 | #define __cpm_stop_all() \ | ||
3837 | do {\ | ||
3838 | (REG_CPM_CLKGR0 = 0xffffffff);\ | ||
3839 | (REG_CPM_CLKGR1 = 0x3ff);\ | ||
3840 | }while(0) | ||
3841 | #define __cpm_stop_emc() (REG_CPM_CLKGR0 |= CLKGR0_EMC) | ||
3842 | #define __cpm_stop_ddr() (REG_CPM_CLKGR0 |= CLKGR0_DDR) | ||
3843 | #define __cpm_stop_ipu() (REG_CPM_CLKGR0 |= CLKGR0_IPU) | ||
3844 | #define __cpm_stop_lcd() (REG_CPM_CLKGR0 |= CLKGR0_LCD) | ||
3845 | #define __cpm_stop_tve() (REG_CPM_CLKGR0 |= CLKGR0_TVE) | ||
3846 | #define __cpm_stop_Cim() (REG_CPM_CLKGR0 |= CLKGR0_CIM) | ||
3847 | #define __cpm_stop_mdma() (REG_CPM_CLKGR0 |= CLKGR0_MDMA) | ||
3848 | #define __cpm_stop_uhc() (REG_CPM_CLKGR0 |= CLKGR0_UHC) | ||
3849 | #define __cpm_stop_mac() (REG_CPM_CLKGR0 |= CLKGR0_MAC) | ||
3850 | #define __cpm_stop_gps() (REG_CPM_CLKGR0 |= CLKGR0_GPS) | ||
3851 | #define __cpm_stop_dmac() (REG_CPM_CLKGR0 |= CLKGR0_DMAC) | ||
3852 | #define __cpm_stop_ssi2() (REG_CPM_CLKGR0 |= CLKGR0_SSI2) | ||
3853 | #define __cpm_stop_ssi1() (REG_CPM_CLKGR0 |= CLKGR0_SSI1) | ||
3854 | #define __cpm_stop_uart3() (REG_CPM_CLKGR0 |= CLKGR0_UART3) | ||
3855 | #define __cpm_stop_uart2() (REG_CPM_CLKGR0 |= CLKGR0_UART2) | ||
3856 | #define __cpm_stop_uart1() (REG_CPM_CLKGR0 |= CLKGR0_UART1) | ||
3857 | #define __cpm_stop_uart0() (REG_CPM_CLKGR0 |= CLKGR0_UART0) | ||
3858 | #define __cpm_stop_sadc() (REG_CPM_CLKGR0 |= CLKGR0_SADC) | ||
3859 | #define __cpm_stop_kbc() (REG_CPM_CLKGR0 |= CLKGR0_KBC) | ||
3860 | #define __cpm_stop_msc2() (REG_CPM_CLKGR0 |= CLKGR0_MSC2) | ||
3861 | #define __cpm_stop_msc1() (REG_CPM_CLKGR0 |= CLKGR0_MSC1) | ||
3862 | #define __cpm_stop_owi() (REG_CPM_CLKGR0 |= CLKGR0_OWI) | ||
3863 | #define __cpm_stop_tssi() (REG_CPM_CLKGR0 |= CLKGR0_TSSI) | ||
3864 | #define __cpm_stop_aic() (REG_CPM_CLKGR0 |= CLKGR0_AIC) | ||
3865 | #define __cpm_stop_scc() (REG_CPM_CLKGR0 |= CLKGR0_SCC) | ||
3866 | #define __cpm_stop_i2c1() (REG_CPM_CLKGR0 |= CLKGR0_I2C1) | ||
3867 | #define __cpm_stop_i2c0() (REG_CPM_CLKGR0 |= CLKGR0_I2C0) | ||
3868 | #define __cpm_stop_ssi0() (REG_CPM_CLKGR0 |= CLKGR0_SSI0) | ||
3869 | #define __cpm_stop_msc0() (REG_CPM_CLKGR0 |= CLKGR0_MSC0) | ||
3870 | #define __cpm_stop_otg() (REG_CPM_CLKGR0 |= CLKGR0_OTG) | ||
3871 | #define __cpm_stop_bch() (REG_CPM_CLKGR0 |= CLKGR0_BCH) | ||
3872 | #define __cpm_stop_nemc() (REG_CPM_CLKGR0 |= CLKGR0_NEMC) | ||
3873 | #define __cpm_stop_gpu() (REG_CPM_CLKGR1 |= CLKGR1_GPU) | ||
3874 | #define __cpm_stop_pcm() (REG_CPM_CLKGR1 |= CLKGR1_PCM) | ||
3875 | #define __cpm_stop_ahb1() (REG_CPM_CLKGR1 |= CLKGR1_AHB1) | ||
3876 | #define __cpm_stop_cabac() (REG_CPM_CLKGR1 |= CLKGR1_CABAC) | ||
3877 | #define __cpm_stop_sram() (REG_CPM_CLKGR1 |= CLKGR1_SRAM) | ||
3878 | #define __cpm_stop_dct() (REG_CPM_CLKGR1 |= CLKGR1_DCT) | ||
3879 | #define __cpm_stop_me() (REG_CPM_CLKGR1 |= CLKGR1_ME) | ||
3880 | #define __cpm_stop_dblk() (REG_CPM_CLKGR1 |= CLKGR1_DBLK) | ||
3881 | #define __cpm_stop_mc() (REG_CPM_CLKGR1 |= CLKGR1_MC) | ||
3882 | #define __cpm_stop_bdma() (REG_CPM_CLKGR1 |= CLKGR1_BDMA) | ||
3883 | |||
3884 | #define __cpm_start_all() \ | ||
3885 | do {\ | ||
3886 | REG_CPM_CLKGR0 = 0x0;\ | ||
3887 | REG_CPM_CLKGR1 = 0x0;\ | ||
3888 | } while(0) | ||
3889 | #define __cpm_start_emc() (REG_CPM_CLKGR0 &= ~CLKGR0_EMC) | ||
3890 | #define __cpm_start_ddr() (REG_CPM_CLKGR0 &= ~CLKGR0_DDR) | ||
3891 | #define __cpm_start_ipu() (REG_CPM_CLKGR0 &= ~CLKGR0_IPU) | ||
3892 | #define __cpm_start_lcd() (REG_CPM_CLKGR0 &= ~CLKGR0_LCD) | ||
3893 | #define __cpm_start_tve() (REG_CPM_CLKGR0 &= ~CLKGR0_TVE) | ||
3894 | #define __cpm_start_Cim() (REG_CPM_CLKGR0 &= ~CLKGR0_CIM) | ||
3895 | #define __cpm_start_mdma() (REG_CPM_CLKGR0 &= ~CLKGR0_MDMA) | ||
3896 | #define __cpm_start_uhc() (REG_CPM_CLKGR0 &= ~CLKGR0_UHC) | ||
3897 | #define __cpm_start_mac() (REG_CPM_CLKGR0 &= ~CLKGR0_MAC) | ||
3898 | #define __cpm_start_gps() (REG_CPM_CLKGR0 &= ~CLKGR0_GPS) | ||
3899 | #define __cpm_start_dmac() (REG_CPM_CLKGR0 &= ~CLKGR0_DMAC) | ||
3900 | #define __cpm_start_ssi2() (REG_CPM_CLKGR0 &= ~CLKGR0_SSI2) | ||
3901 | #define __cpm_start_ssi1() (REG_CPM_CLKGR0 &= ~CLKGR0_SSI1) | ||
3902 | #define __cpm_start_uart3() (REG_CPM_CLKGR0 &= ~CLKGR0_UART3) | ||
3903 | #define __cpm_start_uart2() (REG_CPM_CLKGR0 &= ~CLKGR0_UART2) | ||
3904 | #define __cpm_start_uart1() (REG_CPM_CLKGR0 &= ~CLKGR0_UART1) | ||
3905 | #define __cpm_start_uart0() (REG_CPM_CLKGR0 &= ~CLKGR0_UART0) | ||
3906 | #define __cpm_start_sadc() (REG_CPM_CLKGR0 &= ~CLKGR0_SADC) | ||
3907 | #define __cpm_start_kbc() (REG_CPM_CLKGR0 &= ~CLKGR0_KBC) | ||
3908 | #define __cpm_start_msc2() (REG_CPM_CLKGR0 &= ~CLKGR0_MSC2) | ||
3909 | #define __cpm_start_msc1() (REG_CPM_CLKGR0 &= ~CLKGR0_MSC1) | ||
3910 | #define __cpm_start_owi() (REG_CPM_CLKGR0 &= ~CLKGR0_OWI) | ||
3911 | #define __cpm_start_tssi() (REG_CPM_CLKGR0 &= ~CLKGR0_TSSI) | ||
3912 | #define __cpm_start_aic() (REG_CPM_CLKGR0 &= ~CLKGR0_AIC) | ||
3913 | #define __cpm_start_scc() (REG_CPM_CLKGR0 &= ~CLKGR0_SCC) | ||
3914 | #define __cpm_start_i2c1() (REG_CPM_CLKGR0 &= ~CLKGR0_I2C1) | ||
3915 | #define __cpm_start_i2c0() (REG_CPM_CLKGR0 &= ~CLKGR0_I2C0) | ||
3916 | #define __cpm_start_ssi0() (REG_CPM_CLKGR0 &= ~CLKGR0_SSI0) | ||
3917 | #define __cpm_start_msc0() (REG_CPM_CLKGR0 &= ~CLKGR0_MSC0) | ||
3918 | #define __cpm_start_otg() (REG_CPM_CLKGR0 &= ~CLKGR0_OTG) | ||
3919 | #define __cpm_start_bch() (REG_CPM_CLKGR0 &= ~CLKGR0_BCH) | ||
3920 | #define __cpm_start_nemc() (REG_CPM_CLKGR0 &= ~CLKGR0_NEMC) | ||
3921 | #define __cpm_start_gpu() (REG_CPM_CLKGR1 &= ~CLKGR1_GPU) | ||
3922 | #define __cpm_start_pcm() (REG_CPM_CLKGR1 &= ~CLKGR1_PCM) | ||
3923 | #define __cpm_start_ahb1() (REG_CPM_CLKGR1 &= ~CLKGR1_AHB1) | ||
3924 | #define __cpm_start_cabac() (REG_CPM_CLKGR1 &= ~CLKGR1_CABAC) | ||
3925 | #define __cpm_start_sram() (REG_CPM_CLKGR1 &= ~CLKGR1_SRAM) | ||
3926 | #define __cpm_start_dct() (REG_CPM_CLKGR1 &= ~CLKGR1_DCT) | ||
3927 | #define __cpm_start_me() (REG_CPM_CLKGR1 &= ~CLKGR1_ME) | ||
3928 | #define __cpm_start_dblk() (REG_CPM_CLKGR1 &= ~CLKGR1_DBLK) | ||
3929 | #define __cpm_start_mc() (REG_CPM_CLKGR1 &= ~CLKGR1_MC) | ||
3930 | #define __cpm_start_bdma() (REG_CPM_CLKGR1 &= ~CLKGR1_BDMA) | ||
3931 | |||
3932 | #define __cpm_get_o1st() \ | ||
3933 | ((REG_CPM_OPCR & OPCR_O1ST_MASK) >> OPCR_O1ST_LSB) | ||
3934 | #define __cpm_set_o1st(v) \ | ||
3935 | (REG_CPM_OPCR = (REG_CPM_OPCR & ~OPCR_O1ST_MASK) | ((v) << (OPCR_O1ST_LSB))) | ||
3936 | #define __cpm_suspend_otgphy() (REG_CPM_OPCR &= ~OPCR_OTGPHY_ENABLE) | ||
3937 | #define __cpm_resume_otgphy() (REG_CPM_OPCR |= OPCR_OTGPHY_ENABLE) | ||
3938 | #define __cpm_enable_osc_in_sleep() (REG_CPM_OPCR |= OPCR_OSC_ENABLE) | ||
3939 | #define __cpm_select_rtcclk_rtc() (REG_CPM_OPCR |= OPCR_ERCS) | ||
3940 | #define __cpm_select_rtcclk_exclk() (REG_CPM_OPCR &= ~OPCR_ERCS) | ||
3941 | |||
3942 | #ifdef CFG_EXTAL | ||
3943 | #define JZ_EXTAL CFG_EXTAL | ||
3944 | #else | ||
3945 | #define JZ_EXTAL 12000000 | ||
3946 | #endif | ||
3947 | #define JZ_EXTAL2 32768 /* RTC clock */ | ||
3948 | |||
3949 | /* PLL output frequency */ | ||
3950 | static __inline__ unsigned int __cpm_get_pllout(void) | ||
3951 | { | ||
3952 | unsigned long m, n, no, pllout; | ||
3953 | unsigned long cppcr = REG_CPM_CPPCR0; | ||
3954 | unsigned long od[4] = {1, 2, 4, 8}; | ||
3955 | if ((cppcr & CPPCR0_PLLEN) && (!(cppcr & CPPCR0_PLLBP))) { | ||
3956 | m = __cpm_get_pllm() * 2; | ||
3957 | n = __cpm_get_plln(); | ||
3958 | no = od[__cpm_get_pllod()]; | ||
3959 | pllout = ((JZ_EXTAL) * m / (n * no)); | ||
3960 | } else | ||
3961 | pllout = JZ_EXTAL; | ||
3962 | return pllout; | ||
3963 | } | ||
3964 | |||
3965 | /* PLL output frequency */ | ||
3966 | static __inline__ unsigned int __cpm_get_pll1out(void) | ||
3967 | { | ||
3968 | unsigned long m, n, no, pllout; | ||
3969 | unsigned long cppcr1 = REG_CPM_CPPCR1; | ||
3970 | unsigned long od[4] = {1, 2, 4, 8}; | ||
3971 | if (cppcr1 & CPPCR1_PLL1EN) | ||
3972 | { | ||
3973 | m = __cpm_get_pll1m() * 2; | ||
3974 | n = __cpm_get_pll1n(); | ||
3975 | no = od[__cpm_get_pll1od()]; | ||
3976 | if (cppcr1 & CPPCR1_P1SCS) | ||
3977 | pllout = ((__cpm_get_pllout()) * m / (n * no)); | ||
3978 | else | ||
3979 | pllout = ((JZ_EXTAL) * m / (n * no)); | ||
3980 | |||
3981 | } else | ||
3982 | pllout = JZ_EXTAL; | ||
3983 | return pllout; | ||
3984 | } | ||
3985 | |||
3986 | /* PLL output frequency for MSC/I2S/LCD/USB */ | ||
3987 | static __inline__ unsigned int __cpm_get_pllout2(void) | ||
3988 | { | ||
3989 | if (REG_CPM_CPCCR & CPCCR_PCS) | ||
3990 | return __cpm_get_pllout(); | ||
3991 | else | ||
3992 | return __cpm_get_pllout()/2; | ||
3993 | } | ||
3994 | |||
3995 | /* CPU core clock */ | ||
3996 | static __inline__ unsigned int __cpm_get_cclk(void) | ||
3997 | { | ||
3998 | int div[] = {1, 2, 3, 4, 6, 8}; | ||
3999 | |||
4000 | return __cpm_get_pllout() / div[__cpm_get_cdiv()]; | ||
4001 | } | ||
4002 | |||
4003 | /* AHB system bus clock */ | ||
4004 | static __inline__ unsigned int __cpm_get_hclk(void) | ||
4005 | { | ||
4006 | int div[] = {1, 2, 3, 4, 6, 8}; | ||
4007 | |||
4008 | return __cpm_get_pllout() / div[__cpm_get_hdiv()]; | ||
4009 | } | ||
4010 | |||
4011 | /* Memory bus clock */ | ||
4012 | static __inline__ unsigned int __cpm_get_mclk(void) | ||
4013 | { | ||
4014 | int div[] = {1, 2, 3, 4, 6, 8}; | ||
4015 | |||
4016 | return __cpm_get_pllout() / div[__cpm_get_mdiv()]; | ||
4017 | } | ||
4018 | |||
4019 | /* APB peripheral bus clock */ | ||
4020 | static __inline__ unsigned int __cpm_get_pclk(void) | ||
4021 | { | ||
4022 | int div[] = {1, 2, 3, 4, 6, 8}; | ||
4023 | |||
4024 | return __cpm_get_pllout() / div[__cpm_get_pdiv()]; | ||
4025 | } | ||
4026 | |||
4027 | /* AHB1 module clock */ | ||
4028 | static __inline__ unsigned int __cpm_get_h2clk(void) | ||
4029 | { | ||
4030 | int div[] = {1, 2, 3, 4, 6, 8}; | ||
4031 | |||
4032 | return __cpm_get_pllout() / div[__cpm_get_h2div()]; | ||
4033 | } | ||
4034 | |||
4035 | /* LCD pixel clock */ | ||
4036 | static __inline__ unsigned int __cpm_get_pixclk(void) | ||
4037 | { | ||
4038 | return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1); | ||
4039 | } | ||
4040 | |||
4041 | /* I2S clock */ | ||
4042 | static __inline__ unsigned int __cpm_get_i2sclk(void) | ||
4043 | { | ||
4044 | if (REG_CPM_I2SCDR & I2SCDR_I2CS) { | ||
4045 | return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1); | ||
4046 | } | ||
4047 | else { | ||
4048 | return JZ_EXTAL; | ||
4049 | } | ||
4050 | } | ||
4051 | |||
4052 | /* USB clock */ | ||
4053 | /* | ||
4054 | static __inline__ unsigned int __cpm_get_usbclk(void) | ||
4055 | { | ||
4056 | if (REG_CPM_CPCCR & CPCCR_UCS) { | ||
4057 | return __cpm_get_pllout2() / (__cpm_get_udiv() + 1); | ||
4058 | } | ||
4059 | else { | ||
4060 | return JZ_EXTAL; | ||
4061 | } | ||
4062 | } | ||
4063 | */ | ||
4064 | /* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */ | ||
4065 | static __inline__ unsigned int __cpm_get_extalclk(void) | ||
4066 | { | ||
4067 | return JZ_EXTAL; | ||
4068 | } | ||
4069 | |||
4070 | /* RTC clock for CPM,INTC,RTC,TCU,WDT */ | ||
4071 | static __inline__ unsigned int __cpm_get_rtcclk(void) | ||
4072 | { | ||
4073 | return JZ_EXTAL2; | ||
4074 | } | ||
4075 | |||
4076 | /* | ||
4077 | * Output 24MHz for SD and 16MHz for MMC. | ||
4078 | */ | ||
4079 | static inline void __cpm_select_msc_clk(int sd) | ||
4080 | { | ||
4081 | unsigned int pllout2 = __cpm_get_pllout2(); | ||
4082 | unsigned int div = 0; | ||
4083 | |||
4084 | if (sd) { | ||
4085 | div = pllout2 / 24000000; | ||
4086 | } | ||
4087 | else { | ||
4088 | div = pllout2 / 16000000; | ||
4089 | } | ||
4090 | |||
4091 | REG_CPM_MSCCDR = (div - 1)|(1<<31); | ||
4092 | REG_CPM_CPCCR |= CPCCR_CE; | ||
4093 | } | ||
4094 | |||
4095 | #endif /* __MIPS_ASSEMBLER */ | ||
4096 | |||
4097 | #define DDRC_BASE 0xB3020000 | ||
4098 | |||
4099 | /************************************************************************* | ||
4100 | * DDRC (DDR Controller) | ||
4101 | *************************************************************************/ | ||
4102 | #define DDRC_ST (DDRC_BASE + 0x0) /* DDR Status Register */ | ||
4103 | #define DDRC_CFG (DDRC_BASE + 0x4) /* DDR Configure Register */ | ||
4104 | #define DDRC_CTRL (DDRC_BASE + 0x8) /* DDR Control Register */ | ||
4105 | #define DDRC_LMR (DDRC_BASE + 0xc) /* DDR Load-Mode-Register */ | ||
4106 | #define DDRC_TIMING1 (DDRC_BASE + 0x10) /* DDR Timing Config Register 1 */ | ||
4107 | #define DDRC_TIMING2 (DDRC_BASE + 0x14) /* DDR Timing Config Register 2 */ | ||
4108 | #define DDRC_REFCNT (DDRC_BASE + 0x18) /* DDR Auto-Refresh Counter */ | ||
4109 | #define DDRC_DQS (DDRC_BASE + 0x1c) /* DDR DQS Delay Control Register */ | ||
4110 | #define DDRC_DQS_ADJ (DDRC_BASE + 0x20) /* DDR DQS Delay Adjust Register */ | ||
4111 | #define DDRC_MMAP0 (DDRC_BASE + 0x24) /* DDR Memory Map Config Register */ | ||
4112 | #define DDRC_MMAP1 (DDRC_BASE + 0x28) /* DDR Memory Map Config Register */ | ||
4113 | #define DDRC_DDELAYCTRL1 (DDRC_BASE + 0x2c) | ||
4114 | #define DDRC_DDELAYCTRL2 (DDRC_BASE + 0x30) | ||
4115 | #define DDRC_DSTRB (DDRC_BASE + 0x34) | ||
4116 | #define DDRC_PMEMBS0 (DDRC_BASE + 0x50) | ||
4117 | #define DDRC_PMEMBS1 (DDRC_BASE + 0x54) | ||
4118 | #define DDRC_PMEMOSEL (DDRC_BASE + 0x58) | ||
4119 | #define DDRC_PMEMOEN (DDRC_BASE + 0x5c) | ||
4120 | |||
4121 | /* DDRC Register */ | ||
4122 | #define REG_DDRC_ST REG32(DDRC_ST) | ||
4123 | #define REG_DDRC_CFG REG32(DDRC_CFG) | ||
4124 | #define REG_DDRC_CTRL REG32(DDRC_CTRL) | ||
4125 | #define REG_DDRC_LMR REG32(DDRC_LMR) | ||
4126 | #define REG_DDRC_TIMING1 REG32(DDRC_TIMING1) | ||
4127 | #define REG_DDRC_TIMING2 REG32(DDRC_TIMING2) | ||
4128 | #define REG_DDRC_REFCNT REG32(DDRC_REFCNT) | ||
4129 | #define REG_DDRC_DQS REG32(DDRC_DQS) | ||
4130 | #define REG_DDRC_DQS_ADJ REG32(DDRC_DQS_ADJ) | ||
4131 | #define REG_DDRC_MMAP0 REG32(DDRC_MMAP0) | ||
4132 | #define REG_DDRC_MMAP1 REG32(DDRC_MMAP1) | ||
4133 | #define REG_DDRC_DDELAYCTRL1 REG32(DDRC_DDELAYCTRL1) | ||
4134 | #define REG_DDRC_DDELAYCTRL2 REG32(DDRC_DDELAYCTRL2) | ||
4135 | #define REG_DDRC_DSTRB REG32(DDRC_DSTRB) | ||
4136 | #define REG_DDRC_PMEMBS0 REG32(DDRC_PMEMBS0) | ||
4137 | #define REG_DDRC_PMEMBS1 REG32(DDRC_PMEMBS1) | ||
4138 | #define REG_DDRC_PMEMOSEL REG32(DDRC_PMEMOSEL) | ||
4139 | #define REG_DDRC_PMEMOEN REG32(DDRC_PMEMOEN) | ||
4140 | |||
4141 | /* DDRC Status Register */ | ||
4142 | #define DDRC_ST_ENDIAN (1 << 7) /* 0 Little data endian | ||
4143 | 1 Big data endian */ | ||
4144 | #define DDRC_ST_MISS (1 << 6) | ||
4145 | |||
4146 | #define DDRC_ST_DPDN (1 << 5) /* 0 DDR memory is NOT in deep-power-down state | ||
4147 | 1 DDR memory is in deep-power-down state */ | ||
4148 | #define DDRC_ST_PDN (1 << 4) /* 0 DDR memory is NOT in power-down state | ||
4149 | 1 DDR memory is in power-down state */ | ||
4150 | #define DDRC_ST_AREF (1 << 3) /* 0 DDR memory is NOT in auto-refresh state | ||
4151 | 1 DDR memory is in auto-refresh state */ | ||
4152 | #define DDRC_ST_SREF (1 << 2) /* 0 DDR memory is NOT in self-refresh state | ||
4153 | 1 DDR memory is in self-refresh state */ | ||
4154 | #define DDRC_ST_CKE1 (1 << 1) /* 0 CKE1 Pin is low | ||
4155 | 1 CKE1 Pin is high */ | ||
4156 | #define DDRC_ST_CKE0 (1 << 0) /* 0 CKE0 Pin is low | ||
4157 | 1 CKE0 Pin is high */ | ||
4158 | |||
4159 | /* DDRC Configure Register */ | ||
4160 | #define DDRC_CFG_RDPRI (1 << 29) | ||
4161 | #define DDRC_CFG_ROW1_BIT 27 /* Row Address width. */ | ||
4162 | #define DDRC_CFG_COL1_BIT 25 /* Row Address width. */ | ||
4163 | #define DDRC_CFG_BA1 (1 << 24) | ||
4164 | #define DDRC_CFG_IMBA (1 << 23) | ||
4165 | #define DDRC_CFG_DQSMD (1 << 22) | ||
4166 | #define DDRC_CFG_BTRUN (1 << 21) | ||
4167 | |||
4168 | #define DDRC_CFG_MISPE (1 << 15) | ||
4169 | |||
4170 | #define DDRC_CFG_TYPE_BIT 12 | ||
4171 | #define DDRC_CFG_TYPE_MASK (0x7 << DDRC_CFG_TYPE_BIT) | ||
4172 | #define DDRC_CFG_TYPE_DDR1 (2 << DDRC_CFG_TYPE_BIT) | ||
4173 | #define DDRC_CFG_TYPE_MDDR (3 << DDRC_CFG_TYPE_BIT) | ||
4174 | #define DDRC_CFG_TYPE_DDR2 (4 << DDRC_CFG_TYPE_BIT) | ||
4175 | |||
4176 | #define DDRC_CFG_ROW_BIT 10 /* Row Address width. */ | ||
4177 | #define DDRC_CFG_ROW_MASK (0x3 << DDRC_CFG_ROW_BIT) | ||
4178 | #define DDRC_CFG_ROW_12 (0 << DDRC_CFG_ROW_BIT) /* 12-bit row address is used */ | ||
4179 | #define DDRC_CFG_ROW_13 (1 << DDRC_CFG_ROW_BIT) /* 13-bit row address is used */ | ||
4180 | #define DDRC_CFG_ROW_14 (2 << DDRC_CFG_ROW_BIT) /* 14-bit row address is used */ | ||
4181 | |||
4182 | #define DDRC_CFG_COL_BIT 8 /* Column Address width. | ||
4183 | Specify the Column address width of external DDR. */ | ||
4184 | #define DDRC_CFG_COL_MASK (0x3 << DDRC_CFG_COL_BIT) | ||
4185 | #define DDRC_CFG_COL_8 (0 << DDRC_CFG_COL_BIT) /* 8-bit Column address is used */ | ||
4186 | #define DDRC_CFG_COL_9 (1 << DDRC_CFG_COL_BIT) /* 9-bit Column address is used */ | ||
4187 | #define DDRC_CFG_COL_10 (2 << DDRC_CFG_COL_BIT) /* 10-bit Column address is used */ | ||
4188 | #define DDRC_CFG_COL_11 (3 << DDRC_CFG_COL_BIT) /* 11-bit Column address is used */ | ||
4189 | |||
4190 | #define DDRC_CFG_CS1EN (1 << 7) /* 0 DDR Pin CS1 un-used | ||
4191 | 1 There're DDR memory connected to CS1 */ | ||
4192 | #define DDRC_CFG_CS0EN (1 << 6) /* 0 DDR Pin CS0 un-used | ||
4193 | 1 There're DDR memory connected to CS0 */ | ||
4194 | |||
4195 | #define DDRC_CFG_CL_BIT 2 /* CAS Latency */ | ||
4196 | #define DDRC_CFG_CL_MASK (0xf << DDRC_CFG_CL_BIT) | ||
4197 | #define DDRC_CFG_CL_3 (0x0a << DDRC_CFG_CL_BIT) /* CL = 3 tCK */ | ||
4198 | #define DDRC_CFG_CL_4 (0x0b << DDRC_CFG_CL_BIT) /* CL = 4 tCK */ | ||
4199 | #define DDRC_CFG_CL_5 (0x0c << DDRC_CFG_CL_BIT) /* CL = 5 tCK */ | ||
4200 | #define DDRC_CFG_CL_6 (0x0d << DDRC_CFG_CL_BIT) /* CL = 6 tCK */ | ||
4201 | #define DDRC_CFG_CL_7 (0x0e << DDRC_CFG_CL_BIT) /* CL = 7 tCK */ | ||
4202 | |||
4203 | #define DDRC_CFG_BA (1 << 1) /* 0 4 bank device, Pin ba[1:0] valid, ba[2] un-used | ||
4204 | 1 8 bank device, Pin ba[2:0] valid*/ | ||
4205 | #define DDRC_CFG_DW (1 << 0) /*0 External memory data width is 16-bit | ||
4206 | 1 External memory data width is 32-bit */ | ||
4207 | |||
4208 | /* DDRC Control Register */ | ||
4209 | #define DDRC_CTRL_ACTPD (1 << 15) /* 0 Precharge all banks before entering power-down | ||
4210 | 1 Do not precharge banks before entering power-down */ | ||
4211 | #define DDRC_CTRL_PDT_BIT 12 /* Power-Down Timer */ | ||
4212 | #define DDRC_CTRL_PDT_MASK (0x7 << DDRC_CTRL_PDT_BIT) | ||
4213 | #define DDRC_CTRL_PDT_DIS (0 << DDRC_CTRL_PDT_BIT) /* power-down disabled */ | ||
4214 | #define DDRC_CTRL_PDT_8 (1 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 8 tCK idle */ | ||
4215 | #define DDRC_CTRL_PDT_16 (2 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 16 tCK idle */ | ||
4216 | #define DDRC_CTRL_PDT_32 (3 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 32 tCK idle */ | ||
4217 | #define DDRC_CTRL_PDT_64 (4 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 64 tCK idle */ | ||
4218 | #define DDRC_CTRL_PDT_128 (5 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 128 tCK idle */ | ||
4219 | |||
4220 | #define DDRC_CTRL_PRET_BIT 8 /* Precharge Timer */ | ||
4221 | #define DDRC_CTRL_PRET_MASK (0x7 << DDRC_CTRL_PRET_BIT) /* */ | ||
4222 | #define DDRC_CTRL_PRET_DIS (0 << DDRC_CTRL_PRET_BIT) /* PRET function Disabled */ | ||
4223 | #define DDRC_CTRL_PRET_8 (1 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 8 tCK idle */ | ||
4224 | #define DDRC_CTRL_PRET_16 (2 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 16 tCK idle */ | ||
4225 | #define DDRC_CTRL_PRET_32 (3 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 32 tCK idle */ | ||
4226 | #define DDRC_CTRL_PRET_64 (4 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 64 tCK idle */ | ||
4227 | #define DDRC_CTRL_PRET_128 (5 << DDRC_CTRL_PRET_BIT) /* Precharge active bank after 128 tCK idle */ | ||
4228 | |||
4229 | #define DDRC_CTRL_SR (1 << 5) /* 1 Drive external DDR device entering self-refresh mode | ||
4230 | 0 Drive external DDR device exiting self-refresh mode */ | ||
4231 | #define DDRC_CTRL_UNALIGN (1 << 4) /* 0 Disable unaligned transfer on AXI BUS | ||
4232 | 1 Enable unaligned transfer on AXI BUS */ | ||
4233 | #define DDRC_CTRL_ALH (1 << 3) /* Advanced Latency Hiding: | ||
4234 | 0 Disable ALH | ||
4235 | 1 Enable ALH */ | ||
4236 | #define DDRC_CTRL_CKE (1 << 1) /* 0 Not set CKE Pin High | ||
4237 | 1 Set CKE Pin HIGH */ | ||
4238 | #define DDRC_CTRL_RESET (1 << 0) /* 0 End resetting ddrc_controller | ||
4239 | 1 Resetting ddrc_controller */ | ||
4240 | |||
4241 | /* DDRC Load-Mode-Register */ | ||
4242 | #define DDRC_LMR_DDR_ADDR_BIT 16 /* When performing a DDR command, DDRC_ADDR[13:0] | ||
4243 | corresponding to external DDR address Pin A[13:0] */ | ||
4244 | #define DDRC_LMR_DDR_ADDR_MASK (0x3fff << DDRC_LMR_DDR_ADDR_BIT) | ||
4245 | |||
4246 | #define DDRC_LMR_BA_BIT 8 /* When performing a DDR command, BA[2:0] | ||
4247 | corresponding to external DDR address Pin BA[2:0]. */ | ||
4248 | #define DDRC_LMR_BA_MASK (0x7 << DDRC_LMR_BA_BIT) | ||
4249 | /* For DDR2 */ | ||
4250 | #define DDRC_LMR_BA_MRS (0 << DDRC_LMR_BA_BIT) /* Mode Register set */ | ||
4251 | #define DDRC_LMR_BA_EMRS1 (1 << DDRC_LMR_BA_BIT) /* Extended Mode Register1 set */ | ||
4252 | #define DDRC_LMR_BA_EMRS2 (2 << DDRC_LMR_BA_BIT) /* Extended Mode Register2 set */ | ||
4253 | #define DDRC_LMR_BA_EMRS3 (3 << DDRC_LMR_BA_BIT) /* Extended Mode Register3 set */ | ||
4254 | /* For mobile DDR */ | ||
4255 | #define DDRC_LMR_BA_M_MRS (0 << DDRC_LMR_BA_BIT) /* Mode Register set */ | ||
4256 | #define DDRC_LMR_BA_M_EMRS (2 << DDRC_LMR_BA_BIT) /* Extended Mode Register set */ | ||
4257 | #define DDRC_LMR_BA_M_SR (1 << DDRC_LMR_BA_BIT) /* Status Register set */ | ||
4258 | |||
4259 | #define DDRC_LMR_CMD_BIT 4 | ||
4260 | #define DDRC_LMR_CMD_MASK (0x3 << DDRC_LMR_CMD_BIT) | ||
4261 | #define DDRC_LMR_CMD_PREC (0 << DDRC_LMR_CMD_BIT)/* Precharge one bank/All banks */ | ||
4262 | #define DDRC_LMR_CMD_AUREF (1 << DDRC_LMR_CMD_BIT)/* Auto-Refresh */ | ||
4263 | #define DDRC_LMR_CMD_LMR (2 << DDRC_LMR_CMD_BIT)/* Load Mode Register */ | ||
4264 | |||
4265 | #define DDRC_LMR_START (1 << 0) /* 0 No command is performed | ||
4266 | 1 On the posedge of START, perform a command | ||
4267 | defined by CMD field */ | ||
4268 | /* DDRC Mode Register Set */ | ||
4269 | #define DDR_MRS_PD_BIT (1 << 10) /* Active power down exit time */ | ||
4270 | #define DDR_MRS_PD_MASK (1 << DDR_MRS_PD_BIT) | ||
4271 | #define DDR_MRS_PD_FAST_EXIT (0 << 10) | ||
4272 | #define DDR_MRS_PD_SLOW_EXIT (1 << 10) | ||
4273 | #define DDR_MRS_WR_BIT (1 << 9) /* Write Recovery for autoprecharge */ | ||
4274 | #define DDR_MRS_WR_MASK (7 << DDR_MRS_WR_BIT) | ||
4275 | #define DDR_MRS_DLL_RST (1 << 8) /* DLL Reset */ | ||
4276 | #define DDR_MRS_TM_BIT 7 /* Operating Mode */ | ||
4277 | #define DDR_MRS_TM_MASK (1 << DDR_MRS_OM_BIT) | ||
4278 | #define DDR_MRS_TM_NORMAL (0 << DDR_MRS_OM_BIT) | ||
4279 | #define DDR_MRS_TM_TEST (1 << DDR_MRS_OM_BIT) | ||
4280 | #define DDR_MRS_CAS_BIT 4 /* CAS Latency */ | ||
4281 | #define DDR_MRS_CAS_MASK (7 << DDR_MRS_CAS_BIT) | ||
4282 | #define DDR_MRS_BT_BIT 3 /* Burst Type */ | ||
4283 | #define DDR_MRS_BT_MASK (1 << DDR_MRS_BT_BIT) | ||
4284 | #define DDR_MRS_BT_SEQ (0 << DDR_MRS_BT_BIT) /* Sequential */ | ||
4285 | #define DDR_MRS_BT_INT (1 << DDR_MRS_BT_BIT) /* Interleave */ | ||
4286 | #define DDR_MRS_BL_BIT 0 /* Burst Length */ | ||
4287 | #define DDR_MRS_BL_MASK (7 << DDR_MRS_BL_BIT) | ||
4288 | #define DDR_MRS_BL_4 (2 << DDR_MRS_BL_BIT) | ||
4289 | #define DDR_MRS_BL_8 (3 << DDR_MRS_BL_BIT) | ||
4290 | |||
4291 | /* DDRC Extended Mode Register1 Set */ | ||
4292 | #define DDR_EMRS1_QOFF (1<<12) /* 0 Output buffer enabled | ||
4293 | 1 Output buffer disabled */ | ||
4294 | #define DDR_EMRS1_RDQS_EN (1<<11) /* 0 Disable | ||
4295 | 1 Enable */ | ||
4296 | #define DDR_EMRS1_DQS_DIS (1<<10) /* 0 Enable | ||
4297 | 1 Disable */ | ||
4298 | #define DDR_EMRS1_OCD_BIT 7 /* Additive Latency 0 -> 6 */ | ||
4299 | #define DDR_EMRS1_OCD_MASK (0x7 << DDR_EMRS1_OCD_BIT) | ||
4300 | #define DDR_EMRS1_OCD_EXIT (0 << DDR_EMRS1_OCD_BIT) | ||
4301 | #define DDR_EMRS1_OCD_D0 (1 << DDR_EMRS1_OCD_BIT) | ||
4302 | #define DDR_EMRS1_OCD_D1 (2 << DDR_EMRS1_OCD_BIT) | ||
4303 | #define DDR_EMRS1_OCD_ADJ (4 << DDR_EMRS1_OCD_BIT) | ||
4304 | #define DDR_EMRS1_OCD_DFLT (7 << DDR_EMRS1_OCD_BIT) | ||
4305 | #define DDR_EMRS1_AL_BIT 3 /* Additive Latency 0 -> 6 */ | ||
4306 | #define DDR_EMRS1_AL_MASK (7 << DDR_EMRS1_AL_BIT) | ||
4307 | #define DDR_EMRS1_RTT_BIT 2 /* */ | ||
4308 | #define DDR_EMRS1_RTT_MASK (0x11 << DDR_EMRS1_DIC_BIT) /* Bit 6, Bit 2 */ | ||
4309 | #define DDR_EMRS1_DIC_BIT 1 /* Output Driver Impedence Control */ | ||
4310 | #define DDR_EMRS1_DIC_MASK (1 << DDR_EMRS1_DIC_BIT) /* 100% */ | ||
4311 | #define DDR_EMRS1_DIC_NORMAL (0 << DDR_EMRS1_DIC_BIT) /* 60% */ | ||
4312 | #define DDR_EMRS1_DIC_HALF (1 << DDR_EMRS1_DIC_BIT) | ||
4313 | #define DDR_EMRS1_DLL_BIT 0 /* DLL Enable */ | ||
4314 | #define DDR_EMRS1_DLL_MASK (1 << DDR_EMRS1_DLL_BIT) | ||
4315 | #define DDR_EMRS1_DLL_EN (0 << DDR_EMRS1_DLL_BIT) | ||
4316 | #define DDR_EMRS1_DLL_DIS (1 << DDR_EMRS1_DLL_BIT) | ||
4317 | |||
4318 | /* Mobile SDRAM Extended Mode Register */ | ||
4319 | #define DDR_EMRS_DS_BIT 5 /* Driver strength */ | ||
4320 | #define DDR_EMRS_DS_MASK (7 << DDR_EMRS_DS_BIT) | ||
4321 | #define DDR_EMRS_DS_FULL (0 << DDR_EMRS_DS_BIT) /*Full*/ | ||
4322 | #define DDR_EMRS_DS_HALF (1 << DDR_EMRS_DS_BIT) /*1/2 Strength*/ | ||
4323 | #define DDR_EMRS_DS_QUTR (2 << DDR_EMRS_DS_BIT) /*1/4 Strength*/ | ||
4324 | #define DDR_EMRS_DS_OCTANT (3 << DDR_EMRS_DS_BIT) /*1/8 Strength*/ | ||
4325 | #define DDR_EMRS_DS_QUTR3 (4 << DDR_EMRS_DS_BIT) /*3/4 Strength*/ | ||
4326 | |||
4327 | #define DDR_EMRS_PRSR_BIT 0 /* Partial Array Self Refresh */ | ||
4328 | #define DDR_EMRS_PRSR_MASK (7 << DDR_EMRS_PRSR_BIT) | ||
4329 | #define DDR_EMRS_PRSR_ALL (0 << DDR_EMRS_PRSR_BIT) /*All Banks*/ | ||
4330 | #define DDR_EMRS_PRSR_HALF_TL (1 << DDR_EMRS_PRSR_BIT) /*Half of Total Bank*/ | ||
4331 | #define DDR_EMRS_PRSR_QUTR_TL (2 << DDR_EMRS_PRSR_BIT) /*Quarter of Total Bank*/ | ||
4332 | #define DDR_EMRS_PRSR_HALF_B0 (5 << DDR_EMRS_PRSR_BIT) /*Half of Bank0*/ | ||
4333 | #define DDR_EMRS_PRSR_QUTR_B0 (6 << DDR_EMRS_PRSR_BIT) /*Quarter of Bank0*/ | ||
4334 | |||
4335 | /* DDRC Timing Config Register 1 */ | ||
4336 | #define DDRC_TIMING1_TRAS_BIT 28 /* ACTIVE to PRECHARGE command period (2 * tRAS + 1) */ | ||
4337 | #define DDRC_TIMING1_TRAS_MASK (0xf << DDRC_TIMING1_TRAS_BIT) | ||
4338 | |||
4339 | #define DDRC_TIMING1_TRTP_BIT 24 /* READ to PRECHARGE command period. */ | ||
4340 | #define DDRC_TIMING1_TRTP_MASK (0x3 << DDRC_TIMING1_TRTP_BIT) | ||
4341 | |||
4342 | #define DDRC_TIMING1_TRP_BIT 20 /* PRECHARGE command period. */ | ||
4343 | #define DDRC_TIMING1_TRP_MASK (0x7 << DDRC_TIMING1_TRP_BIT) | ||
4344 | |||
4345 | #define DDRC_TIMING1_TRCD_BIT 16 /* ACTIVE to READ or WRITE command period. */ | ||
4346 | #define DDRC_TIMING1_TRCD_MASK (0x7 << DDRC_TIMING1_TRCD_BIT) | ||
4347 | |||
4348 | #define DDRC_TIMING1_TRC_BIT 12 /* ACTIVE to ACTIVE command period. */ | ||
4349 | #define DDRC_TIMING1_TRC_MASK (0xf << DDRC_TIMING1_TRC_BIT) | ||
4350 | |||
4351 | #define DDRC_TIMING1_TRRD_BIT 8 /* ACTIVE bank A to ACTIVE bank B command period. */ | ||
4352 | #define DDRC_TIMING1_TRRD_MASK (0x3 << DDRC_TIMING1_TRRD_BIT) | ||
4353 | #define DDRC_TIMING1_TRRD_DISABLE (0 << DDRC_TIMING1_TRRD_BIT) | ||
4354 | #define DDRC_TIMING1_TRRD_2 (1 << DDRC_TIMING1_TRRD_BIT) | ||
4355 | #define DDRC_TIMING1_TRRD_3 (2 << DDRC_TIMING1_TRRD_BIT) | ||
4356 | #define DDRC_TIMING1_TRRD_4 (3 << DDRC_TIMING1_TRRD_BIT) | ||
4357 | |||
4358 | #define DDRC_TIMING1_TWR_BIT 4 /* WRITE Recovery Time defined by register MR of DDR2 memory */ | ||
4359 | #define DDRC_TIMING1_TWR_MASK (0x7 << DDRC_TIMING1_TWR_BIT) | ||
4360 | #define DDRC_TIMING1_TWR_1 (0 << DDRC_TIMING1_TWR_BIT) | ||
4361 | #define DDRC_TIMING1_TWR_2 (1 << DDRC_TIMING1_TWR_BIT) | ||
4362 | #define DDRC_TIMING1_TWR_3 (2 << DDRC_TIMING1_TWR_BIT) | ||
4363 | #define DDRC_TIMING1_TWR_4 (3 << DDRC_TIMING1_TWR_BIT) | ||
4364 | #define DDRC_TIMING1_TWR_5 (4 << DDRC_TIMING1_TWR_BIT) | ||
4365 | #define DDRC_TIMING1_TWR_6 (5 << DDRC_TIMING1_TWR_BIT) | ||
4366 | |||
4367 | #define DDRC_TIMING1_TWTR_BIT 0 /* WRITE to READ command delay. */ | ||
4368 | #define DDRC_TIMING1_TWTR_MASK (0x3 << DDRC_TIMING1_TWTR_BIT) | ||
4369 | #define DDRC_TIMING1_TWTR_1 (0 << DDRC_TIMING1_TWTR_BIT) | ||
4370 | #define DDRC_TIMING1_TWTR_2 (1 << DDRC_TIMING1_TWTR_BIT) | ||
4371 | #define DDRC_TIMING1_TWTR_3 (2 << DDRC_TIMING1_TWTR_BIT) | ||
4372 | #define DDRC_TIMING1_TWTR_4 (3 << DDRC_TIMING1_TWTR_BIT) | ||
4373 | |||
4374 | /* DDRC Timing Config Register 2 */ | ||
4375 | #define DDRC_TIMING2_TRFC_BIT 24 /* AUTO-REFRESH command period. */ | ||
4376 | #define DDRC_TIMING2_TRFC_MASK (0xf << DDRC_TIMING2_TRFC_BIT) | ||
4377 | #define DDRC_TIMING2_RWCOV_BIT 19 /* Equal to Tsel of MDELAY. */ | ||
4378 | #define DDRC_TIMING2_RWCOV_MASK (0x3 << DDRC_TIMING2_RWCOV_BIT) | ||
4379 | #define DDRC_TIMING2_TCKE_BIT 16 | ||
4380 | #define DDRC_TIMING2_TCKE_MASK (0x7 << DDRC_TIMING2_TCKE_BIT) | ||
4381 | #define DDRC_TIMING2_TMINSR_BIT 8 /* Minimum Self-Refresh / Deep-Power-Down time */ | ||
4382 | #define DDRC_TIMING2_TMINSR_MASK (0xf << DDRC_TIMING2_TMINSR_BIT) | ||
4383 | #define DDRC_TIMING2_TXP_BIT 4 /* EXIT-POWER-DOWN to next valid command period. */ | ||
4384 | #define DDRC_TIMING2_TXP_MASK (0x7 << DDRC_TIMING2_TXP_BIT) | ||
4385 | #define DDRC_TIMING2_TMRD_BIT 0 /* Load-Mode-Register to next valid command period. */ | ||
4386 | #define DDRC_TIMING2_TMRD_MASK (0x3 << DDRC_TIMING2_TMRD_BIT) | ||
4387 | |||
4388 | /* DDRC Auto-Refresh Counter */ | ||
4389 | #define DDRC_REFCNT_CON_BIT 16 /* Constant value used to compare with CNT value. */ | ||
4390 | #define DDRC_REFCNT_CON_MASK (0xff << DDRC_REFCNT_CON_BIT) | ||
4391 | #define DDRC_REFCNT_CNT_BIT 8 /* 8-bit counter */ | ||
4392 | #define DDRC_REFCNT_CNT_MASK (0xff << DDRC_REFCNT_CNT_BIT) | ||
4393 | #define DDRC_REFCNT_CLKDIV_BIT 1 /* Clock Divider for auto-refresh counter. */ | ||
4394 | #define DDRC_REFCNT_CLKDIV_MASK (0x7 << DDRC_REFCNT_CLKDIV_BIT) | ||
4395 | #define DDRC_REFCNT_REF_EN (1 << 0) /* Enable Refresh Counter */ | ||
4396 | |||
4397 | /* DDRC DQS Delay Control Register */ | ||
4398 | #define DDRC_DQS_ERROR (1 << 29) /* ahb_clk Delay Detect ERROR, read-only. */ | ||
4399 | #define DDRC_DQS_READY (1 << 28) /* ahb_clk Delay Detect READY, read-only. */ | ||
4400 | #define DDRC_DQS_SRDET (1 << 25) | ||
4401 | #define DDRC_DQS_DET (1 << 24) /* Start delay detecting. */ | ||
4402 | #define DDRC_DQS_AUTO (1 << 23) /* Hardware auto-detect & set delay line */ | ||
4403 | #define DDRC_DQS_CLKD_BIT 16 /* CLKD is reference value for setting WDQS and RDQS.*/ | ||
4404 | #define DDRC_DQS_CLKD_MASK (0x3f << DDRC_DQS_CLKD_BIT) | ||
4405 | #define DDRC_DQS_WDQS_BIT 8 /* Set delay element number to write DQS delay-line. */ | ||
4406 | #define DDRC_DQS_WDQS_MASK (0x3f << DDRC_DQS_WDQS_BIT) | ||
4407 | #define DDRC_DQS_RDQS_BIT 0 /* Set delay element number to read DQS delay-line. */ | ||
4408 | #define DDRC_DQS_RDQS_MASK (0x3f << DDRC_DQS_RDQS_BIT) | ||
4409 | |||
4410 | /* DDRC DQS Delay Adjust Register */ | ||
4411 | #define DDRC_DQS_ADJDQSCON_BIT 16 | ||
4412 | #define DDRC_DQS_ADJDQSCON_MASK (0xffff << DDRC_DQS_ADJDQSCON_BIT) | ||
4413 | #define DDRC_DQS_ADJWSIGN (1 << 13) | ||
4414 | #define DDRC_DQS_ADJWDQS_BIT 8 /* The adjust value for WRITE DQS delay */ | ||
4415 | #define DDRC_DQS_ADJWDQS_MASK (0x1f << DDRC_DQS_ADJWDQS_BIT) | ||
4416 | #define DDRC_DQS_ADJRSIGN (1 << 5) | ||
4417 | #define DDRC_DQS_ADJRDQS_BIT 0 /* The adjust value for READ DQS delay */ | ||
4418 | #define DDRC_DQS_ADJRDQS_MASK (0x1f << DDRC_DQS_ADJRDQS_BIT) | ||
4419 | |||
4420 | /* DDRC Memory Map Config Register */ | ||
4421 | #define DDRC_MMAP_BASE_BIT 8 /* base address */ | ||
4422 | #define DDRC_MMAP_BASE_MASK (0xff << DDRC_MMAP_BASE_BIT) | ||
4423 | #define DDRC_MMAP_MASK_BIT 0 /* address mask */ | ||
4424 | #define DDRC_MMAP_MASK_MASK (0xff << DDRC_MMAP_MASK_BIT) | ||
4425 | |||
4426 | #define DDRC_MMAP0_BASE (0x20 << DDRC_MMAP_BASE_BIT) | ||
4427 | #define DDRC_MMAP1_BASE_64M (0x24 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/ | ||
4428 | #define DDRC_MMAP1_BASE_128M (0x28 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/ | ||
4429 | #define DDRC_MMAP1_BASE_256M (0x30 << DDRC_MMAP_BASE_BIT) /*when bank0 is 128M*/ | ||
4430 | |||
4431 | #define DDRC_MMAP_MASK_64_64 (0xfc << DDRC_MMAP_MASK_BIT) /*mask for two 128M SDRAM*/ | ||
4432 | #define DDRC_MMAP_MASK_128_128 (0xf8 << DDRC_MMAP_MASK_BIT) /*mask for two 128M SDRAM*/ | ||
4433 | #define DDRC_MMAP_MASK_256_256 (0xf0 << DDRC_MMAP_MASK_BIT) /*mask for two 128M SDRAM*/ | ||
4434 | |||
4435 | /* DDRC Timing Configure Register 1 */ | ||
4436 | #define DDRC_DDELAYCTRL1_TSEL_BIT 18 | ||
4437 | #define DDRC_DDELAYCTRL1_TSEL_MASK (0x3 << DDRC_DDELAYCTRL1_TSEL_BIT) | ||
4438 | #define DDRC_DDELAYCTRL1_MSEL_BIT 16 | ||
4439 | #define DDRC_DDELAYCTRL1_MSEL_MASK (0x3 << DDRC_DDELAYCTRL1_MSEL_BIT) | ||
4440 | #define DDRC_DDELAYCTRL1_HL (1 << 15) | ||
4441 | #define DDRC_DDELAYCTRL1_QUAR (1 << 14) | ||
4442 | #define DDRC_DDELAYCTRL1_MAUTO (1 << 6) | ||
4443 | #define DDRC_DDELAYCTRL1_MSIGN (1 << 5) | ||
4444 | #define DDRC_DDELAYCTRL1_MASK_DELAY_SEL_ADJ_BIT 0 | ||
4445 | #define DDRC_DDELAYCTRL1_MASK_DELAY_SEL_ADJ_MASK (0x1f << DDRC_DDELAYCTRL1_MASK_DELAY_SEL_ADJ_BIT) | ||
4446 | |||
4447 | /* DDRC Timing Configure Register 2 */ | ||
4448 | #define DDRC_DDELAYCTRL2_MASK_DELAY_SEL_BIT 0 | ||
4449 | #define DDRC_DDELAYCTRL2_MASK_DELAY_SEL_MASK (0x3f << DDRC_DDELAYCTRL2_MASK_DELAY_SEL_BIT) | ||
4450 | |||
4451 | /* DDRC Multi-media stride Register */ | ||
4452 | #define DDRC_DSTRB_STRB0_BIT 16 | ||
4453 | #define DDRC_DSTRB_STRB0_MASK (0x1fff << DDRC_DSTRB_STRB0_BIT) | ||
4454 | #define DDRC_DSTRB_STRB1_BIT 0 | ||
4455 | #define DDRC_DSTRB_STRB1_MASK (0x1fff << DDRC_DSTRB_STRB1_BIT) | ||
4456 | /* DDRC IO pad control Register */ | ||
4457 | #define DDRC_PMEMBS0_PDDQS3 (1 << 31) | ||
4458 | #define DDRC_PMEMBS0_PDDQS2 (1 << 30) | ||
4459 | #define DDRC_PMEMBS0_PDDQS1 (1 << 29) | ||
4460 | #define DDRC_PMEMBS0_PDDQS0 (1 << 28) | ||
4461 | #define DDRC_PMEMBS0_PDDQ3 (1 << 27) | ||
4462 | #define DDRC_PMEMBS0_PDDQ2 (1 << 26) | ||
4463 | #define DDRC_PMEMBS0_PDDQ1 (1 << 25) | ||
4464 | #define DDRC_PMEMBS0_PDDQ0 (1 << 24) | ||
4465 | #define DDRC_PMEMBS0_STDQS3 (1 << 23) | ||
4466 | #define DDRC_PMEMBS0_STDQS2 (1 << 22) | ||
4467 | #define DDRC_PMEMBS0_STDQS1 (1 << 21) | ||
4468 | #define DDRC_PMEMBS0_STDQS0 (1 << 20) | ||
4469 | #define DDRC_PMEMBS0_STDQ3 (1 << 19) | ||
4470 | #define DDRC_PMEMBS0_STDQ2 (1 << 18) | ||
4471 | #define DDRC_PMEMBS0_STDQ1 (1 << 17) | ||
4472 | #define DDRC_PMEMBS0_STDQ0 (1 << 16) | ||
4473 | #define DDRC_PMEMBS0_PEDQS3 (1 << 15) | ||
4474 | #define DDRC_PMEMBS0_PEDQS2 (1 << 14) | ||
4475 | #define DDRC_PMEMBS0_PEDQS1 (1 << 13) | ||
4476 | #define DDRC_PMEMBS0_PEDQS0 (1 << 12) | ||
4477 | #define DDRC_PMEMBS0_PEDQ3 (1 << 11) | ||
4478 | #define DDRC_PMEMBS0_PEDQ2 (1 << 10) | ||
4479 | #define DDRC_PMEMBS0_PEDQ1 (1 << 9) | ||
4480 | #define DDRC_PMEMBS0_PEDQ0 (1 << 8) | ||
4481 | #define DDRC_PMEMBS0_PSDQS3 (1 << 7) | ||
4482 | #define DDRC_PMEMBS0_PSDQS2 (1 << 6) | ||
4483 | #define DDRC_PMEMBS0_PSDQS1 (1 << 5) | ||
4484 | #define DDRC_PMEMBS0_PSDQS0 (1 << 4) | ||
4485 | #define DDRC_PMEMBS0_PSDQ3 (1 << 3) | ||
4486 | #define DDRC_PMEMBS0_PSDQ2 (1 << 2) | ||
4487 | #define DDRC_PMEMBS0_PSDQ1 (1 << 1) | ||
4488 | #define DDRC_PMEMBS0_PSDQ0 (1 << 0) | ||
4489 | /* DDRC IO pad control Register */ | ||
4490 | #define DDRC_PMEMBS1_IENDQS3 (1 << 31) | ||
4491 | #define DDRC_PMEMBS1_IENDQS2 (1 << 30) | ||
4492 | #define DDRC_PMEMBS1_IENDQS1 (1 << 29) | ||
4493 | #define DDRC_PMEMBS1_IENDQS0 (1 << 28) | ||
4494 | #define DDRC_PMEMBS1_IENDQ3 (1 << 27) | ||
4495 | #define DDRC_PMEMBS1_IENDQ2 (1 << 26) | ||
4496 | #define DDRC_PMEMBS1_IENDQ1 (1 << 25) | ||
4497 | #define DDRC_PMEMBS1_IENDQ0 (1 << 24) | ||
4498 | #define DDRC_PMEMBS1_SSTL (1 << 16) | ||
4499 | |||
4500 | #define DDRC_PMEMBS1_SSELDQS3_BIT 14 | ||
4501 | #define DDRC_PMEMBS1_SSELDQS3_MASK (0x3 << DDRC_PMEMBS1_SSELDQS3_BIT) | ||
4502 | |||
4503 | #define DDRC_PMEMBS1_SSELDQS2_BIT 12 | ||
4504 | #define DDRC_PMEMBS1_SSELDQS2_MASK (0x3 << DDRC_PMEMBS1_SSELDQS2_BIT) | ||
4505 | |||
4506 | #define DDRC_PMEMBS1_SSELDQS1_BIT 10 | ||
4507 | #define DDRC_PMEMBS1_SSELDQS1_MASK (0x3 << DDRC_PMEMBS1_SSELDQS1_BIT) | ||
4508 | |||
4509 | #define DDRC_PMEMBS1_SSELDQS0_BIT 8 | ||
4510 | #define DDRC_PMEMBS1_SSELDQS0_MASK (0x3 << DDRC_PMEMBS1_SSELDQS0_BIT) | ||
4511 | |||
4512 | #define DDRC_PMEMBS1_SSELDQ3_BIT 6 | ||
4513 | #define DDRC_PMEMBS1_SSELDQ3_MASK (0x3 << DDRC_PMEMBS1_SSELDQ3_BIT) | ||
4514 | |||
4515 | #define DDRC_PMEMBS1_SSELDQ2_BIT 4 | ||
4516 | #define DDRC_PMEMBS1_SSELDQ2_MASK (0x3 << DDRC_PMEMBS1_SSELDQ2_BIT) | ||
4517 | |||
4518 | #define DDRC_PMEMBS1_SSELDQ1_BIT 2 | ||
4519 | #define DDRC_PMEMBS1_SSELDQ1_MASK (0x3 << DDRC_PMEMBS1_SSELDQ1_BIT) | ||
4520 | |||
4521 | #define DDRC_PMEMBS1_SSELDQ0_BIT 0 | ||
4522 | #define DDRC_PMEMBS1_SSELDQ0_MASK (0x3 << DDRC_PMEMBS1_SSELDQ0_BIT) | ||
4523 | |||
4524 | /* DDRC IO pad control Register */ | ||
4525 | #define DDRC_PMEMOSEL_CKSSEL_BIT 18 | ||
4526 | #define DDRC_PMEMOSEL_CKSSEL_MASK (0x3 << DDRC_PMEMOSEL_CKSSEL_BIT) | ||
4527 | |||
4528 | #define DDRC_PMEMOSEL_CKESSEL_BIT 16 | ||
4529 | #define DDRC_PMEMOSEL_CKESSEL_MASK (0x3 << DDRC_PMEMOSEL_CKESSEL_BIT) | ||
4530 | |||
4531 | #define DDRC_PMEMOSEL_ADDRSSEL_BIT 14 | ||
4532 | #define DDRC_PMEMOSEL_ADDRSSEL_MASK (0x3 << DDRC_PMEMOSEL_ADDRSSEL_BIT) | ||
4533 | |||
4534 | #define DDRC_PMEMOSEL_DMSSEL3_BIT 12 | ||
4535 | #define DDRC_PMEMOSEL_DMSSEL3_MASK (0x3 << DDRC_PMEMOSEL_DMSSEL3_BIT) | ||
4536 | |||
4537 | #define DDRC_PMEMOSEL_DMSSEL2_BIT 10 | ||
4538 | #define DDRC_PMEMOSEL_DMSSEL2_MASK (0x3 << DDRC_PMEMOSEL_DMSSEL2_BIT) | ||
4539 | |||
4540 | #define DDRC_PMEMOSEL_DMSSEL1_BIT 8 | ||
4541 | #define DDRC_PMEMOSEL_DMSSEL1_MASK (0x3 << DDRC_PMEMOSEL_DMSSEL1_BIT) | ||
4542 | |||
4543 | #define DDRC_PMEMOSEL_DMSSEL0_BIT 6 | ||
4544 | #define DDRC_PMEMOSEL_DMSSEL0_MASK (0x3 << DDRC_PMEMOSEL_DMSSEL0_BIT) | ||
4545 | |||
4546 | #define DDRC_PMEMOSEL_CMDSSEL_BIT 4 | ||
4547 | #define DDRC_PMEMOSEL_CMDSSEL_MASK (0x3 << DDRC_PMEMOSEL_CMDSSEL_BIT) | ||
4548 | |||
4549 | #define DDRC_PMEMOSEL_CSSSEL1_BIT 2 | ||
4550 | #define DDRC_PMEMOSEL_CSSSEL1_MASK (0x3 << DDRC_PMEMOSEL_CSSSEL1_BIT) | ||
4551 | |||
4552 | #define DDRC_PMEMOSEL_CSSSEL0_BIT 0 | ||
4553 | #define DDRC_PMEMOSEL_CSSSEL0_MASK (0x3 << DDRC_PMEMOSEL_CSSSEL0_BIT) | ||
4554 | |||
4555 | /* DDRC IO pad control Register */ | ||
4556 | #define DDRC_PMEMOEN_CKOEN (1 << 14) | ||
4557 | #define DDRC_PMEMOEN_BAOEN2 (1 << 13) | ||
4558 | #define DDRC_PMEMOEN_BAOEN1 (1 << 12) | ||
4559 | #define DDRC_PMEMOEN_BAOEN0 (1 << 11) | ||
4560 | #define DDRC_PMEMOEN_AOEN13 (1 << 10) | ||
4561 | #define DDRC_PMEMOEN_AOEN12 (1 << 9) | ||
4562 | #define DDRC_PMEMOEN_AOEN11_0 (1 << 8) | ||
4563 | #define DDRC_PMEMOEN_DMOEN3 (1 << 7) | ||
4564 | #define DDRC_PMEMOEN_DMOEN2 (1 << 6) | ||
4565 | #define DDRC_PMEMOEN_DMOEN1 (1 << 5) | ||
4566 | #define DDRC_PMEMOEN_DMOEN0 (1 << 4) | ||
4567 | #define DDRC_PMEMOEN_CMDOEN (1 << 3) | ||
4568 | #define DDRC_PMEMOEN_CSOEN1 (1 << 2) | ||
4569 | #define DDRC_PMEMOEN_CSOEN0 (1 << 1) | ||
4570 | #define DDRC_PMEMOEN_CKEOEN (1 << 0) | ||
4571 | |||
4572 | #ifndef __MIPS_ASSEMBLER | ||
4573 | |||
4574 | #define DDR_GET_VALUE(x, y) \ | ||
4575 | ({ \ | ||
4576 | unsigned long value, tmp; \ | ||
4577 | tmp = x * 1000; \ | ||
4578 | value = (tmp % y == 0) ? (tmp / y) : (tmp / y + 1); \ | ||
4579 | value; \ | ||
4580 | }) | ||
4581 | |||
4582 | #endif /* __MIPS_ASSEMBLER */ | ||
4583 | |||
4584 | #define EMC_BASE 0xB3410000 | ||
4585 | |||
4586 | /************************************************************************* | ||
4587 | * EMC (External Memory Controller) | ||
4588 | *************************************************************************/ | ||
4589 | #define EMC_BCR (EMC_BASE + 0x00) /* Bus Control Register */ | ||
4590 | #define EMC_PMEMBS1 (EMC_BASE + 0x6004) | ||
4591 | #define EMC_PMEMBS0 (EMC_BASE + 0x6008) | ||
4592 | #define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 ??? */ | ||
4593 | #define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */ | ||
4594 | #define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */ | ||
4595 | #define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */ | ||
4596 | #define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */ | ||
4597 | #define EMC_SMCR5 (EMC_BASE + 0x24) /* Static Memory Control Register 5 */ | ||
4598 | #define EMC_SMCR6 (EMC_BASE + 0x28) /* Static Memory Control Register 6 */ | ||
4599 | #define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */ | ||
4600 | #define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */ | ||
4601 | #define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */ | ||
4602 | #define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */ | ||
4603 | #define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */ | ||
4604 | #define EMC_SACR5 (EMC_BASE + 0x44) /* Static Memory Bank 5 Addr Config Reg */ | ||
4605 | #define EMC_SACR6 (EMC_BASE + 0x48) /* Static Memory Bank 6 Addr Config Reg */ | ||
4606 | #define EMC_NFCSR (EMC_BASE + 0x50) /* NAND Flash Control/Status Register */ | ||
4607 | #define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */ | ||
4608 | #define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */ | ||
4609 | #define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */ | ||
4610 | #define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */ | ||
4611 | #define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */ | ||
4612 | #define EMC_DMAR1 (EMC_BASE + 0x94) /* SDRAM Bank 1 Addr Config Register */ | ||
4613 | #define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */ | ||
4614 | |||
4615 | #define REG_EMC_BCR REG32(EMC_BCR) | ||
4616 | #define REG_EMC_PMEMBS1 REG32(EMC_PMEMBS1) | ||
4617 | #define REG_EMC_PMEMBS0 REG32(EMC_PMEMBS0) | ||
4618 | #define REG_EMC_SMCR0 REG32(EMC_SMCR0) // ??? | ||
4619 | #define REG_EMC_SMCR1 REG32(EMC_SMCR1) | ||
4620 | #define REG_EMC_SMCR2 REG32(EMC_SMCR2) | ||
4621 | #define REG_EMC_SMCR3 REG32(EMC_SMCR3) | ||
4622 | #define REG_EMC_SMCR4 REG32(EMC_SMCR4) | ||
4623 | #define REG_EMC_SMCR5 REG32(EMC_SMCR5) | ||
4624 | #define REG_EMC_SMCR6 REG32(EMC_SMCR6) | ||
4625 | #define REG_EMC_SACR0 REG32(EMC_SACR0) | ||
4626 | #define REG_EMC_SACR1 REG32(EMC_SACR1) | ||
4627 | #define REG_EMC_SACR2 REG32(EMC_SACR2) | ||
4628 | #define REG_EMC_SACR3 REG32(EMC_SACR3) | ||
4629 | #define REG_EMC_SACR4 REG32(EMC_SACR4) | ||
4630 | |||
4631 | #define REG_EMC_NFCSR REG32(EMC_NFCSR) | ||
4632 | |||
4633 | #define REG_EMC_DMCR REG32(EMC_DMCR) | ||
4634 | #define REG_EMC_RTCSR REG16(EMC_RTCSR) | ||
4635 | #define REG_EMC_RTCNT REG16(EMC_RTCNT) | ||
4636 | #define REG_EMC_RTCOR REG16(EMC_RTCOR) | ||
4637 | #define REG_EMC_DMAR0 REG32(EMC_DMAR0) | ||
4638 | #define REG_EMC_DMAR1 REG32(EMC_DMAR1) | ||
4639 | |||
4640 | /* Bus Control Register */ | ||
4641 | #define EMC_BCR_BT_SEL_BIT 30 | ||
4642 | #define EMC_BCR_BT_SEL_MASK (0x3 << EMC_BCR_BT_SEL_BIT) | ||
4643 | #define EMC_BCR_PK_SEL (1 << 24) | ||
4644 | #define EMC_BCR_BSR_MASK (1 << 2) /* Nand and SDRAM Bus Share Select: 0, share; 1, unshare */ | ||
4645 | #define EMC_BCR_BSR_SHARE (0 << 2) | ||
4646 | #define EMC_BCR_BSR_UNSHARE (1 << 2) | ||
4647 | #define EMC_BCR_BRE (1 << 1) | ||
4648 | #define EMC_BCR_ENDIAN (1 << 0) | ||
4649 | |||
4650 | /* Static Memory Control Register */ | ||
4651 | #define EMC_SMCR_STRV_BIT 24 | ||
4652 | #define EMC_SMCR_STRV_MASK (0x1f << EMC_SMCR_STRV_BIT) | ||
4653 | #define EMC_SMCR_TAW_BIT 20 | ||
4654 | #define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) | ||
4655 | #define EMC_SMCR_TBP_BIT 16 | ||
4656 | #define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) | ||
4657 | #define EMC_SMCR_TAH_BIT 12 | ||
4658 | #define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) | ||
4659 | #define EMC_SMCR_TAS_BIT 8 | ||
4660 | #define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) | ||
4661 | #define EMC_SMCR_BW_BIT 6 | ||
4662 | #define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) | ||
4663 | #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) | ||
4664 | #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) | ||
4665 | #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) | ||
4666 | #define EMC_SMCR_BCM (1 << 3) | ||
4667 | #define EMC_SMCR_BL_BIT 1 | ||
4668 | #define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) | ||
4669 | #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) | ||
4670 | #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) | ||
4671 | #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) | ||
4672 | #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) | ||
4673 | #define EMC_SMCR_SMT (1 << 0) | ||
4674 | |||
4675 | /* Static Memory Bank Addr Config Reg */ | ||
4676 | #define EMC_SACR_BASE_BIT 8 | ||
4677 | #define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) | ||
4678 | #define EMC_SACR_MASK_BIT 0 | ||
4679 | #define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) | ||
4680 | |||
4681 | /* NAND Flash Control/Status Register */ | ||
4682 | #define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */ | ||
4683 | #define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */ | ||
4684 | #define EMC_NFCSR_NFCE3 (1 << 5) | ||
4685 | #define EMC_NFCSR_NFE3 (1 << 4) | ||
4686 | #define EMC_NFCSR_NFCE2 (1 << 3) | ||
4687 | #define EMC_NFCSR_NFE2 (1 << 2) | ||
4688 | #define EMC_NFCSR_NFCE1 (1 << 1) | ||
4689 | #define EMC_NFCSR_NFE1 (1 << 0) | ||
4690 | #define EMC_NFCSR_NFE(n) (1 << (((n)-1)*2)) | ||
4691 | #define EMC_NFCSR_NFCE(n) (1 << (((n)*2)-1)) | ||
4692 | |||
4693 | /* DRAM Control Register */ | ||
4694 | #define EMC_DMCR_BW_BIT 31 | ||
4695 | #define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) | ||
4696 | #define EMC_DMCR_CA_BIT 26 | ||
4697 | #define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) | ||
4698 | #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) | ||
4699 | #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) | ||
4700 | #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) | ||
4701 | #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) | ||
4702 | #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) | ||
4703 | #define EMC_DMCR_RMODE (1 << 25) | ||
4704 | #define EMC_DMCR_RFSH (1 << 24) | ||
4705 | #define EMC_DMCR_MRSET (1 << 23) | ||
4706 | #define EMC_DMCR_RA_BIT 20 | ||
4707 | #define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) | ||
4708 | #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) | ||
4709 | #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) | ||
4710 | #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) | ||
4711 | #define EMC_DMCR_BA_BIT 19 | ||
4712 | #define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) | ||
4713 | #define EMC_DMCR_PDM (1 << 18) | ||
4714 | #define EMC_DMCR_EPIN (1 << 17) | ||
4715 | #define EMC_DMCR_MBSEL (1 << 16) | ||
4716 | #define EMC_DMCR_TRAS_BIT 13 | ||
4717 | #define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) | ||
4718 | #define EMC_DMCR_RCD_BIT 11 | ||
4719 | #define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) | ||
4720 | #define EMC_DMCR_TPC_BIT 8 | ||
4721 | #define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) | ||
4722 | #define EMC_DMCR_TRWL_BIT 5 | ||
4723 | #define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) | ||
4724 | #define EMC_DMCR_TRC_BIT 2 | ||
4725 | #define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) | ||
4726 | #define EMC_DMCR_TCL_BIT 0 | ||
4727 | #define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) | ||
4728 | |||
4729 | /* Refresh Time Control/Status Register */ | ||
4730 | #define EMC_RTCSR_SFR (1 << 8) /* self refresh flag */ | ||
4731 | #define EMC_RTCSR_CMF (1 << 7) | ||
4732 | #define EMC_RTCSR_CKS_BIT 0 | ||
4733 | #define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) | ||
4734 | #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) | ||
4735 | #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) | ||
4736 | #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) | ||
4737 | #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) | ||
4738 | #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) | ||
4739 | #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) | ||
4740 | #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) | ||
4741 | #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) | ||
4742 | |||
4743 | /* SDRAM Bank Address Configuration Register */ | ||
4744 | #define EMC_DMAR_BASE_BIT 8 | ||
4745 | #define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) | ||
4746 | #define EMC_DMAR_MASK_BIT 0 | ||
4747 | #define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) | ||
4748 | |||
4749 | /* Mode Register of SDRAM bank 0 */ | ||
4750 | #define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */ | ||
4751 | #define EMC_SDMR_OM_BIT 7 /* Operating Mode */ | ||
4752 | #define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) | ||
4753 | #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) | ||
4754 | #define EMC_SDMR_CAS_BIT 4 /* CAS Latency */ | ||
4755 | #define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) | ||
4756 | #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) | ||
4757 | #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) | ||
4758 | #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) | ||
4759 | #define EMC_SDMR_BT_BIT 3 /* Burst Type */ | ||
4760 | #define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) | ||
4761 | #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */ | ||
4762 | #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */ | ||
4763 | #define EMC_SDMR_BL_BIT 0 /* Burst Length */ | ||
4764 | #define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) | ||
4765 | #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) | ||
4766 | #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) | ||
4767 | #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) | ||
4768 | #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) | ||
4769 | |||
4770 | #define EMC_SDMR_CAS2_16BIT \ | ||
4771 | (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) | ||
4772 | #define EMC_SDMR_CAS2_32BIT \ | ||
4773 | (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) | ||
4774 | #define EMC_SDMR_CAS3_16BIT \ | ||
4775 | (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) | ||
4776 | #define EMC_SDMR_CAS3_32BIT \ | ||
4777 | (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) | ||
4778 | |||
4779 | #define I2C0_BASE 0xB0050000 | ||
4780 | #define I2C1_BASE 0xB0051000 | ||
4781 | |||
4782 | /************************************************************************* | ||
4783 | * I2C | ||
4784 | *************************************************************************/ | ||
4785 | #define I2C_CTRL(n) (I2C0_BASE + (n)*0x1000 + 0x00) | ||
4786 | #define I2C_TAR(n) (I2C0_BASE + (n)*0x1000 + 0x04) | ||
4787 | #define I2C_SAR(n) (I2C0_BASE + (n)*0x1000 + 0x08) | ||
4788 | #define I2C_DC(n) (I2C0_BASE + (n)*0x1000 + 0x10) | ||
4789 | #define I2C_SHCNT(n) (I2C0_BASE + (n)*0x1000 + 0x14) | ||
4790 | #define I2C_SLCNT(n) (I2C0_BASE + (n)*0x1000 + 0x18) | ||
4791 | #define I2C_FHCNT(n) (I2C0_BASE + (n)*0x1000 + 0x1C) | ||
4792 | #define I2C_FLCNT(n) (I2C0_BASE + (n)*0x1000 + 0x20) | ||
4793 | #define I2C_INTST(n) (I2C0_BASE + (n)*0x1000 + 0x2C) | ||
4794 | #define I2C_INTM(n) (I2C0_BASE + (n)*0x1000 + 0x30) | ||
4795 | #define I2C_RXTL(n) (I2C0_BASE + (n)*0x1000 + 0x38) | ||
4796 | #define I2C_TXTL(n) (I2C0_BASE + (n)*0x1000 + 0x3c) | ||
4797 | #define I2C_CINTR(n) (I2C0_BASE + (n)*0x1000 + 0x40) | ||
4798 | #define I2C_CRXUF(n) (I2C0_BASE + (n)*0x1000 + 0x44) | ||
4799 | #define I2C_CRXOF(n) (I2C0_BASE + (n)*0x1000 + 0x48) | ||
4800 | #define I2C_CTXOF(n) (I2C0_BASE + (n)*0x1000 + 0x4C) | ||
4801 | #define I2C_CRXREQ(n) (I2C0_BASE + (n)*0x1000 + 0x50) | ||
4802 | #define I2C_CTXABRT(n) (I2C0_BASE + (n)*0x1000 + 0x54) | ||
4803 | #define I2C_CRXDONE(n) (I2C0_BASE + (n)*0x1000 + 0x58) | ||
4804 | #define I2C_CACT(n) (I2C0_BASE + (n)*0x1000 + 0x5C) | ||
4805 | #define I2C_CSTP(n) (I2C0_BASE + (n)*0x1000 + 0x60) | ||
4806 | #define I2C_CSTT(n) (I2C0_BASE + (n)*0x1000 + 0x64) | ||
4807 | #define I2C_CGC(n) (I2C0_BASE + (n)*0x1000 + 0x68) | ||
4808 | #define I2C_ENB(n) (I2C0_BASE + (n)*0x1000 + 0x6C) | ||
4809 | #define I2C_STA(n) (I2C0_BASE + (n)*0x1000 + 0x70) | ||
4810 | #define I2C_TXABRT(n) (I2C0_BASE + (n)*0x1000 + 0x80) | ||
4811 | #define I2C_DMACR(n) (I2C0_BASE + (n)*0x1000 + 0x88) | ||
4812 | #define I2C_DMATDLR(n) (I2C0_BASE + (n)*0x1000 + 0x8c) | ||
4813 | #define I2C_DMARDLR(n) (I2C0_BASE + (n)*0x1000 + 0x90) | ||
4814 | #define I2C_SDASU(n) (I2C0_BASE + (n)*0x1000 + 0x94) | ||
4815 | #define I2C_ACKGC(n) (I2C0_BASE + (n)*0x1000 + 0x98) | ||
4816 | #define I2C_ENSTA(n) (I2C0_BASE + (n)*0x1000 + 0x9C) | ||
4817 | |||
4818 | #define REG_I2C_CTRL(n) REG8(I2C_CTRL(n)) /* I2C Control Register (I2C_CTRL) */ | ||
4819 | #define REG_I2C_TAR(n) REG16(I2C_TAR(n)) /* I2C target address (I2C_TAR) */ | ||
4820 | #define REG_I2C_SAR(n) REG16(I2C_SAR(n)) | ||
4821 | #define REG_I2C_DC(n) REG16(I2C_DC(n)) | ||
4822 | #define REG_I2C_SHCNT(n) REG16(I2C_SHCNT(n)) | ||
4823 | #define REG_I2C_SLCNT(n) REG16(I2C_SLCNT(n)) | ||
4824 | #define REG_I2C_FHCNT(n) REG16(I2C_FHCNT(n)) | ||
4825 | #define REG_I2C_FLCNT(n) REG16(I2C_FLCNT(n)) | ||
4826 | #define REG_I2C_INTST(n) REG16(I2C_INTST(n)) /* i2c interrupt status (I2C_INTST) */ | ||
4827 | #define REG_I2C_INTM(n) REG16(I2C_INTM(n)) /* i2c interrupt mask status (I2C_INTM) */ | ||
4828 | #define REG_I2C_RXTL(n) REG8(I2C_RXTL(n)) | ||
4829 | #define REG_I2C_TXTL(n) REG8(I2C_TXTL(n)) | ||
4830 | #define REG_I2C_CINTR(n) REG8(I2C_CINTR(n)) | ||
4831 | #define REG_I2C_CRXUF(n) REG8(I2C_CRXUF(n)) | ||
4832 | #define REG_I2C_CRXOF(n) REG8(I2C_CRXOF(n)) | ||
4833 | #define REG_I2C_CTXOF(n) REG8(I2C_CTXOF(n)) | ||
4834 | #define REG_I2C_CRXREQ(n) REG8(I2C_CRXREQ(n)) | ||
4835 | #define REG_I2C_CTXABRT(n) REG8(I2C_CTXABRT(n)) | ||
4836 | #define REG_I2C_CRXDONE(n) REG8(I2C_CRXDONE(n)) | ||
4837 | #define REG_I2C_CACT(n) REG8(I2C_CACT(n)) | ||
4838 | #define REG_I2C_CSTP(n) REG8(I2C_CSTP(n)) | ||
4839 | #define REG_I2C_CSTT(n) REG16(I2C_CSTT(n)) | ||
4840 | #define REG_I2C_CGC(n) REG8(I2C_CGC(n)) | ||
4841 | #define REG_I2C_ENB(n) REG8(I2C_ENB(n)) | ||
4842 | #define REG_I2C_STA(n) REG8(I2C_STA(n)) | ||
4843 | #define REG_I2C_TXABRT(n) REG16(I2C_TXABRT(n)) | ||
4844 | #define REG_I2C_DMACR(n) REG8(I2C_DMACR(n)) | ||
4845 | #define REG_I2C_DMATDLR(n) REG8(I2C_DMATDLR(n)) | ||
4846 | #define REG_I2C_DMARDLR(n) REG8(I2C_DMARDLR(n)) | ||
4847 | #define REG_I2C_SDASU(n) REG8(I2C_SDASU(n)) | ||
4848 | #define REG_I2C_ACKGC(n) REG8(I2C_ACKGC(n)) | ||
4849 | #define REG_I2C_ENSTA(n) REG8(I2C_ENSTA(n)) | ||
4850 | |||
4851 | /* I2C Control Register (I2C_CTRL) */ | ||
4852 | |||
4853 | #define I2C_CTRL_STPHLD (1 << 7) /* Stop Hold Enable bit: when tx fifo empty, 0: send stop 1: never send stop*/ | ||
4854 | #define I2C_CTRL_SLVDIS (1 << 6) /* after reset slave is disabled*/ | ||
4855 | #define I2C_CTRL_REST (1 << 5) | ||
4856 | #define I2C_CTRL_MATP (1 << 4) /* 1: 10bit address 0: 7bit addressing*/ | ||
4857 | #define I2C_CTRL_SATP (1 << 3) /* 1: 10bit address 0: 7bit address*/ | ||
4858 | #define I2C_CTRL_SPDF (2 << 1) /* fast mode 400kbps */ | ||
4859 | #define I2C_CTRL_SPDS (1 << 1) /* standard mode 100kbps */ | ||
4860 | #define I2C_CTRL_MD (1 << 0) /* master enabled*/ | ||
4861 | |||
4862 | /* I2C target address (I2C_TAR) */ | ||
4863 | |||
4864 | #define I2C_TAR_MATP (1 << 12) | ||
4865 | #define I2C_TAR_SPECIAL (1 << 11) | ||
4866 | #define I2C_TAR_GC_OR_START (1 << 10) | ||
4867 | #define I2C_TAR_I2CTAR_BIT 0 | ||
4868 | #define I2C_TAR_I2CTAR_MASK (0x3ff << I2C_TAR_I2CTAR_BIT) | ||
4869 | |||
4870 | /* I2C slave address */ | ||
4871 | #define I2C_SAR_I2CSAR_BIT 0 | ||
4872 | #define I2C_SAR_I2CSAR_MASK (0x3ff << I2C_SAR_I2CSAR_BIT) | ||
4873 | |||
4874 | /* I2C data buffer and command (I2C_DC) */ | ||
4875 | |||
4876 | #define I2C_DC_CMD (1 << 8) /* 1 read 0 write*/ | ||
4877 | #define I2C_DC_DAT_BIT 0 | ||
4878 | #define I2C_DC_DAT_MASK (0xff << I2C_DC_DAT_BIT) /* 1 read 0 write*/ | ||
4879 | |||
4880 | /* i2c interrupt status (I2C_INTST) */ | ||
4881 | |||
4882 | #define I2C_INTST_IGC (1 << 11) /* */ | ||
4883 | #define I2C_INTST_ISTT (1 << 10) | ||
4884 | #define I2C_INTST_ISTP (1 << 9) | ||
4885 | #define I2C_INTST_IACT (1 << 8) | ||
4886 | #define I2C_INTST_RXDN (1 << 7) | ||
4887 | #define I2C_INTST_TXABT (1 << 6) | ||
4888 | #define I2C_INTST_RDREQ (1 << 5) | ||
4889 | #define I2C_INTST_TXEMP (1 << 4) | ||
4890 | #define I2C_INTST_TXOF (1 << 3) | ||
4891 | #define I2C_INTST_RXFL (1 << 2) | ||
4892 | #define I2C_INTST_RXOF (1 << 1) | ||
4893 | #define I2C_INTST_RXUF (1 << 0) | ||
4894 | |||
4895 | /* i2c interrupt mask status (I2C_INTM) */ | ||
4896 | |||
4897 | #define I2C_INTM_MIGC (1 << 11) /* */ | ||
4898 | #define I2C_INTM_MISTT (1 << 10) | ||
4899 | #define I2C_INTM_MISTP (1 << 9) | ||
4900 | #define I2C_INTM_MIACT (1 << 8) | ||
4901 | #define I2C_INTM_MRXDN (1 << 7) | ||
4902 | #define I2C_INTM_MTXABT (1 << 6) | ||
4903 | #define I2C_INTM_MRDREQ (1 << 5) | ||
4904 | #define I2C_INTM_MTXEMP (1 << 4) | ||
4905 | #define I2C_INTM_MTXOF (1 << 3) | ||
4906 | #define I2C_INTM_MRXFL (1 << 2) | ||
4907 | #define I2C_INTM_MRXOF (1 << 1) | ||
4908 | #define I2C_INTM_MRXUF (1 << 0) | ||
4909 | |||
4910 | /* I2C Clear Combined and Individual Interrupts (I2C_CINTR) */ | ||
4911 | |||
4912 | #define I2C_CINTR_CINT (1 << 0) | ||
4913 | |||
4914 | /* I2C Clear TX_OVER Interrupt */ | ||
4915 | /* I2C Clear RDREQ Interrupt */ | ||
4916 | /* I2C Clear TX_ABRT Interrupt */ | ||
4917 | /* I2C Clear RX_DONE Interrupt */ | ||
4918 | /* I2C Clear ACTIVITY Interrupt */ | ||
4919 | /* I2C Clear STOP Interrupts */ | ||
4920 | /* I2C Clear START Interrupts */ | ||
4921 | /* I2C Clear GEN_CALL Interrupts */ | ||
4922 | |||
4923 | /* I2C Enable (I2C_ENB) */ | ||
4924 | |||
4925 | #define I2C_ENB_I2CENB (1 << 0) /* Enable the i2c */ | ||
4926 | |||
4927 | /* I2C Status Register (I2C_STA) */ | ||
4928 | |||
4929 | #define I2C_STA_SLVACT (1 << 6) /* Slave FSM is not in IDLE state */ | ||
4930 | #define I2C_STA_MSTACT (1 << 5) /* Master FSM is not in IDLE state */ | ||
4931 | #define I2C_STA_RFF (1 << 4) /* RFIFO if full */ | ||
4932 | #define I2C_STA_RFNE (1 << 3) /* RFIFO is not empty */ | ||
4933 | #define I2C_STA_TFE (1 << 2) /* TFIFO is empty */ | ||
4934 | #define I2C_STA_TFNF (1 << 1) /* TFIFO is not full */ | ||
4935 | #define I2C_STA_ACT (1 << 0) /* I2C Activity Status */ | ||
4936 | |||
4937 | /* I2C Transmit Abort Status Register (I2C_TXABRT) */ | ||
4938 | |||
4939 | #define I2C_TXABRT_SLVRD_INTX (1 << 15) | ||
4940 | #define I2C_TXABRT_SLV_ARBLOST (1 << 14) | ||
4941 | #define I2C_TXABRT_SLVFLUSH_TXFIFO (1 << 13) | ||
4942 | #define I2C_TXABRT_ARB_LOST (1 << 12) | ||
4943 | #define I2C_TXABRT_ABRT_MASTER_DIS (1 << 11) | ||
4944 | #define I2C_TXABRT_ABRT_10B_RD_NORSTRT (1 << 10) | ||
4945 | #define I2C_TXABRT_SBYTE_NORSTRT (1 << 9) | ||
4946 | #define I2C_TXABRT_ABRT_HS_NORSTRT (1 << 8) | ||
4947 | #define I2C_TXABRT_SBYTE_ACKDET (1 << 7) | ||
4948 | #define I2C_TXABRT_ABRT_HS_ACKD (1 << 6) | ||
4949 | #define I2C_TXABRT_ABRT_GCALL_READ (1 << 5) | ||
4950 | #define I2C_TXABRT_ABRT_GCALL_NOACK (1 << 4) | ||
4951 | #define I2C_TXABRT_ABRT_XDATA_NOACK (1 << 3) | ||
4952 | #define I2C_TXABRT_ABRT_10ADDR2_NOACK (1 << 2) | ||
4953 | #define I2C_TXABRT_ABRT_10ADDR1_NOACK (1 << 1) | ||
4954 | #define I2C_TXABRT_ABRT_7B_ADDR_NOACK (1 << 0) | ||
4955 | |||
4956 | /* */ | ||
4957 | #define I2C_DMACR_TDEN (1 << 1) | ||
4958 | #define I2C_DMACR_RDEN (1 << 0) | ||
4959 | |||
4960 | /* */ | ||
4961 | #define I2C_DMATDLR_TDLR_BIT 0 | ||
4962 | #define I2C_DMATDLR_TDLR_MASK (0x1f << I2C_DMATDLR_TDLR_BIT) | ||
4963 | |||
4964 | /* */ | ||
4965 | #define I2C_DMARDLR_RDLR_BIT 0 | ||
4966 | #define I2C_DMARDLR_RDLR_MASK (0x1f << I2C_DMARDLR_RDLR_BIT) | ||
4967 | |||
4968 | /* I2C Enable Status Register (I2C_ENSTA) */ | ||
4969 | |||
4970 | #define I2C_ENSTA_SLVRDLST (1 << 2) | ||
4971 | #define I2C_ENSTA_SLVDISB (1 << 1) | ||
4972 | #define I2C_ENSTA_I2CEN (1 << 0) /* when read as 1, i2c is deemed to be in an enabled state | ||
4973 | when read as 0, i2c is deemed completely inactive. The cpu can | ||
4974 | safely read this bit anytime .When this bit is read as 0 ,the cpu can | ||
4975 | safely read SLVRDLST and SLVDISB */ | ||
4976 | |||
4977 | /* I2C standard mode high count register(I2CSHCNT) */ | ||
4978 | #define I2CSHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8)) | ||
4979 | |||
4980 | /* I2C standard mode low count register(I2CSLCNT) */ | ||
4981 | #define I2CSLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1)) | ||
4982 | |||
4983 | /* I2C fast mode high count register(I2CFHCNT) */ | ||
4984 | #define I2CFHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8)) | ||
4985 | |||
4986 | /* I2C fast mode low count register(I2CFLCNT) */ | ||
4987 | #define I2CFLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1)) | ||
4988 | |||
4989 | #ifndef __MIPS_ASSEMBLER | ||
4990 | |||
4991 | /*************************************************************************** | ||
4992 | * I2C | ||
4993 | ***************************************************************************/ | ||
4994 | |||
4995 | #define __i2c_enable(n) ( REG_I2C_ENB(n) = 1 ) | ||
4996 | #define __i2c_disable(n) ( REG_I2C_ENB(n) = 0 ) | ||
4997 | |||
4998 | #define __i2c_is_enable(n) ( REG_I2C_ENSTA(n) & I2C_ENB_I2CENB ) | ||
4999 | #define __i2c_is_disable(n) ( !(REG_I2C_ENSTA(n) & I2C_ENB_I2CENB) ) | ||
5000 | |||
5001 | #define __i2c_abrt(n) ( REG_I2C_TXABRT(n) != 0 ) | ||
5002 | #define __i2c_abrt_intr(n) (REG_I2C_INTST(n) & I2C_INTST_TXABT) | ||
5003 | #define __i2c_master_active(n) ( REG_I2C_STA(n) & I2C_STA_MSTACT ) | ||
5004 | #define __i2c_abrt_7b_addr_nack(n) ( REG_I2C_TXABRT(n) & I2C_TXABRT_ABRT_7B_ADDR_NOACK ) | ||
5005 | #define __i2c_txfifo_is_empty(n) ( REG_I2C_STA(n) & I2C_STA_TFE ) | ||
5006 | #define __i2c_clear_interrupts(ret,n) ( ret = REG_I2C_CINTR(n) ) | ||
5007 | |||
5008 | #define __i2c_dma_rd_enable(n) SETREG8(I2C_DMACR(n),1 << 0) | ||
5009 | #define __i2c_dma_rd_disable(n) CLRREG8(I2C_DMACR(n),1 << 0) | ||
5010 | #define __i2c_dma_td_enable(n) SETREG8(I2C_DMACR(n),1 << 1) | ||
5011 | #define __i2c_dma_td_disable(n) CLRREG8(I2C_DMACR(n),1 << 1) | ||
5012 | |||
5013 | #define __i2c_send_stop(n) CLRREG8(I2C_CTRL(n), I2C_CTRL_STPHLD) | ||
5014 | #define __i2c_nsend_stop(n) SETREG8(I2C_CTRL(n), I2C_CTRL_STPHLD) | ||
5015 | |||
5016 | #define __i2c_set_dma_td_level(n,data) OUTREG8(I2C_DMATDLR(n),data) | ||
5017 | #define __i2c_set_dma_rd_level(n,data) OUTREG8(I2C_DMARDLR(n),data) | ||
5018 | |||
5019 | /* | ||
5020 | #define __i2c_set_clk(dev_clk, i2c_clk) \ | ||
5021 | ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 ) | ||
5022 | */ | ||
5023 | |||
5024 | #define __i2c_read(n) ( REG_I2C_DC(n) & 0xff ) | ||
5025 | #define __i2c_write(val,n) ( REG_I2C_DC(n) = (val) ) | ||
5026 | |||
5027 | #endif /* __MIPS_ASSEMBLER */ | ||
5028 | |||
5029 | #define IPU_BASE 0xB3080000 | ||
5030 | |||
5031 | /************************************************************************* | ||
5032 | * IPU (Image Processing Unit) | ||
5033 | *************************************************************************/ | ||
5034 | #define IPU_V_BASE 0xB3080000 | ||
5035 | #define IPU_P_BASE 0x13080000 | ||
5036 | |||
5037 | /* Register offset */ | ||
5038 | #define REG_CTRL 0x0 /* IPU Control Register */ | ||
5039 | #define REG_STATUS 0x4 /* IPU Status Register */ | ||
5040 | #define REG_D_FMT 0x8 /* Data Format Register */ | ||
5041 | #define REG_Y_ADDR 0xc /* Input Y or YUV422 Packaged Data Address Register */ | ||
5042 | #define REG_U_ADDR 0x10 /* Input U Data Address Register */ | ||
5043 | #define REG_V_ADDR 0x14 /* Input V Data Address Register */ | ||
5044 | #define REG_IN_FM_GS 0x18 /* Input Geometric Size Register */ | ||
5045 | #define REG_Y_STRIDE 0x1c /* Input Y Data Line Stride Register */ | ||
5046 | #define REG_UV_STRIDE 0x20 /* Input UV Data Line Stride Register */ | ||
5047 | #define REG_OUT_ADDR 0x24 /* Output Frame Start Address Register */ | ||
5048 | #define REG_OUT_GS 0x28 /* Output Geometric Size Register */ | ||
5049 | #define REG_OUT_STRIDE 0x2c /* Output Data Line Stride Register */ | ||
5050 | #define REG_RSZ_COEF_INDEX 0x30 /* Resize Coefficients Table Index Register */ | ||
5051 | #define REG_CSC_CO_COEF 0x34 /* CSC C0 Coefficient Register */ | ||
5052 | #define REG_CSC_C1_COEF 0x38 /* CSC C1 Coefficient Register */ | ||
5053 | #define REG_CSC_C2_COEF 0x3c /* CSC C2 Coefficient Register */ | ||
5054 | #define REG_CSC_C3_COEF 0x40 /* CSC C3 Coefficient Register */ | ||
5055 | #define REG_CSC_C4_COEF 0x44 /* CSC C4 Coefficient Register */ | ||
5056 | #define HRSZ_LUT_BASE 0x48 /* Horizontal Resize Coefficients Look Up Table Register group */ | ||
5057 | #define VRSZ_LUT_BASE 0x4c /* Virtical Resize Coefficients Look Up Table Register group */ | ||
5058 | #define REG_CSC_OFSET_PARA 0x50 /* CSC Offset Parameter Register */ | ||
5059 | #define REG_Y_PHY_T_ADDR 0x54 /* Input Y Physical Table Address Register */ | ||
5060 | #define REG_U_PHY_T_ADDR 0x58 /* Input U Physical Table Address Register */ | ||
5061 | #define REG_V_PHY_T_ADDR 0x5c /* Input V Physical Table Address Register */ | ||
5062 | #define REG_OUT_PHY_T_ADDR 0x60 /* Output Physical Table Address Register */ | ||
5063 | |||
5064 | /* REG_CTRL: IPU Control Register */ | ||
5065 | #define IPU_CE_SFT 0x0 | ||
5066 | #define IPU_CE_MSK 0x1 | ||
5067 | #define IPU_RUN_SFT 0x1 | ||
5068 | #define IPU_RUN_MSK 0x1 | ||
5069 | #define HRSZ_EN_SFT 0x2 | ||
5070 | #define HRSZ_EN_MSK 0x1 | ||
5071 | #define VRSZ_EN_SFT 0x3 | ||
5072 | #define VRSZ_EN_MSK 0x1 | ||
5073 | #define CSC_EN_SFT 0x4 | ||
5074 | #define CSC_EN_MSK 0x1 | ||
5075 | #define FM_IRQ_EN_SFT 0x5 | ||
5076 | #define FM_IRQ_EN_MSK 0x1 | ||
5077 | #define IPU_RST_SFT 0x6 | ||
5078 | #define IPU_RST_MSK 0x1 | ||
5079 | #define H_SCALE_SFT 0x8 | ||
5080 | #define H_SCALE_MSK 0x1 | ||
5081 | #define V_SCALE_SFT 0x9 | ||
5082 | #define V_SCALE_MSK 0x1 | ||
5083 | #define PKG_SEL_SFT 0xA | ||
5084 | #define PKG_SEL_MSK 0x1 | ||
5085 | #define LCDC_SEL_SFT 0xB | ||
5086 | #define LCDC_SEL_MSK 0x1 | ||
5087 | #define SPAGE_MAP_SFT 0xC | ||
5088 | #define SPAGE_MAP_MSK 0x1 | ||
5089 | #define DPAGE_SEL_SFT 0xD | ||
5090 | #define DPAGE_SEL_MSK 0x1 | ||
5091 | #define DISP_SEL_SFT 0xE | ||
5092 | #define DISP_SEL_MSK 0x1 | ||
5093 | #define FIELD_CONF_EN_SFT 15 | ||
5094 | #define FIELD_CONF_EN_MSK 1 | ||
5095 | #define FIELD_SEL_SFT 16 | ||
5096 | #define FIELD_SEL_MSK 1 | ||
5097 | #define DFIX_SEL_SFT 17 | ||
5098 | #define DFIX_SEL_MSK 1 | ||
5099 | |||
5100 | /* REG_STATUS: IPU Status Register */ | ||
5101 | #define OUT_END_SFT 0x0 | ||
5102 | #define OUT_END_MSK 0x1 | ||
5103 | #define FMT_ERR_SFT 0x1 | ||
5104 | #define FMT_ERR_MSK 0x1 | ||
5105 | #define SIZE_ERR_SFT 0x2 | ||
5106 | #define SIZE_ERR_MSK 0x1 | ||
5107 | |||
5108 | /* D_FMT: Data Format Register */ | ||
5109 | #define IN_FMT_SFT 0x0 | ||
5110 | #define IN_FMT_MSK 0x3 | ||
5111 | #define IN_OFT_SFT 0x2 | ||
5112 | #define IN_OFT_MSK 0x3 | ||
5113 | #define YUV_PKG_OUT_SFT 0x10 | ||
5114 | #define YUV_PKG_OUT_MSK 0x7 | ||
5115 | #define OUT_FMT_SFT 0x13 | ||
5116 | #define OUT_FMT_MSK 0x3 | ||
5117 | #define RGB_OUT_OFT_SFT 0x15 | ||
5118 | #define RGB_OUT_OFT_MSK 0x7 | ||
5119 | #define RGB888_FMT_SFT 0x18 | ||
5120 | #define RGB888_FMT_MSK 0x1 | ||
5121 | |||
5122 | /* IN_FM_GS: Input Geometric Size Register */ | ||
5123 | #define IN_FM_H_SFT 0x0 | ||
5124 | #define IN_FM_H_MSK 0xFFF | ||
5125 | #define IN_FM_W_SFT 0x10 | ||
5126 | #define IN_FM_W_MSK 0xFFF | ||
5127 | |||
5128 | /* Y_STRIDE: Input Y Data Line Stride Register */ | ||
5129 | #define Y_S_SFT 0x0 | ||
5130 | #define Y_S_MSK 0x3FFF | ||
5131 | |||
5132 | /* UV_STRIDE: Input UV Data Line Stride Register */ | ||
5133 | #define V_S_SFT 0x0 | ||
5134 | #define V_S_MSK 0x1FFF | ||
5135 | #define U_S_SFT 0x10 | ||
5136 | #define U_S_MSK 0x1FFF | ||
5137 | |||
5138 | /* OUT_GS: Output Geometric Size Register */ | ||
5139 | #define OUT_FM_H_SFT 0x0 | ||
5140 | #define OUT_FM_H_MSK 0x1FFF | ||
5141 | #define OUT_FM_W_SFT 0x10 | ||
5142 | #define OUT_FM_W_MSK 0x7FFF | ||
5143 | |||
5144 | /* OUT_STRIDE: Output Data Line Stride Register */ | ||
5145 | #define OUT_S_SFT 0x0 | ||
5146 | #define OUT_S_MSK 0xFFFF | ||
5147 | |||
5148 | /* RSZ_COEF_INDEX: Resize Coefficients Table Index Register */ | ||
5149 | #define VE_IDX_SFT 0x0 | ||
5150 | #define VE_IDX_MSK 0x1F | ||
5151 | #define HE_IDX_SFT 0x10 | ||
5152 | #define HE_IDX_MSK 0x1F | ||
5153 | |||
5154 | /* CSC_CX_COEF: CSC CX Coefficient Register */ | ||
5155 | #define CX_COEF_SFT 0x0 | ||
5156 | #define CX_COEF_MSK 0xFFF | ||
5157 | |||
5158 | /* HRSZ_LUT_BASE, VRSZ_LUT_BASE: Resize Coefficients Look Up Table Register group */ | ||
5159 | #define LUT_LEN 20 | ||
5160 | |||
5161 | #define OUT_N_SFT 0x0 | ||
5162 | #define OUT_N_MSK 0x1 | ||
5163 | #define IN_N_SFT 0x1 | ||
5164 | #define IN_N_MSK 0x1 | ||
5165 | #define W_COEF_SFT 0x2 | ||
5166 | #define W_COEF_MSK 0x3FF | ||
5167 | |||
5168 | /* CSC_OFSET_PARA: CSC Offset Parameter Register */ | ||
5169 | #define CHROM_OF_SFT 0x10 | ||
5170 | #define CHROM_OF_MSK 0xFF | ||
5171 | #define LUMA_OF_SFT 0x00 | ||
5172 | #define LUMA_OF_MSK 0xFF | ||
5173 | |||
5174 | #ifndef __MIPS_ASSEMBLER | ||
5175 | |||
5176 | #if 0 | ||
5177 | /************************************************************************* | ||
5178 | * IPU (Image Processing Unit) | ||
5179 | *************************************************************************/ | ||
5180 | #define u32 volatile unsigned long | ||
5181 | |||
5182 | #define write_reg(reg, val) \ | ||
5183 | do { \ | ||
5184 | *(u32 *)(reg) = (val); \ | ||
5185 | } while(0) | ||
5186 | |||
5187 | #define read_reg(reg, off) (*(u32 *)((reg)+(off))) | ||
5188 | |||
5189 | #define set_ipu_fmt(rgb_888_out_fmt, rgb_out_oft, out_fmt, yuv_pkg_out, in_oft, in_fmt ) \ | ||
5190 | ({ write_reg( (IPU_V_BASE + REG_D_FMT), ((in_fmt) & IN_FMT_MSK)<<IN_FMT_SFT \ | ||
5191 | | ((in_oft) & IN_OFT_MSK)<< IN_OFT_SFT \ | ||
5192 | | ((out_fmt) & OUT_FMT_MSK)<<OUT_FMT_SFT \ | ||
5193 | | ((yuv_pkg_out) & YUV_PKG_OUT_MSK ) << YUV_PKG_OUT_SFT \ | ||
5194 | | ((rgb_888_out_fmt) & RGB888_FMT_MSK ) << RGB888_FMT_SFT \ | ||
5195 | | ((rgb_out_oft) & RGB_OUT_OFT_MSK ) << RGB_OUT_OFT_SFT); \ | ||
5196 | }) | ||
5197 | #define set_y_addr(y_addr) \ | ||
5198 | ({ write_reg( (IPU_V_BASE + REG_Y_ADDR), y_addr); \ | ||
5199 | }) | ||
5200 | #define set_u_addr(u_addr) \ | ||
5201 | ({ write_reg( (IPU_V_BASE + REG_U_ADDR), u_addr); \ | ||
5202 | }) | ||
5203 | |||
5204 | #define set_v_addr(v_addr) \ | ||
5205 | ({ write_reg( (IPU_V_BASE + REG_V_ADDR), v_addr); \ | ||
5206 | }) | ||
5207 | |||
5208 | #define set_y_phy_t_addr(y_phy_t_addr) \ | ||
5209 | ({ write_reg( (IPU_V_BASE + REG_Y_PHY_T_ADDR), y_phy_t_addr); \ | ||
5210 | }) | ||
5211 | |||
5212 | #define set_u_phy_t_addr(u_phy_t_addr) \ | ||
5213 | ({ write_reg( (IPU_V_BASE + REG_U_PHY_T_ADDR), u_phy_t_addr); \ | ||
5214 | }) | ||
5215 | |||
5216 | #define set_v_phy_t_addr(v_phy_t_addr) \ | ||
5217 | ({ write_reg( (IPU_V_BASE + REG_V_PHY_T_ADDR), v_phy_t_addr); \ | ||
5218 | }) | ||
5219 | |||
5220 | #define set_out_phy_t_addr(out_phy_t_addr) \ | ||
5221 | ({ write_reg( (IPU_V_BASE + REG_OUT_PHY_T_ADDR), out_phy_t_addr); \ | ||
5222 | }) | ||
5223 | |||
5224 | #define set_inframe_gsize(width, height, y_stride, u_stride, v_stride) \ | ||
5225 | ({ write_reg( (IPU_V_BASE + REG_IN_FM_GS), ((width) & IN_FM_W_MSK)<<IN_FM_W_SFT \ | ||
5226 | | ((height) & IN_FM_H_MSK)<<IN_FM_H_SFT); \ | ||
5227 | write_reg( (IPU_V_BASE + REG_Y_STRIDE), ((y_stride) & Y_S_MSK)<<Y_S_SFT); \ | ||
5228 | write_reg( (IPU_V_BASE + REG_UV_STRIDE), ((u_stride) & U_S_MSK)<<U_S_SFT \ | ||
5229 | | ((v_stride) & V_S_MSK)<<V_S_SFT); \ | ||
5230 | }) | ||
5231 | #define set_out_addr(out_addr) \ | ||
5232 | ({ write_reg( (IPU_V_BASE + REG_OUT_ADDR), out_addr); \ | ||
5233 | }) | ||
5234 | #define set_outframe_gsize(width, height, o_stride) \ | ||
5235 | ({ write_reg( (IPU_V_BASE + REG_OUT_GS), ((width) & OUT_FM_W_MSK)<<OUT_FM_W_SFT \ | ||
5236 | | ((height) & OUT_FM_H_MSK)<<OUT_FM_H_SFT); \ | ||
5237 | write_reg( (IPU_V_BASE + REG_OUT_STRIDE), ((o_stride) & OUT_S_MSK)<<OUT_S_SFT); \ | ||
5238 | }) | ||
5239 | #define set_rsz_lut_end(h_end, v_end) \ | ||
5240 | ({ write_reg( (IPU_V_BASE + REG_RSZ_COEF_INDEX), ((h_end) & HE_IDX_MSK)<<HE_IDX_SFT \ | ||
5241 | | ((v_end) & VE_IDX_MSK)<<VE_IDX_SFT); \ | ||
5242 | }) | ||
5243 | #define set_csc_c0(c0_coeff) \ | ||
5244 | ({ write_reg( (IPU_V_BASE + REG_CSC_CO_COEF), ((c0_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \ | ||
5245 | }) | ||
5246 | #define set_csc_c1(c1_coeff) \ | ||
5247 | ({ write_reg( (IPU_V_BASE + REG_CSC_C1_COEF), ((c1_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \ | ||
5248 | }) | ||
5249 | #define set_csc_c2(c2_coeff) \ | ||
5250 | ({ write_reg( (IPU_V_BASE + REG_CSC_C2_COEF), ((c2_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \ | ||
5251 | }) | ||
5252 | #define set_csc_c3(c3_coeff) \ | ||
5253 | ({ write_reg( (IPU_V_BASE + REG_CSC_C3_COEF), ((c3_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \ | ||
5254 | }) | ||
5255 | #define set_csc_c4(c4_coeff) \ | ||
5256 | ({ write_reg( (IPU_V_BASE + REG_CSC_C4_COEF), ((c4_coeff) & CX_COEF_MSK)<<CX_COEF_SFT); \ | ||
5257 | }) | ||
5258 | #define set_hrsz_lut_coef(coef, in_n, out_n) \ | ||
5259 | ({ write_reg( (IPU_V_BASE + HRSZ_LUT_BASE ), ((coef) & W_COEF_MSK)<<W_COEF_SFT \ | ||
5260 | | ((in_n) & IN_N_MSK)<<IN_N_SFT | ((out_n) & OUT_N_MSK)<<OUT_N_SFT); \ | ||
5261 | }) | ||
5262 | #define set_vrsz_lut_coef(coef, in_n, out_n) \ | ||
5263 | ({ write_reg( (IPU_V_BASE + VRSZ_LUT_BASE), ((coef) & W_COEF_MSK)<<W_COEF_SFT \ | ||
5264 | | ((in_n) & IN_N_MSK)<<IN_N_SFT | ((out_n) & OUT_N_MSK)<<OUT_N_SFT); \ | ||
5265 | }) | ||
5266 | |||
5267 | #define set_primary_ctrl(vrsz_en, hrsz_en,csc_en, irq_en) \ | ||
5268 | ({ write_reg( (IPU_V_BASE + REG_CTRL), ((irq_en) & FM_IRQ_EN_MSK)<<FM_IRQ_EN_SFT \ | ||
5269 | | ((vrsz_en) & VRSZ_EN_MSK)<<VRSZ_EN_SFT \ | ||
5270 | | ((hrsz_en) & HRSZ_EN_MSK)<<HRSZ_EN_SFT \ | ||
5271 | | ((csc_en) & CSC_EN_MSK)<<CSC_EN_SFT \ | ||
5272 | | (read_reg(IPU_V_BASE, REG_CTRL)) \ | ||
5273 | & ~(CSC_EN_MSK<<CSC_EN_SFT | FM_IRQ_EN_MSK<<FM_IRQ_EN_SFT | VRSZ_EN_MSK<<VRSZ_EN_SFT | HRSZ_EN_MSK<<HRSZ_EN_SFT ) ); \ | ||
5274 | }) | ||
5275 | |||
5276 | #define set_source_ctrl(pkg_sel, spage_sel) \ | ||
5277 | ({ write_reg( (IPU_V_BASE + REG_CTRL), ((pkg_sel) & PKG_SEL_MSK )<< PKG_SEL_SFT \ | ||
5278 | | ((spage_sel) & SPAGE_MAP_MSK )<< SPAGE_MAP_SFT \ | ||
5279 | | (read_reg(IPU_V_BASE, REG_CTRL)) \ | ||
5280 | & ~(SPAGE_MAP_MSK << SPAGE_MAP_SFT | PKG_SEL_MSK << PKG_SEL_SFT ) ) ; \ | ||
5281 | }) | ||
5282 | |||
5283 | #define set_out_ctrl(lcdc_sel, dpage_sel, disp_sel) \ | ||
5284 | ({ write_reg( (IPU_V_BASE + REG_CTRL), ((lcdc_sel) & LCDC_SEL_MSK )<< LCDC_SEL_SFT \ | ||
5285 | | ((dpage_sel) & DPAGE_SEL_MSK )<< DPAGE_SEL_SFT \ | ||
5286 | | ((disp_sel) & DISP_SEL_MSK )<< DISP_SEL_SFT \ | ||
5287 | | (read_reg(IPU_V_BASE, REG_CTRL)) \ | ||
5288 | & ~(LCDC_SEL_MSK<< LCDC_SEL_SFT | DPAGE_SEL_MSK << DPAGE_SEL_SFT | DISP_SEL_MSK << DISP_SEL_SFT ) ); \ | ||
5289 | }) | ||
5290 | |||
5291 | #define set_scale_ctrl(v_scal, h_scal) \ | ||
5292 | ({ write_reg( (IPU_V_BASE + REG_CTRL), ((v_scal) & V_SCALE_MSK)<<V_SCALE_SFT \ | ||
5293 | | ((h_scal) & H_SCALE_MSK)<<H_SCALE_SFT \ | ||
5294 | | (read_reg(IPU_V_BASE, REG_CTRL)) & ~(V_SCALE_MSK<<V_SCALE_SFT | H_SCALE_MSK<<H_SCALE_SFT ) ); \ | ||
5295 | }) | ||
5296 | |||
5297 | #define set_csc_ofset_para(chrom_oft, luma_oft) \ | ||
5298 | ({ write_reg( (IPU_V_BASE + REG_CSC_OFSET_PARA ), ((chrom_oft) & CHROM_OF_MSK ) << CHROM_OF_SFT \ | ||
5299 | | ((luma_oft) & LUMA_OF_MSK ) << LUMA_OF_SFT ) ; \ | ||
5300 | }) | ||
5301 | |||
5302 | #define sw_reset_ipu() \ | ||
5303 | ({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) \ | ||
5304 | | IPU_RST_MSK<<IPU_RST_SFT); \ | ||
5305 | }) | ||
5306 | #define enable_ipu() \ | ||
5307 | ({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) | 0x1); \ | ||
5308 | }) | ||
5309 | #define disable_ipu() \ | ||
5310 | ({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) & ~0x1); \ | ||
5311 | }) | ||
5312 | #define run_ipu() \ | ||
5313 | ({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) | 0x2); \ | ||
5314 | }) | ||
5315 | #define stop_ipu() \ | ||
5316 | ({ write_reg( (IPU_V_BASE + REG_CTRL), (read_reg(IPU_V_BASE, REG_CTRL)) & ~0x2); \ | ||
5317 | }) | ||
5318 | |||
5319 | #define polling_end_flag() \ | ||
5320 | ({ (read_reg(IPU_V_BASE, REG_STATUS)) & 0x01; \ | ||
5321 | }) | ||
5322 | |||
5323 | #define start_vlut_coef_write() \ | ||
5324 | ({ write_reg( (IPU_V_BASE + VRSZ_LUT_BASE), ( 0x1<<12 ) ); \ | ||
5325 | }) | ||
5326 | |||
5327 | #define start_hlut_coef_write() \ | ||
5328 | ({ write_reg( (IPU_V_BASE + HRSZ_LUT_BASE), ( 0x01<<12 ) ); \ | ||
5329 | }) | ||
5330 | |||
5331 | #define clear_end_flag() \ | ||
5332 | ({ write_reg( (IPU_V_BASE + REG_STATUS), 0); \ | ||
5333 | }) | ||
5334 | #endif /* #if 0 */ | ||
5335 | |||
5336 | #endif /* __MIPS_ASSEMBLER */ | ||
5337 | |||
5338 | #define LCD_BASE 0xB3050000 | ||
5339 | #define SLCD_BASE 0xB3050000 | ||
5340 | |||
5341 | /************************************************************************* | ||
5342 | * SLCD (Smart LCD Controller) | ||
5343 | *************************************************************************/ | ||
5344 | |||
5345 | #define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */ | ||
5346 | #define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */ | ||
5347 | #define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */ | ||
5348 | #define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */ | ||
5349 | |||
5350 | #define REG_SLCD_CFG REG32(SLCD_CFG) | ||
5351 | #define REG_SLCD_CTRL REG8(SLCD_CTRL) | ||
5352 | #define REG_SLCD_STATE REG8(SLCD_STATE) | ||
5353 | #define REG_SLCD_DATA REG32(SLCD_DATA) | ||
5354 | |||
5355 | /* SLCD Configure Register */ | ||
5356 | #define SLCD_CFG_DWIDTH_BIT 10 | ||
5357 | #define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT) | ||
5358 | #define SLCD_CFG_DWIDTH_18BIT (0 << SLCD_CFG_DWIDTH_BIT) | ||
5359 | #define SLCD_CFG_DWIDTH_16BIT (1 << SLCD_CFG_DWIDTH_BIT) | ||
5360 | #define SLCD_CFG_DWIDTH_8BIT_x3 (2 << SLCD_CFG_DWIDTH_BIT) | ||
5361 | #define SLCD_CFG_DWIDTH_8BIT_x2 (3 << SLCD_CFG_DWIDTH_BIT) | ||
5362 | #define SLCD_CFG_DWIDTH_8BIT_x1 (4 << SLCD_CFG_DWIDTH_BIT) | ||
5363 | #define SLCD_CFG_DWIDTH_24BIT (5 << SLCD_CFG_DWIDTH_BIT) | ||
5364 | #define SLCD_CFG_DWIDTH_9BIT_x2 (7 << SLCD_CFG_DWIDTH_BIT) | ||
5365 | #define SLCD_CFG_CWIDTH_BIT (8) | ||
5366 | #define SLCD_CFG_CWIDTH_MASK (0x3 << SLCD_CFG_CWIDTH_BIT) | ||
5367 | #define SLCD_CFG_CWIDTH_16BIT (0 << SLCD_CFG_CWIDTH_BIT) | ||
5368 | #define SLCD_CFG_CWIDTH_8BIT (1 << SLCD_CFG_CWIDTH_BIT) | ||
5369 | #define SLCD_CFG_CWIDTH_18BIT (2 << SLCD_CFG_CWIDTH_BIT) | ||
5370 | #define SLCD_CFG_CWIDTH_24BIT (3 << SLCD_CFG_CWIDTH_BIT) | ||
5371 | #define SLCD_CFG_CS_ACTIVE_LOW (0 << 4) | ||
5372 | #define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4) | ||
5373 | #define SLCD_CFG_RS_CMD_LOW (0 << 3) | ||
5374 | #define SLCD_CFG_RS_CMD_HIGH (1 << 3) | ||
5375 | #define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1) | ||
5376 | #define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1) | ||
5377 | #define SLCD_CFG_TYPE_PARALLEL (0 << 0) | ||
5378 | #define SLCD_CFG_TYPE_SERIAL (1 << 0) | ||
5379 | |||
5380 | /* SLCD Control Register */ | ||
5381 | #define SLCD_CTRL_DMA_MODE (1 << 2) | ||
5382 | #define SLCD_CTRL_DMA_START (1 << 1) | ||
5383 | #define SLCD_CTRL_DMA_EN (1 << 0) | ||
5384 | |||
5385 | /* SLCD Status Register */ | ||
5386 | #define SLCD_STATE_BUSY (1 << 0) | ||
5387 | |||
5388 | /* SLCD Data Register */ | ||
5389 | #define SLCD_DATA_RS_DATA (0 << 31) | ||
5390 | #define SLCD_DATA_RS_COMMAND (1 << 31) | ||
5391 | |||
5392 | /************************************************************************* | ||
5393 | * LCD (LCD Controller) | ||
5394 | *************************************************************************/ | ||
5395 | #define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */ | ||
5396 | #define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */ | ||
5397 | #define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */ | ||
5398 | |||
5399 | #define LCD_OSDC (LCD_BASE + 0x100) /* LCD OSD Configure Register */ | ||
5400 | #define LCD_OSDCTRL (LCD_BASE + 0x104) /* LCD OSD Control Register */ | ||
5401 | #define LCD_OSDS (LCD_BASE + 0x108) /* LCD OSD Status Register */ | ||
5402 | #define LCD_BGC (LCD_BASE + 0x10C) /* LCD Background Color Register */ | ||
5403 | #define LCD_KEY0 (LCD_BASE + 0x110) /* LCD Foreground Color Key Register 0 */ | ||
5404 | #define LCD_KEY1 (LCD_BASE + 0x114) /* LCD Foreground Color Key Register 1 */ | ||
5405 | #define LCD_ALPHA (LCD_BASE + 0x118) /* LCD ALPHA Register */ | ||
5406 | #define LCD_IPUR (LCD_BASE + 0x11C) /* LCD IPU Restart Register */ | ||
5407 | #define LCD_RGBC (LCD_BASE + 0x90) /* RGB Controll Register */ | ||
5408 | |||
5409 | #define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */ | ||
5410 | #define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */ | ||
5411 | #define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */ | ||
5412 | |||
5413 | #define LCD_XYP0 (LCD_BASE + 0x120) /* Foreground 0 XY Position Register */ | ||
5414 | #define LCD_XYP0_PART2 (LCD_BASE + 0x1F0) /* Foreground 0 PART2 XY Position Register */ | ||
5415 | #define LCD_XYP1 (LCD_BASE + 0x124) /* Foreground 1 XY Position Register */ | ||
5416 | #define LCD_SIZE0 (LCD_BASE + 0x128) /* Foreground 0 Size Register */ | ||
5417 | #define LCD_SIZE0_PART2 (LCD_BASE + 0x1F4) /*Foreground 0 PART2 Size Register */ | ||
5418 | #define LCD_SIZE1 (LCD_BASE + 0x12C) /* Foreground 1 Size Register */ | ||
5419 | |||
5420 | #define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */ | ||
5421 | #define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */ | ||
5422 | #define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */ | ||
5423 | #define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */ | ||
5424 | #define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */ | ||
5425 | #define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */ | ||
5426 | #define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */ | ||
5427 | #define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */ | ||
5428 | #define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */ | ||
5429 | #define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */ | ||
5430 | #define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */ | ||
5431 | |||
5432 | #define LCD_OFFS0 (LCD_BASE + 0x60) /* DMA Offsize Register 0 */ | ||
5433 | #define LCD_PW0 (LCD_BASE + 0x64) /* DMA Page Width Register 0 */ | ||
5434 | #define LCD_CNUM0 (LCD_BASE + 0x68) /* DMA Command Counter Register 0 */ | ||
5435 | #define LCD_DESSIZE0 (LCD_BASE + 0x6C) /* Foreground Size in Descriptor 0 Register*/ | ||
5436 | |||
5437 | #define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */ | ||
5438 | #define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */ | ||
5439 | #define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */ | ||
5440 | #define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */ | ||
5441 | #define LCD_OFFS1 (LCD_BASE + 0x70) /* DMA Offsize Register 1 */ | ||
5442 | #define LCD_PW1 (LCD_BASE + 0x74) /* DMA Page Width Register 1 */ | ||
5443 | #define LCD_CNUM1 (LCD_BASE + 0x78) /* DMA Command Counter Register 1 */ | ||
5444 | #define LCD_DESSIZE1 (LCD_BASE + 0x7C) /* Foreground Size in Descriptor 1 Register*/ | ||
5445 | |||
5446 | #define LCD_DA0_PART2 (LCD_BASE + 0x1C0) /* Descriptor Address Register PART2 */ | ||
5447 | #define LCD_SA0_PART2 (LCD_BASE + 0x1C4) /* Source Address Register PART2 */ | ||
5448 | #define LCD_FID0_PART2 (LCD_BASE + 0x1C8) /* Frame ID Register PART2 */ | ||
5449 | #define LCD_CMD0_PART2 (LCD_BASE + 0x1CC) /* DMA Command Register PART2 */ | ||
5450 | #define LCD_OFFS0_PART2 (LCD_BASE + 0x1E0) /* DMA Offsize Register PART2 */ | ||
5451 | #define LCD_PW0_PART2 (LCD_BASE + 0x1E4) /* DMA Command Counter Register PART2 */ | ||
5452 | #define LCD_CNUM0_PART2 (LCD_BASE + 0x1E8) /* Foreground Size in Descriptor PART2 Register */ | ||
5453 | #define LCD_DESSIZE0_PART2 (LCD_BASE + 0x1EC) /* */ | ||
5454 | #define LCD_PCFG (LCD_BASE + 0x2C0) | ||
5455 | |||
5456 | #define REG_LCD_CFG REG32(LCD_CFG) | ||
5457 | #define REG_LCD_CTRL REG32(LCD_CTRL) | ||
5458 | #define REG_LCD_STATE REG32(LCD_STATE) | ||
5459 | |||
5460 | #define REG_LCD_OSDC REG16(LCD_OSDC) | ||
5461 | #define REG_LCD_OSDCTRL REG16(LCD_OSDCTRL) | ||
5462 | #define REG_LCD_OSDS REG16(LCD_OSDS) | ||
5463 | #define REG_LCD_BGC REG32(LCD_BGC) | ||
5464 | #define REG_LCD_KEY0 REG32(LCD_KEY0) | ||
5465 | #define REG_LCD_KEY1 REG32(LCD_KEY1) | ||
5466 | #define REG_LCD_ALPHA REG8(LCD_ALPHA) | ||
5467 | #define REG_LCD_IPUR REG32(LCD_IPUR) | ||
5468 | |||
5469 | #define REG_LCD_VAT REG32(LCD_VAT) | ||
5470 | #define REG_LCD_DAH REG32(LCD_DAH) | ||
5471 | #define REG_LCD_DAV REG32(LCD_DAV) | ||
5472 | |||
5473 | #define REG_LCD_XYP0 REG32(LCD_XYP0) | ||
5474 | #define REG_LCD_XYP0_PART2 REG32(LCD_XYP0_PART2) | ||
5475 | #define REG_LCD_XYP1 REG32(LCD_XYP1) | ||
5476 | #define REG_LCD_SIZE0 REG32(LCD_SIZE0) | ||
5477 | #define REG_LCD_SIZE0_PART2 REG32(LCD_SIZE0_PART2) | ||
5478 | #define REG_LCD_SIZE1 REG32(LCD_SIZE1) | ||
5479 | |||
5480 | #define REG_LCD_RGBC REG16(LCD_RGBC) | ||
5481 | |||
5482 | #define REG_LCD_VSYNC REG32(LCD_VSYNC) | ||
5483 | #define REG_LCD_HSYNC REG32(LCD_HSYNC) | ||
5484 | #define REG_LCD_PS REG32(LCD_PS) | ||
5485 | #define REG_LCD_CLS REG32(LCD_CLS) | ||
5486 | #define REG_LCD_SPL REG32(LCD_SPL) | ||
5487 | #define REG_LCD_REV REG32(LCD_REV) | ||
5488 | #define REG_LCD_IID REG32(LCD_IID) | ||
5489 | #define REG_LCD_DA0 REG32(LCD_DA0) | ||
5490 | #define REG_LCD_SA0 REG32(LCD_SA0) | ||
5491 | #define REG_LCD_FID0 REG32(LCD_FID0) | ||
5492 | #define REG_LCD_CMD0 REG32(LCD_CMD0) | ||
5493 | |||
5494 | #define REG_LCD_OFFS0 REG32(LCD_OFFS0) | ||
5495 | #define REG_LCD_PW0 REG32(LCD_PW0) | ||
5496 | #define REG_LCD_CNUM0 REG32(LCD_CNUM0) | ||
5497 | #define REG_LCD_DESSIZE0 REG32(LCD_DESSIZE0) | ||
5498 | |||
5499 | #define REG_LCD_DA0_PART2 REG32(LCD_DA0_PART2) | ||
5500 | #define REG_LCD_SA0_PART2 REG32(LCD_SA0_PART2) | ||
5501 | #define REG_LCD_FID0_PART2 REG32(LCD_FID0_PART2) | ||
5502 | #define REG_LCD_CMD0_PART2 REG32(LCD_CMD0_PART2) | ||
5503 | #define REG_LCD_OFFS0_PART2 REG32(LCD_OFFS0_PART2) | ||
5504 | #define REG_LCD_PW0_PART2 REG32(LCD_PW0_PART2) | ||
5505 | #define REG_LCD_CNUM0_PART2 REG32(LCD_CNUM0_PART2) | ||
5506 | #define REG_LCD_DESSIZE0_PART2 REG32(LCD_DESSIZE0_PART2) | ||
5507 | |||
5508 | #define REG_LCD_DA1 REG32(LCD_DA1) | ||
5509 | #define REG_LCD_SA1 REG32(LCD_SA1) | ||
5510 | #define REG_LCD_FID1 REG32(LCD_FID1) | ||
5511 | #define REG_LCD_CMD1 REG32(LCD_CMD1) | ||
5512 | #define REG_LCD_OFFS1 REG32(LCD_OFFS1) | ||
5513 | #define REG_LCD_PW1 REG32(LCD_PW1) | ||
5514 | #define REG_LCD_CNUM1 REG32(LCD_CNUM1) | ||
5515 | #define REG_LCD_DESSIZE1 REG32(LCD_DESSIZE1) | ||
5516 | #define REG_LCD_PCFG REG32(LCD_PCFG) | ||
5517 | |||
5518 | /* LCD Configure Register */ | ||
5519 | #define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */ | ||
5520 | #define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT) | ||
5521 | #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT) | ||
5522 | #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT) | ||
5523 | #define LCD_CFG_TVEPEH (1 << 30) /* TVE PAL enable extra halfline signal */ | ||
5524 | //#define LCD_CFG_FUHOLD (1 << 29) /* hold pixel clock when outFIFO underrun */ | ||
5525 | #define LCD_CFG_NEWDES (1 << 28) /* use new descripter. old: 4words, new:8words */ | ||
5526 | #define LCD_CFG_PALBP (1 << 27) /* bypass data format and alpha blending */ | ||
5527 | #define LCD_CFG_TVEN (1 << 26) /* indicate the terminal is lcd or tv */ | ||
5528 | #define LCD_CFG_RECOVER (1 << 25) /* Auto recover when output fifo underrun */ | ||
5529 | #define LCD_CFG_DITHER (1 << 24) /* Dither function */ | ||
5530 | #define LCD_CFG_PSM (1 << 23) /* PS signal mode */ | ||
5531 | #define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */ | ||
5532 | #define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */ | ||
5533 | #define LCD_CFG_REVM (1 << 20) /* REV signal mode */ | ||
5534 | #define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */ | ||
5535 | #define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */ | ||
5536 | #define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */ | ||
5537 | #define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */ | ||
5538 | #define LCD_CFG_PSP (1 << 15) /* PS pin reset state */ | ||
5539 | #define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */ | ||
5540 | #define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */ | ||
5541 | #define LCD_CFG_REVP (1 << 12) /* REV pin reset state */ | ||
5542 | #define LCD_CFG_HSP (1 << 11) /* HSYNC polarity:0-active high,1-active low */ | ||
5543 | #define LCD_CFG_PCP (1 << 10) /* PCLK polarity:0-rising,1-falling */ | ||
5544 | #define LCD_CFG_DEP (1 << 9) /* DE polarity:0-active high,1-active low */ | ||
5545 | #define LCD_CFG_VSP (1 << 8) /* VSYNC polarity:0-rising,1-falling */ | ||
5546 | #define LCD_CFG_MODE_TFT_18BIT (1 << 7) /* 18bit TFT */ | ||
5547 | #define LCD_CFG_MODE_TFT_16BIT (0 << 7) /* 16bit TFT */ | ||
5548 | #define LCD_CFG_MODE_TFT_24BIT (1 << 6) /* 24bit TFT */ | ||
5549 | #define LCD_CFG_PDW_BIT 4 /* STN pins utilization */ | ||
5550 | #define LCD_CFG_PDW_MASK (0x3 << LCD_CFG_PDW_BIT) | ||
5551 | #define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */ | ||
5552 | #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */ | ||
5553 | #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */ | ||
5554 | #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */ | ||
5555 | #define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */ | ||
5556 | #define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT) | ||
5557 | #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */ | ||
5558 | #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT) | ||
5559 | #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT) | ||
5560 | #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT) | ||
5561 | #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT) | ||
5562 | #define LCD_CFG_MODE_INTER_CCIR656 (6 << LCD_CFG_MODE_BIT) | ||
5563 | #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT) | ||
5564 | #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT) | ||
5565 | #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT) | ||
5566 | #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT) | ||
5567 | #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT) | ||
5568 | #define LCD_CFG_MODE_LCM (13 << LCD_CFG_MODE_BIT) | ||
5569 | #define LCD_CFG_MODE_SLCD LCD_CFG_MODE_LCM | ||
5570 | |||
5571 | /* LCD Control Register */ | ||
5572 | #define LCD_CTRL_PINMD (1 << 31) /* This register set Pin distribution in 16-bit parallel mode | ||
5573 | 0: 16-bit data correspond with LCD_D[15:0] | ||
5574 | 1: 16-bit data correspond with LCD_D[17:10], LCD_D[8:1] */ | ||
5575 | #define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */ | ||
5576 | #define LCD_CTRL_BST_MASK (0x7 << LCD_CTRL_BST_BIT) | ||
5577 | #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */ | ||
5578 | #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */ | ||
5579 | #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */ | ||
5580 | #define LCD_CTRL_BST_32 (3 << LCD_CTRL_BST_BIT) /* 32-word */ | ||
5581 | #define LCD_CTRL_BST_C16 (5 << LCD_CTRL_BST_BIT) /* 32-word */ | ||
5582 | #define LCD_CTRL_BST_64 (4 << LCD_CTRL_BST_BIT) /* 32-word */ | ||
5583 | #define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode(foreground 0 in OSD mode) */ | ||
5584 | #define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode(foreground 0 in OSD mode) */ | ||
5585 | #define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */ | ||
5586 | #define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */ | ||
5587 | #define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT) | ||
5588 | #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */ | ||
5589 | #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */ | ||
5590 | #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */ | ||
5591 | #define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */ | ||
5592 | #define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) | ||
5593 | //#define LCD_CTRL_VGA (1 << 15) /* VGA interface enable */ | ||
5594 | #define LCD_CTRL_DACTE (1 << 14) /* DAC loop back test */ | ||
5595 | #define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */ | ||
5596 | #define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */ | ||
5597 | #define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */ | ||
5598 | #define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */ | ||
5599 | #define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */ | ||
5600 | #define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */ | ||
5601 | #define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */ | ||
5602 | #define LCD_CTRL_BEDN (1 << 6) /* Endian selection */ | ||
5603 | #define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */ | ||
5604 | #define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */ | ||
5605 | #define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */ | ||
5606 | #define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */ | ||
5607 | #define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT) | ||
5608 | #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */ | ||
5609 | #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */ | ||
5610 | #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */ | ||
5611 | #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */ | ||
5612 | #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */ | ||
5613 | #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */ | ||
5614 | #define LCD_CTRL_BPP_CMPS_24 (6 << LCD_CTRL_BPP_BIT) /* 24 compress bpp */ | ||
5615 | #define LCD_CTRL_BPP_30 (7 << LCD_CTRL_BPP_BIT) /* 30 bpp */ | ||
5616 | |||
5617 | /* LCD Status Register */ | ||
5618 | #define LCD_STATE_QD (1 << 7) /* Quick Disable Done */ | ||
5619 | #define LCD_STATE_EOF (1 << 5) /* EOF Flag */ | ||
5620 | #define LCD_STATE_SOF (1 << 4) /* SOF Flag */ | ||
5621 | #define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */ | ||
5622 | #define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */ | ||
5623 | #define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */ | ||
5624 | #define LCD_STATE_LDD (1 << 0) /* LCD Disabled */ | ||
5625 | |||
5626 | /* OSD Configure Register */ | ||
5627 | #define LCD_OSDC_SOFM1 (1 << 15) /* Start of frame interrupt mask for foreground 1 */ | ||
5628 | #define LCD_OSDC_EOFM1 (1 << 14) /* End of frame interrupt mask for foreground 1 */ | ||
5629 | #define LCD_OSDC_OSDIV (1 << 12) | ||
5630 | #define LCD_OSDC_SOFM0 (1 << 11) /* Start of frame interrupt mask for foreground 0 */ | ||
5631 | #define LCD_OSDC_EOFM0 (1 << 10) /* End of frame interrupt mask for foreground 0 */ | ||
5632 | #if 0 | ||
5633 | #define LCD_OSDC_ENDM (1 << 9) /* End of frame interrupt mask for panel. */ | ||
5634 | #define LCD_OSDC_F0DIVMD (1 << 8) /* Divide Foreground 0 into 2 parts. | ||
5635 | * 0: Foreground 0 only has one part. */ | ||
5636 | #define LCD_OSDC_F0P1EN (1 << 7) /* 1: Foreground 0 PART1 is enabled. | ||
5637 | * 0: Foreground 0 PART1 is disabled. */ | ||
5638 | #define LCD_OSDC_F0P2MD (1 << 6) /* 1: PART 1&2 same level and same heighth | ||
5639 | * 0: PART 1&2 have no same line */ | ||
5640 | #define LCD_OSDC_F0P2EN (1 << 5) /* 1: Foreground 0 PART2 is enabled. | ||
5641 | * 0: Foreground 0 PART2 is disabled.*/ | ||
5642 | #endif | ||
5643 | #define LCD_OSDC_F1EN (1 << 4) /* enable foreground 1 */ | ||
5644 | #define LCD_OSDC_F0EN (1 << 3) /* enable foreground 0 */ | ||
5645 | #define LCD_OSDC_ALPHAEN (1 << 2) /* enable alpha blending */ | ||
5646 | #define LCD_OSDC_ALPHAMD (1 << 1) /* alpha blending mode */ | ||
5647 | #define LCD_OSDC_OSDEN (1 << 0) /* OSD mode enable */ | ||
5648 | |||
5649 | /* OSD Controll Register */ | ||
5650 | #define LCD_OSDCTRL_IPU (1 << 15) /* input data from IPU */ | ||
5651 | #define LCD_OSDCTRL_RGB565 (0 << 4) /* foreground 1, 16bpp, 0-RGB565, 1-RGB555 */ | ||
5652 | #define LCD_OSDCTRL_RGB555 (1 << 4) /* foreground 1, 16bpp, 0-RGB565, 1-RGB555 */ | ||
5653 | #define LCD_OSDCTRL_CHANGES (1 << 3) /* Change size flag */ | ||
5654 | #define LCD_OSDCTRL_OSDBPP_BIT 0 /* Bits Per Pixel of OSD Channel 1 */ | ||
5655 | #define LCD_OSDCTRL_OSDBPP_MASK (0x7<<LCD_OSDCTRL_OSDBPP_BIT) /* Bits Per Pixel of OSD Channel 1's MASK */ | ||
5656 | #define LCD_OSDCTRL_OSDBPP_16 (4 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 15,16 bit*/ | ||
5657 | #define LCD_OSDCTRL_OSDBPP_15_16 (4 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 15,16 bit*/ | ||
5658 | #define LCD_OSDCTRL_OSDBPP_18_24 (5 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 18,24 bit*/ | ||
5659 | #define LCD_OSDCTRL_OSDBPP_CMPS_24 (6 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB compress 24 bit*/ | ||
5660 | #define LCD_OSDCTRL_OSDBPP_30 (7 << LCD_OSDCTRL_OSDBPP_BIT) /* RGB 30 bit*/ | ||
5661 | |||
5662 | /* OSD State Register */ | ||
5663 | #define LCD_OSDS_SOF1 (1 << 15) /* Start of frame flag for foreground 1 */ | ||
5664 | #define LCD_OSDS_EOF1 (1 << 14) /* End of frame flag for foreground 1 */ | ||
5665 | #define LCD_OSDS_SOF0 (1 << 11) /* Start of frame flag for foreground 0 */ | ||
5666 | #define LCD_OSDS_EOF0 (1 << 10) /* End of frame flag for foreground 0 */ | ||
5667 | #define LCD_OSDS_READY (1 << 0) /* Read for accept the change */ | ||
5668 | |||
5669 | /* Background Color Register */ | ||
5670 | #define LCD_BGC_RED_OFFSET (1 << 16) /* Red color offset */ | ||
5671 | #define LCD_BGC_RED_MASK (0xFF<<LCD_BGC_RED_OFFSET) | ||
5672 | #define LCD_BGC_GREEN_OFFSET (1 << 8) /* Green color offset */ | ||
5673 | #define LCD_BGC_GREEN_MASK (0xFF<<LCD_BGC_GREEN_OFFSET) | ||
5674 | #define LCD_BGC_BLUE_OFFSET (1 << 0) /* Blue color offset */ | ||
5675 | #define LCD_BGC_BLUE_MASK (0xFF<<LCD_BGC_BLUE_OFFSET) | ||
5676 | |||
5677 | /* Foreground Color Key Register 0,1(foreground 0, foreground 1) */ | ||
5678 | #define LCD_KEY_KEYEN (1 << 31) /* enable color key */ | ||
5679 | #define LCD_KEY_KEYMD (1 << 30) /* color key mode */ | ||
5680 | #define LCD_KEY_RED_OFFSET 16 /* Red color offset */ | ||
5681 | #define LCD_KEY_RED_MASK (0xFF<<LCD_KEY_RED_OFFSET) | ||
5682 | #define LCD_KEY_GREEN_OFFSET 8 /* Green color offset */ | ||
5683 | #define LCD_KEY_GREEN_MASK (0xFF<<LCD_KEY_GREEN_OFFSET) | ||
5684 | #define LCD_KEY_BLUE_OFFSET 0 /* Blue color offset */ | ||
5685 | #define LCD_KEY_BLUE_MASK (0xFF<<LCD_KEY_BLUE_OFFSET) | ||
5686 | #define LCD_KEY_MASK (LCD_KEY_RED_MASK|LCD_KEY_GREEN_MASK|LCD_KEY_BLUE_MASK) | ||
5687 | |||
5688 | /* IPU Restart Register */ | ||
5689 | #define LCD_IPUR_IPUREN (1 << 31) /* IPU restart function enable*/ | ||
5690 | #define LCD_IPUR_IPURMASK (0xFFFFFF) /* IPU restart value mask*/ | ||
5691 | |||
5692 | /* RGB Control Register */ | ||
5693 | #define LCD_RGBC_RGBDM (1 << 15) /* enable RGB Dummy data */ | ||
5694 | #define LCD_RGBC_DMM (1 << 14) /* RGB Dummy mode */ | ||
5695 | #define LCD_RGBC_YCC (1 << 8) /* RGB to YCC */ | ||
5696 | #define LCD_RGBC_ODDRGB_BIT 4 /* odd line serial RGB data arrangement */ | ||
5697 | #define LCD_RGBC_ODDRGB_MASK (0x7<<LCD_RGBC_ODDRGB_BIT) | ||
5698 | #define LCD_RGBC_ODD_RGB 0 | ||
5699 | #define LCD_RGBC_ODD_RBG 1 | ||
5700 | #define LCD_RGBC_ODD_GRB 2 | ||
5701 | #define LCD_RGBC_ODD_GBR 3 | ||
5702 | #define LCD_RGBC_ODD_BRG 4 | ||
5703 | #define LCD_RGBC_ODD_BGR 5 | ||
5704 | #define LCD_RGBC_EVENRGB_BIT 0 /* even line serial RGB data arrangement */ | ||
5705 | #define LCD_RGBC_EVENRGB_MASK (0x7<<LCD_RGBC_EVENRGB_BIT) | ||
5706 | #define LCD_RGBC_EVEN_RGB 0 | ||
5707 | #define LCD_RGBC_EVEN_RBG 1 | ||
5708 | #define LCD_RGBC_EVEN_GRB 2 | ||
5709 | #define LCD_RGBC_EVEN_GBR 3 | ||
5710 | #define LCD_RGBC_EVEN_BRG 4 | ||
5711 | #define LCD_RGBC_EVEN_BGR 5 | ||
5712 | |||
5713 | /* Vertical Synchronize Register */ | ||
5714 | #define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */ | ||
5715 | #define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT) | ||
5716 | #define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */ | ||
5717 | #define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT) | ||
5718 | |||
5719 | /* Horizontal Synchronize Register */ | ||
5720 | #define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */ | ||
5721 | #define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT) | ||
5722 | #define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */ | ||
5723 | #define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT) | ||
5724 | |||
5725 | /* Virtual Area Setting Register */ | ||
5726 | #define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */ | ||
5727 | #define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT) | ||
5728 | #define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */ | ||
5729 | #define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT) | ||
5730 | |||
5731 | /* Display Area Horizontal Start/End Point Register */ | ||
5732 | #define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */ | ||
5733 | #define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT) | ||
5734 | #define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */ | ||
5735 | #define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT) | ||
5736 | |||
5737 | /* Display Area Vertical Start/End Point Register */ | ||
5738 | #define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */ | ||
5739 | #define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT) | ||
5740 | #define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */ | ||
5741 | #define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT) | ||
5742 | |||
5743 | /* Foreground XY Position Register */ | ||
5744 | #define LCD_XYP_YPOS_BIT 16 /* Y position bit of foreground 0 or 1 */ | ||
5745 | #define LCD_XYP_YPOS_MASK (0xffff << LCD_XYP_YPOS_BIT) | ||
5746 | #define LCD_XYP_XPOS_BIT 0 /* X position bit of foreground 0 or 1 */ | ||
5747 | #define LCD_XYP_XPOS_MASK (0xffff << LCD_XYP_XPOS_BIT) | ||
5748 | |||
5749 | /* PS Signal Setting */ | ||
5750 | #define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */ | ||
5751 | #define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT) | ||
5752 | #define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */ | ||
5753 | #define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT) | ||
5754 | |||
5755 | /* CLS Signal Setting */ | ||
5756 | #define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */ | ||
5757 | #define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT) | ||
5758 | #define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */ | ||
5759 | #define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT) | ||
5760 | |||
5761 | /* SPL Signal Setting */ | ||
5762 | #define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */ | ||
5763 | #define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT) | ||
5764 | #define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */ | ||
5765 | #define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT) | ||
5766 | |||
5767 | /* REV Signal Setting */ | ||
5768 | #define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */ | ||
5769 | #define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT) | ||
5770 | |||
5771 | /* DMA Command Register */ | ||
5772 | #define LCD_CMD_SOFINT (1 << 31) | ||
5773 | #define LCD_CMD_EOFINT (1 << 30) | ||
5774 | #define LCD_CMD_CMD (1 << 29) /* indicate command in slcd mode */ | ||
5775 | #define LCD_CMD_PAL (1 << 28) | ||
5776 | #define LCD_CMD_UNCOMP_EN (1 << 27) | ||
5777 | #define LCD_CMD_UNCOMPRESS_WITHOUT_ALPHA (1 << 26) | ||
5778 | #define LCD_CMD_LEN_BIT 0 | ||
5779 | #define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT) | ||
5780 | |||
5781 | /* DMA Offsize Register 0,1 */ | ||
5782 | |||
5783 | /* DMA Page Width Register 0,1 */ | ||
5784 | |||
5785 | /* DMA Command Counter Register 0,1 */ | ||
5786 | |||
5787 | /* Foreground 0,1 Size Register */ | ||
5788 | #define LCD_DESSIZE_HEIGHT_BIT 16 /* height of foreground 1 */ | ||
5789 | #define LCD_DESSIZE_HEIGHT_MASK (0xffff << LCD_DESSIZE_HEIGHT_BIT) | ||
5790 | #define LCD_DESSIZE_WIDTH_BIT 0 /* width of foreground 1 */ | ||
5791 | #define LCD_DESSIZE_WIDTH_MASK (0xffff << LCD_DESSIZE_WIDTH_BIT) | ||
5792 | |||
5793 | /* Priority level threshold configure Register */ | ||
5794 | #define LCD_PCFG_LCD_PRI_MD (1 << 31) | ||
5795 | #define LCD_PCFG_HP_BST_BIT 28 | ||
5796 | #define LCD_PCFG_HP_BST_MASK (0x7 << LCD_PCFG_HP_BST_BIT) | ||
5797 | #define LCD_PCFG_PCFG2_BIT 8 | ||
5798 | #define LCD_PCFG_PCFG2_MASK (0xf << LCD_PCFG_PCFG2_BIT) | ||
5799 | #define LCD_PCFG_PCFG1_BIT 4 | ||
5800 | #define LCD_PCFG_PCFG1_MASK (0xf << LCD_PCFG_PCFG1_BIT) | ||
5801 | #define LCD_PCFG_PCFG0_BIT 0 | ||
5802 | #define LCD_PCFG_PCFG0_MASK (0xf << LCD_PCFG_PCFG0_BIT) | ||
5803 | |||
5804 | #ifndef __MIPS_ASSEMBLER | ||
5805 | |||
5806 | /************************************************************************* | ||
5807 | * SLCD (Smart LCD Controller) | ||
5808 | *************************************************************************/ | ||
5809 | #define __slcd_set_data_18bit() \ | ||
5810 | ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_18BIT ) | ||
5811 | #define __slcd_set_data_16bit() \ | ||
5812 | ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_16BIT ) | ||
5813 | #define __slcd_set_data_8bit_x3() \ | ||
5814 | ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_8BIT_x3 ) | ||
5815 | #define __slcd_set_data_8bit_x2() \ | ||
5816 | ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_8BIT_x2 ) | ||
5817 | #define __slcd_set_data_8bit_x1() \ | ||
5818 | ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_8BIT_x1 ) | ||
5819 | #define __slcd_set_data_24bit() \ | ||
5820 | ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_24BIT ) | ||
5821 | #define __slcd_set_data_9bit_x2() \ | ||
5822 | ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_DWIDTH_MASK) | SLCD_CFG_DWIDTH_9BIT_x2 ) | ||
5823 | |||
5824 | #define __slcd_set_cmd_16bit() \ | ||
5825 | ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_CWIDTH_MASK) | SLCD_CFG_CWIDTH_16BIT ) | ||
5826 | #define __slcd_set_cmd_8bit() \ | ||
5827 | ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_CWIDTH_MASK) | SLCD_CFG_CWIDTH_8BIT ) | ||
5828 | #define __slcd_set_cmd_18bit() \ | ||
5829 | ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_CWIDTH_MASK) | SLCD_CFG_CWIDTH_18BIT ) | ||
5830 | #define __slcd_set_cmd_24bit() \ | ||
5831 | ( REG_SLCD_CFG = (REG_SLCD_CFG & ~SLCD_CFG_CWIDTH_MASK) | SLCD_CFG_CWIDTH_24BIT ) | ||
5832 | |||
5833 | #define __slcd_set_cs_high() ( REG_SLCD_CFG |= SLCD_CFG_CS_ACTIVE_HIGH ) | ||
5834 | #define __slcd_set_cs_low() ( REG_SLCD_CFG &= ~SLCD_CFG_CS_ACTIVE_HIGH ) | ||
5835 | |||
5836 | #define __slcd_set_rs_high() ( REG_SLCD_CFG |= SLCD_CFG_RS_CMD_HIGH ) | ||
5837 | #define __slcd_set_rs_low() ( REG_SLCD_CFG &= ~SLCD_CFG_RS_CMD_HIGH ) | ||
5838 | |||
5839 | #define __slcd_set_clk_falling() ( REG_SLCD_CFG &= ~SLCD_CFG_CLK_ACTIVE_RISING ) | ||
5840 | #define __slcd_set_clk_rising() ( REG_SLCD_CFG |= SLCD_CFG_CLK_ACTIVE_RISING ) | ||
5841 | |||
5842 | #define __slcd_set_parallel_type() ( REG_SLCD_CFG &= ~SLCD_CFG_TYPE_SERIAL ) | ||
5843 | #define __slcd_set_serial_type() ( REG_SLCD_CFG |= SLCD_CFG_TYPE_SERIAL ) | ||
5844 | |||
5845 | /* SLCD Control Register */ | ||
5846 | #define __slcd_enable_dma() ( REG_SLCD_CTRL |= SLCD_CTRL_DMA_EN ) | ||
5847 | #define __slcd_disable_dma() ( REG_SLCD_CTRL &= ~SLCD_CTRL_DMA_EN ) | ||
5848 | |||
5849 | /* SLCD Status Register */ | ||
5850 | #define __slcd_is_busy() ( REG_SLCD_STATE & SLCD_STATE_BUSY ) | ||
5851 | |||
5852 | /* SLCD Data Register */ | ||
5853 | #define __slcd_set_cmd_rs() ( REG_SLCD_DATA |= SLCD_DATA_RS_COMMAND) | ||
5854 | #define __slcd_set_data_rs() ( REG_SLCD_DATA &= ~SLCD_DATA_RS_COMMAND) | ||
5855 | |||
5856 | /*************************************************************************** | ||
5857 | * LCD | ||
5858 | ***************************************************************************/ | ||
5859 | #define __lcd_as_smart_lcd() ( REG_LCD_CFG |= ( LCD_CFG_LCDPIN_SLCD | LCD_CFG_MODE_SLCD)) | ||
5860 | #define __lcd_as_general_lcd() ( REG_LCD_CFG &= ~( LCD_CFG_LCDPIN_SLCD | LCD_CFG_MODE_SLCD)) | ||
5861 | |||
5862 | #define __lcd_enable_tvepeh() ( REG_LCD_CFG |= LCD_CFG_TVEPEH ) | ||
5863 | #define __lcd_disable_tvepeh() ( REG_LCD_CFG &= ~LCD_CFG_TVEPEH ) | ||
5864 | |||
5865 | #define __lcd_enable_fuhold() ( REG_LCD_CFG |= LCD_CFG_FUHOLD ) | ||
5866 | #define __lcd_disable_fuhold() ( REG_LCD_CFG &= ~LCD_CFG_FUHOLD ) | ||
5867 | |||
5868 | #define __lcd_des_8word() ( REG_LCD_CFG |= LCD_CFG_NEWDES ) | ||
5869 | #define __lcd_des_4word() ( REG_LCD_CFG &= ~LCD_CFG_NEWDES ) | ||
5870 | |||
5871 | #define __lcd_enable_bypass_pal() ( REG_LCD_CFG |= LCD_CFG_PALBP ) | ||
5872 | #define __lcd_disable_bypass_pal() ( REG_LCD_CFG &= ~LCD_CFG_PALBP ) | ||
5873 | |||
5874 | #define __lcd_set_lcdpnl_term() ( REG_LCD_CFG |= LCD_CFG_TVEN ) | ||
5875 | #define __lcd_set_tv_term() ( REG_LCD_CFG &= ~LCD_CFG_TVEN ) | ||
5876 | |||
5877 | #define __lcd_enable_auto_recover() ( REG_LCD_CFG |= LCD_CFG_RECOVER ) | ||
5878 | #define __lcd_disable_auto_recover() ( REG_LCD_CFG &= ~LCD_CFG_RECOVER ) | ||
5879 | |||
5880 | #define __lcd_enable_dither() ( REG_LCD_CFG |= LCD_CFG_DITHER ) | ||
5881 | #define __lcd_disable_dither() ( REG_LCD_CFG &= ~LCD_CFG_DITHER ) | ||
5882 | |||
5883 | #define __lcd_disable_ps_mode() ( REG_LCD_CFG |= LCD_CFG_PSM ) | ||
5884 | #define __lcd_enable_ps_mode() ( REG_LCD_CFG &= ~LCD_CFG_PSM ) | ||
5885 | |||
5886 | #define __lcd_disable_cls_mode() ( REG_LCD_CFG |= LCD_CFG_CLSM ) | ||
5887 | #define __lcd_enable_cls_mode() ( REG_LCD_CFG &= ~LCD_CFG_CLSM ) | ||
5888 | |||
5889 | #define __lcd_disable_spl_mode() ( REG_LCD_CFG |= LCD_CFG_SPLM ) | ||
5890 | #define __lcd_enable_spl_mode() ( REG_LCD_CFG &= ~LCD_CFG_SPLM ) | ||
5891 | |||
5892 | #define __lcd_disable_rev_mode() ( REG_LCD_CFG |= LCD_CFG_REVM ) | ||
5893 | #define __lcd_enable_rev_mode() ( REG_LCD_CFG &= ~LCD_CFG_REVM ) | ||
5894 | |||
5895 | #define __lcd_disable_hsync_mode() ( REG_LCD_CFG |= LCD_CFG_HSYNM ) | ||
5896 | #define __lcd_enable_hsync_mode() ( REG_LCD_CFG &= ~LCD_CFG_HSYNM ) | ||
5897 | |||
5898 | #define __lcd_disable_pclk_mode() ( REG_LCD_CFG |= LCD_CFG_PCLKM ) | ||
5899 | #define __lcd_enable_pclk_mode() ( REG_LCD_CFG &= ~LCD_CFG_PCLKM ) | ||
5900 | |||
5901 | #define __lcd_normal_outdata() ( REG_LCD_CFG &= ~LCD_CFG_INVDAT ) | ||
5902 | #define __lcd_inverse_outdata() ( REG_LCD_CFG |= LCD_CFG_INVDAT ) | ||
5903 | |||
5904 | #define __lcd_sync_input() ( REG_LCD_CFG |= LCD_CFG_SYNDIR_IN ) | ||
5905 | #define __lcd_sync_output() ( REG_LCD_CFG &= ~LCD_CFG_SYNDIR_IN ) | ||
5906 | |||
5907 | #define __lcd_hsync_active_high() ( REG_LCD_CFG &= ~LCD_CFG_HSP ) | ||
5908 | #define __lcd_hsync_active_low() ( REG_LCD_CFG |= LCD_CFG_HSP ) | ||
5909 | |||
5910 | #define __lcd_pclk_rising() ( REG_LCD_CFG &= ~LCD_CFG_PCP ) | ||
5911 | #define __lcd_pclk_falling() ( REG_LCD_CFG |= LCD_CFG_PCP ) | ||
5912 | |||
5913 | #define __lcd_de_active_high() ( REG_LCD_CFG &= ~LCD_CFG_DEP ) | ||
5914 | #define __lcd_de_active_low() ( REG_LCD_CFG |= LCD_CFG_DEP ) | ||
5915 | |||
5916 | #define __lcd_vsync_rising() ( REG_LCD_CFG &= ~LCD_CFG_VSP ) | ||
5917 | #define __lcd_vsync_falling() ( REG_LCD_CFG |= LCD_CFG_VSP ) | ||
5918 | |||
5919 | #define __lcd_set_16_tftpnl() \ | ||
5920 | ( REG_LCD_CFG = (REG_LCD_CFG & ~LCD_CFG_MODE_TFT_MASK) | LCD_CFG_MODE_TFT_16BIT ) | ||
5921 | |||
5922 | #define __lcd_set_18_tftpnl() \ | ||
5923 | ( REG_LCD_CFG = (REG_LCD_CFG & ~LCD_CFG_MODE_TFT_MASK) | LCD_CFG_MODE_TFT_18BIT ) | ||
5924 | |||
5925 | #define __lcd_set_24_tftpnl() ( REG_LCD_CFG |= LCD_CFG_MODE_TFT_24BIT ) | ||
5926 | |||
5927 | /* | ||
5928 | * n=1,2,4,8 for single mono-STN | ||
5929 | * n=4,8 for dual mono-STN | ||
5930 | */ | ||
5931 | #define __lcd_set_panel_datawidth(n) \ | ||
5932 | do { \ | ||
5933 | REG_LCD_CFG &= ~LCD_CFG_PDW_MASK; \ | ||
5934 | REG_LCD_CFG |= LCD_CFG_PDW_n##; \ | ||
5935 | } while (0) | ||
5936 | |||
5937 | /* m = LCD_CFG_MODE_GENERUIC_TFT_xxx */ | ||
5938 | #define __lcd_set_panel_mode(m) \ | ||
5939 | do { \ | ||
5940 | REG_LCD_CFG &= ~LCD_CFG_MODE_MASK; \ | ||
5941 | REG_LCD_CFG |= (m); \ | ||
5942 | } while(0) | ||
5943 | |||
5944 | /* n=4,8,16 */ | ||
5945 | #define __lcd_set_burst_length(n) \ | ||
5946 | do { \ | ||
5947 | REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \ | ||
5948 | REG_LCD_CTRL |= LCD_CTRL_BST_n##; \ | ||
5949 | } while (0) | ||
5950 | |||
5951 | #define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 ) | ||
5952 | #define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 ) | ||
5953 | |||
5954 | #define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP ) | ||
5955 | #define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP ) | ||
5956 | |||
5957 | /* n=2,4,16 */ | ||
5958 | #define __lcd_set_stn_frc(n) \ | ||
5959 | do { \ | ||
5960 | REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \ | ||
5961 | REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \ | ||
5962 | } while (0) | ||
5963 | |||
5964 | #define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM ) | ||
5965 | #define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM ) | ||
5966 | |||
5967 | #define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM ) | ||
5968 | #define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM ) | ||
5969 | |||
5970 | #define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM ) | ||
5971 | #define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM ) | ||
5972 | |||
5973 | #define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 ) | ||
5974 | #define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 ) | ||
5975 | |||
5976 | #define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 ) | ||
5977 | #define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 ) | ||
5978 | |||
5979 | #define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM ) | ||
5980 | #define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM ) | ||
5981 | |||
5982 | #define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM ) | ||
5983 | #define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM ) | ||
5984 | |||
5985 | #define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN ) | ||
5986 | #define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN ) | ||
5987 | |||
5988 | #define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN ) | ||
5989 | #define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN ) | ||
5990 | |||
5991 | #define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS ) | ||
5992 | #define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS ) | ||
5993 | |||
5994 | #define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA ) | ||
5995 | #define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA ) | ||
5996 | |||
5997 | /* n=1,2,4,8,16 */ | ||
5998 | #define __lcd_set_bpp(n) \ | ||
5999 | ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n ) | ||
6000 | |||
6001 | /* LCD status register indication */ | ||
6002 | |||
6003 | #define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD ) | ||
6004 | #define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD ) | ||
6005 | #define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 ) | ||
6006 | #define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 ) | ||
6007 | #define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU ) | ||
6008 | #define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF ) | ||
6009 | #define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF ) | ||
6010 | |||
6011 | #define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU ) | ||
6012 | #define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF ) | ||
6013 | #define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF ) | ||
6014 | |||
6015 | /* OSD functions */ | ||
6016 | #define __lcd_enable_osd() (REG_LCD_OSDC |= LCD_OSDC_OSDEN) | ||
6017 | #define __lcd_enable_f0() (REG_LCD_OSDC |= LCD_OSDC_F0EN) | ||
6018 | #define __lcd_enable_f1() (REG_LCD_OSDC |= LCD_OSDC_F1EN) | ||
6019 | #define __lcd_enable_alpha() (REG_LCD_OSDC |= LCD_OSDC_ALPHAEN) | ||
6020 | #define __lcd_enable_alphamd() (REG_LCD_OSDC |= LCD_OSDC_ALPHAMD) | ||
6021 | |||
6022 | #define __lcd_disable_osd() (REG_LCD_OSDC &= ~LCD_OSDC_OSDEN) | ||
6023 | #define __lcd_disable_f0() (REG_LCD_OSDC &= ~LCD_OSDC_F0EN) | ||
6024 | #define __lcd_disable_f1() (REG_LCD_OSDC &= ~LCD_OSDC_F1EN) | ||
6025 | #define __lcd_disable_alpha() (REG_LCD_OSDC &= ~LCD_OSDC_ALPHAEN) | ||
6026 | #define __lcd_disable_alphamd() (REG_LCD_OSDC &= ~LCD_OSDC_ALPHAMD) | ||
6027 | |||
6028 | /* OSD Controll Register */ | ||
6029 | #define __lcd_fg1_use_ipu() (REG_LCD_OSDCTRL |= LCD_OSDCTRL_IPU) | ||
6030 | #define __lcd_fg1_use_dma_chan1() (REG_LCD_OSDCTRL &= ~LCD_OSDCTRL_IPU) | ||
6031 | #define __lcd_fg1_unuse_ipu() __lcd_fg1_use_dma_chan1() | ||
6032 | #define __lcd_osd_rgb555_mode() ( REG_LCD_OSDCTRL |= LCD_OSDCTRL_RGB555 ) | ||
6033 | #define __lcd_osd_rgb565_mode() ( REG_LCD_OSDCTRL &= ~LCD_OSDCTRL_RGB555 ) | ||
6034 | #define __lcd_osd_change_size() ( REG_LCD_OSDCTRL |= LCD_OSDCTRL_CHANGES ) | ||
6035 | #define __lcd_osd_bpp_15_16() \ | ||
6036 | ( REG_LCD_OSDCTRL = (REG_LCD_OSDCTRL & ~LCD_OSDCTRL_OSDBPP_MASK) | LCD_OSDCTRL_OSDBPP_15_16 ) | ||
6037 | #define __lcd_osd_bpp_18_24() \ | ||
6038 | ( REG_LCD_OSDCTRL = (REG_LCD_OSDCTRL & ~LCD_OSDCTRL_OSDBPP_MASK) | LCD_OSDCTRL_OSDBPP_18_24 ) | ||
6039 | |||
6040 | /* OSD State Register */ | ||
6041 | #define __lcd_start_of_fg1() ( REG_LCD_STATE & LCD_OSDS_SOF1 ) | ||
6042 | #define __lcd_end_of_fg1() ( REG_LCD_STATE & LCD_OSDS_EOF1 ) | ||
6043 | #define __lcd_start_of_fg0() ( REG_LCD_STATE & LCD_OSDS_SOF0 ) | ||
6044 | #define __lcd_end_of_fg0() ( REG_LCD_STATE & LCD_OSDS_EOF0 ) | ||
6045 | #define __lcd_change_is_rdy() ( REG_LCD_STATE & LCD_OSDS_READY ) | ||
6046 | |||
6047 | /* Foreground Color Key Register 0,1(foreground 0, foreground 1) */ | ||
6048 | #define __lcd_enable_colorkey0() (REG_LCD_KEY0 |= LCD_KEY_KEYEN) | ||
6049 | #define __lcd_enable_colorkey1() (REG_LCD_KEY1 |= LCD_KEY_KEYEN) | ||
6050 | #define __lcd_enable_colorkey0_md() (REG_LCD_KEY0 |= LCD_KEY_KEYMD) | ||
6051 | #define __lcd_enable_colorkey1_md() (REG_LCD_KEY1 |= LCD_KEY_KEYMD) | ||
6052 | #define __lcd_set_colorkey0(key) (REG_LCD_KEY0 = (REG_LCD_KEY0&~0xFFFFFF)|(key)) | ||
6053 | #define __lcd_set_colorkey1(key) (REG_LCD_KEY1 = (REG_LCD_KEY1&~0xFFFFFF)|(key)) | ||
6054 | |||
6055 | #define __lcd_disable_colorkey0() (REG_LCD_KEY0 &= ~LCD_KEY_KEYEN) | ||
6056 | #define __lcd_disable_colorkey1() (REG_LCD_KEY1 &= ~LCD_KEY_KEYEN) | ||
6057 | #define __lcd_disable_colorkey0_md() (REG_LCD_KEY0 &= ~LCD_KEY_KEYMD) | ||
6058 | #define __lcd_disable_colorkey1_md() (REG_LCD_KEY1 &= ~LCD_KEY_KEYMD) | ||
6059 | |||
6060 | /* IPU Restart Register */ | ||
6061 | #define __lcd_enable_ipu_restart() (REG_LCD_IPUR |= LCD_IPUR_IPUREN) | ||
6062 | #define __lcd_disable_ipu_restart() (REG_LCD_IPUR &= ~LCD_IPUR_IPUREN) | ||
6063 | #define __lcd_set_ipu_restart_triger(n) (REG_LCD_IPUR = (REG_LCD_IPUR&(~0xFFFFFF))|(n)) | ||
6064 | |||
6065 | /* RGB Control Register */ | ||
6066 | #define __lcd_enable_rgb_dummy() (REG_LCD_RGBC |= LCD_RGBC_RGBDM) | ||
6067 | #define __lcd_disable_rgb_dummy() (REG_LCD_RGBC &= ~LCD_RGBC_RGBDM) | ||
6068 | |||
6069 | #define __lcd_dummy_rgb() (REG_LCD_RGBC |= LCD_RGBC_DMM) | ||
6070 | #define __lcd_rgb_dummy() (REG_LCD_RGBC &= ~LCD_RGBC_DMM) | ||
6071 | |||
6072 | #define __lcd_rgb2ycc() (REG_LCD_RGBC |= LCD_RGBC_YCC) | ||
6073 | #define __lcd_notrgb2ycc() (REG_LCD_RGBC &= ~LCD_RGBC_YCC) | ||
6074 | |||
6075 | #define __lcd_odd_mode_rgb() \ | ||
6076 | ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_RGB ) | ||
6077 | #define __lcd_odd_mode_rbg() \ | ||
6078 | ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_RBG ) | ||
6079 | #define __lcd_odd_mode_grb() \ | ||
6080 | ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_GRB) | ||
6081 | |||
6082 | #define __lcd_odd_mode_gbr() \ | ||
6083 | ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_GBR) | ||
6084 | #define __lcd_odd_mode_brg() \ | ||
6085 | ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_BRG) | ||
6086 | #define __lcd_odd_mode_bgr() \ | ||
6087 | ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_ODDRGB_MASK) | LCD_RGBC_ODD_BGR) | ||
6088 | |||
6089 | #define __lcd_even_mode_rgb() \ | ||
6090 | ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_RGB ) | ||
6091 | #define __lcd_even_mode_rbg() \ | ||
6092 | ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_RBG ) | ||
6093 | #define __lcd_even_mode_grb() \ | ||
6094 | ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_GRB) | ||
6095 | |||
6096 | #define __lcd_even_mode_gbr() \ | ||
6097 | ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_GBR) | ||
6098 | #define __lcd_even_mode_brg() \ | ||
6099 | ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_BRG) | ||
6100 | #define __lcd_even_mode_bgr() \ | ||
6101 | ( REG_LCD_RGBC = (REG_LCD_RGBC & ~LCD_RGBC_EVENRGB_MASK) | LCD_RGBC_EVEN_BGR) | ||
6102 | |||
6103 | /* Vertical Synchronize Register */ | ||
6104 | #define __lcd_vsync_get_vps() \ | ||
6105 | ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT ) | ||
6106 | |||
6107 | #define __lcd_vsync_get_vpe() \ | ||
6108 | ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT ) | ||
6109 | #define __lcd_vsync_set_vpe(n) \ | ||
6110 | do { \ | ||
6111 | REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \ | ||
6112 | REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \ | ||
6113 | } while (0) | ||
6114 | |||
6115 | #define __lcd_hsync_get_hps() \ | ||
6116 | ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT ) | ||
6117 | #define __lcd_hsync_set_hps(n) \ | ||
6118 | do { \ | ||
6119 | REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \ | ||
6120 | REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \ | ||
6121 | } while (0) | ||
6122 | |||
6123 | #define __lcd_hsync_get_hpe() \ | ||
6124 | ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT ) | ||
6125 | #define __lcd_hsync_set_hpe(n) \ | ||
6126 | do { \ | ||
6127 | REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \ | ||
6128 | REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \ | ||
6129 | } while (0) | ||
6130 | |||
6131 | #define __lcd_vat_get_ht() \ | ||
6132 | ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT ) | ||
6133 | #define __lcd_vat_set_ht(n) \ | ||
6134 | do { \ | ||
6135 | REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \ | ||
6136 | REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \ | ||
6137 | } while (0) | ||
6138 | |||
6139 | #define __lcd_vat_get_vt() \ | ||
6140 | ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT ) | ||
6141 | #define __lcd_vat_set_vt(n) \ | ||
6142 | do { \ | ||
6143 | REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \ | ||
6144 | REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \ | ||
6145 | } while (0) | ||
6146 | |||
6147 | #define __lcd_dah_get_hds() \ | ||
6148 | ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT ) | ||
6149 | #define __lcd_dah_set_hds(n) \ | ||
6150 | do { \ | ||
6151 | REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \ | ||
6152 | REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \ | ||
6153 | } while (0) | ||
6154 | |||
6155 | #define __lcd_dah_get_hde() \ | ||
6156 | ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT ) | ||
6157 | #define __lcd_dah_set_hde(n) \ | ||
6158 | do { \ | ||
6159 | REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \ | ||
6160 | REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \ | ||
6161 | } while (0) | ||
6162 | |||
6163 | #define __lcd_dav_get_vds() \ | ||
6164 | ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT ) | ||
6165 | #define __lcd_dav_set_vds(n) \ | ||
6166 | do { \ | ||
6167 | REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \ | ||
6168 | REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \ | ||
6169 | } while (0) | ||
6170 | |||
6171 | #define __lcd_dav_get_vde() \ | ||
6172 | ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT ) | ||
6173 | #define __lcd_dav_set_vde(n) \ | ||
6174 | do { \ | ||
6175 | REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \ | ||
6176 | REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \ | ||
6177 | } while (0) | ||
6178 | |||
6179 | /* DMA Command Register */ | ||
6180 | #define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT ) | ||
6181 | #define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT ) | ||
6182 | #define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT ) | ||
6183 | #define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT ) | ||
6184 | |||
6185 | #define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT ) | ||
6186 | #define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT ) | ||
6187 | #define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT ) | ||
6188 | #define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT ) | ||
6189 | |||
6190 | #define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL ) | ||
6191 | #define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL ) | ||
6192 | |||
6193 | #define __lcd_cmd0_get_len() \ | ||
6194 | ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) | ||
6195 | #define __lcd_cmd1_get_len() \ | ||
6196 | ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) | ||
6197 | |||
6198 | #endif /* __MIPS_ASSEMBLER */ | ||
6199 | |||
6200 | /* | ||
6201 | * Motion compensation module(MC) address definition | ||
6202 | */ | ||
6203 | #define MC_BASE 0xb3250000 | ||
6204 | |||
6205 | /* | ||
6206 | * MC registers offset address definition | ||
6207 | */ | ||
6208 | #define MC_MCCR_OFFSET (0x00) /* rw, 32, 0x???????? */ | ||
6209 | #define MC_MCSR_OFFSET (0x04) /* rw, 32, 0x???????? */ | ||
6210 | #define MC_MCRBAR_OFFSET (0x08) /* rw, 32, 0x???????? */ | ||
6211 | #define MC_MCT1LFCR_OFFSET (0x0c) /* rw, 32, 0x???????? */ | ||
6212 | #define MC_MCT2LFCR_OFFSET (0x10) /* rw, 32, 0x???????? */ | ||
6213 | #define MC_MCCBAR_OFFSET (0x14) /* rw, 32, 0x???????? */ | ||
6214 | #define MC_MCIIR_OFFSET (0x18) /* rw, 32, 0x???????? */ | ||
6215 | #define MC_MCSIR_OFFSET (0x1c) /* rw, 32, 0x???????? */ | ||
6216 | #define MC_MCT1MFCR_OFFSET (0x20) /* rw, 32, 0x???????? */ | ||
6217 | #define MC_MCT2MFCR_OFFSET (0x24) /* rw, 32, 0x???????? */ | ||
6218 | #define MC_MCFGIR_OFFSET (0x28) /* rw, 32, 0x???????? */ | ||
6219 | #define MC_MCFCIR_OFFSET (0x2c) /* rw, 32, 0x???????? */ | ||
6220 | #define MC_MCRNDTR_OFFSET (0x40) /* rw, 32, 0x???????? */ | ||
6221 | |||
6222 | #define MC_MC2CR_OFFSET (0x8000) /* rw, 32, 0x???????? */ | ||
6223 | #define MC_MC2SR_OFFSET (0x8004) /* rw, 32, 0x???????? */ | ||
6224 | #define MC_MC2RBAR_OFFSET (0x8008) /* rw, 32, 0x???????? */ | ||
6225 | #define MC_MC2CBAR_OFFSET (0x800c) /* rw, 32, 0x???????? */ | ||
6226 | #define MC_MC2IIR_OFFSET (0x8010) /* rw, 32, 0x???????? */ | ||
6227 | #define MC_MC2TFCR_OFFSET (0x8014) /* rw, 32, 0x???????? */ | ||
6228 | #define MC_MC2SIR_OFFSET (0x8018) /* rw, 32, 0x???????? */ | ||
6229 | #define MC_MC2FCIR_OFFSET (0x801c) /* rw, 32, 0x???????? */ | ||
6230 | #define MC_MC2RNDTR_OFFSET (0x8040) /* rw, 32, 0x???????? */ | ||
6231 | |||
6232 | /* | ||
6233 | * MC registers address definition | ||
6234 | */ | ||
6235 | #define MC_MCCR (MC_BASE + MC_MCCR_OFFSET) | ||
6236 | #define MC_MCSR (MC_BASE + MC_MCSR_OFFSET) | ||
6237 | #define MC_MCRBAR (MC_BASE + MC_MCRBAR_OFFSET) | ||
6238 | #define MC_MCT1LFCR (MC_BASE + MC_MCT1LFCR_OFFSET) | ||
6239 | #define MC_MCT2LFCR (MC_BASE + MC_MCT2LFCR_OFFSET) | ||
6240 | #define MC_MCCBAR (MC_BASE + MC_MCCBAR_OFFSET) | ||
6241 | #define MC_MCIIR (MC_BASE + MC_MCIIR_OFFSET) | ||
6242 | #define MC_MCSIR (MC_BASE + MC_MCSIR_OFFSET) | ||
6243 | #define MC_MCT1MFCR (MC_BASE + MC_MCT1MFCR_OFFSET) | ||
6244 | #define MC_MCT2MFCR (MC_BASE + MC_MCT2MFCR_OFFSET) | ||
6245 | #define MC_MCFGIR (MC_BASE + MC_MCFGIR_OFFSET) | ||
6246 | #define MC_MCFCIR (MC_BASE + MC_MCFCIR_OFFSET) | ||
6247 | #define MC_MCRNDTR (MC_BASE + MC_MCRNDTR_OFFSET) | ||
6248 | |||
6249 | #define MC_MC2CR (MC_BASE + MC_MC2CR_OFFSET) | ||
6250 | #define MC_MC2SR (MC_BASE + MC_MC2SR_OFFSET) | ||
6251 | #define MC_MC2RBAR (MC_BASE + MC_MC2RBAR_OFFSET) | ||
6252 | #define MC_MC2CBAR (MC_BASE + MC_MC2CBAR_OFFSET) | ||
6253 | #define MC_MC2IIR (MC_BASE + MC_MC2IIR_OFFSET) | ||
6254 | #define MC_MC2TFCR (MC_BASE + MC_MC2TFCR_OFFSET) | ||
6255 | #define MC_MC2SIR (MC_BASE + MC_MC2SIR_OFFSET) | ||
6256 | #define MC_MC2FCIR (MC_BASE + MC_MC2FCIR_OFFSET) | ||
6257 | #define MC_MC2RNDTR (MC_BASE + MC_MC2RNDTR_OFFSET) | ||
6258 | |||
6259 | /* | ||
6260 | * MC registers common define | ||
6261 | */ | ||
6262 | |||
6263 | /* MC Control Register(MCCR) */ | ||
6264 | #define MCCR_RETE BIT16 | ||
6265 | #define MCCR_DIPE BIT7 | ||
6266 | #define MCCR_CKGEN BIT6 | ||
6267 | #define MCCR_FDDEN BIT5 | ||
6268 | #define MCCR_DINSE BIT3 | ||
6269 | #define MCCR_FAE BIT2 | ||
6270 | #define MCCR_RST BIT1 | ||
6271 | #define MCCR_CHEN BIT0 | ||
6272 | |||
6273 | #define MCCR_FDDPGN_LSB 8 | ||
6274 | #define MCCR_FDDPGN_MASK BITS_H2L(15, MCCR_FDDPGN_LSB) | ||
6275 | |||
6276 | /* MC Status Register(MCSR) */ | ||
6277 | #define MCSR_DLEND BIT1 | ||
6278 | #define MCSR_BKLEND BIT0 | ||
6279 | |||
6280 | #ifndef __MIPS_ASSEMBLER | ||
6281 | |||
6282 | #define REG_MC_MCCR REG32(REG_MC_MCCR) | ||
6283 | #define REG_MC_MCSR REG32(REG_MC_MCSR) | ||
6284 | #define REG_MC_MCRBAR REG32(REG_MC_MCRBAR) | ||
6285 | #define REG_MC_MCT1LFCR REG32(REG_MC_MCT1LFCR) | ||
6286 | #define REG_MC_MCT2LFCR REG32(REG_MC_MCT2LFCR) | ||
6287 | #define REG_MC_MCCBAR REG32(REG_MC_MCCBAR) | ||
6288 | #define REG_MC_MCIIR REG32(REG_MC_MCIIR) | ||
6289 | #define REG_MC_MCSIR REG32(REG_MC_MCSIR) | ||
6290 | #define REG_MC_MCT1MFCR REG32(REG_MC_MCT1MFCR) | ||
6291 | #define REG_MC_MCT2MFCR REG32(REG_MC_MCT2MFCR) | ||
6292 | #define REG_MC_MCFGIR REG32(REG_MC_MCFGIR) | ||
6293 | #define REG_MC_MCFCIR REG32(REG_MC_MCFCIR) | ||
6294 | #define REG_MC_MCRNDTR REG32(REG_MC_MCRNDTR) | ||
6295 | |||
6296 | #define REG_MC_MC2CR REG32(REG_MC_MC2CR) | ||
6297 | #define REG_MC_MC2SR REG32(REG_MC_MC2SR) | ||
6298 | #define REG_MC_MC2RBAR REG32(REG_MC_MC2RBAR) | ||
6299 | #define REG_MC_MC2CBAR REG32(REG_MC_MC2CBAR) | ||
6300 | #define REG_MC_MC2IIR REG32(REG_MC_MC2IIR) | ||
6301 | #define REG_MC_MC2TFCR REG32(REG_MC_MC2TFCR) | ||
6302 | #define REG_MC_MC2SIR REG32(REG_MC_MC2SIR) | ||
6303 | #define REG_MC_MC2FCIR REG32(REG_MC_MC2FCIR) | ||
6304 | #define REG_MC_MC2RNDTR REG32(REG_MC_MC2RNDTR) | ||
6305 | |||
6306 | #endif /* __MIPS_ASSEMBLER */ | ||
6307 | |||
6308 | #define MDMAC_BASE 0xB3030000 /* Memory Copy DMAC */ | ||
6309 | |||
6310 | /************************************************************************* | ||
6311 | * MDMAC (MEM Copy DMA Controller) | ||
6312 | *************************************************************************/ | ||
6313 | |||
6314 | /* m is the DMA controller index (0, 1), n is the DMA channel index (0 - 11) */ | ||
6315 | |||
6316 | #define MDMAC_DSAR(n) (MDMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */ | ||
6317 | #define MDMAC_DTAR(n) (MDMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */ | ||
6318 | #define MDMAC_DTCR(n) (MDMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */ | ||
6319 | #define MDMAC_DRSR(n) (MDMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */ | ||
6320 | #define MDMAC_DCCSR(n) (MDMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */ | ||
6321 | #define MDMAC_DCMD(n) (MDMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */ | ||
6322 | #define MDMAC_DDA(n) (MDMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */ | ||
6323 | #define MDMAC_DSD(n) (MDMAC_BASE + (0x1c + (n) * 0x20)) /* DMA Stride Address */ | ||
6324 | |||
6325 | #define MDMAC_DMACR (MDMAC_BASE + 0x0300) /* DMA control register */ | ||
6326 | #define MDMAC_DMAIPR (MDMAC_BASE + 0x0304) /* DMA interrupt pending */ | ||
6327 | #define MDMAC_DMADBR (MDMAC_BASE + 0x0308) /* DMA doorbell */ | ||
6328 | #define MDMAC_DMADBSR (MDMAC_BASE + 0x030C) /* DMA doorbell set */ | ||
6329 | #define MDMAC_DMACKE (MDMAC_BASE + 0x0310) | ||
6330 | #define MDMAC_DMACKES (MDMAC_BASE + 0x0314) | ||
6331 | #define MDMAC_DMACKEC (MDMAC_BASE + 0x0318) | ||
6332 | |||
6333 | #define REG_MDMAC_DSAR(n) REG32(MDMAC_DSAR((n))) | ||
6334 | #define REG_MDMAC_DTAR(n) REG32(MDMAC_DTAR((n))) | ||
6335 | #define REG_MDMAC_DTCR(n) REG32(MDMAC_DTCR((n))) | ||
6336 | #define REG_MDMAC_DRSR(n) REG32(MDMAC_DRSR((n))) | ||
6337 | #define REG_MDMAC_DCCSR(n) REG32(MDMAC_DCCSR((n))) | ||
6338 | #define REG_MDMAC_DCMD(n) REG32(MDMAC_DCMD((n))) | ||
6339 | #define REG_MDMAC_DDA(n) REG32(MDMAC_DDA((n))) | ||
6340 | #define REG_MDMAC_DSD(n) REG32(MDMAC_DSD(n)) | ||
6341 | #define REG_MDMAC_DMACR REG32(MDMAC_DMACR) | ||
6342 | #define REG_MDMAC_DMAIPR REG32(MDMAC_DMAIPR) | ||
6343 | #define REG_MDMAC_DMADBR REG32(MDMAC_DMADBR) | ||
6344 | #define REG_MDMAC_DMADBSR REG32(MDMAC_DMADBSR) | ||
6345 | #define REG_MDMAC_DMACKE REG32(MDMAC_DMACKE) | ||
6346 | #define REG_MDMAC_DMACKES REG32(MDMAC_DMACKES) | ||
6347 | #define REG_MDMAC_DMACKEC REG32(MDMAC_DMACKEC) | ||
6348 | |||
6349 | // DMA control register | ||
6350 | #define DMAC_MDMACR_HLT (1 << 3) /* DMA halt flag */ | ||
6351 | #define DMAC_MDMACR_AR (1 << 2) /* address error flag */ | ||
6352 | #define DMAC_MDMACR_DMAE (1 << 0) /* DMA enable bit */ | ||
6353 | |||
6354 | #ifndef __MIPS_ASSEMBLER | ||
6355 | |||
6356 | /*************************************************************************** | ||
6357 | * Mem Copy DMAC | ||
6358 | ***************************************************************************/ | ||
6359 | |||
6360 | #define __mdmac_enable_module() \ | ||
6361 | ( REG_MDMAC_DMACR |= DMAC_MDMACR_DMAE ) | ||
6362 | #define __mdmac_disable_module() \ | ||
6363 | ( REG_MDMAC_DMACR &= ~DMAC_MDMACR_DMAE ) | ||
6364 | |||
6365 | #define __mdmac_test_halt_error ( REG_MDMAC_DMACR & DMAC_MDMACR_HLT ) | ||
6366 | #define __mdmac_test_addr_error ( REG_MDMAC_DMACR & DMAC_MDMACR_AR ) | ||
6367 | |||
6368 | #define __mdmac_channel_enable_clk \ | ||
6369 | REG_MDMAC_DMACKES = 1 << (n); | ||
6370 | |||
6371 | #define __mdmac_channel_disable_clk \ | ||
6372 | REG_MDMAC_DMACKEC = 1 << (n); | ||
6373 | |||
6374 | #define __mdmac_enable_descriptor(n) \ | ||
6375 | ( REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES ) | ||
6376 | #define __mdmac_disable_descriptor(n) \ | ||
6377 | ( REG_MDMAC_DCCSR((n)) |= DMAC_DCCSR_NDES ) | ||
6378 | |||
6379 | #define __mdmac_enable_channel(n) \ | ||
6380 | do { \ | ||
6381 | REG_MDMAC_DCCSR((n)) |= DMAC_DCCSR_EN; \ | ||
6382 | } while (0) | ||
6383 | #define __mdmac_disable_channel(n) \ | ||
6384 | do { \ | ||
6385 | REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN; \ | ||
6386 | } while (0) | ||
6387 | #define __mdmac_channel_enabled(n) \ | ||
6388 | ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_EN ) | ||
6389 | |||
6390 | #define __mdmac_channel_enable_irq(n) \ | ||
6391 | ( REG_MDMAC_DCMD((n)) |= DMAC_DCMD_TIE ) | ||
6392 | #define __mdmac_channel_disable_irq(n) \ | ||
6393 | ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE ) | ||
6394 | |||
6395 | #define __mdmac_channel_transmit_halt_detected(n) \ | ||
6396 | ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_HLT ) | ||
6397 | #define __mdmac_channel_transmit_end_detected(n) \ | ||
6398 | ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_TT ) | ||
6399 | #define __mdmac_channel_address_error_detected(n) \ | ||
6400 | ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR ) | ||
6401 | #define __mdmac_channel_count_terminated_detected(n) \ | ||
6402 | ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_CT ) | ||
6403 | #define __mdmac_channel_descriptor_invalid_detected(n) \ | ||
6404 | ( REG_MDMAC_DCCSR((n)) & DMAC_DCCSR_INV ) | ||
6405 | |||
6406 | #define __mdmac_channel_clear_transmit_halt(n) \ | ||
6407 | do { \ | ||
6408 | /* clear both channel halt error and globle halt error */ \ | ||
6409 | REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT; \ | ||
6410 | REG_MDMAC_DMACR &= ~DMAC_DMACR_HLT; \ | ||
6411 | } while (0) | ||
6412 | #define __mdmac_channel_clear_transmit_end(n) \ | ||
6413 | ( REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_TT ) | ||
6414 | #define __mdmac_channel_clear_address_error(n) \ | ||
6415 | do { \ | ||
6416 | REG_MDMAC_DDA(n) = 0; /* clear descriptor address register */ \ | ||
6417 | REG_MDMAC_DSAR(n) = 0; /* clear source address register */ \ | ||
6418 | REG_MDMAC_DTAR(n) = 0; /* clear target address register */ \ | ||
6419 | /* clear both channel addr error and globle address error */ \ | ||
6420 | REG_MDMAC_DCCSR(n) &= ~DMAC_DCCSR_AR; \ | ||
6421 | REG_MDMAC_DMACR &= ~DMAC_DMACR_AR; \ | ||
6422 | } while (0) | ||
6423 | #define __mdmac_channel_clear_count_terminated(n) \ | ||
6424 | ( REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT ) | ||
6425 | #define __mdmac_channel_clear_descriptor_invalid(n) \ | ||
6426 | ( REG_MDMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV ) | ||
6427 | |||
6428 | #define __mdmac_channel_set_transfer_unit_32bit(n) \ | ||
6429 | do { \ | ||
6430 | REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ | ||
6431 | REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \ | ||
6432 | } while (0) | ||
6433 | |||
6434 | #define __mdmac_channel_set_transfer_unit_16bit(n) \ | ||
6435 | do { \ | ||
6436 | REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ | ||
6437 | REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \ | ||
6438 | } while (0) | ||
6439 | |||
6440 | #define __mdmac_channel_set_transfer_unit_8bit(n) \ | ||
6441 | do { \ | ||
6442 | REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ | ||
6443 | REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \ | ||
6444 | } while (0) | ||
6445 | |||
6446 | #define __mdmac_channel_set_transfer_unit_16byte(n) \ | ||
6447 | do { \ | ||
6448 | REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ | ||
6449 | REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \ | ||
6450 | } while (0) | ||
6451 | |||
6452 | #define __mdmac_channel_set_transfer_unit_32byte(n) \ | ||
6453 | do { \ | ||
6454 | REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ | ||
6455 | REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \ | ||
6456 | } while (0) | ||
6457 | |||
6458 | /* w=8,16,32 */ | ||
6459 | #define __mdmac_channel_set_dest_port_width(n,w) \ | ||
6460 | do { \ | ||
6461 | REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \ | ||
6462 | REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \ | ||
6463 | } while (0) | ||
6464 | |||
6465 | /* w=8,16,32 */ | ||
6466 | #define __mdmac_channel_set_src_port_width(n,w) \ | ||
6467 | do { \ | ||
6468 | REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \ | ||
6469 | REG_MDMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \ | ||
6470 | } while (0) | ||
6471 | |||
6472 | /* v=0-15 */ | ||
6473 | #define __mdmac_channel_set_rdil(n,v) \ | ||
6474 | do { \ | ||
6475 | REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \ | ||
6476 | REG_MDMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \ | ||
6477 | } while (0) | ||
6478 | |||
6479 | #define __mdmac_channel_dest_addr_fixed(n) \ | ||
6480 | (REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_DAI) | ||
6481 | #define __mdmac_channel_dest_addr_increment(n) \ | ||
6482 | (REG_MDMAC_DCMD((n)) |= DMAC_DCMD_DAI) | ||
6483 | |||
6484 | #define __mdmac_channel_src_addr_fixed(n) \ | ||
6485 | (REG_MDMAC_DCMD((n)) &= ~DMAC_DCMD_SAI) | ||
6486 | #define __mdmac_channel_src_addr_increment(n) \ | ||
6487 | (REG_MDMAC_DCMD((n)) |= DMAC_DCMD_SAI) | ||
6488 | |||
6489 | #define __mdmac_channel_set_doorbell(n) \ | ||
6490 | (REG_MDMAC_DMADBSR = (1 << (n))) | ||
6491 | |||
6492 | #define __mdmac_channel_irq_detected(n) (REG_MDMAC_DMAIPR & (1 << (n))) | ||
6493 | #define __mdmac_channel_ack_irq(n) (REG_MDMAC_DMAIPR &= ~(1 <<(n))) | ||
6494 | |||
6495 | static __inline__ int __mdmac_get_irq(void) | ||
6496 | { | ||
6497 | int i; | ||
6498 | for (i = 0; i < MAX_MDMA_NUM; i++) | ||
6499 | if (__mdmac_channel_irq_detected(i)) | ||
6500 | return i; | ||
6501 | return -1; | ||
6502 | } | ||
6503 | |||
6504 | #endif /* __MIPS_ASSEMBLER */ | ||
6505 | |||
6506 | /* | ||
6507 | * Motion estimation module(ME) address definition | ||
6508 | */ | ||
6509 | #define ME_BASE 0xb3260000 | ||
6510 | |||
6511 | /* | ||
6512 | * ME registers offset address definition | ||
6513 | */ | ||
6514 | #define ME_MECR_OFFSET (0x00) /* rw, 32, 0x???????0 */ | ||
6515 | #define ME_MERBAR_OFFSET (0x04) /* rw, 32, 0x???????? */ | ||
6516 | #define ME_MECBAR_OFFSET (0x08) /* rw, 32, 0x???????? */ | ||
6517 | #define ME_MEDAR_OFFSET (0x0c) /* rw, 32, 0x???????? */ | ||
6518 | #define ME_MERFSR_OFFSET (0x10) /* rw, 32, 0x???????? */ | ||
6519 | #define ME_MECFSR_OFFSET (0x14) /* rw, 32, 0x???????? */ | ||
6520 | #define ME_MEDFSR_OFFSET (0x18) /* rw, 32, 0x???????? */ | ||
6521 | #define ME_MESR_OFFSET (0x1c) /* rw, 32, 0x???????? */ | ||
6522 | #define ME_MEMR_OFFSET (0x20) /* rw, 32, 0x???????? */ | ||
6523 | #define ME_MEFR_OFFSET (0x24) /* rw, 32, 0x???????? */ | ||
6524 | |||
6525 | /* | ||
6526 | * ME registers address definition | ||
6527 | */ | ||
6528 | #define ME_MECR (ME_BASE + ME_MECR_OFFSET) | ||
6529 | #define ME_MERBAR (ME_BASE + ME_MERBAR_OFFSET) | ||
6530 | #define ME_MECBAR (ME_BASE + ME_MECBAR_OFFSET) | ||
6531 | #define ME_MEDAR (ME_BASE + ME_MEDAR_OFFSET) | ||
6532 | #define ME_MERFSR (ME_BASE + ME_MERFSR_OFFSET) | ||
6533 | #define ME_MECFSR (ME_BASE + ME_MECFSR_OFFSET) | ||
6534 | #define ME_MEDFSR (ME_BASE + ME_MEDFSR_OFFSET) | ||
6535 | #define ME_MESR (ME_BASE + ME_MESR_OFFSET) | ||
6536 | #define ME_MEMR (ME_BASE + ME_MEMR_OFFSET) | ||
6537 | #define ME_MEFR (ME_BASE + ME_MEFR_OFFSET) | ||
6538 | |||
6539 | /* | ||
6540 | * ME registers common define | ||
6541 | */ | ||
6542 | |||
6543 | /* ME control register(MECR) */ | ||
6544 | #define MECR_FLUSH BIT2 | ||
6545 | #define MECR_RESET BIT1 | ||
6546 | #define MECR_ENABLE BIT0 | ||
6547 | |||
6548 | /* ME settings register(MESR) */ | ||
6549 | #define MESR_GATE_LSB 16 | ||
6550 | #define MESR_GATE_MASK BITS_H2L(31, MESR_GATE_LSB) | ||
6551 | |||
6552 | #define MESR_NUM_LSB 0 | ||
6553 | #define MESR_NUM_MASK BITS_H2L(5, MESR_NUM_LSB) | ||
6554 | |||
6555 | /* ME MVD register(MEMR) */ | ||
6556 | #define MEMR_MVDY_LSB 16 | ||
6557 | #define MESR_MVDY_MASK BITS_H2L(31, MEMR_MVDY_LSB) | ||
6558 | |||
6559 | #define MEMR_MVDX_LSB 0 | ||
6560 | #define MESR_MVDX_MASK BITS_H2L(15, MEMR_MVDX_LSB) | ||
6561 | |||
6562 | /* ME flag register(MEFR) */ | ||
6563 | #define MEFR_INTRA BIT1 | ||
6564 | #define MEFR_COMPLETED BIT0 | ||
6565 | |||
6566 | #ifndef __MIPS_ASSEMBLER | ||
6567 | |||
6568 | #define REG_ME_MECR REG32(ME_MECR) | ||
6569 | #define REG_ME_MERBAR REG32(ME_MERBAR) | ||
6570 | #define REG_ME_MECBAR REG32(ME_MECBAR) | ||
6571 | #define REG_ME_MEDAR REG32(ME_MEDAR) | ||
6572 | #define REG_ME_MERFSR REG32(ME_MERFSR) | ||
6573 | #define REG_ME_MECFSR REG32(ME_MECFSR) | ||
6574 | #define REG_ME_MEDFSR REG32(ME_MEDFSR) | ||
6575 | #define REG_ME_MESR REG32(ME_MESR) | ||
6576 | #define REG_ME_MEMR REG32(ME_MEMR) | ||
6577 | #define REG_ME_MEFR REG32(ME_MEFR) | ||
6578 | |||
6579 | #endif /* __MIPS_ASSEMBLER */ | ||
6580 | |||
6581 | #define MSC0_BASE 0xB0021000 | ||
6582 | #define MSC1_BASE 0xB0022000 | ||
6583 | #define MSC2_BASE 0xB0023000 | ||
6584 | |||
6585 | /************************************************************************* | ||
6586 | * MSC | ||
6587 | ************************************************************************/ | ||
6588 | /* n = 0, 1 (MSC0, MSC1) */ | ||
6589 | #define MSC_STRPCL(n) (MSC0_BASE + (n)*0x1000 + 0x000) | ||
6590 | #define MSC_STAT(n) (MSC0_BASE + (n)*0x1000 + 0x004) | ||
6591 | #define MSC_CLKRT(n) (MSC0_BASE + (n)*0x1000 + 0x008) | ||
6592 | #define MSC_CMDAT(n) (MSC0_BASE + (n)*0x1000 + 0x00C) | ||
6593 | #define MSC_RESTO(n) (MSC0_BASE + (n)*0x1000 + 0x010) | ||
6594 | #define MSC_RDTO(n) (MSC0_BASE + (n)*0x1000 + 0x014) | ||
6595 | #define MSC_BLKLEN(n) (MSC0_BASE + (n)*0x1000 + 0x018) | ||
6596 | #define MSC_NOB(n) (MSC0_BASE + (n)*0x1000 + 0x01C) | ||
6597 | #define MSC_SNOB(n) (MSC0_BASE + (n)*0x1000 + 0x020) | ||
6598 | #define MSC_IMASK(n) (MSC0_BASE + (n)*0x1000 + 0x024) | ||
6599 | #define MSC_IREG(n) (MSC0_BASE + (n)*0x1000 + 0x028) | ||
6600 | #define MSC_CMD(n) (MSC0_BASE + (n)*0x1000 + 0x02C) | ||
6601 | #define MSC_ARG(n) (MSC0_BASE + (n)*0x1000 + 0x030) | ||
6602 | #define MSC_RES(n) (MSC0_BASE + (n)*0x1000 + 0x034) | ||
6603 | #define MSC_RXFIFO(n) (MSC0_BASE + (n)*0x1000 + 0x038) | ||
6604 | #define MSC_TXFIFO(n) (MSC0_BASE + (n)*0x1000 + 0x03C) | ||
6605 | #define MSC_LPM(n) (MSC0_BASE + (n)*0x1000 + 0x040) | ||
6606 | |||
6607 | #define REG_MSC_STRPCL(n) REG16(MSC_STRPCL(n)) | ||
6608 | #define REG_MSC_STAT(n) REG32(MSC_STAT(n)) | ||
6609 | #define REG_MSC_CLKRT(n) REG16(MSC_CLKRT(n)) | ||
6610 | #define REG_MSC_CMDAT(n) REG32(MSC_CMDAT(n)) | ||
6611 | #define REG_MSC_RESTO(n) REG16(MSC_RESTO(n)) | ||
6612 | #define REG_MSC_RDTO(n) REG32(MSC_RDTO(n)) | ||
6613 | #define REG_MSC_BLKLEN(n) REG16(MSC_BLKLEN(n)) | ||
6614 | #define REG_MSC_NOB(n) REG16(MSC_NOB(n)) | ||
6615 | #define REG_MSC_SNOB(n) REG16(MSC_SNOB(n)) | ||
6616 | #define REG_MSC_IMASK(n) REG32(MSC_IMASK(n)) | ||
6617 | #define REG_MSC_IREG(n) REG16(MSC_IREG(n)) | ||
6618 | #define REG_MSC_CMD(n) REG8(MSC_CMD(n)) | ||
6619 | #define REG_MSC_ARG(n) REG32(MSC_ARG(n)) | ||
6620 | #define REG_MSC_RES(n) REG16(MSC_RES(n)) | ||
6621 | #define REG_MSC_RXFIFO(n) REG32(MSC_RXFIFO(n)) | ||
6622 | #define REG_MSC_TXFIFO(n) REG32(MSC_TXFIFO(n)) | ||
6623 | #define REG_MSC_LPM(n) REG32(MSC_LPM(n)) | ||
6624 | |||
6625 | /* MSC Clock and Control Register (MSC_STRPCL) */ | ||
6626 | #define MSC_STRPCL_SEND_CCSD (1 << 15) /*send command completion signal disable to ceata */ | ||
6627 | #define MSC_STRPCL_SEND_AS_CCSD (1 << 14) /*send internally generated stop after sending ccsd */ | ||
6628 | #define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) | ||
6629 | #define MSC_STRPCL_EXIT_TRANSFER (1 << 6) | ||
6630 | #define MSC_STRPCL_START_READWAIT (1 << 5) | ||
6631 | #define MSC_STRPCL_STOP_READWAIT (1 << 4) | ||
6632 | #define MSC_STRPCL_RESET (1 << 3) | ||
6633 | #define MSC_STRPCL_START_OP (1 << 2) | ||
6634 | #define MSC_STRPCL_CLOCK_CONTROL_BIT 0 | ||
6635 | #define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) | ||
6636 | #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */ | ||
6637 | #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */ | ||
6638 | |||
6639 | /* MSC Status Register (MSC_STAT) */ | ||
6640 | #define MSC_STAT_AUTO_CMD_DONE (1 << 31) /*12 is internally generated by controller has finished */ | ||
6641 | #define MSC_STAT_IS_RESETTING (1 << 15) | ||
6642 | #define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) | ||
6643 | #define MSC_STAT_PRG_DONE (1 << 13) | ||
6644 | #define MSC_STAT_DATA_TRAN_DONE (1 << 12) | ||
6645 | #define MSC_STAT_END_CMD_RES (1 << 11) | ||
6646 | #define MSC_STAT_DATA_FIFO_AFULL (1 << 10) | ||
6647 | #define MSC_STAT_IS_READWAIT (1 << 9) | ||
6648 | #define MSC_STAT_CLK_EN (1 << 8) | ||
6649 | #define MSC_STAT_DATA_FIFO_FULL (1 << 7) | ||
6650 | #define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) | ||
6651 | #define MSC_STAT_CRC_RES_ERR (1 << 5) | ||
6652 | #define MSC_STAT_CRC_READ_ERROR (1 << 4) | ||
6653 | #define MSC_STAT_CRC_WRITE_ERROR_BIT 2 | ||
6654 | #define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) | ||
6655 | #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */ | ||
6656 | #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */ | ||
6657 | #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */ | ||
6658 | #define MSC_STAT_TIME_OUT_RES (1 << 1) | ||
6659 | #define MSC_STAT_TIME_OUT_READ (1 << 0) | ||
6660 | |||
6661 | /* MSC Bus Clock Control Register (MSC_CLKRT) */ | ||
6662 | #define MSC_CLKRT_CLK_DIV_BIT 14 | ||
6663 | #define MSC_CLKRT_CLK_DIV_MASK (0x3 << MSC_CLKRT_CLK_DIV_BIT) | ||
6664 | #define MSC_CLKRT_CLK_SRC_DIV_1 (0x0 << MSC_CLKRT_CLK_DIV_BIT) /* CLK_SRC */ | ||
6665 | #define MSC_CLKRT_CLK_SRC_DIV_2 (0x1 << MSC_CLKRT_CLK_DIV_BIT) /* 1/2 of CLK_SRC */ | ||
6666 | #define MSC_CLKRT_CLK_SRC_DIV_3 (0x2 << MSC_CLKRT_CLK_DIV_BIT) /* 1/3 of CLK_SRC */ | ||
6667 | #define MSC_CLKRT_CLK_SRC_DIV_4 (0x3 << MSC_CLKRT_CLK_DIV_BIT) /* 1/4 of CLK_SRC */ | ||
6668 | |||
6669 | #define MSC_CLKRT_CLK_RATE_BIT 0 | ||
6670 | #define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) | ||
6671 | #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */ | ||
6672 | #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */ | ||
6673 | #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */ | ||
6674 | #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */ | ||
6675 | #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */ | ||
6676 | #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */ | ||
6677 | #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */ | ||
6678 | #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */ | ||
6679 | |||
6680 | /* MSC Command Sequence Control Register (MSC_CMDAT) */ | ||
6681 | #define MSC_CMDAT_CCS_EXPECTED (1 << 31) /* interrupts are enabled in ce-ata */ | ||
6682 | #define MSC_CMDAT_READ_CEATA (1 << 30) | ||
6683 | #define MSC_CMDAT_SDIO_PRDT (1 << 17) /* exact 2 cycle */ | ||
6684 | #define MSC_CMDAT_SEND_AS_STOP (1 << 16) | ||
6685 | #define MSC_CMDAT_RTRG_BIT 14 | ||
6686 | #define MSC_CMDAT_RTRG_EQUALT_8 (0x0 << MSC_CMDAT_RTRG_BIT) /*reset value*/ | ||
6687 | #define MSC_CMDAT_RTRG_EQUALT_16 (0x1 << MSC_CMDAT_RTRG_BIT) | ||
6688 | #define MSC_CMDAT_RTRG_EQUALT_24 (0x2 << MSC_CMDAT_RTRG_BIT) | ||
6689 | |||
6690 | #define MSC_CMDAT_TTRG_BIT 12 | ||
6691 | #define MSC_CMDAT_TTRG_LESS_8 (0x0 << MSC_CMDAT_TTRG_BIT) /*reset value*/ | ||
6692 | #define MSC_CMDAT_TTRG_LESS_16 (0x1 << MSC_CMDAT_TTRG_BIT) | ||
6693 | #define MSC_CMDAT_TTRG_LESS_24 (0x2 << MSC_CMDAT_TTRG_BIT) | ||
6694 | #define MSC_CMDAT_STOP_ABORT (1 << 11) | ||
6695 | #define MSC_CMDAT_BUS_WIDTH_BIT 9 | ||
6696 | #define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) | ||
6697 | #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */ | ||
6698 | #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */ | ||
6699 | #define MSC_CMDAT_BUS_WIDTH_8BIT (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) /* 8-bit data bus */ | ||
6700 | #define MSC_CMDAT_DMA_EN (1 << 8) | ||
6701 | #define MSC_CMDAT_INIT (1 << 7) | ||
6702 | #define MSC_CMDAT_BUSY (1 << 6) | ||
6703 | #define MSC_CMDAT_STREAM_BLOCK (1 << 5) | ||
6704 | #define MSC_CMDAT_WRITE (1 << 4) | ||
6705 | #define MSC_CMDAT_READ (0 << 4) | ||
6706 | #define MSC_CMDAT_DATA_EN (1 << 3) | ||
6707 | #define MSC_CMDAT_RESPONSE_BIT 0 | ||
6708 | #define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) | ||
6709 | #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */ | ||
6710 | #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */ | ||
6711 | #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */ | ||
6712 | #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */ | ||
6713 | #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */ | ||
6714 | #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */ | ||
6715 | #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */ | ||
6716 | #define MSC_CMDAT_RESRONSE_R7 (0x7 << MSC_CMDAT_RESPONSE_BIT) /* Format R7 */ | ||
6717 | |||
6718 | #define CMDAT_DMA_EN (1 << 8) | ||
6719 | #define CMDAT_INIT (1 << 7) | ||
6720 | #define CMDAT_BUSY (1 << 6) | ||
6721 | #define CMDAT_STREAM (1 << 5) | ||
6722 | #define CMDAT_WRITE (1 << 4) | ||
6723 | #define CMDAT_DATA_EN (1 << 3) | ||
6724 | |||
6725 | /* MSC Interrupts Mask Register (MSC_IMASK) */ | ||
6726 | #define MSC_IMASK_AUTO_CMD_DONE (1 << 15) | ||
6727 | #define MSC_IMASK_DATA_FIFO_FULL (1 << 14) | ||
6728 | #define MSC_IMASK_DATA_FIFO_EMP (1 << 13) | ||
6729 | #define MSC_IMASK_CRC_RES_ERR (1 << 12) | ||
6730 | #define MSC_IMASK_CRC_READ_ERR (1 << 11) | ||
6731 | #define MSC_IMASK_CRC_WRITE_ERR (1 << 10) | ||
6732 | #define MSC_IMASK_TIME_OUT_RES (1 << 9) | ||
6733 | #define MSC_IMASK_TIME_OUT_READ (1 << 8) | ||
6734 | #define MSC_IMASK_SDIO (1 << 7) | ||
6735 | #define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) | ||
6736 | #define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) | ||
6737 | #define MSC_IMASK_END_CMD_RES (1 << 2) | ||
6738 | #define MSC_IMASK_PRG_DONE (1 << 1) | ||
6739 | #define MSC_IMASK_DATA_TRAN_DONE (1 << 0) | ||
6740 | |||
6741 | /* MSC Interrupts Status Register (MSC_IREG) */ | ||
6742 | #define MSC_IREG_AUTO_CMD_DONE (1 << 15) | ||
6743 | #define MSC_IREG_DATA_FIFO_FULL (1 << 14) | ||
6744 | #define MSC_IREG_DATA_FIFO_EMP (1 << 13) | ||
6745 | #define MSC_IREG_CRC_RES_ERR (1 << 12) | ||
6746 | #define MSC_IREG_CRC_READ_ERR (1 << 11) | ||
6747 | #define MSC_IREG_CRC_WRITE_ERR (1 << 10) | ||
6748 | #define MSC_IREG_TIMEOUT_RES (1 << 9) | ||
6749 | #define MSC_IREG_TIMEOUT_READ (1 << 8) | ||
6750 | #define MSC_IREG_SDIO (1 << 7) | ||
6751 | #define MSC_IREG_TXFIFO_WR_REQ (1 << 6) | ||
6752 | #define MSC_IREG_RXFIFO_RD_REQ (1 << 5) | ||
6753 | #define MSC_IREG_END_CMD_RES (1 << 2) | ||
6754 | #define MSC_IREG_PRG_DONE (1 << 1) | ||
6755 | #define MSC_IREG_DATA_TRAN_DONE (1 << 0) | ||
6756 | |||
6757 | /* MSC Low Power Mode Register (MSC_LPM) */ | ||
6758 | #define MSC_SET_HISPD (1 << 31) | ||
6759 | #define MSC_SET_LPM (1 << 0) | ||
6760 | |||
6761 | #ifndef __MIPS_ASSEMBLER | ||
6762 | |||
6763 | /*************************************************************************** | ||
6764 | * MSC | ||
6765 | ***************************************************************************/ | ||
6766 | /* n = 0, 1 (MSC0, MSC1) */ | ||
6767 | |||
6768 | #define __msc_start_op(n) \ | ||
6769 | ( REG_MSC_STRPCL(n) = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START ) | ||
6770 | |||
6771 | #define __msc_set_resto(n, to) ( REG_MSC_RESTO(n) = to ) | ||
6772 | #define __msc_set_rdto(n, to) ( REG_MSC_RDTO(n) = to ) | ||
6773 | #define __msc_set_cmd(n, cmd) ( REG_MSC_CMD(n) = cmd ) | ||
6774 | #define __msc_set_arg(n, arg) ( REG_MSC_ARG(n) = arg ) | ||
6775 | #define __msc_set_nob(n, nob) ( REG_MSC_NOB(n) = nob ) | ||
6776 | #define __msc_get_nob(n) ( REG_MSC_NOB(n) ) | ||
6777 | #define __msc_set_blklen(n, len) ( REG_MSC_BLKLEN(n) = len ) | ||
6778 | #define __msc_set_cmdat(n, cmdat) ( REG_MSC_CMDAT(n) = cmdat ) | ||
6779 | |||
6780 | #define __msc_set_cmdat_bus_width1(n) \ | ||
6781 | do { \ | ||
6782 | REG_MSC_CMDAT(n) &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ | ||
6783 | REG_MSC_CMDAT(n) |= MSC_CMDAT_BUS_WIDTH_1BIT; \ | ||
6784 | } while(0) | ||
6785 | |||
6786 | #define __msc_set_cmdat_bus_width4(n) \ | ||
6787 | do { \ | ||
6788 | REG_MSC_CMDAT(n) &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ | ||
6789 | REG_MSC_CMDAT(n) |= MSC_CMDAT_BUS_WIDTH_4BIT; \ | ||
6790 | } while(0) | ||
6791 | |||
6792 | #define __msc_set_cmdat_dma_en(n) ( REG_MSC_CMDAT(n) |= MSC_CMDAT_DMA_EN ) | ||
6793 | #define __msc_set_cmdat_init(n) ( REG_MSC_CMDAT(n) |= MSC_CMDAT_INIT ) | ||
6794 | #define __msc_set_cmdat_busy(n) ( REG_MSC_CMDAT(n) |= MSC_CMDAT_BUSY ) | ||
6795 | #define __msc_set_cmdat_stream(n) ( REG_MSC_CMDAT(n) |= MSC_CMDAT_STREAM_BLOCK ) | ||
6796 | #define __msc_set_cmdat_block(n) ( REG_MSC_CMDAT(n) &= ~MSC_CMDAT_STREAM_BLOCK ) | ||
6797 | #define __msc_set_cmdat_read(n) ( REG_MSC_CMDAT(n) &= ~MSC_CMDAT_WRITE ) | ||
6798 | #define __msc_set_cmdat_write(n) ( REG_MSC_CMDAT(n) |= MSC_CMDAT_WRITE ) | ||
6799 | #define __msc_set_cmdat_data_en(n) ( REG_MSC_CMDAT(n) |= MSC_CMDAT_DATA_EN ) | ||
6800 | |||
6801 | /* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */ | ||
6802 | #define __msc_set_cmdat_res_format(n, r) \ | ||
6803 | do { \ | ||
6804 | REG_MSC_CMDAT(n) &= ~MSC_CMDAT_RESPONSE_MASK; \ | ||
6805 | REG_MSC_CMDAT(n) |= (r); \ | ||
6806 | } while(0) | ||
6807 | |||
6808 | #define __msc_clear_cmdat(n) \ | ||
6809 | REG_MSC_CMDAT(n) &= ~( MSC_CMDAT_STOP_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \ | ||
6810 | MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE | \ | ||
6811 | MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_MASK ) | ||
6812 | |||
6813 | #define __msc_get_imask(n) ( REG_MSC_IMASK(n) ) | ||
6814 | #define __msc_mask_all_intrs(n) ( REG_MSC_IMASK(n) = 0xff ) | ||
6815 | #define __msc_unmask_all_intrs(n) ( REG_MSC_IMASK(n) = 0x00 ) | ||
6816 | #define __msc_mask_rd(n) ( REG_MSC_IMASK(n) |= MSC_IMASK_RXFIFO_RD_REQ ) | ||
6817 | #define __msc_unmask_rd(n) ( REG_MSC_IMASK(n) &= ~MSC_IMASK_RXFIFO_RD_REQ ) | ||
6818 | #define __msc_mask_wr(n) ( REG_MSC_IMASK(n) |= MSC_IMASK_TXFIFO_WR_REQ ) | ||
6819 | #define __msc_unmask_wr(n) ( REG_MSC_IMASK(n) &= ~MSC_IMASK_TXFIFO_WR_REQ ) | ||
6820 | #define __msc_mask_endcmdres(n) ( REG_MSC_IMASK(n) |= MSC_IMASK_END_CMD_RES ) | ||
6821 | #define __msc_unmask_endcmdres(n) ( REG_MSC_IMASK(n) &= ~MSC_IMASK_END_CMD_RES ) | ||
6822 | #define __msc_mask_datatrandone(n) ( REG_MSC_IMASK(n) |= MSC_IMASK_DATA_TRAN_DONE ) | ||
6823 | #define __msc_unmask_datatrandone(n) ( REG_MSC_IMASK(n) &= ~MSC_IMASK_DATA_TRAN_DONE ) | ||
6824 | #define __msc_mask_prgdone(n) ( REG_MSC_IMASK(n) |= MSC_IMASK_PRG_DONE ) | ||
6825 | #define __msc_unmask_prgdone(n) ( REG_MSC_IMASK(n) &= ~MSC_IMASK_PRG_DONE ) | ||
6826 | |||
6827 | /* m=0,1,2,3,4,5,6,7 */ | ||
6828 | #define __msc_set_clkrt(n, m) \ | ||
6829 | do { \ | ||
6830 | REG_MSC_CLKRT(n) = m; \ | ||
6831 | } while(0) | ||
6832 | |||
6833 | #define __msc_get_ireg(n) ( REG_MSC_IREG(n) ) | ||
6834 | #define __msc_ireg_rd(n) ( REG_MSC_IREG(n) & MSC_IREG_RXFIFO_RD_REQ ) | ||
6835 | #define __msc_ireg_wr(n) ( REG_MSC_IREG(n) & MSC_IREG_TXFIFO_WR_REQ ) | ||
6836 | #define __msc_ireg_end_cmd_res(n) ( REG_MSC_IREG(n) & MSC_IREG_END_CMD_RES ) | ||
6837 | #define __msc_ireg_data_tran_done(n) ( REG_MSC_IREG(n) & MSC_IREG_DATA_TRAN_DONE ) | ||
6838 | #define __msc_ireg_prg_done(n) ( REG_MSC_IREG(n) & MSC_IREG_PRG_DONE ) | ||
6839 | #define __msc_ireg_clear_end_cmd_res(n) ( REG_MSC_IREG(n) = MSC_IREG_END_CMD_RES ) | ||
6840 | #define __msc_ireg_clear_data_tran_done(n) ( REG_MSC_IREG(n) = MSC_IREG_DATA_TRAN_DONE ) | ||
6841 | #define __msc_ireg_clear_prg_done(n) ( REG_MSC_IREG(n) = MSC_IREG_PRG_DONE ) | ||
6842 | |||
6843 | #define __msc_get_stat(n) ( REG_MSC_STAT(n) ) | ||
6844 | #define __msc_stat_not_end_cmd_res(n) ( (REG_MSC_STAT(n) & MSC_STAT_END_CMD_RES) == 0) | ||
6845 | #define __msc_stat_crc_err(n) \ | ||
6846 | ( REG_MSC_STAT(n) & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) ) | ||
6847 | #define __msc_stat_res_crc_err(n) ( REG_MSC_STAT(n) & MSC_STAT_CRC_RES_ERR ) | ||
6848 | #define __msc_stat_rd_crc_err(n) ( REG_MSC_STAT(n) & MSC_STAT_CRC_READ_ERROR ) | ||
6849 | #define __msc_stat_wr_crc_err(n) ( REG_MSC_STAT(n) & MSC_STAT_CRC_WRITE_ERROR_YES ) | ||
6850 | #define __msc_stat_resto_err(n) ( REG_MSC_STAT(n) & MSC_STAT_TIME_OUT_RES ) | ||
6851 | #define __msc_stat_rdto_err(n) ( REG_MSC_STAT(n) & MSC_STAT_TIME_OUT_READ ) | ||
6852 | |||
6853 | #define __msc_rd_resfifo(n) ( REG_MSC_RES(n) ) | ||
6854 | #define __msc_rd_rxfifo(n) ( REG_MSC_RXFIFO(n) ) | ||
6855 | #define __msc_wr_txfifo(n, v) ( REG_MSC_TXFIFO(n) = v ) | ||
6856 | |||
6857 | #define __msc_reset(n) \ | ||
6858 | do { \ | ||
6859 | REG_MSC_STRPCL(n) = MSC_STRPCL_RESET; \ | ||
6860 | while (REG_MSC_STAT(n) & MSC_STAT_IS_RESETTING); \ | ||
6861 | } while (0) | ||
6862 | |||
6863 | #define __msc_start_clk(n) \ | ||
6864 | do { \ | ||
6865 | REG_MSC_STRPCL(n) = MSC_STRPCL_CLOCK_CONTROL_START; \ | ||
6866 | } while (0) | ||
6867 | |||
6868 | #define __msc_stop_clk(n) \ | ||
6869 | do { \ | ||
6870 | REG_MSC_STRPCL(n) = MSC_STRPCL_CLOCK_CONTROL_STOP; \ | ||
6871 | } while (0) | ||
6872 | |||
6873 | #define MMC_CLK 19169200 | ||
6874 | #define SD_CLK 24576000 | ||
6875 | |||
6876 | /* msc_clk should little than pclk and little than clk retrieve from card */ | ||
6877 | #define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \ | ||
6878 | do { \ | ||
6879 | unsigned int rate, pclk, i; \ | ||
6880 | pclk = dev_clk; \ | ||
6881 | rate = type?SD_CLK:MMC_CLK; \ | ||
6882 | if (msc_clk && msc_clk < pclk) \ | ||
6883 | pclk = msc_clk; \ | ||
6884 | i = 0; \ | ||
6885 | while (pclk < rate) \ | ||
6886 | { \ | ||
6887 | i ++; \ | ||
6888 | rate >>= 1; \ | ||
6889 | } \ | ||
6890 | lv = i; \ | ||
6891 | } while(0) | ||
6892 | |||
6893 | /* divide rate to little than or equal to 400kHz */ | ||
6894 | #define __msc_calc_slow_clk_divisor(type, lv) \ | ||
6895 | do { \ | ||
6896 | unsigned int rate, i; \ | ||
6897 | rate = (type?SD_CLK:MMC_CLK)/1000/400; \ | ||
6898 | i = 0; \ | ||
6899 | while (rate > 0) \ | ||
6900 | { \ | ||
6901 | rate >>= 1; \ | ||
6902 | i ++; \ | ||
6903 | } \ | ||
6904 | lv = i; \ | ||
6905 | } while(0) | ||
6906 | |||
6907 | #endif /* __MIPS_ASSEMBLER */ | ||
6908 | |||
6909 | #define NEMC_BASE 0xB3410000 | ||
6910 | |||
6911 | /************************************************************************* | ||
6912 | * NEMC (External Memory Controller for NAND) | ||
6913 | *************************************************************************/ | ||
6914 | |||
6915 | #define NEMC_NFCSR (NEMC_BASE + 0x50) /* NAND Flash Control/Status Register */ | ||
6916 | #define NEMC_SMCR (NEMC_BASE + 0x14) /* Static Memory Control Register 1 */ | ||
6917 | #define NEMC_PNCR (NEMC_BASE + 0x100) | ||
6918 | #define NEMC_PNDR (NEMC_BASE + 0x104) | ||
6919 | #define NEMC_BITCNT (NEMC_BASE + 0x108) | ||
6920 | |||
6921 | #define REG_NEMC_NFCSR REG32(NEMC_NFCSR) | ||
6922 | #define REG_NEMC_SMCR1 REG32(NEMC_SMCR) | ||
6923 | #define REG_NEMC_PNCR REG32(NEMC_PNCR) | ||
6924 | #define REG_NEMC_PNDR REG32(NEMC_PNDR) | ||
6925 | #define REG_NEMC_BITCNT REG32(NEMC_BITCNT) | ||
6926 | |||
6927 | /* NAND Flash Control/Status Register */ | ||
6928 | #define NEMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */ | ||
6929 | #define NEMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */ | ||
6930 | #define NEMC_NFCSR_NFCE3 (1 << 5) | ||
6931 | #define NEMC_NFCSR_NFE3 (1 << 4) | ||
6932 | #define NEMC_NFCSR_NFCE2 (1 << 3) | ||
6933 | #define NEMC_NFCSR_NFE2 (1 << 2) | ||
6934 | #define NEMC_NFCSR_NFCE1 (1 << 1) | ||
6935 | #define NEMC_NFCSR_NFE1 (1 << 0) | ||
6936 | |||
6937 | #define UDC_BASE 0xB3440000 | ||
6938 | |||
6939 | /************************************************************************* | ||
6940 | * USB Device | ||
6941 | *************************************************************************/ | ||
6942 | #define USB_BASE UDC_BASE | ||
6943 | |||
6944 | #define USB_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */ | ||
6945 | #define USB_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */ | ||
6946 | #define USB_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */ | ||
6947 | #define USB_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */ | ||
6948 | #define USB_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */ | ||
6949 | #define USB_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */ | ||
6950 | #define USB_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */ | ||
6951 | #define USB_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */ | ||
6952 | #define USB_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */ | ||
6953 | #define USB_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */ | ||
6954 | #define USB_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */ | ||
6955 | |||
6956 | #define USB_CSR0 (USB_BASE + 0x12) /* EP0 CSR 16-bit */ | ||
6957 | #define USB_COUNT0 (USB_BASE + 0x18) /* EP0 OUT FIFO count 8-bit */ | ||
6958 | |||
6959 | #define USB_INMAXP (USB_BASE + 0x10) /* EP1-15 IN Max Pkt Size 16-bit */ | ||
6960 | #define USB_INCSR (USB_BASE + 0x12) /* EP1-15 IN CSR LSB 8/16bit */ | ||
6961 | #define USB_INCSRH (USB_BASE + 0x13) /* EP1-15 IN CSR MSB 8-bit */ | ||
6962 | #define USB_OUTMAXP (USB_BASE + 0x14) /* EP1-15 OUT Max Pkt Size 16-bit */ | ||
6963 | #define USB_OUTCSR (USB_BASE + 0x16) /* EP1-15 OUT CSR LSB 8/16bit */ | ||
6964 | #define USB_OUTCSRH (USB_BASE + 0x17) /* EP1-15 OUT CSR MSB 8-bit */ | ||
6965 | #define USB_OUTCOUNT (USB_BASE + 0x18) /* EP1-15 OUT FIFO count 16-bit */ | ||
6966 | |||
6967 | #define USB_FIFO_EP(n) (USB_BASE + (n)*4 + 0x20) | ||
6968 | |||
6969 | #define USB_EPINFO (USB_BASE + 0x78) /* Endpoint information */ | ||
6970 | #define USB_RAMINFO (USB_BASE + 0x79) /* RAM information */ | ||
6971 | |||
6972 | #define USB_INTR (USB_BASE + 0x200) /* DMA pending interrupts */ | ||
6973 | #define USB_CNTL(n) (USB_BASE + (n)*0x10 + 0x204) /* DMA channel n control */ | ||
6974 | #define USB_ADDR(n) (USB_BASE + (n)*0x10 + 0x208) /* DMA channel n AHB memory addr */ | ||
6975 | #define USB_COUNT(n) (USB_BASE + (n)*0x10 + 0x20c) /* DMA channel n byte count */ | ||
6976 | |||
6977 | /* Power register bit masks */ | ||
6978 | #define USB_POWER_SUSPENDM 0x01 | ||
6979 | #define USB_POWER_RESUME 0x04 | ||
6980 | #define USB_POWER_HSMODE 0x10 | ||
6981 | #define USB_POWER_HSENAB 0x20 | ||
6982 | #define USB_POWER_SOFTCONN 0x40 | ||
6983 | |||
6984 | /* Interrupt register bit masks */ | ||
6985 | #define USB_INTR_SUSPEND 0x01 | ||
6986 | #define USB_INTR_RESUME 0x02 | ||
6987 | #define USB_INTR_RESET 0x04 | ||
6988 | |||
6989 | #define USB_INTR_EP(n) (1 << (n)) | ||
6990 | |||
6991 | /* CSR0 bit masks */ | ||
6992 | #define USB_CSR0_OUTPKTRDY 0x01 | ||
6993 | #define USB_CSR0_INPKTRDY 0x02 | ||
6994 | #define USB_CSR0_SENTSTALL 0x04 | ||
6995 | #define USB_CSR0_DATAEND 0x08 | ||
6996 | #define USB_CSR0_SETUPEND 0x10 | ||
6997 | #define USB_CSR0_SENDSTALL 0x20 | ||
6998 | #define USB_CSR0_SVDOUTPKTRDY 0x40 | ||
6999 | #define USB_CSR0_SVDSETUPEND 0x80 | ||
7000 | #define USB_CSR0_FLUSHFIFO 0x100 | ||
7001 | |||
7002 | /* Endpoint CSR register bits */ | ||
7003 | #define USB_INCSRH_AUTOSET 0x80 | ||
7004 | #define USB_INCSRH_ISO 0x40 | ||
7005 | #define USB_INCSRH_MODE 0x20 | ||
7006 | #define USB_INCSRH_DMAREQENAB 0x10 | ||
7007 | #define USB_INCSRH_FRCDATATOG 0x08 | ||
7008 | #define USB_INCSRH_DMAREQMODE 0x04 | ||
7009 | #define USB_INCSR_CDT 0x40 | ||
7010 | #define USB_INCSR_SENTSTALL 0x20 | ||
7011 | #define USB_INCSR_SENDSTALL 0x10 | ||
7012 | #define USB_INCSR_FF 0x08 | ||
7013 | #define USB_INCSR_UNDERRUN 0x04 | ||
7014 | #define USB_INCSR_FFNOTEMPT 0x02 | ||
7015 | #define USB_INCSR_INPKTRDY 0x01 | ||
7016 | #define USB_OUTCSRH_AUTOCLR 0x80 | ||
7017 | #define USB_OUTCSRH_ISO 0x40 | ||
7018 | #define USB_OUTCSRH_DMAREQENAB 0x20 | ||
7019 | #define USB_OUTCSRH_DNYT 0x10 | ||
7020 | #define USB_OUTCSRH_DMAREQMODE 0x08 | ||
7021 | #define USB_OUTCSR_CDT 0x80 | ||
7022 | #define USB_OUTCSR_SENTSTALL 0x40 | ||
7023 | #define USB_OUTCSR_SENDSTALL 0x20 | ||
7024 | #define USB_OUTCSR_FF 0x10 | ||
7025 | #define USB_OUTCSR_DATAERR 0x08 | ||
7026 | #define USB_OUTCSR_OVERRUN 0x04 | ||
7027 | #define USB_OUTCSR_FFFULL 0x02 | ||
7028 | #define USB_OUTCSR_OUTPKTRDY 0x01 | ||
7029 | |||
7030 | /* Testmode register bits */ | ||
7031 | #define USB_TEST_SE0NAK 0x01 | ||
7032 | #define USB_TEST_J 0x02 | ||
7033 | #define USB_TEST_K 0x04 | ||
7034 | #define USB_TEST_PACKET 0x08 | ||
7035 | #define USB_TEST_FORCE_HS 0x10 | ||
7036 | #define USB_TEST_FORCE_FS 0x20 | ||
7037 | #define USB_TEST_ALL ( USB_TEST_SE0NAK | USB_TEST_J \ | ||
7038 | | USB_TEST_K | USB_TEST_PACKET \ | ||
7039 | | USB_TEST_FORCE_HS | USB_TEST_FORCE_FS) | ||
7040 | |||
7041 | /* DMA control bits */ | ||
7042 | #define USB_CNTL_ENA 0x01 | ||
7043 | #define USB_CNTL_DIR_IN 0x02 | ||
7044 | #define USB_CNTL_MODE_1 0x04 | ||
7045 | #define USB_CNTL_INTR_EN 0x08 | ||
7046 | #define USB_CNTL_EP(n) ((n) << 4) | ||
7047 | #define USB_CNTL_BURST_0 (0 << 9) | ||
7048 | #define USB_CNTL_BURST_4 (1 << 9) | ||
7049 | #define USB_CNTL_BURST_8 (2 << 9) | ||
7050 | #define USB_CNTL_BURST_16 (3 << 9) | ||
7051 | |||
7052 | /* DMA interrupt bits */ | ||
7053 | #define USB_INTR_DMA_BULKIN 1 | ||
7054 | #define USB_INTR_DMA_BULKOUT 2 | ||
7055 | |||
7056 | #define REG_USB_FADDR REG8(USB_FADDR) | ||
7057 | #define REG_USB_POWER REG8(USB_POWER) | ||
7058 | #define REG_USB_INTRIN REG16(USB_INTRIN) | ||
7059 | #define REG_USB_INTROUT REG16(USB_INTROUT) | ||
7060 | #define REG_USB_INTRINE REG16(USB_INTRINE) | ||
7061 | #define REG_USB_INTROUTE REG16(USB_INTROUTE) | ||
7062 | #define REG_USB_INTRUSB REG8(USB_INTRUSB) | ||
7063 | #define REG_USB_INTRUSBE REG8(USB_INTRUSBE) | ||
7064 | #define REG_USB_FRAME REG16(USB_FRAME) | ||
7065 | #define REG_USB_INDEX REG8(USB_INDEX) | ||
7066 | #define REG_USB_TESTMODE REG8(USB_TESTMODE) | ||
7067 | |||
7068 | #define REG_USB_CSR0 REG16(USB_CSR0) | ||
7069 | #define REG_USB_COUNT0 REG8(USB_COUNT0) | ||
7070 | |||
7071 | #define REG_USB_INMAXP REG16(USB_INMAXP) | ||
7072 | #define REG_USB_INCSR REG16(USB_INCSR) | ||
7073 | #define REG_USB_INCSRH REG8(USB_INCSRH) | ||
7074 | #define REG_USB_OUTMAXP REG16(USB_OUTMAXP) | ||
7075 | #define REG_USB_OUTCSR REG16(USB_OUTCSR) | ||
7076 | #define REG_USB_OUTCSRH REG8(USB_OUTCSRH) | ||
7077 | #define REG_USB_OUTCOUNT REG16(USB_OUTCOUNT) | ||
7078 | |||
7079 | #define REG_USB_FIFO_EP(n) REG32(USB_FIFO_EP(n)) | ||
7080 | |||
7081 | #define REG_USB_INTR REG8(USB_INTR) | ||
7082 | #define REG_USB_CNTL(n) REG16(USB_CNTL(n)) | ||
7083 | #define REG_USB_ADDR(n) REG32(USB_ADDR(n)) | ||
7084 | #define REG_USB_COUNT(n) REG32(USB_COUNT(n)) | ||
7085 | |||
7086 | #define REG_USB_EPINFO REG8(USB_EPINFO) | ||
7087 | #define REG_USB_RAMINFO REG8(USB_RAMINFO) | ||
7088 | |||
7089 | /* | ||
7090 | * One wire bus interface(OWI) address definition | ||
7091 | */ | ||
7092 | #define OWI_BASE 0xb0072000 | ||
7093 | |||
7094 | /* | ||
7095 | * OWI registers offset address definition | ||
7096 | */ | ||
7097 | #define OWI_OWICFG_OFFSET (0x00) /* rw, 8, 0x00 */ | ||
7098 | #define OWI_OWICTL_OFFSET (0x04) /* rw, 8, 0x00 */ | ||
7099 | #define OWI_OWISTS_OFFSET (0x08) /* rw, 8, 0x00 */ | ||
7100 | #define OWI_OWIDAT_OFFSET (0x0c) /* rw, 8, 0x00 */ | ||
7101 | #define OWI_OWIDIV_OFFSET (0x10) /* rw, 8, 0x00 */ | ||
7102 | |||
7103 | /* | ||
7104 | * OWI registers address definition | ||
7105 | */ | ||
7106 | #define OWI_OWICFG (OWI_BASE + OWI_OWICFG_OFFSET) | ||
7107 | #define OWI_OWICTL (OWI_BASE + OWI_OWICTL_OFFSET) | ||
7108 | #define OWI_OWISTS (OWI_BASE + OWI_OWISTS_OFFSET) | ||
7109 | #define OWI_OWIDAT (OWI_BASE + OWI_OWIDAT_OFFSET) | ||
7110 | #define OWI_OWIDIV (OWI_BASE + OWI_OWIDIV_OFFSET) | ||
7111 | |||
7112 | /* | ||
7113 | * OWI registers common define | ||
7114 | */ | ||
7115 | |||
7116 | /* OWI configure register(OWICFG) */ | ||
7117 | #define OWICFG_MODE BIT7 | ||
7118 | #define OWICFG_RDDATA BIT6 | ||
7119 | #define OWICFG_WRDATA BIT5 | ||
7120 | #define OWICFG_RDST BIT4 | ||
7121 | #define OWICFG_WR1RD BIT3 | ||
7122 | #define OWICFG_WR0 BIT2 | ||
7123 | #define OWICFG_RST BIT1 | ||
7124 | #define OWICFG_ENA BIT0 | ||
7125 | |||
7126 | /* OWI control register(OWICTL) */ | ||
7127 | #define OWICTL_EBYTE BIT2 | ||
7128 | #define OWICTL_EBIT BIT1 | ||
7129 | #define OWICTL_ERST BIT0 | ||
7130 | |||
7131 | /* OWI status register(OWISTS) */ | ||
7132 | #define OWISTS_PST BIT7 | ||
7133 | #define OWISTS_BYTE_RDY BIT2 | ||
7134 | #define OWISTS_BIT_RDY BIT1 | ||
7135 | #define OWISTS_PST_RDY BIT0 | ||
7136 | |||
7137 | /* OWI clock divide register(OWIDIV) */ | ||
7138 | #define OWIDIV_CLKDIV_LSB 0 | ||
7139 | #define OWIDIV_CLKDIV_MASK BITS_H2L(5, OWIDIV_CLKDIV_LSB) | ||
7140 | |||
7141 | #ifndef __MIPS_ASSEMBLER | ||
7142 | |||
7143 | /* Basic ops */ | ||
7144 | #define REG_OWI_OWICFG REG8(OWI_OWICFG) | ||
7145 | #define REG_OWI_OWICTL REG8(OWI_OWICTL) | ||
7146 | #define REG_OWI_OWISTS REG8(OWI_OWISTS) | ||
7147 | #define REG_OWI_OWIDAT REG8(OWI_OWIDAT) | ||
7148 | #define REG_OWI_OWIDIV REG8(OWI_OWIDIV) | ||
7149 | |||
7150 | #endif /* __MIPS_ASSEMBLER */ | ||
7151 | |||
7152 | /* | ||
7153 | * Pulse-code modulation module(PCM) address definition | ||
7154 | */ | ||
7155 | #define PCM_BASE 0xb0071000 | ||
7156 | |||
7157 | /* | ||
7158 | * pcm number, jz4760x has only PCM0 | ||
7159 | */ | ||
7160 | |||
7161 | #define PCM0 0 | ||
7162 | #define PCM1 1 | ||
7163 | |||
7164 | /* PCM groups offset */ | ||
7165 | #define PCM_GOS 0x3000 | ||
7166 | |||
7167 | /* | ||
7168 | * PCM registers offset address definition | ||
7169 | */ | ||
7170 | #define PCM_PCTL_OFFSET (0x00) /* rw, 32, 0x00000000 */ | ||
7171 | #define PCM_PCFG_OFFSET (0x04) /* rw, 32, 0x00000110 */ | ||
7172 | #define PCM_PDP_OFFSET (0x08) /* rw, 32, 0x00000000 */ | ||
7173 | #define PCM_PINTC_OFFSET (0x0c) /* rw, 32, 0x00000000 */ | ||
7174 | #define PCM_PINTS_OFFSET (0x10) /* rw, 32, 0x00000100 */ | ||
7175 | #define PCM_PDIV_OFFSET (0x14) /* rw, 32, 0x00000001 */ | ||
7176 | |||
7177 | /* | ||
7178 | * PCM registers address definition | ||
7179 | */ | ||
7180 | #define PCM_PCTL(n) (PCM_BASE + (n) * PCM_GOS + PCM_PCTL_OFFSET) | ||
7181 | #define PCM_PCFG(n) (PCM_BASE + (n) * PCM_GOS + PCM_PCFG_OFFSET) | ||
7182 | #define PCM_PDP(n) (PCM_BASE + (n) * PCM_GOS + PCM_PDP_OFFSET) | ||
7183 | #define PCM_PINTC(n) (PCM_BASE + (n) * PCM_GOS + PCM_PINTC_OFFSET) | ||
7184 | #define PCM_PINTS(n) (PCM_BASE + (n) * PCM_GOS + PCM_PINTS_OFFSET) | ||
7185 | #define PCM_PDIV(n) (PCM_BASE + (n) * PCM_GOS + PCM_PDIV_OFFSET) | ||
7186 | |||
7187 | /* | ||
7188 | * CPM registers common define | ||
7189 | */ | ||
7190 | |||
7191 | /* PCM controller control register (PCTL) */ | ||
7192 | #define PCTL_ERDMA BIT9 | ||
7193 | #define PCTL_ETDMA BIT8 | ||
7194 | #define PCTL_LSMP BIT7 | ||
7195 | #define PCTL_ERPL BIT6 | ||
7196 | #define PCTL_EREC BIT5 | ||
7197 | #define PCTL_FLUSH BIT4 | ||
7198 | #define PCTL_RST BIT3 | ||
7199 | #define PCTL_CLKEN BIT1 | ||
7200 | #define PCTL_PCMEN BIT0 | ||
7201 | |||
7202 | /* PCM controller configure register (PCFG) */ | ||
7203 | #define PCFG_ISS_16BIT BIT12 | ||
7204 | #define PCFG_OSS_16BIT BIT11 | ||
7205 | #define PCFG_IMSBPOS BIT10 | ||
7206 | #define PCFG_OMSBPOS BIT9 | ||
7207 | #define PCFG_MODE_SLAVE BIT0 | ||
7208 | |||
7209 | #define PCFG_SLOT_LSB 13 | ||
7210 | #define PCFG_SLOT_MASK BITS_H2L(14, PCFG_SLOT_LSB) | ||
7211 | #define PCFG_SLOT(val) ((val) << PCFG_SLOT_LSB) | ||
7212 | |||
7213 | #define PCFG_RFTH_LSB 5 | ||
7214 | #define PCFG_RFTH_MASK BITS_H2L(8, PCFG_RFTH_LSB) | ||
7215 | |||
7216 | #define PCFG_TFTH_LSB 1 | ||
7217 | #define PCFG_TFTH_MASK BITS_H2L(4, PCFG_TFTH_LSB) | ||
7218 | |||
7219 | /* PCM controller interrupt control register(PINTC) */ | ||
7220 | #define PINTC_ETFS BIT3 | ||
7221 | #define PINTC_ETUR BIT2 | ||
7222 | #define PINTC_ERFS BIT1 | ||
7223 | #define PINTC_EROR BIT0 | ||
7224 | |||
7225 | /* PCM controller interrupt status register(PINTS) */ | ||
7226 | #define PINTS_RSTS BIT14 | ||
7227 | #define PINTS_TFS BIT8 | ||
7228 | #define PINTS_TUR BIT7 | ||
7229 | #define PINTS_RFS BIT1 | ||
7230 | #define PINTS_ROR BIT0 | ||
7231 | |||
7232 | #define PINTS_TFL_LSB 9 | ||
7233 | #define PINTS_TFL_MASK BITS_H2L(13, PINTS_TFL_LSB) | ||
7234 | |||
7235 | #define PINTS_RFL_LSB 2 | ||
7236 | #define PINTS_RFL_MASK BITS_H2L(6, PINTS_RFL_LSB) | ||
7237 | |||
7238 | /* PCM controller clock division register(PDIV) */ | ||
7239 | #define PDIV_SYNL_LSB 11 | ||
7240 | #define PDIV_SYNL_MASK BITS_H2L(16, PDIV_SYNL_LSB) | ||
7241 | |||
7242 | #define PDIV_SYNDIV_LSB 6 | ||
7243 | #define PDIV_SYNDIV_MASK BITS_H2L(10, PDIV_SYNDIV_LSB) | ||
7244 | |||
7245 | #define PDIV_CLKDIV_LSB 0 | ||
7246 | #define PDIV_CLKDIV_MASK BITS_H2L(5, PDIV_CLKDIV_LSB) | ||
7247 | |||
7248 | #ifndef __MIPS_ASSEMBLER | ||
7249 | |||
7250 | #define REG_PCM_PCTL(n) REG32(PCM_PCTL(n)) | ||
7251 | #define REG_PCM_PCFG(n) REG32(PCM_PCFG(n)) | ||
7252 | #define REG_PCM_PDP(n) REG32(PCM_PDP(n)) | ||
7253 | #define REG_PCM_PINTC(n) REG32(PCM_PINTC(n)) | ||
7254 | #define REG_PCM_PINTS(n) REG32(PCM_PINTS(n)) | ||
7255 | #define REG_PCM_PDIV(n) REG32(PCM_PDIV(n)) | ||
7256 | |||
7257 | /* | ||
7258 | * PCM_DIN, PCM_DOUT, PCM_CLK, PCM_SYN | ||
7259 | */ | ||
7260 | #define __gpio_as_pcm(n) \ | ||
7261 | do { \ | ||
7262 | switch(n) { \ | ||
7263 | case PCM0: __gpio_as_pcm0();break; \ | ||
7264 | case PCM1: __gpio_as_pcm1();break; \ | ||
7265 | } \ | ||
7266 | \ | ||
7267 | } while (0) | ||
7268 | |||
7269 | #define __pcm_enable(n) (REG_PCM_PCTL(n) |= PCTL_PCMEN) | ||
7270 | #define __pcm_disable(n) (REG_PCM_PCTL(n) &= ~PCTL_PCMEN) | ||
7271 | |||
7272 | #define __pcm_clk_enable(n) (REG_PCM_PCTL(n) |= PCTL_CLKEN) | ||
7273 | #define __pcm_clk_disable(n) (REG_PCM_PCTL(n) &= ~PCTL_CLKEN) | ||
7274 | |||
7275 | #define __pcm_reset(n) (REG_PCM_PCTL(n) |= PCTL_RST) | ||
7276 | #define __pcm_flush_fifo(n) (REG_PCM_PCTL(n) |= PCTL_FLUSH) | ||
7277 | |||
7278 | #define __pcm_enable_record(n) (REG_PCM_PCTL(n) |= PCTL_EREC) | ||
7279 | #define __pcm_disable_record(n) (REG_PCM_PCTL(n) &= ~PCTL_EREC) | ||
7280 | #define __pcm_enable_playback(n) (REG_PCM_PCTL(n) |= PCTL_ERPL) | ||
7281 | #define __pcm_disable_playback(n) (REG_PCM_PCTL(n) &= ~PCTL_ERPL) | ||
7282 | |||
7283 | #define __pcm_enable_rxfifo(n) __pcm_enable_record(n) | ||
7284 | #define __pcm_disable_rxfifo(n) __pcm_disable_record(n) | ||
7285 | #define __pcm_enable_txfifo(n) __pcm_enable_playback(n) | ||
7286 | #define __pcm_disable_txfifo(n) __pcm_disable_playback(n) | ||
7287 | |||
7288 | #define __pcm_last_sample(n) (REG_PCM_PCTL(n) |= PCTL_LSMP) | ||
7289 | #define __pcm_zero_sample(n) (REG_PCM_PCTL(n) &= ~PCTL_LSMP) | ||
7290 | |||
7291 | #define __pcm_enable_transmit_dma(n) (REG_PCM_PCTL(n) |= PCTL_ETDMA) | ||
7292 | #define __pcm_disable_transmit_dma(n) (REG_PCM_PCTL(n) &= ~PCTL_ETDMA) | ||
7293 | #define __pcm_enable_receive_dma(n) (REG_PCM_PCTL(n) |= PCTL_ERDMA) | ||
7294 | #define __pcm_disable_receive_dma(n) (REG_PCM_PCTL(n) &= ~PCTL_ERDMA) | ||
7295 | |||
7296 | #define __pcm_as_master(n) (REG_PCM_PCFG(n) &= ~PCFG_MODE_SLAVE) | ||
7297 | #define __pcm_as_slave(n) (REG_PCM_PCFG(n) |= PCFG_MODE_SLAVE) | ||
7298 | |||
7299 | #define __pcm_set_transmit_trigger(n, val) \ | ||
7300 | do { \ | ||
7301 | REG_PCM_PCFG(n) &= ~PCFG_TFTH_MASK; \ | ||
7302 | REG_PCM_PCFG(n) |= ((val) << PCFG_TFTH_LSB); \ | ||
7303 | \ | ||
7304 | } while(0) | ||
7305 | |||
7306 | #define __pcm_set_receive_trigger(n, val) \ | ||
7307 | do { \ | ||
7308 | REG_PCM_PCFG(n) &= ~PCFG_RFTH_MASK; \ | ||
7309 | REG_PCM_PCFG(n) |= ((val) << PCFG_RFTH_LSB); \ | ||
7310 | \ | ||
7311 | } while(0) | ||
7312 | |||
7313 | #define __pcm_omsb_same_sync(n) (REG_PCM_PCFG(n) &= ~PCFG_OMSBPOS) | ||
7314 | #define __pcm_omsb_next_sync(n) (REG_PCM_PCFG(n) |= PCFG_OMSBPOS) | ||
7315 | |||
7316 | #define __pcm_imsb_same_sync(n) (REG_PCM_PCFG(n) &= ~PCFG_IMSBPOS) | ||
7317 | #define __pcm_imsb_next_sync(n) (REG_PCM_PCFG(n) |= PCFG_IMSBPOS) | ||
7318 | |||
7319 | #define __pcm_set_iss(n, val) \ | ||
7320 | do { \ | ||
7321 | if ((val) == 16) \ | ||
7322 | REG_PCM_PCFG(n) |= PCFG_ISS_16BIT; \ | ||
7323 | else \ | ||
7324 | REG_PCM_PCFG(n) &= ~PCFG_ISS_16BIT; \ | ||
7325 | \ | ||
7326 | } while (0) | ||
7327 | |||
7328 | #define __pcm_set_oss(n, val) \ | ||
7329 | do { \ | ||
7330 | if ((val) == 16) \ | ||
7331 | REG_PCM_PCFG(n) |= PCFG_OSS_16BIT; \ | ||
7332 | else \ | ||
7333 | REG_PCM_PCFG(n) &= ~PCFG_OSS_16BIT; \ | ||
7334 | \ | ||
7335 | } while (0) \ | ||
7336 | |||
7337 | #define __pcm_set_valid_slot(n, val) \ | ||
7338 | (REG_PCM_PCFG(n) = (REG_PCM_PCFG(n) & ~PCFG_SLOT_MASK) | PCFG_SLOT(val)) | ||
7339 | |||
7340 | #define __pcm_write_data(n, val) (REG_PCM_PDP(n) = (val)) | ||
7341 | #define __pcm_read_data(n) (REG_PCM_PDP(n)) | ||
7342 | |||
7343 | #define __pcm_enable_tfs_intr(n) (REG_PCM_PINTC(n) |= PINTC_ETFS) | ||
7344 | #define __pcm_disable_tfs_intr(n) (REG_PCM_PINTC(n) &= ~PINTC_ETFS) | ||
7345 | |||
7346 | #define __pcm_enable_tur_intr(n) (REG_PCM_PINTC(n) |= PINTC_ETUR) | ||
7347 | #define __pcm_disable_tur_intr(n) (REG_PCM_PINTC(n) &= ~PINTC_ETUR) | ||
7348 | |||
7349 | #define __pcm_enable_rfs_intr(n) (REG_PCM_PINTC(n) |= PINTC_ERFS) | ||
7350 | #define __pcm_disable_rfs_intr(n) (REG_PCM_PINTC(n) &= ~PINTC_ERFS) | ||
7351 | |||
7352 | #define __pcm_enable_ror_intr(n) (REG_PCM_PINTC(n) |= PINTC_EROR) | ||
7353 | #define __pcm_disable_ror_intr(n) (REG_PCM_PINTC(n) &= ~PINTC_EROR) | ||
7354 | |||
7355 | #define __pcm_ints_valid_tx(n) (((REG_PCM_PINTS(n) & PINTS_TFL_MASK) >> PINTS_TFL_LSB)) | ||
7356 | #define __pcm_ints_valid_rx(n) (((REG_PCM_PINTS(n) & PINTS_RFL_MASK) >> PINTS_RFL_LSB)) | ||
7357 | |||
7358 | #define __pcm_set_clk_div(n, val) \ | ||
7359 | (REG_PCM_PDIV(n) = (REG_PCM_PDIV(n) & ~PDIV_CLKDIV_MASK) | ((val) << PDIV_CLKDIV_LSB)) | ||
7360 | |||
7361 | #define __pcm_set_clk_rate(n, sysclk, pcmclk) \ | ||
7362 | __pcm_set_clk_div((n), ((sysclk) / (pcmclk) - 1)) | ||
7363 | |||
7364 | #define __pcm_set_sync_div(n, val) \ | ||
7365 | (REG_PCM_PDIV(n) = (REG_PCM_PDIV(n) & ~PDIV_SYNDIV_MASK) | ((val) << PDIV_SYNDIV_LSB)) | ||
7366 | |||
7367 | #define __pcm_set_sync_rate(n, pcmclk, sync) \ | ||
7368 | __pcm_set_sync_div((n), ((pcmclk) / (8 * (sync)) - 1)) | ||
7369 | |||
7370 | #define __pcm_set_sync_len(n, val) \ | ||
7371 | (REG_PCM_PDIV(n) = (REG_PCM_PDIV(n) & ~PDIV_SYNL_MASK) | ((val) << PDIV_SYNL_LSB)) | ||
7372 | |||
7373 | #endif /* __MIPS_ASSEMBLER */ | ||
7374 | |||
7375 | /* | ||
7376 | * Real time clock module(RTC) address definition | ||
7377 | */ | ||
7378 | #define RTC_BASE 0xb0003000 | ||
7379 | |||
7380 | /* | ||
7381 | * RTC registers offset address definition | ||
7382 | */ | ||
7383 | #define RTC_RTCCR_OFFSET (0x00) /* rw, 32, 0x00000081 */ | ||
7384 | #define RTC_RTCSR_OFFSET (0x04) /* rw, 32, 0x???????? */ | ||
7385 | #define RTC_RTCSAR_OFFSET (0x08) /* rw, 32, 0x???????? */ | ||
7386 | #define RTC_RTCGR_OFFSET (0x0c) /* rw, 32, 0x0??????? */ | ||
7387 | |||
7388 | #define RTC_HCR_OFFSET (0x20) /* rw, 32, 0x00000000 */ | ||
7389 | #define RTC_HWFCR_OFFSET (0x24) /* rw, 32, 0x0000???0 */ | ||
7390 | #define RTC_HRCR_OFFSET (0x28) /* rw, 32, 0x00000??0 */ | ||
7391 | #define RTC_HWCR_OFFSET (0x2c) /* rw, 32, 0x00000008 */ | ||
7392 | #define RTC_HWRSR_OFFSET (0x30) /* rw, 32, 0x00000000 */ | ||
7393 | #define RTC_HSPR_OFFSET (0x34) /* rw, 32, 0x???????? */ | ||
7394 | #define RTC_WENR_OFFSET (0x3c) /* rw, 32, 0x00000000 */ | ||
7395 | |||
7396 | /* | ||
7397 | * RTC registers address definition | ||
7398 | */ | ||
7399 | #define RTC_RTCCR (RTC_BASE + RTC_RTCCR_OFFSET) | ||
7400 | #define RTC_RTCSR (RTC_BASE + RTC_RTCSR_OFFSET) | ||
7401 | #define RTC_RTCSAR (RTC_BASE + RTC_RTCSAR_OFFSET) | ||
7402 | #define RTC_RTCGR (RTC_BASE + RTC_RTCGR_OFFSET) | ||
7403 | |||
7404 | #define RTC_HCR (RTC_BASE + RTC_HCR_OFFSET) | ||
7405 | #define RTC_HWFCR (RTC_BASE + RTC_HWFCR_OFFSET) | ||
7406 | #define RTC_HRCR (RTC_BASE + RTC_HRCR_OFFSET) | ||
7407 | #define RTC_HWCR (RTC_BASE + RTC_HWCR_OFFSET) | ||
7408 | #define RTC_HWRSR (RTC_BASE + RTC_HWRSR_OFFSET) | ||
7409 | #define RTC_HSPR (RTC_BASE + RTC_HSPR_OFFSET) | ||
7410 | #define RTC_WENR (RTC_BASE + RTC_WENR_OFFSET) | ||
7411 | |||
7412 | /* | ||
7413 | * RTC registers common define | ||
7414 | */ | ||
7415 | |||
7416 | /* RTC control register(RTCCR) */ | ||
7417 | #define RTCCR_WRDY BIT7 | ||
7418 | #define RTCCR_1HZ BIT6 | ||
7419 | #define RTCCR_1HZIE BIT5 | ||
7420 | #define RTCCR_AF BIT4 | ||
7421 | #define RTCCR_AIE BIT3 | ||
7422 | #define RTCCR_AE BIT2 | ||
7423 | #define RTCCR_SELEXC BIT1 | ||
7424 | #define RTCCR_RTCE BIT0 | ||
7425 | |||
7426 | /* RTC regulator register(RTCGR) */ | ||
7427 | #define RTCGR_LOCK BIT31 | ||
7428 | |||
7429 | #define RTCGR_ADJC_LSB 16 | ||
7430 | #define RTCGR_ADJC_MASK BITS_H2L(25, RTCGR_ADJC_LSB) | ||
7431 | |||
7432 | #define RTCGR_NC1HZ_LSB 0 | ||
7433 | #define RTCGR_NC1HZ_MASK BITS_H2L(15, RTCGR_NC1HZ_LSB) | ||
7434 | |||
7435 | /* Hibernate control register(HCR) */ | ||
7436 | #define HCR_PD BIT0 | ||
7437 | |||
7438 | /* Hibernate wakeup filter counter register(HWFCR) */ | ||
7439 | #define HWFCR_LSB 5 | ||
7440 | #define HWFCR_MASK BITS_H2L(15, HWFCR_LSB) | ||
7441 | #define HWFCR_WAIT_TIME(ms) (((ms) << HWFCR_LSB) > HWFCR_MASK ? HWFCR_MASK : ((ms) << HWFCR_LSB)) | ||
7442 | |||
7443 | /* Hibernate reset counter register(HRCR) */ | ||
7444 | #define HRCR_LSB 5 | ||
7445 | #define HRCR_MASK BITS_H2L(11, HRCR_LSB) | ||
7446 | #define HRCR_WAIT_TIME(ms) (((ms) << HRCR_LSB) > HRCR_MASK ? HRCR_MASK : ((ms) << HRCR_LSB)) | ||
7447 | |||
7448 | /* Hibernate wakeup control register(HWCR) */ | ||
7449 | #define HWCR_EPDET BIT3 | ||
7450 | #define HWCR_WKUPVL BIT2 | ||
7451 | #define HWCR_EALM BIT0 | ||
7452 | |||
7453 | /* Hibernate wakeup status register(HWRSR) */ | ||
7454 | #define HWRSR_APD BIT8 | ||
7455 | #define HWRSR_HR BIT5 | ||
7456 | #define HWRSR_PPR BIT4 | ||
7457 | #define HWRSR_PIN BIT1 | ||
7458 | #define HWRSR_ALM BIT0 | ||
7459 | |||
7460 | /* write enable pattern register(WENR) */ | ||
7461 | #define WENR_WEN BIT31 | ||
7462 | |||
7463 | #define WENR_WENPAT_LSB 0 | ||
7464 | #define WENR_WENPAT_MASK BITS_H2L(15, WENR_WENPAT_LSB) | ||
7465 | #define WENR_WENPAT_WRITABLE (0xa55a) | ||
7466 | |||
7467 | /* Hibernate scratch pattern register(HSPR) */ | ||
7468 | #define HSPR_RTCV 0x52544356 /* The value is 'RTCV', means rtc is valid */ | ||
7469 | |||
7470 | #ifndef __MIPS_ASSEMBLER | ||
7471 | |||
7472 | /* Waiting for the RTC register writing finish */ | ||
7473 | #define __wait_write_ready() \ | ||
7474 | do { \ | ||
7475 | int timeout = 0x1000; \ | ||
7476 | while (!(rtc_read_reg(RTC_RTCCR) & RTCCR_WRDY) && timeout--); \ | ||
7477 | }while(0); | ||
7478 | |||
7479 | /* Waiting for the RTC register writable */ | ||
7480 | #define __wait_writable() \ | ||
7481 | do { \ | ||
7482 | int timeout = 0x1000; \ | ||
7483 | __wait_write_ready(); \ | ||
7484 | OUTREG32(RTC_WENR, WENR_WENPAT_WRITABLE); \ | ||
7485 | __wait_write_ready(); \ | ||
7486 | while (!(rtc_read_reg(RTC_WENR) & WENR_WEN) && timeout--); \ | ||
7487 | }while(0); | ||
7488 | |||
7489 | /* Basic RTC ops */ | ||
7490 | #define rtc_read_reg(reg) \ | ||
7491 | ({ \ | ||
7492 | unsigned int data, timeout = 0x10000; \ | ||
7493 | do { \ | ||
7494 | data = INREG32(reg); \ | ||
7495 | } while (INREG32(reg) != data && timeout--); \ | ||
7496 | data; \ | ||
7497 | }) | ||
7498 | |||
7499 | #define rtc_write_reg(reg, data) \ | ||
7500 | do { \ | ||
7501 | __wait_writable(); \ | ||
7502 | OUTREG32(reg, data); \ | ||
7503 | __wait_write_ready(); \ | ||
7504 | }while(0); | ||
7505 | |||
7506 | #define rtc_set_reg(reg, data) rtc_write_reg(reg, rtc_read_reg(reg) | (data)) | ||
7507 | #define rtc_clr_reg(reg, data) rtc_write_reg(reg, rtc_read_reg(reg) & ~(data)) | ||
7508 | |||
7509 | #endif /* __MIPS_ASSEMBLER */ | ||
7510 | |||
7511 | /* | ||
7512 | * SAR A/D Controller(SADC) address definition | ||
7513 | */ | ||
7514 | #define SADC_BASE 0xb0070000 | ||
7515 | |||
7516 | /* | ||
7517 | * SADC registers offset definition | ||
7518 | */ | ||
7519 | #define SADC_ADENA_OFFSET (0x00) /* rw, 8, 0x00 */ | ||
7520 | #define SADC_ADCFG_OFFSET (0x04) /* rw, 32, 0x0002000c */ | ||
7521 | #define SADC_ADCTRL_OFFSET (0x08) /* rw, 8, 0x3f */ | ||
7522 | #define SADC_ADSTATE_OFFSET (0x0c) /* rw, 8, 0x00 */ | ||
7523 | #define SADC_ADSAME_OFFSET (0x10) /* rw, 16, 0x0000 */ | ||
7524 | #define SADC_ADWAIT_OFFSET (0x14) /* rw, 16, 0x0000 */ | ||
7525 | #define SADC_ADTCH_OFFSET (0x18) /* rw, 32, 0x00000000 */ | ||
7526 | #define SADC_ADVDAT_OFFSET (0x1c) /* rw, 16, 0x0000 */ | ||
7527 | #define SADC_ADADAT_OFFSET (0x20) /* rw, 16, 0x0000 */ | ||
7528 | #define SADC_ADFLT_OFFSET (0x24) /* rw, 16, 0x0000 */ | ||
7529 | #define SADC_ADCLK_OFFSET (0x28) /* rw, 32, 0x00000000 */ | ||
7530 | |||
7531 | /* | ||
7532 | * SADC registers address definition | ||
7533 | */ | ||
7534 | #define SADC_ADENA (SADC_BASE + SADC_ADENA_OFFSET) /* ADC Enable Register */ | ||
7535 | #define SADC_ADCFG (SADC_BASE + SADC_ADCFG_OFFSET) /* ADC Configure Register */ | ||
7536 | #define SADC_ADCTRL (SADC_BASE + SADC_ADCTRL_OFFSET) /* ADC Control Register */ | ||
7537 | #define SADC_ADSTATE (SADC_BASE + SADC_ADSTATE_OFFSET)/* ADC Status Register*/ | ||
7538 | #define SADC_ADSAME (SADC_BASE + SADC_ADSAME_OFFSET) /* ADC Same Point Time Register */ | ||
7539 | #define SADC_ADWAIT (SADC_BASE + SADC_ADWAIT_OFFSET) /* ADC Wait Time Register */ | ||
7540 | #define SADC_ADTCH (SADC_BASE + SADC_ADTCH_OFFSET) /* ADC Touch Screen Data Register */ | ||
7541 | #define SADC_ADVDAT (SADC_BASE + SADC_ADVDAT_OFFSET) /* ADC VBAT Data Register */ | ||
7542 | #define SADC_ADADAT (SADC_BASE + SADC_ADADAT_OFFSET) /* ADC AUX Data Register */ | ||
7543 | #define SADC_ADFLT (SADC_BASE + SADC_ADFLT_OFFSET) /* ADC Filter Register */ | ||
7544 | #define SADC_ADCLK (SADC_BASE + SADC_ADCLK_OFFSET) /* ADC Clock Divide Register */ | ||
7545 | |||
7546 | /* | ||
7547 | * SADC registers common define | ||
7548 | */ | ||
7549 | |||
7550 | /* ADC Enable Register (ADENA) */ | ||
7551 | #define ADENA_POWER BIT7 | ||
7552 | #define ADENA_SLP_MD BIT6 | ||
7553 | #define ADENA_PENDEN BIT3 | ||
7554 | #define ADENA_TCHEN BIT2 | ||
7555 | #define ADENA_VBATEN BIT1 | ||
7556 | #define ADENA_AUXEN BIT0 | ||
7557 | |||
7558 | /* ADC Configure Register (ADCFG) */ | ||
7559 | #define ADCFG_SPZZ BIT31 | ||
7560 | #define ADCFG_VBAT_SEL BIT30 | ||
7561 | #define ADCFG_DMA_EN BIT15 | ||
7562 | |||
7563 | #define ADCFG_XYZ_LSB 13 | ||
7564 | #define ADCFG_XYZ_MASK BITS_H2L(14, ADCFG_XYZ_LSB) | ||
7565 | #define ADCFG_XYZ_XYS (0x0 << ADCFG_XYZ_LSB) | ||
7566 | #define ADCFG_XYZ_XYD (0x1 << ADCFG_XYZ_LSB) | ||
7567 | #define ADCFG_XYZ_XYZ1Z2 (0x2 << ADCFG_XYZ_LSB) | ||
7568 | |||
7569 | #define ADCFG_SNUM_LSB 10 | ||
7570 | #define ADCFG_SNUM_MASK BITS_H2L(12, ADCFG_SNUM_LSB) | ||
7571 | #define ADCFG_SNUM(n) (((n) <= 6 ? ((n)-1) : ((n)-2)) << ADCFG_SNUM_LSB) | ||
7572 | |||
7573 | #define ADCFG_CMD_LSB 0 | ||
7574 | #define ADCFG_CMD_MASK BITS_H2L(1, ADCFG_CMD_LSB) | ||
7575 | #define ADCFG_CMD_AUX(n) ((n) << ADCFG_CMD_LSB) | ||
7576 | |||
7577 | /* ADC Control Register (ADCCTRL) */ | ||
7578 | #define ADCTRL_SLPENDM BIT5 | ||
7579 | #define ADCTRL_PENDM BIT4 | ||
7580 | #define ADCTRL_PENUM BIT3 | ||
7581 | #define ADCTRL_DTCHM BIT2 | ||
7582 | #define ADCTRL_VRDYM BIT1 | ||
7583 | #define ADCTRL_ARDYM BIT0 | ||
7584 | #define ADCTRL_MASK_ALL (ADCTRL_SLPENDM | ADCTRL_PENDM | ADCTRL_PENUM \ | ||
7585 | | ADCTRL_DTCHM | ADCTRL_VRDYM | ADCTRL_ARDYM) | ||
7586 | |||
7587 | /* ADC Status Register (ADSTATE) */ | ||
7588 | #define ADSTATE_SLP_RDY BIT7 | ||
7589 | #define ADSTATE_SLPEND BIT5 | ||
7590 | #define ADSTATE_PEND BIT4 | ||
7591 | #define ADSTATE_PENU BIT3 | ||
7592 | #define ADSTATE_DTCH BIT2 | ||
7593 | #define ADSTATE_VRDY BIT1 | ||
7594 | #define ADSTATE_ARDY BIT0 | ||
7595 | |||
7596 | /* ADC Same Point Time Register (ADSAME) */ | ||
7597 | #define ADSAME_SCNT_LSB 0 | ||
7598 | #define ADSAME_SCNT_MASK BITS_H2L(15, ADSAME_SCNT_LSB) | ||
7599 | |||
7600 | /* ADC Wait Pen Down Time Register (ADWAIT) */ | ||
7601 | #define ADWAIT_WCNT_LSB 0 | ||
7602 | #define ADWAIT_WCNT_MASK BITS_H2L(15, ADWAIT_WCNT_LSB) | ||
7603 | |||
7604 | /* ADC Touch Screen Data Register (ADTCH) */ | ||
7605 | #define ADTCH_TYPE1 BIT31 | ||
7606 | #define ADTCH_TYPE0 BIT15 | ||
7607 | |||
7608 | #define ADTCH_DATA1_LSB 16 | ||
7609 | #define ADTCH_DATA1_MASK BITS_H2L(27, ADTCH_DATA1_LSB) | ||
7610 | |||
7611 | #define ADTCH_DATA0_LSB 0 | ||
7612 | #define ADTCH_DATA0_MASK BITS_H2L(11, ADTCH_DATA0_LSB) | ||
7613 | |||
7614 | /* ADC VBAT Date Register (ADVDAT) */ | ||
7615 | #define ADVDAT_VDATA_LSB 0 | ||
7616 | #define ADVDAT_VDATA_MASK BITS_H2L(11, ADVDAT_VDATA_LSB) | ||
7617 | |||
7618 | /* ADC AUX Data Register (ADADAT) */ | ||
7619 | #define ADADAT_ADATA_LSB 0 | ||
7620 | #define ADADAT_ADATA_MASK BITS_H2L(11, ADADAT_ADATA_LSB) | ||
7621 | |||
7622 | /* ADC Clock Divide Register (ADCLK) */ | ||
7623 | #define ADCLK_CLKDIV_MS_LSB 16 | ||
7624 | #define ADCLK_CLKDIV_MS_MASK BITS_H2L(31, ADCLK_CLKDIV_MS_LSB) | ||
7625 | |||
7626 | #define ADCLK_CLKDIV_US_LSB 8 | ||
7627 | #define ADCLK_CLKDIV_US_MASK BITS_H2L(15, ADCLK_CLKDIV_US_LSB) | ||
7628 | |||
7629 | #define ADCLK_CLKDIV_LSB 0 | ||
7630 | #define ADCLK_CLKDIV_MASK BITS_H2L(7, ADCLK_CLKDIV_LSB) | ||
7631 | |||
7632 | /* ADC Filter Register (ADFLT) */ | ||
7633 | #define ADFLT_FLT_EN BIT15 | ||
7634 | |||
7635 | #define ADFLT_FLT_D_LSB 0 | ||
7636 | #define ADFLT_FLT_D_MASK BITS_H2L(11, ADFLT_FLT_D_LSB) | ||
7637 | |||
7638 | #ifndef __MIPS_ASSEMBLER | ||
7639 | |||
7640 | #define REG_SADC_ADENA REG8(SADC_ADENA) | ||
7641 | #define REG_SADC_ADCFG REG32(SADC_ADCFG) | ||
7642 | #define REG_SADC_ADCTRL REG8(SADC_ADCTRL) | ||
7643 | #define REG_SADC_ADSTATE REG8(SADC_ADSTATE) | ||
7644 | #define REG_SADC_ADSAME REG16(SADC_ADSAME) | ||
7645 | #define REG_SADC_ADWAIT REG16(SADC_ADWAIT) | ||
7646 | #define REG_SADC_ADTCH REG32(SADC_ADTCH) | ||
7647 | #define REG_SADC_ADVDAT REG16(SADC_ADVDAT) | ||
7648 | #define REG_SADC_ADADAT REG16(SADC_ADADAT) | ||
7649 | #define REG_SADC_ADFLT REG16(SADC_ADFLT) | ||
7650 | #define REG_SADC_ADCLK REG32(SADC_ADCLK) | ||
7651 | |||
7652 | #endif /* __MIPS_ASSEMBLER */ | ||
7653 | |||
7654 | #define SCC_BASE 0xB0040000 | ||
7655 | |||
7656 | /************************************************************************* | ||
7657 | * SCC | ||
7658 | *************************************************************************/ | ||
7659 | #define SCC_DR (SCC_BASE + 0x000) | ||
7660 | #define SCC_FDR (SCC_BASE + 0x004) | ||
7661 | #define SCC_CR (SCC_BASE + 0x008) | ||
7662 | #define SCC_SR (SCC_BASE + 0x00C) | ||
7663 | #define SCC_TFR (SCC_BASE + 0x010) | ||
7664 | #define SCC_EGTR (SCC_BASE + 0x014) | ||
7665 | #define SCC_ECR (SCC_BASE + 0x018) | ||
7666 | #define SCC_RTOR (SCC_BASE + 0x01C) | ||
7667 | |||
7668 | #define REG_SCC_DR REG8(SCC_DR) | ||
7669 | #define REG_SCC_FDR REG8(SCC_FDR) | ||
7670 | #define REG_SCC_CR REG32(SCC_CR) | ||
7671 | #define REG_SCC_SR REG16(SCC_SR) | ||
7672 | #define REG_SCC_TFR REG16(SCC_TFR) | ||
7673 | #define REG_SCC_EGTR REG8(SCC_EGTR) | ||
7674 | #define REG_SCC_ECR REG32(SCC_ECR) | ||
7675 | #define REG_SCC_RTOR REG8(SCC_RTOR) | ||
7676 | |||
7677 | /* SCC FIFO Data Count Register (SCC_FDR) */ | ||
7678 | |||
7679 | #define SCC_FDR_EMPTY 0x00 | ||
7680 | #define SCC_FDR_FULL 0x10 | ||
7681 | |||
7682 | /* SCC Control Register (SCC_CR) */ | ||
7683 | |||
7684 | #define SCC_CR_SCCE (1 << 31) | ||
7685 | #define SCC_CR_TRS (1 << 30) | ||
7686 | #define SCC_CR_T2R (1 << 29) | ||
7687 | #define SCC_CR_FDIV_BIT 24 | ||
7688 | #define SCC_CR_FDIV_MASK (0x3 << SCC_CR_FDIV_BIT) | ||
7689 | #define SCC_CR_FDIV_1 (0 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is the same as device clock */ | ||
7690 | #define SCC_CR_FDIV_2 (1 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is half of device clock */ | ||
7691 | #define SCC_CR_FLUSH (1 << 23) | ||
7692 | #define SCC_CR_TRIG_BIT 16 | ||
7693 | #define SCC_CR_TRIG_MASK (0x3 << SCC_CR_TRIG_BIT) | ||
7694 | #define SCC_CR_TRIG_1 (0 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 1 */ | ||
7695 | #define SCC_CR_TRIG_4 (1 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 4 */ | ||
7696 | #define SCC_CR_TRIG_8 (2 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 8 */ | ||
7697 | #define SCC_CR_TRIG_14 (3 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 14 */ | ||
7698 | #define SCC_CR_TP (1 << 15) | ||
7699 | #define SCC_CR_CONV (1 << 14) | ||
7700 | #define SCC_CR_TXIE (1 << 13) | ||
7701 | #define SCC_CR_RXIE (1 << 12) | ||
7702 | #define SCC_CR_TENDIE (1 << 11) | ||
7703 | #define SCC_CR_RTOIE (1 << 10) | ||
7704 | #define SCC_CR_ECIE (1 << 9) | ||
7705 | #define SCC_CR_EPIE (1 << 8) | ||
7706 | #define SCC_CR_RETIE (1 << 7) | ||
7707 | #define SCC_CR_EOIE (1 << 6) | ||
7708 | #define SCC_CR_TSEND (1 << 3) | ||
7709 | #define SCC_CR_PX_BIT 1 | ||
7710 | #define SCC_CR_PX_MASK (0x3 << SCC_CR_PX_BIT) | ||
7711 | #define SCC_CR_PX_NOT_SUPPORT (0 << SCC_CR_PX_BIT) /* SCC does not support clock stop */ | ||
7712 | #define SCC_CR_PX_STOP_LOW (1 << SCC_CR_PX_BIT) /* SCC_CLK stops at state low */ | ||
7713 | #define SCC_CR_PX_STOP_HIGH (2 << SCC_CR_PX_BIT) /* SCC_CLK stops at state high */ | ||
7714 | #define SCC_CR_CLKSTP (1 << 0) | ||
7715 | |||
7716 | /* SCC Status Register (SCC_SR) */ | ||
7717 | |||
7718 | #define SCC_SR_TRANS (1 << 15) | ||
7719 | #define SCC_SR_ORER (1 << 12) | ||
7720 | #define SCC_SR_RTO (1 << 11) | ||
7721 | #define SCC_SR_PER (1 << 10) | ||
7722 | #define SCC_SR_TFTG (1 << 9) | ||
7723 | #define SCC_SR_RFTG (1 << 8) | ||
7724 | #define SCC_SR_TEND (1 << 7) | ||
7725 | #define SCC_SR_RETR_3 (1 << 4) | ||
7726 | #define SCC_SR_ECNTO (1 << 0) | ||
7727 | |||
7728 | #ifndef __MIPS_ASSEMBLER | ||
7729 | |||
7730 | /*************************************************************************** | ||
7731 | * SCC | ||
7732 | ***************************************************************************/ | ||
7733 | |||
7734 | #define __scc_enable() ( REG_SCC_CR |= SCC_CR_SCCE ) | ||
7735 | #define __scc_disable() ( REG_SCC_CR &= ~SCC_CR_SCCE ) | ||
7736 | |||
7737 | #define __scc_set_tx_mode() ( REG_SCC_CR |= SCC_CR_TRS ) | ||
7738 | #define __scc_set_rx_mode() ( REG_SCC_CR &= ~SCC_CR_TRS ) | ||
7739 | |||
7740 | #define __scc_enable_t2r() ( REG_SCC_CR |= SCC_CR_T2R ) | ||
7741 | #define __scc_disable_t2r() ( REG_SCC_CR &= ~SCC_CR_T2R ) | ||
7742 | |||
7743 | #define __scc_clk_as_devclk() \ | ||
7744 | do { \ | ||
7745 | REG_SCC_CR &= ~SCC_CR_FDIV_MASK; \ | ||
7746 | REG_SCC_CR |= SCC_CR_FDIV_1; \ | ||
7747 | } while (0) | ||
7748 | |||
7749 | #define __scc_clk_as_half_devclk() \ | ||
7750 | do { \ | ||
7751 | REG_SCC_CR &= ~SCC_CR_FDIV_MASK; \ | ||
7752 | REG_SCC_CR |= SCC_CR_FDIV_2; \ | ||
7753 | } while (0) | ||
7754 | |||
7755 | /* n=1,4,8,14 */ | ||
7756 | #define __scc_set_fifo_trigger(n) \ | ||
7757 | do { \ | ||
7758 | REG_SCC_CR &= ~SCC_CR_TRIG_MASK; \ | ||
7759 | REG_SCC_CR |= SCC_CR_TRIG_##n; \ | ||
7760 | } while (0) | ||
7761 | |||
7762 | #define __scc_set_protocol(p) \ | ||
7763 | do { \ | ||
7764 | if (p) \ | ||
7765 | REG_SCC_CR |= SCC_CR_TP; \ | ||
7766 | else \ | ||
7767 | REG_SCC_CR &= ~SCC_CR_TP; \ | ||
7768 | } while (0) | ||
7769 | |||
7770 | #define __scc_flush_fifo() ( REG_SCC_CR |= SCC_CR_FLUSH ) | ||
7771 | |||
7772 | #define __scc_set_invert_mode() ( REG_SCC_CR |= SCC_CR_CONV ) | ||
7773 | #define __scc_set_direct_mode() ( REG_SCC_CR &= ~SCC_CR_CONV ) | ||
7774 | |||
7775 | #define SCC_ERR_INTRS \ | ||
7776 | ( SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE ) | ||
7777 | #define SCC_ALL_INTRS \ | ||
7778 | ( SCC_CR_TXIE | SCC_CR_RXIE | SCC_CR_TENDIE | SCC_CR_RTOIE | \ | ||
7779 | SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE ) | ||
7780 | |||
7781 | #define __scc_enable_err_intrs() ( REG_SCC_CR |= SCC_ERR_INTRS ) | ||
7782 | #define __scc_disable_err_intrs() ( REG_SCC_CR &= ~SCC_ERR_INTRS ) | ||
7783 | |||
7784 | #define SCC_ALL_ERRORS \ | ||
7785 | ( SCC_SR_ORER | SCC_SR_RTO | SCC_SR_PER | SCC_SR_RETR_3 | SCC_SR_ECNTO) | ||
7786 | |||
7787 | #define __scc_clear_errors() ( REG_SCC_SR &= ~SCC_ALL_ERRORS ) | ||
7788 | |||
7789 | #define __scc_enable_all_intrs() ( REG_SCC_CR |= SCC_ALL_INTRS ) | ||
7790 | #define __scc_disable_all_intrs() ( REG_SCC_CR &= ~SCC_ALL_INTRS ) | ||
7791 | |||
7792 | #define __scc_enable_tx_intr() ( REG_SCC_CR |= SCC_CR_TXIE | SCC_CR_TENDIE ) | ||
7793 | #define __scc_disable_tx_intr() ( REG_SCC_CR &= ~(SCC_CR_TXIE | SCC_CR_TENDIE) ) | ||
7794 | |||
7795 | #define __scc_enable_rx_intr() ( REG_SCC_CR |= SCC_CR_RXIE) | ||
7796 | #define __scc_disable_rx_intr() ( REG_SCC_CR &= ~SCC_CR_RXIE) | ||
7797 | |||
7798 | #define __scc_set_tsend() ( REG_SCC_CR |= SCC_CR_TSEND ) | ||
7799 | #define __scc_clear_tsend() ( REG_SCC_CR &= ~SCC_CR_TSEND ) | ||
7800 | |||
7801 | #define __scc_set_clockstop() ( REG_SCC_CR |= SCC_CR_CLKSTP ) | ||
7802 | #define __scc_clear_clockstop() ( REG_SCC_CR &= ~SCC_CR_CLKSTP ) | ||
7803 | |||
7804 | #define __scc_clockstop_low() \ | ||
7805 | do { \ | ||
7806 | REG_SCC_CR &= ~SCC_CR_PX_MASK; \ | ||
7807 | REG_SCC_CR |= SCC_CR_PX_STOP_LOW; \ | ||
7808 | } while (0) | ||
7809 | |||
7810 | #define __scc_clockstop_high() \ | ||
7811 | do { \ | ||
7812 | REG_SCC_CR &= ~SCC_CR_PX_MASK; \ | ||
7813 | REG_SCC_CR |= SCC_CR_PX_STOP_HIGH; \ | ||
7814 | } while (0) | ||
7815 | |||
7816 | /* SCC status checking */ | ||
7817 | #define __scc_check_transfer_status() ( REG_SCC_SR & SCC_SR_TRANS ) | ||
7818 | #define __scc_check_rx_overrun_error() ( REG_SCC_SR & SCC_SR_ORER ) | ||
7819 | #define __scc_check_rx_timeout() ( REG_SCC_SR & SCC_SR_RTO ) | ||
7820 | #define __scc_check_parity_error() ( REG_SCC_SR & SCC_SR_PER ) | ||
7821 | #define __scc_check_txfifo_trigger() ( REG_SCC_SR & SCC_SR_TFTG ) | ||
7822 | #define __scc_check_rxfifo_trigger() ( REG_SCC_SR & SCC_SR_RFTG ) | ||
7823 | #define __scc_check_tx_end() ( REG_SCC_SR & SCC_SR_TEND ) | ||
7824 | #define __scc_check_retx_3() ( REG_SCC_SR & SCC_SR_RETR_3 ) | ||
7825 | #define __scc_check_ecnt_overflow() ( REG_SCC_SR & SCC_SR_ECNTO ) | ||
7826 | |||
7827 | #endif /* __MIPS_ASSEMBLER */ | ||
7828 | |||
7829 | #define SSI0_BASE 0xB0043000 | ||
7830 | #define SSI1_BASE 0xB0044000 | ||
7831 | #define SSI2_BASE 0xB0045000 | ||
7832 | |||
7833 | /************************************************************************* | ||
7834 | * SSI (Synchronous Serial Interface) | ||
7835 | *************************************************************************/ | ||
7836 | /* n = 0, 1 (SSI0, SSI1) */ | ||
7837 | #define SSI_DR(n) (SSI0_BASE + 0x000 + (n)*0x1000) | ||
7838 | #define SSI_CR0(n) (SSI0_BASE + 0x004 + (n)*0x1000) | ||
7839 | #define SSI_CR1(n) (SSI0_BASE + 0x008 + (n)*0x1000) | ||
7840 | #define SSI_SR(n) (SSI0_BASE + 0x00C + (n)*0x1000) | ||
7841 | #define SSI_ITR(n) (SSI0_BASE + 0x010 + (n)*0x1000) | ||
7842 | #define SSI_ICR(n) (SSI0_BASE + 0x014 + (n)*0x1000) | ||
7843 | #define SSI_GR(n) (SSI0_BASE + 0x018 + (n)*0x1000) | ||
7844 | |||
7845 | #define REG_SSI_DR(n) REG32(SSI_DR(n)) | ||
7846 | #define REG_SSI_CR0(n) REG16(SSI_CR0(n)) | ||
7847 | #define REG_SSI_CR1(n) REG32(SSI_CR1(n)) | ||
7848 | #define REG_SSI_SR(n) REG32(SSI_SR(n)) | ||
7849 | #define REG_SSI_ITR(n) REG16(SSI_ITR(n)) | ||
7850 | #define REG_SSI_ICR(n) REG8(SSI_ICR(n)) | ||
7851 | #define REG_SSI_GR(n) REG16(SSI_GR(n)) | ||
7852 | |||
7853 | /* SSI Data Register (SSI_DR) */ | ||
7854 | |||
7855 | #define SSI_DR_GPC_BIT 0 | ||
7856 | #define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT) | ||
7857 | |||
7858 | #define SSI_MAX_FIFO_ENTRIES 128 /* 128 txfifo and 128 rxfifo */ | ||
7859 | |||
7860 | /* SSI Control Register 0 (SSI_CR0) */ | ||
7861 | |||
7862 | #define SSI_CR0_SSIE (1 << 15) | ||
7863 | #define SSI_CR0_TIE (1 << 14) | ||
7864 | #define SSI_CR0_RIE (1 << 13) | ||
7865 | #define SSI_CR0_TEIE (1 << 12) | ||
7866 | #define SSI_CR0_REIE (1 << 11) | ||
7867 | #define SSI_CR0_LOOP (1 << 10) | ||
7868 | #define SSI_CR0_RFINE (1 << 9) | ||
7869 | #define SSI_CR0_RFINC (1 << 8) | ||
7870 | #define SSI_CR0_EACLRUN (1 << 7) /* hardware auto clear underrun when TxFifo no empty */ | ||
7871 | #define SSI_CR0_FSEL (1 << 6) | ||
7872 | #define SSI_CR0_TFLUSH (1 << 2) | ||
7873 | #define SSI_CR0_RFLUSH (1 << 1) | ||
7874 | #define SSI_CR0_DISREV (1 << 0) | ||
7875 | |||
7876 | /* SSI Control Register 1 (SSI_CR1) */ | ||
7877 | |||
7878 | #define SSI_CR1_FRMHL_BIT 30 | ||
7879 | #define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT) | ||
7880 | #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */ | ||
7881 | #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */ | ||
7882 | #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */ | ||
7883 | #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */ | ||
7884 | #define SSI_CR1_TFVCK_BIT 28 | ||
7885 | #define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT) | ||
7886 | #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT) | ||
7887 | #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT) | ||
7888 | #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT) | ||
7889 | #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT) | ||
7890 | #define SSI_CR1_TCKFI_BIT 26 | ||
7891 | #define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT) | ||
7892 | #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT) | ||
7893 | #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT) | ||
7894 | #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT) | ||
7895 | #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT) | ||
7896 | #define SSI_CR1_LFST (1 << 25) | ||
7897 | #define SSI_CR1_ITFRM (1 << 24) | ||
7898 | #define SSI_CR1_UNFIN (1 << 23) | ||
7899 | #define SSI_CR1_MULTS (1 << 22) | ||
7900 | #define SSI_CR1_FMAT_BIT 20 | ||
7901 | #define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) | ||
7902 | #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */ | ||
7903 | #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ | ||
7904 | #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ | ||
7905 | #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ | ||
7906 | #define SSI_CR1_TTRG_BIT 16 /* SSI1 TX trigger */ | ||
7907 | #define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT) | ||
7908 | #define SSI_CR1_MCOM_BIT 12 | ||
7909 | #define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT) | ||
7910 | #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */ | ||
7911 | #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */ | ||
7912 | #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */ | ||
7913 | #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */ | ||
7914 | #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */ | ||
7915 | #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */ | ||
7916 | #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */ | ||
7917 | #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */ | ||
7918 | #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */ | ||
7919 | #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */ | ||
7920 | #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */ | ||
7921 | #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */ | ||
7922 | #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */ | ||
7923 | #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */ | ||
7924 | #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */ | ||
7925 | #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */ | ||
7926 | #define SSI_CR1_RTRG_BIT 8 /* SSI RX trigger */ | ||
7927 | #define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT) | ||
7928 | #define SSI_CR1_FLEN_BIT 4 | ||
7929 | #define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT) | ||
7930 | #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT) | ||
7931 | #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT) | ||
7932 | #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT) | ||
7933 | #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT) | ||
7934 | #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT) | ||
7935 | #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT) | ||
7936 | #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT) | ||
7937 | #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT) | ||
7938 | #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT) | ||
7939 | #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT) | ||
7940 | #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT) | ||
7941 | #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT) | ||
7942 | #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT) | ||
7943 | #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT) | ||
7944 | #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT) | ||
7945 | #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT) | ||
7946 | #define SSI_CR1_PHA (1 << 1) | ||
7947 | #define SSI_CR1_POL (1 << 0) | ||
7948 | |||
7949 | /* SSI Status Register (SSI_SR) */ | ||
7950 | |||
7951 | #define SSI_SR_TFIFONUM_BIT 16 | ||
7952 | #define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT) | ||
7953 | #define SSI_SR_RFIFONUM_BIT 8 | ||
7954 | #define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT) | ||
7955 | #define SSI_SR_END (1 << 7) | ||
7956 | #define SSI_SR_BUSY (1 << 6) | ||
7957 | #define SSI_SR_TFF (1 << 5) | ||
7958 | #define SSI_SR_RFE (1 << 4) | ||
7959 | #define SSI_SR_TFHE (1 << 3) | ||
7960 | #define SSI_SR_RFHF (1 << 2) | ||
7961 | #define SSI_SR_UNDR (1 << 1) | ||
7962 | #define SSI_SR_OVER (1 << 0) | ||
7963 | |||
7964 | /* SSI Interval Time Control Register (SSI_ITR) */ | ||
7965 | |||
7966 | #define SSI_ITR_CNTCLK (1 << 15) | ||
7967 | #define SSI_ITR_IVLTM_BIT 0 | ||
7968 | #define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT) | ||
7969 | |||
7970 | /* | ||
7971 | * SSI Character-per-frame Control Register (SSI_ICR) | ||
7972 | * SSI_ICR is ignored for SSI_ICR1.FMT != 00b | ||
7973 | */ | ||
7974 | |||
7975 | #ifndef __MIPS_ASSEMBLER | ||
7976 | |||
7977 | /*************************************************************************** | ||
7978 | * SSI (Synchronous Serial Interface) | ||
7979 | ***************************************************************************/ | ||
7980 | /* n = 0, 1 (SSI0, SSI1) */ | ||
7981 | #define __ssi_enable(n) ( REG_SSI_CR0(n) |= SSI_CR0_SSIE ) | ||
7982 | #define __ssi_disable(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_SSIE ) | ||
7983 | #define __ssi_select_ce(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_FSEL ) | ||
7984 | |||
7985 | #define __ssi_normal_mode(n) ( REG_SSI_ITR(n) &= ~SSI_ITR_IVLTM_MASK ) | ||
7986 | |||
7987 | #define __ssi_select_ce2(n) \ | ||
7988 | do { \ | ||
7989 | REG_SSI_CR0(n) |= SSI_CR0_FSEL; \ | ||
7990 | REG_SSI_CR1(n) &= ~SSI_CR1_MULTS; \ | ||
7991 | } while (0) | ||
7992 | |||
7993 | #define __ssi_select_gpc(n) \ | ||
7994 | do { \ | ||
7995 | REG_SSI_CR0(n) &= ~SSI_CR0_FSEL; \ | ||
7996 | REG_SSI_CR1(n) |= SSI_CR1_MULTS; \ | ||
7997 | } while (0) | ||
7998 | |||
7999 | #define __ssi_underrun_auto_clear(n) \ | ||
8000 | do { \ | ||
8001 | REG_SSI_CR0(n) |= SSI_CR0_EACLRUN; \ | ||
8002 | } while (0) | ||
8003 | |||
8004 | #define __ssi_underrun_clear_manually(n) \ | ||
8005 | do { \ | ||
8006 | REG_SSI_CR0(n) &= ~SSI_CR0_EACLRUN; \ | ||
8007 | } while (0) | ||
8008 | |||
8009 | #define __ssi_enable_tx_intr(n) \ | ||
8010 | ( REG_SSI_CR0(n) |= SSI_CR0_TIE | SSI_CR0_TEIE ) | ||
8011 | |||
8012 | #define __ssi_disable_tx_intr(n) \ | ||
8013 | ( REG_SSI_CR0(n) &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) ) | ||
8014 | |||
8015 | #define __ssi_enable_rx_intr(n) \ | ||
8016 | ( REG_SSI_CR0(n) |= SSI_CR0_RIE | SSI_CR0_REIE ) | ||
8017 | |||
8018 | #define __ssi_disable_rx_intr(n) \ | ||
8019 | ( REG_SSI_CR0(n) &= ~(SSI_CR0_RIE | SSI_CR0_REIE) ) | ||
8020 | |||
8021 | #define __ssi_enable_txfifo_half_empty_intr(n) \ | ||
8022 | ( REG_SSI_CR0(n) |= SSI_CR0_TIE ) | ||
8023 | #define __ssi_disable_txfifo_half_empty_intr(n) \ | ||
8024 | ( REG_SSI_CR0(n) &= ~SSI_CR0_TIE ) | ||
8025 | #define __ssi_enable_tx_error_intr(n) \ | ||
8026 | ( REG_SSI_CR0(n) |= SSI_CR0_TEIE ) | ||
8027 | #define __ssi_disable_tx_error_intr(n) \ | ||
8028 | ( REG_SSI_CR0(n) &= ~SSI_CR0_TEIE ) | ||
8029 | #define __ssi_enable_rxfifo_half_full_intr(n) \ | ||
8030 | ( REG_SSI_CR0(n) |= SSI_CR0_RIE ) | ||
8031 | #define __ssi_disable_rxfifo_half_full_intr(n) \ | ||
8032 | ( REG_SSI_CR0(n) &= ~SSI_CR0_RIE ) | ||
8033 | #define __ssi_enable_rx_error_intr(n) \ | ||
8034 | ( REG_SSI_CR0(n) |= SSI_CR0_REIE ) | ||
8035 | #define __ssi_disable_rx_error_intr(n) \ | ||
8036 | ( REG_SSI_CR0(n) &= ~SSI_CR0_REIE ) | ||
8037 | |||
8038 | #define __ssi_enable_loopback(n) ( REG_SSI_CR0(n) |= SSI_CR0_LOOP ) | ||
8039 | #define __ssi_disable_loopback(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_LOOP ) | ||
8040 | |||
8041 | #define __ssi_enable_receive(n) ( REG_SSI_CR0(n) &= ~SSI_CR0_DISREV ) | ||
8042 | #define __ssi_disable_receive(n) ( REG_SSI_CR0(n) |= SSI_CR0_DISREV ) | ||
8043 | |||
8044 | #define __ssi_finish_receive(n) \ | ||
8045 | ( REG_SSI_CR0(n) |= (SSI_CR0_RFINE | SSI_CR0_RFINC) ) | ||
8046 | |||
8047 | #define __ssi_disable_recvfinish(n) \ | ||
8048 | ( REG_SSI_CR0(n) &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) ) | ||
8049 | |||
8050 | #define __ssi_flush_txfifo(n) ( REG_SSI_CR0(n) |= SSI_CR0_TFLUSH ) | ||
8051 | #define __ssi_flush_rxfifo(n) ( REG_SSI_CR0(n) |= SSI_CR0_RFLUSH ) | ||
8052 | |||
8053 | #define __ssi_flush_fifo(n) \ | ||
8054 | ( REG_SSI_CR0(n) |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH ) | ||
8055 | |||
8056 | #define __ssi_finish_transmit(n) ( REG_SSI_CR1(n) &= ~SSI_CR1_UNFIN ) | ||
8057 | #define __ssi_wait_transmit(n) ( REG_SSI_CR1(n) |= SSI_CR1_UNFIN ) | ||
8058 | #define __ssi_use_busy_wait_mode(n) __ssi_wait_transmit(n) | ||
8059 | #define __ssi_unset_busy_wait_mode(n) __ssi_finish_transmit(n) | ||
8060 | |||
8061 | #define __ssi_spi_format(n) \ | ||
8062 | do { \ | ||
8063 | REG_SSI_CR1(n) &= ~SSI_CR1_FMAT_MASK; \ | ||
8064 | REG_SSI_CR1(n) |= SSI_CR1_FMAT_SPI; \ | ||
8065 | REG_SSI_CR1(n) &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK); \ | ||
8066 | REG_SSI_CR1(n) |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \ | ||
8067 | } while (0) | ||
8068 | |||
8069 | /* TI's SSP format, must clear SSI_CR1.UNFIN */ | ||
8070 | #define __ssi_ssp_format(n) \ | ||
8071 | do { \ | ||
8072 | REG_SSI_CR1(n) &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \ | ||
8073 | REG_SSI_CR1(n) |= SSI_CR1_FMAT_SSP; \ | ||
8074 | } while (0) | ||
8075 | |||
8076 | /* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */ | ||
8077 | #define __ssi_microwire_format(n) \ | ||
8078 | do { \ | ||
8079 | REG_SSI_CR1(n) &= ~SSI_CR1_FMAT_MASK; \ | ||
8080 | REG_SSI_CR1(n) |= SSI_CR1_FMAT_MW1; \ | ||
8081 | REG_SSI_CR1(n) &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK); \ | ||
8082 | REG_SSI_CR1(n) |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \ | ||
8083 | REG_SSI_CR0(n) &= ~SSI_CR0_RFINE; \ | ||
8084 | } while (0) | ||
8085 | |||
8086 | /* CE# level (FRMHL), CE# in interval time (ITFRM), | ||
8087 | clock phase and polarity (PHA POL), | ||
8088 | interval time (SSIITR), interval characters/frame (SSIICR) */ | ||
8089 | |||
8090 | /* frmhl,endian,mcom,flen,pha,pol MASK */ | ||
8091 | #define SSICR1_MISC_MASK \ | ||
8092 | ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \ | ||
8093 | | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) | ||
8094 | |||
8095 | #define __ssi_spi_set_misc(n,frmhl,endian,flen,mcom,pha,pol) \ | ||
8096 | do { \ | ||
8097 | REG_SSI_CR1(n) &= ~SSICR1_MISC_MASK; \ | ||
8098 | REG_SSI_CR1(n) |= ((frmhl) << 30) | ((endian) << 25) | \ | ||
8099 | (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \ | ||
8100 | ((pha) << 1) | (pol); \ | ||
8101 | } while(0) | ||
8102 | |||
8103 | /* Transfer with MSB or LSB first */ | ||
8104 | #define __ssi_set_msb(n) ( REG_SSI_CR1(n) &= ~SSI_CR1_LFST ) | ||
8105 | #define __ssi_set_lsb(n) ( REG_SSI_CR1(n) |= SSI_CR1_LFST ) | ||
8106 | |||
8107 | #define __ssi_set_frame_length(n, m) \ | ||
8108 | REG_SSI_CR1(n) = (REG_SSI_CR1(n) & ~SSI_CR1_FLEN_MASK) | (((m) - 2) << 4) | ||
8109 | |||
8110 | /* m = 1 - 16 */ | ||
8111 | #define __ssi_set_microwire_command_length(n,m) \ | ||
8112 | ( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##m##BIT) ) | ||
8113 | |||
8114 | /* Set the clock phase for SPI */ | ||
8115 | #define __ssi_set_spi_clock_phase(n, m) \ | ||
8116 | ( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_PHA) | (((m)&0x1)<< 1))) | ||
8117 | |||
8118 | /* Set the clock polarity for SPI */ | ||
8119 | #define __ssi_set_spi_clock_polarity(n, p) \ | ||
8120 | ( REG_SSI_CR1(n) = ((REG_SSI_CR1(n) & ~SSI_CR1_POL) | ((p)&0x1)) ) | ||
8121 | |||
8122 | /* SSI tx trigger, m = i x 8 */ | ||
8123 | #define __ssi_set_tx_trigger(n, m) \ | ||
8124 | do { \ | ||
8125 | REG_SSI_CR1(n) &= ~SSI_CR1_TTRG_MASK; \ | ||
8126 | REG_SSI_CR1(n) |= ((m)/8)<<SSI_CR1_TTRG_BIT; \ | ||
8127 | } while (0) | ||
8128 | |||
8129 | /* SSI rx trigger, m = i x 8 */ | ||
8130 | #define __ssi_set_rx_trigger(n, m) \ | ||
8131 | do { \ | ||
8132 | REG_SSI_CR1(n) &= ~SSI_CR1_RTRG_MASK; \ | ||
8133 | REG_SSI_CR1(n) |= ((m)/8)<<SSI_CR1_RTRG_BIT; \ | ||
8134 | } while (0) | ||
8135 | |||
8136 | #define __ssi_get_txfifo_count(n) \ | ||
8137 | ( (REG_SSI_SR(n) & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT ) | ||
8138 | |||
8139 | #define __ssi_get_rxfifo_count(n) \ | ||
8140 | ( (REG_SSI_SR(n) & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT ) | ||
8141 | |||
8142 | #define __ssi_transfer_end(n) ( REG_SSI_SR(n) & SSI_SR_END ) | ||
8143 | #define __ssi_is_busy(n) ( REG_SSI_SR(n) & SSI_SR_BUSY ) | ||
8144 | |||
8145 | #define __ssi_txfifo_full(n) ( REG_SSI_SR(n) & SSI_SR_TFF ) | ||
8146 | #define __ssi_rxfifo_empty(n) ( REG_SSI_SR(n) & SSI_SR_RFE ) | ||
8147 | #define __ssi_rxfifo_half_full(n) ( REG_SSI_SR(n) & SSI_SR_RFHF ) | ||
8148 | #define __ssi_txfifo_half_empty(n) ( REG_SSI_SR(n) & SSI_SR_TFHE ) | ||
8149 | #define __ssi_underrun(n) ( REG_SSI_SR(n) & SSI_SR_UNDR ) | ||
8150 | #define __ssi_overrun(n) ( REG_SSI_SR(n) & SSI_SR_OVER ) | ||
8151 | #define __ssi_clear_underrun(n) ( REG_SSI_SR(n) = ~SSI_SR_UNDR ) | ||
8152 | #define __ssi_clear_overrun(n) ( REG_SSI_SR(n) = ~SSI_SR_OVER ) | ||
8153 | #define __ssi_clear_errors(n) ( REG_SSI_SR(n) &= ~(SSI_SR_UNDR | SSI_SR_OVER) ) | ||
8154 | |||
8155 | #define __ssi_set_clk(n, dev_clk, ssi_clk) \ | ||
8156 | ( REG_SSI_GR(n) = (dev_clk) / (2*(ssi_clk)) - 1 ) | ||
8157 | |||
8158 | #define __ssi_receive_data(n) REG_SSI_DR(n) | ||
8159 | #define __ssi_transmit_data(n, v) (REG_SSI_DR(n) = (v)) | ||
8160 | |||
8161 | #endif /* __MIPS_ASSEMBLER */ | ||
8162 | |||
8163 | /* | ||
8164 | * Timer and counter unit module(TCU) address definition | ||
8165 | */ | ||
8166 | #define TCU_BASE 0xb0002000 | ||
8167 | |||
8168 | /* TCU group offset */ | ||
8169 | #define TCU_GOS 0x10 | ||
8170 | |||
8171 | /* TCU total channel number */ | ||
8172 | #define TCU_CHANNEL_NUM 8 | ||
8173 | |||
8174 | /* | ||
8175 | * TCU registers offset definition | ||
8176 | */ | ||
8177 | #define TCU_TER_OFFSET (0x10) /* r, 16, 0x0000 */ | ||
8178 | #define TCU_TESR_OFFSET (0x14) /* w, 16, 0x???? */ | ||
8179 | #define TCU_TECR_OFFSET (0x18) /* w, 16, 0x???? */ | ||
8180 | |||
8181 | #define TCU_TSR_OFFSET (0x1c) /* r, 32, 0x00000000 */ | ||
8182 | #define TCU_TSSR_OFFSET (0x2c) /* w, 32, 0x00000000 */ | ||
8183 | #define TCU_TSCR_OFFSET (0x3c) /* w, 32, 0x0000 */ | ||
8184 | |||
8185 | #define TCU_TFR_OFFSET (0x20) /* r, 32, 0x003F003F */ | ||
8186 | #define TCU_TFSR_OFFSET (0x24) /* w, 32, 0x???????? */ | ||
8187 | #define TCU_TFCR_OFFSET (0x28) /* w, 32, 0x???????? */ | ||
8188 | |||
8189 | #define TCU_TMR_OFFSET (0x30) /* r, 32, 0x00000000 */ | ||
8190 | #define TCU_TMSR_OFFSET (0x34) /* w, 32, 0x???????? */ | ||
8191 | #define TCU_TMCR_OFFSET (0x38) /* w, 32, 0x???????? */ | ||
8192 | |||
8193 | #define TCU_TSTR_OFFSET (0xf0) /* r, 32, 0x00000000 */ | ||
8194 | #define TCU_TSTSR_OFFSET (0xf4) /* w, 32, 0x???????? */ | ||
8195 | #define TCU_TSTCR_OFFSET (0xf8) /* w, 32, 0x???????? */ | ||
8196 | |||
8197 | #define TCU_TDFR_OFFSET (0x40) /* rw,16, 0x???? */ | ||
8198 | #define TCU_TDHR_OFFSET (0x44) /* rw,16, 0x???? */ | ||
8199 | #define TCU_TCNT_OFFSET (0x48) /* rw,16, 0x???? */ | ||
8200 | #define TCU_TCSR_OFFSET (0x4c) /* rw,16, 0x0000 */ | ||
8201 | |||
8202 | /* | ||
8203 | * TCU registers address definition | ||
8204 | */ | ||
8205 | #define TCU_TER (TCU_BASE + TCU_TER_OFFSET) | ||
8206 | #define TCU_TESR (TCU_BASE + TCU_TESR_OFFSET) | ||
8207 | #define TCU_TECR (TCU_BASE + TCU_TECR_OFFSET) | ||
8208 | #define TCU_TSR (TCU_BASE + TCU_TSR_OFFSET) | ||
8209 | #define TCU_TFR (TCU_BASE + TCU_TFR_OFFSET) | ||
8210 | #define TCU_TFSR (TCU_BASE + TCU_TFSR_OFFSET) | ||
8211 | #define TCU_TFCR (TCU_BASE + TCU_TFCR_OFFSET) | ||
8212 | #define TCU_TSSR (TCU_BASE + TCU_TSSR_OFFSET) | ||
8213 | #define TCU_TMR (TCU_BASE + TCU_TMR_OFFSET) | ||
8214 | #define TCU_TMSR (TCU_BASE + TCU_TMSR_OFFSET) | ||
8215 | #define TCU_TMCR (TCU_BASE + TCU_TMCR_OFFSET) | ||
8216 | #define TCU_TSCR (TCU_BASE + TCU_TSCR_OFFSET) | ||
8217 | #define TCU_TSTR (TCU_BASE + TCU_TSTR_OFFSET) | ||
8218 | #define TCU_TSTSR (TCU_BASE + TCU_TSTSR_OFFSET) | ||
8219 | #define TCU_TSTCR (TCU_BASE + TCU_TSTCR_OFFSET) | ||
8220 | |||
8221 | /* n is the TCU channel index (0 - 7) */ | ||
8222 | #define TCU_TDFR(n) (TCU_BASE + (n) * TCU_GOS + TCU_TDFR_OFFSET) | ||
8223 | #define TCU_TDHR(n) (TCU_BASE + (n) * TCU_GOS + TCU_TDHR_OFFSET) | ||
8224 | #define TCU_TCNT(n) (TCU_BASE + (n) * TCU_GOS + TCU_TCNT_OFFSET) | ||
8225 | #define TCU_TCSR(n) (TCU_BASE + (n) * TCU_GOS + TCU_TCSR_OFFSET) | ||
8226 | |||
8227 | /* | ||
8228 | * TCU registers bit field common define | ||
8229 | */ | ||
8230 | |||
8231 | /* When n is NOT less than TCU_CHANNEL_NUM, change to TCU_CHANNEL_NUM - 1 */ | ||
8232 | #define __TIMER(n) (1 << ((n) < TCU_CHANNEL_NUM ? (n) : (TCU_CHANNEL_NUM - 1)) | ||
8233 | |||
8234 | /* Timer counter enable register(TER) */ | ||
8235 | #define TER_OSTEN BIT15 | ||
8236 | #define TER_TCEN(n) __TIMER(n) | ||
8237 | |||
8238 | /* Timer counter enable set register(TESR) */ | ||
8239 | #define TESR_OST BIT15 | ||
8240 | #define TESR_TIMER(n) __TIMER(n) | ||
8241 | |||
8242 | /* Timer counter enable clear register(TECR) */ | ||
8243 | #define TECR_OST BIT15 | ||
8244 | #define TECR_TIMER(n) __TIMER(n) | ||
8245 | |||
8246 | /* Timer stop register(TSR) */ | ||
8247 | #define TSR_WDT_STOP BIT16 | ||
8248 | #define TSR_OST_STOP BIT15 | ||
8249 | #define TSR_TIMER_STOP(n) __TIMER(n) | ||
8250 | |||
8251 | /* Timer stop set register(TSSR) */ | ||
8252 | #define TSSR_WDT BIT16 | ||
8253 | #define TSSR_OST BIT15 | ||
8254 | #define TSSR_TIMER(n) __TIMER(n) | ||
8255 | |||
8256 | /* Timer stop clear register(TSCR) */ | ||
8257 | #define TSCR_WDT BIT16 | ||
8258 | #define TSCR_OST BIT15 | ||
8259 | #define TSSR_TIMER(n) __TIMER(n) | ||
8260 | |||
8261 | /* Timer flag register(TFR) */ | ||
8262 | #define TFR_HFLAG(n) (__TIMER(n) << 16) | ||
8263 | #define TFR_OSTFLAG BIT15 | ||
8264 | #define TFR_FFLAG(n) __TIMER(n) | ||
8265 | |||
8266 | /* Timer flag set register(TFSR) */ | ||
8267 | #define TFSR_HFLAG(n) (__TIMER(n) << 16) | ||
8268 | #define TFSR_OSTFLAG BIT15 | ||
8269 | #define TFSR_FFLAG(n) __TIMER(n) | ||
8270 | |||
8271 | /* Timer flag clear register(TFCR) */ | ||
8272 | #define TFCR_HFLAG(n) (__TIMER(n) << 16) | ||
8273 | #define TFCR_OSTFLAG BIT15 | ||
8274 | #define TFCR_FFLAG(n) (__TIMER(n)) | ||
8275 | |||
8276 | /* Timer mast register(TMR) */ | ||
8277 | #define TMR_HMASK(n) (__TIMER(n) << 16) | ||
8278 | #define TMR_OSTMASK BIT15 | ||
8279 | #define TMR_FMASK(n) (__TIMER(n)) | ||
8280 | |||
8281 | /* Timer mask set register(TMSR) */ | ||
8282 | #define TMSR_HMASK(n) (__TIMER(n) << 16) | ||
8283 | #define TMSR_OSTMASK BIT15 | ||
8284 | #define TMSR_FMASK(n) (__TIMER(n)) | ||
8285 | |||
8286 | /* Timer mask clear register(TMCR) */ | ||
8287 | #define TMCR_HMASK(n) (__TIMER(n) << 16) | ||
8288 | #define TMCR_OSTMASK BIT15 | ||
8289 | #define TMCR_FMASK(n) (__TIMER(n)) | ||
8290 | |||
8291 | /* Timer control register(TCSR) */ | ||
8292 | #define TCSR_BYPASS BIT11 | ||
8293 | #define TCSR_CLRZ BIT10 | ||
8294 | #define TCSR_SD_ABRUPT BIT9 | ||
8295 | #define TCSR_INITL_HIGH BIT8 | ||
8296 | #define TCSR_PWM_EN BIT7 | ||
8297 | #define TCSR_PWM_IN_EN BIT6 | ||
8298 | #define TCSR_EXT_EN BIT2 | ||
8299 | #define TCSR_RTC_EN BIT1 | ||
8300 | #define TCSR_PCK_EN BIT0 | ||
8301 | |||
8302 | #define TCSR_PRESCALE_LSB 3 | ||
8303 | #define TCSR_PRESCALE_MASK BITS_H2L(5, TCSR_PRESCALE_LSB) | ||
8304 | #define TCSR_PRESCALE1 (0x0 << TCSR_PRESCALE_LSB) | ||
8305 | #define TCSR_PRESCALE4 (0x1 << TCSR_PRESCALE_LSB) | ||
8306 | #define TCSR_PRESCALE16 (0x2 << TCSR_PRESCALE_LSB) | ||
8307 | #define TCSR_PRESCALE64 (0x3 << TCSR_PRESCALE_LSB) | ||
8308 | #define TCSR_PRESCALE256 (0x4 << TCSR_PRESCALE_LSB) | ||
8309 | #define TCSR_PRESCALE1024 (0x5 << TCSR_PRESCALE_LSB) | ||
8310 | |||
8311 | /* Timer data full register(TDFR) */ | ||
8312 | #define TDFR_TDFR_LSB 0 | ||
8313 | #define TDFR_TDFR_MASK BITS_H2L(15, TDFR_TDFR_LSB) | ||
8314 | |||
8315 | /* Timer data half register(TDHR) */ | ||
8316 | #define TDHR_TDHR_LSB 0 | ||
8317 | #define TDHR_TDHR_MASK BITS_H2L(15, TDHR_TDHR_LSB) | ||
8318 | |||
8319 | /* Timer counter register(TCNT) */ | ||
8320 | #define TCNT_TCNT_LSB 0 | ||
8321 | #define TCNT_TCNT_MASK BITS_H2L(15, TCNT_TCNT_LSB) | ||
8322 | |||
8323 | /* Timer status register(TSTR) */ | ||
8324 | #define TSTR_REAL2 BIT18 | ||
8325 | #define TSTR_REAL1 BIT17 | ||
8326 | #define TSTR_BUSY2 BIT2 | ||
8327 | #define TSTR_BUSY1 BIT1 | ||
8328 | |||
8329 | /* Timer status set register(TSTSR) */ | ||
8330 | #define TSTSR_REALS2 BIT18 | ||
8331 | #define TSTSR_REALS1 BIT17 | ||
8332 | #define TSTSR_BUSYS2 BIT2 | ||
8333 | #define TSTSR_BUSYS1 BIT1 | ||
8334 | |||
8335 | /* Timer status clear register(TSTCR) */ | ||
8336 | #define TSTCR_REALC2 BIT18 | ||
8337 | #define TSTCR_REALC1 BIT17 | ||
8338 | #define TSTCR_BUSYC2 BIT2 | ||
8339 | #define TSTCR_BUSYC1 BIT1 | ||
8340 | |||
8341 | #ifndef __MIPS_ASSEMBLER | ||
8342 | |||
8343 | #define REG_TCU_TER REG16(TCU_TER) | ||
8344 | #define REG_TCU_TESR REG16(TCU_TESR) | ||
8345 | #define REG_TCU_TECR REG16(TCU_TECR) | ||
8346 | #define REG_TCU_TSR REG32(TCU_TSR) | ||
8347 | #define REG_TCU_TFR REG32(TCU_TFR) | ||
8348 | #define REG_TCU_TFSR REG32(TCU_TFSR) | ||
8349 | #define REG_TCU_TFCR REG32(TCU_TFCR) | ||
8350 | #define REG_TCU_TSSR REG32(TCU_TSSR) | ||
8351 | #define REG_TCU_TMR REG32(TCU_TMR) | ||
8352 | #define REG_TCU_TMSR REG32(TCU_TMSR) | ||
8353 | #define REG_TCU_TMCR REG32(TCU_TMCR) | ||
8354 | #define REG_TCU_TSCR REG32(TCU_TSCR) | ||
8355 | #define REG_TCU_TSTR REG32(TCU_TSTR) | ||
8356 | #define REG_TCU_TSTSR REG32(TCU_TSTSR) | ||
8357 | #define REG_TCU_TSTCR REG32(TCU_TSTCR) | ||
8358 | |||
8359 | #define REG_TCU_TDFR(n) REG16(TCU_TDFR(n)) | ||
8360 | #define REG_TCU_TDHR(n) REG16(TCU_TDHR(n)) | ||
8361 | #define REG_TCU_TCNT(n) REG16(TCU_TCNT(n)) | ||
8362 | #define REG_TCU_TCSR(n) REG16(TCU_TCSR(n)) | ||
8363 | |||
8364 | // where 'n' is the TCU channel | ||
8365 | #define __tcu_select_extalclk(n) \ | ||
8366 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCSR_EXT_EN | TCSR_RTC_EN | TCSR_PCK_EN)) | TCSR_EXT_EN) | ||
8367 | #define __tcu_select_rtcclk(n) \ | ||
8368 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCSR_EXT_EN | TCSR_RTC_EN | TCSR_PCK_EN)) | TCSR_RTC_EN) | ||
8369 | #define __tcu_select_pclk(n) \ | ||
8370 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCSR_EXT_EN | TCSR_RTC_EN | TCSR_PCK_EN)) | TCSR_PCK_EN) | ||
8371 | #define __tcu_disable_pclk(n) \ | ||
8372 | REG_TCU_TCSR(n) = (REG_TCU_TCSR((n)) & ~TCSR_PCK_EN); | ||
8373 | #define __tcu_select_clk_div1(n) \ | ||
8374 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE1) | ||
8375 | #define __tcu_select_clk_div4(n) \ | ||
8376 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE4) | ||
8377 | #define __tcu_select_clk_div16(n) \ | ||
8378 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE16) | ||
8379 | #define __tcu_select_clk_div64(n) \ | ||
8380 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE64) | ||
8381 | #define __tcu_select_clk_div256(n) \ | ||
8382 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE256) | ||
8383 | #define __tcu_select_clk_div1024(n) \ | ||
8384 | (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCSR_PRESCALE_MASK) | TCSR_PRESCALE1024) | ||
8385 | |||
8386 | #define __tcu_enable_pwm_output(n) (REG_TCU_TCSR((n)) |= TCSR_PWM_EN) | ||
8387 | #define __tcu_disable_pwm_output(n) (REG_TCU_TCSR((n)) &= ~TCSR_PWM_EN) | ||
8388 | |||
8389 | #define __tcu_init_pwm_output_high(n) (REG_TCU_TCSR((n)) |= TCSR_INITL_HIGH) | ||
8390 | #define __tcu_init_pwm_output_low(n) (REG_TCU_TCSR((n)) &= ~TCSR_INITL_HIGH) | ||
8391 | |||
8392 | #define __tcu_set_pwm_output_shutdown_graceful(n) (REG_TCU_TCSR((n)) &= ~TCSR_SD_ABRUPT) | ||
8393 | #define __tcu_set_pwm_output_shutdown_abrupt(n) (REG_TCU_TCSR((n)) |= TCSR_SD_ABRUPT) | ||
8394 | |||
8395 | #define __tcu_clear_counter_to_zero(n) (REG_TCU_TCSR((n)) |= TCSR_CLRZ) | ||
8396 | |||
8397 | #define __tcu_ost_enabled() (REG_TCU_TER & TER_OSTEN) | ||
8398 | #define __tcu_enable_ost() (REG_TCU_TESR = TESR_OST) | ||
8399 | #define __tcu_disable_ost() (REG_TCU_TECR = TECR_OST) | ||
8400 | |||
8401 | #define __tcu_counter_enabled(n) (REG_TCU_TER & (1 << (n))) | ||
8402 | #define __tcu_start_counter(n) (REG_TCU_TESR |= (1 << (n))) | ||
8403 | #define __tcu_stop_counter(n) (REG_TCU_TECR |= (1 << (n))) | ||
8404 | |||
8405 | #define __tcu_half_match_flag(n) (REG_TCU_TFR & (1 << ((n) + 16))) | ||
8406 | #define __tcu_full_match_flag(n) (REG_TCU_TFR & (1 << (n))) | ||
8407 | #define __tcu_set_half_match_flag(n) (REG_TCU_TFSR = (1 << ((n) + 16))) | ||
8408 | #define __tcu_set_full_match_flag(n) (REG_TCU_TFSR = (1 << (n))) | ||
8409 | #define __tcu_clear_half_match_flag(n) (REG_TCU_TFCR = (1 << ((n) + 16))) | ||
8410 | #define __tcu_clear_full_match_flag(n) (REG_TCU_TFCR = (1 << (n))) | ||
8411 | #define __tcu_mask_half_match_irq(n) (REG_TCU_TMSR = (1 << ((n) + 16))) | ||
8412 | #define __tcu_mask_full_match_irq(n) (REG_TCU_TMSR = (1 << (n))) | ||
8413 | #define __tcu_unmask_half_match_irq(n) (REG_TCU_TMCR = (1 << ((n) + 16))) | ||
8414 | #define __tcu_unmask_full_match_irq(n) (REG_TCU_TMCR = (1 << (n))) | ||
8415 | |||
8416 | #define __tcu_ost_match_flag() (REG_TCU_TFR & TFR_OSTFLAG) | ||
8417 | #define __tcu_set_ost_match_flag() (REG_TCU_TFSR = TFSR_OSTFLAG) | ||
8418 | #define __tcu_clear_ost_match_flag() (REG_TCU_TFCR = TFCR_OSTFLAG) | ||
8419 | #define __tcu_ost_match_irq_masked() (REG_TCU_TMR & TMR_OSTMASK) | ||
8420 | #define __tcu_mask_ost_match_irq() (REG_TCU_TMSR = TMSR_OSTMASK) | ||
8421 | #define __tcu_unmask_ost_match_irq() (REG_TCU_TMCR = TMCR_OSTMASK) | ||
8422 | |||
8423 | #define __tcu_wdt_clock_stopped() (REG_TCU_TSR & TSR_WDT_STOP) | ||
8424 | #define __tcu_ost_clock_stopped() (REG_TCU_TSR & TSR_OST_STOP) | ||
8425 | #define __tcu_timer_clock_stopped(n) (REG_TCU_TSR & (1 << (n))) | ||
8426 | |||
8427 | #define __tcu_start_wdt_clock() (REG_TCU_TSCR = TSCR_WDT) | ||
8428 | #define __tcu_start_ost_clock() (REG_TCU_TSCR = TSCR_OST) | ||
8429 | #define __tcu_start_timer_clock(n) (REG_TCU_TSCR = (1 << (n))) | ||
8430 | |||
8431 | #define __tcu_stop_wdt_clock() (REG_TCU_TSSR = TSSR_WDT) | ||
8432 | #define __tcu_stop_ost_clock() (REG_TCU_TSSR = TSSR_OST) | ||
8433 | #define __tcu_stop_timer_clock(n) (REG_TCU_TSSR = (1 << (n))) | ||
8434 | |||
8435 | #define __tcu_get_count(n) (REG_TCU_TCNT((n))) | ||
8436 | #define __tcu_set_count(n,v) (REG_TCU_TCNT((n)) = (v)) | ||
8437 | #define __tcu_set_full_data(n,v) (REG_TCU_TDFR((n)) = (v)) | ||
8438 | #define __tcu_set_half_data(n,v) (REG_TCU_TDHR((n)) = (v)) | ||
8439 | |||
8440 | /* TCU2, counter 1, 2*/ | ||
8441 | #define __tcu_read_real_value(n) (REG_TCU_TSTR & (1 << ((n) + 16))) | ||
8442 | #define __tcu_read_false_value(n) (REG_TCU_TSTR & (1 << ((n) + 16))) | ||
8443 | #define __tcu_counter_busy(n) (REG_TCU_TSTR & (1 << (n))) | ||
8444 | #define __tcu_counter_ready(n) (REG_TCU_TSTR & (1 << (n))) | ||
8445 | |||
8446 | #define __tcu_set_read_real_value(n) (REG_TCU_TSTSR = (1 << ((n) + 16))) | ||
8447 | #define __tcu_set_read_false_value(n) (REG_TCU_TSTCR = (1 << ((n) + 16))) | ||
8448 | #define __tcu_set_counter_busy(n) (REG_TCU_TSTSR = (1 << (n))) | ||
8449 | #define __tcu_set_counter_ready(n) (REG_TCU_TSTCR = (1 << (n))) | ||
8450 | |||
8451 | #endif /* __MIPS_ASSEMBLER */ | ||
8452 | |||
8453 | #define TSSI0_BASE 0xB0073000 | ||
8454 | |||
8455 | /************************************************************************* | ||
8456 | * TSSI MPEG 2-TS slave interface | ||
8457 | *************************************************************************/ | ||
8458 | #define TSSI_ENA ( TSSI0_BASE + 0x00 ) /* TSSI enable register */ | ||
8459 | #define TSSI_CFG ( TSSI0_BASE + 0x04 ) /* TSSI configure register */ | ||
8460 | #define TSSI_CTRL ( TSSI0_BASE + 0x08 ) /* TSSI control register */ | ||
8461 | #define TSSI_STAT ( TSSI0_BASE + 0x0c ) /* TSSI state register */ | ||
8462 | #define TSSI_FIFO ( TSSI0_BASE + 0x10 ) /* TSSI FIFO register */ | ||
8463 | #define TSSI_PEN ( TSSI0_BASE + 0x14 ) /* TSSI PID enable register */ | ||
8464 | #define TSSI_NUM ( TSSI0_BASE + 0x18 ) | ||
8465 | #define TSSI_DTR ( TSSI0_BASE + 0x1c ) | ||
8466 | #define TSSI_PID(n) ( TSSI0_BASE + 0x20 + 4*(n) ) /* TSSI PID filter register */ | ||
8467 | #define TSSI_PID0 ( TSSI0_BASE + 0x20 ) | ||
8468 | #define TSSI_PID1 ( TSSI0_BASE + 0x24 ) | ||
8469 | #define TSSI_PID2 ( TSSI0_BASE + 0x28 ) | ||
8470 | #define TSSI_PID3 ( TSSI0_BASE + 0x2c ) | ||
8471 | #define TSSI_PID4 ( TSSI0_BASE + 0x30 ) | ||
8472 | #define TSSI_PID5 ( TSSI0_BASE + 0x34 ) | ||
8473 | #define TSSI_PID6 ( TSSI0_BASE + 0x38 ) | ||
8474 | #define TSSI_PID7 ( TSSI0_BASE + 0x3c ) | ||
8475 | #define TSSI_PID8 ( TSSI0_BASE + 0x40 ) | ||
8476 | #define TSSI_PID9 ( TSSI0_BASE + 0x44 ) | ||
8477 | #define TSSI_PID10 ( TSSI0_BASE + 0x48 ) | ||
8478 | #define TSSI_PID11 ( TSSI0_BASE + 0x4c ) | ||
8479 | #define TSSI_PID12 ( TSSI0_BASE + 0x50 ) | ||
8480 | #define TSSI_PID13 ( TSSI0_BASE + 0x54 ) | ||
8481 | #define TSSI_PID14 ( TSSI0_BASE + 0x58 ) | ||
8482 | #define TSSI_PID15 ( TSSI0_BASE + 0x5c ) | ||
8483 | #define TSSI_PID_MAX 16 /* max PID: 15 */ | ||
8484 | |||
8485 | #define TSSI_DDA ( TSSI0_BASE + 0x60 ) | ||
8486 | #define TSSI_DTA ( TSSI0_BASE + 0x64 ) | ||
8487 | #define TSSI_DID ( TSSI0_BASE + 0x68 ) | ||
8488 | #define TSSI_DCMD ( TSSI0_BASE + 0x6c ) | ||
8489 | #define TSSI_DST ( TSSI0_BASE + 0x70 ) | ||
8490 | #define TSSI_TC ( TSSI0_BASE + 0x74 ) | ||
8491 | |||
8492 | #define REG_TSSI_ENA REG8( TSSI_ENA ) | ||
8493 | #define REG_TSSI_CFG REG16( TSSI_CFG ) | ||
8494 | #define REG_TSSI_CTRL REG8( TSSI_CTRL ) | ||
8495 | #define REG_TSSI_STAT REG8( TSSI_STAT ) | ||
8496 | #define REG_TSSI_FIFO REG32( TSSI_FIFO ) | ||
8497 | #define REG_TSSI_PEN REG32( TSSI_PEN ) | ||
8498 | #define REG_TSSI_NUM REG32( TSSI_NUM ) | ||
8499 | #define REG_TSSI_DTR REG32( TSSI_DTR ) | ||
8500 | #define REG_TSSI_PID(n) REG32( TSSI_PID(n) ) | ||
8501 | #define REG_TSSI_PID0 REG32( TSSI_PID0 ) | ||
8502 | #define REG_TSSI_PID1 REG32( TSSI_PID1 ) | ||
8503 | #define REG_TSSI_PID2 REG32( TSSI_PID2 ) | ||
8504 | #define REG_TSSI_PID3 REG32( TSSI_PID3 ) | ||
8505 | #define REG_TSSI_PID4 REG32( TSSI_PID4 ) | ||
8506 | #define REG_TSSI_PID5 REG32( TSSI_PID5 ) | ||
8507 | #define REG_TSSI_PID6 REG32( TSSI_PID6 ) | ||
8508 | #define REG_TSSI_PID7 REG32( TSSI_PID7 ) | ||
8509 | #define REG_TSSI_PID8 REG32( TSSI_PID8 ) | ||
8510 | #define REG_TSSI_PID9 REG32( TSSI_PID9 ) | ||
8511 | #define REG_TSSI_PID10 REG32( TSSI_PID10 ) | ||
8512 | #define REG_TSSI_PID11 REG32( TSSI_PID11 ) | ||
8513 | #define REG_TSSI_PID12 REG32( TSSI_PID12 ) | ||
8514 | #define REG_TSSI_PID13 REG32( TSSI_PID13 ) | ||
8515 | #define REG_TSSI_PID14 REG32( TSSI_PID14 ) | ||
8516 | #define REG_TSSI_PID15 REG32( TSSI_PID15 ) | ||
8517 | |||
8518 | /* TSSI enable register */ | ||
8519 | #define TSSI_ENA_SFT_RST ( 1 << 7 ) /* soft reset bit */ | ||
8520 | #define TSSI_ENA_PID_EN ( 1 << 2 ) /* soft filtering function enable bit */ | ||
8521 | #define TSSI_ENA_FAIL ( 1 << 4 ) /* fail signal bit */ | ||
8522 | #define TSSI_ENA_PEN_0 ( 1 << 3 ) /* PID filter enable bit for PID */ | ||
8523 | #define TSSI_ENA_DMA_EN ( 1 << 1 ) /* DMA enable bit */ | ||
8524 | #define TSSI_ENA_ENA ( 1 << 0 ) /* TSSI enable bit */ | ||
8525 | |||
8526 | /* TSSI configure register */ | ||
8527 | #define TSSI_CFG_TRIG_BIT 14 /* fifo trig number */ | ||
8528 | #define TSSI_CFG_TRIG_MASK ( 0x7 << TSSI_CFG_TRIG_BIT) | ||
8529 | #define TSSI_CFG_TRIG_4 ( 0 << TSSI_CFG_TRIG_BIT) | ||
8530 | #define TSSI_CFG_TRIG_8 ( 1 << TSSI_CFG_TRIG_BIT) | ||
8531 | #define TSSI_CFG_TRIG_16 ( 2 << TSSI_CFG_TRIG_BIT) | ||
8532 | #define TSSI_CFG_TRIG_32 ( 3 << TSSI_CFG_TRIG_BIT) | ||
8533 | #define TSSI_CFG_TRIG_48 ( 4 << TSSI_CFG_TRIG_BIT) | ||
8534 | #define TSSI_CFG_TRIG_64 ( 5 << TSSI_CFG_TRIG_BIT) | ||
8535 | #define TSSI_CFG_TRIG_80 ( 6 << TSSI_CFG_TRIG_BIT) | ||
8536 | #define TSSI_CFG_TRIG_96 ( 7 << TSSI_CFG_TRIG_BIT) | ||
8537 | |||
8538 | /* mode of adding data 0 select bit */ | ||
8539 | #define TSSI_CFG_TRANS_MD_BIT 10 | ||
8540 | #define TSSI_CFG_TRANS_MD_MASK ( 0x3 << TSSI_CFG_TRANS_MD_BIT) | ||
8541 | #define TSSI_CFG_TRANS_MD_0 (0 << TSSI_CFG_TRANS_MD_BIT) | ||
8542 | #define TSSI_CFG_TRANS_MD_1 (1 << TSSI_CFG_TRANS_MD_BIT) | ||
8543 | #define TSSI_CFG_TRANS_MD_2 (2 << TSSI_CFG_TRANS_MD_BIT) | ||
8544 | |||
8545 | #define TSSI_CFG_END_WD ( 1 << 9 ) /* order of data in word */ | ||
8546 | #define TSSI_CFG_END_BT ( 1 << 8 ) /* order of data in byte */ | ||
8547 | |||
8548 | #define TSSI_CFG_TSDI_H ( 1 << 7 ) /* data pin polarity */ | ||
8549 | #define TSSI_CFG_USE_0 ( 1 << 6 ) /* serial mode data pin select */ | ||
8550 | #define TSSI_CFG_USE_TSDI0 ( 1 << 6 ) /* TSDI0 as serial mode data pin */ | ||
8551 | #define TSSI_CFG_USE_TSDI7 ( 0 << 6 ) /* TSDI7 as serial mode data pin */ | ||
8552 | #define TSSI_CFG_TSCLK_CH ( 1 << 5 ) /* clk channel select */ | ||
8553 | #define TSSI_CFG_PARAL ( 1 << 4 ) /* mode select */ | ||
8554 | #define TSSI_CFG_PARAL_MODE ( 1 << 4 ) /* parallel select */ | ||
8555 | #define TSSI_CFG_SERIAL_MODE ( 0 << 4 ) /* serial select */ | ||
8556 | #define TSSI_CFG_TSCLK_P ( 1 << 3 ) /* clk edge select */ | ||
8557 | #define TSSI_CFG_TSFRM_H ( 1 << 2 ) /* TSFRM polarity select */ | ||
8558 | #define TSSI_CFG_TSSTR_H ( 1 << 1 ) /* TSSTR polarity select */ | ||
8559 | #define TSSI_CFG_TSFAIL_H ( 1 << 0 ) /* TSFAIL polarity select */ | ||
8560 | |||
8561 | /* TSSI control register */ | ||
8562 | #define TSSI_CTRL_DTRM ( 1 << 2 ) /* FIFO data trigger interrupt mask bit */ | ||
8563 | #define TSSI_CTRL_OVRNM ( 1 << 1 ) /* FIFO overrun interrupt mask bit */ | ||
8564 | #define TSSI_CTRL_TRIGM ( 1 << 0 ) /* FIFO trigger interrupt mask bit */ | ||
8565 | |||
8566 | /* TSSI state register */ | ||
8567 | #define TSSI_STAT_DTR ( 1 << 2 ) /* FIFO data trigger interrupt flag bit */ | ||
8568 | #define TSSI_STAT_OVRN ( 1 << 1 ) /* FIFO overrun interrupt flag bit */ | ||
8569 | #define TSSI_STAT_TRIG ( 1 << 0 ) /* FIFO trigger interrupt flag bit */ | ||
8570 | |||
8571 | /* TSSI PID enable register */ | ||
8572 | #define TSSI_PEN_EN00 ( 1 << 0 ) /* enable PID n */ | ||
8573 | #define TSSI_PEN_EN10 ( 1 << 1 ) | ||
8574 | #define TSSI_PEN_EN20 ( 1 << 2 ) | ||
8575 | #define TSSI_PEN_EN30 ( 1 << 3 ) | ||
8576 | #define TSSI_PEN_EN40 ( 1 << 4 ) | ||
8577 | #define TSSI_PEN_EN50 ( 1 << 5 ) | ||
8578 | #define TSSI_PEN_EN60 ( 1 << 6 ) | ||
8579 | #define TSSI_PEN_EN70 ( 1 << 7 ) | ||
8580 | #define TSSI_PEN_EN80 ( 1 << 8 ) | ||
8581 | #define TSSI_PEN_EN90 ( 1 << 9 ) | ||
8582 | #define TSSI_PEN_EN100 ( 1 << 10 ) | ||
8583 | #define TSSI_PEN_EN110 ( 1 << 11 ) | ||
8584 | #define TSSI_PEN_EN120 ( 1 << 12 ) | ||
8585 | #define TSSI_PEN_EN130 ( 1 << 13 ) | ||
8586 | #define TSSI_PEN_EN140 ( 1 << 14 ) | ||
8587 | #define TSSI_PEN_EN150 ( 1 << 15 ) | ||
8588 | #define TSSI_PEN_EN01 ( 1 << 16 ) | ||
8589 | #define TSSI_PEN_EN11 ( 1 << 17 ) | ||
8590 | #define TSSI_PEN_EN21 ( 1 << 18 ) | ||
8591 | #define TSSI_PEN_EN31 ( 1 << 19 ) | ||
8592 | #define TSSI_PEN_EN41 ( 1 << 20 ) | ||
8593 | #define TSSI_PEN_EN51 ( 1 << 21 ) | ||
8594 | #define TSSI_PEN_EN61 ( 1 << 22 ) | ||
8595 | #define TSSI_PEN_EN71 ( 1 << 23 ) | ||
8596 | #define TSSI_PEN_EN81 ( 1 << 24 ) | ||
8597 | #define TSSI_PEN_EN91 ( 1 << 25 ) | ||
8598 | #define TSSI_PEN_EN101 ( 1 << 26 ) | ||
8599 | #define TSSI_PEN_EN111 ( 1 << 27 ) | ||
8600 | #define TSSI_PEN_EN121 ( 1 << 28 ) | ||
8601 | #define TSSI_PEN_EN131 ( 1 << 29 ) | ||
8602 | #define TSSI_PEN_EN141 ( 1 << 30 ) | ||
8603 | #define TSSI_PEN_EN151 ( 1 << 31 ) | ||
8604 | //#define TSSI_PEN_PID0 ( 1 << 31 ) /* PID filter enable PID0 */ | ||
8605 | |||
8606 | /* TSSI Data Number Registers */ | ||
8607 | #define TSSI_DNUM_BIT 0 | ||
8608 | #define TSSI_DNUM_MASK (0x7f << TSSI_DNUM_BIT) | ||
8609 | |||
8610 | /* TSSI Data Trigger Register */ | ||
8611 | #define TSSI_DTRG_BIT 0 | ||
8612 | #define TSSI_DTRG_MASK (0x7f << TSSI_DTRG_BIT) | ||
8613 | |||
8614 | /* TSSI PID Filter Registers */ | ||
8615 | #define TSSI_PID_PID1_BIT 16 | ||
8616 | #define TSSI_PID_PID1_MASK (0x1fff<<TSSI_PID_PID1_BIT) | ||
8617 | #define TSSI_PID_PID0_BIT 0 | ||
8618 | #define TSSI_PID_PID0_MASK (0x1fff<<TSSI_PID_PID0_BIT) | ||
8619 | |||
8620 | /* TSSI DMA Identifier Registers */ | ||
8621 | #define TSSI_DMA_ID_BIT 0 | ||
8622 | #define TSSI_DMA_ID_MASK (0xffff << TSSI_DMA_ID_BIT) | ||
8623 | |||
8624 | /* TSSI DMA Command Registers */ | ||
8625 | #define TSSI_DCMD_TLEN_BIT 8 | ||
8626 | #define TSSI_DCMD_TLEN_MASK (0xff << TSSI_DCMD_TLEN_BIT) | ||
8627 | #define TSSI_DCMD_TEFE (1 << 4) | ||
8628 | #define TSSI_DCMD_TSZ_BIT 2 | ||
8629 | #define TSSI_DCMD_TSZ_MASK (0x3 << TSSI_DCMD_TSZ_BIT) | ||
8630 | #define TSSI_DCMD_TSZ_4 (0 << TSSI_DCMD_TSZ_BIT) | ||
8631 | #define TSSI_DCMD_TSZ_8 (1 << TSSI_DCMD_TSZ_BIT) | ||
8632 | #define TSSI_DCMD_TSZ_16 (2 << TSSI_DCMD_TSZ_BIT) | ||
8633 | #define TSSI_DCMD_TSZ_32 (3 << TSSI_DCMD_TSZ_BIT) | ||
8634 | #define TSSI_DCMD_TEIE (1 << 1) | ||
8635 | #define TSSI_DCMD_LINK (1 << 0) | ||
8636 | |||
8637 | /* TSSI DMA Status Registers */ | ||
8638 | #define TSSI_DST_DID_BIT 16 | ||
8639 | #define TSSI_DST_DID_MASK (0xffff << 16) | ||
8640 | #define TSSI_DST_TEND (1 << 0) | ||
8641 | |||
8642 | /* TSSI Transfer Control Registers */ | ||
8643 | #define TSSI_TC_OP_BIT 4 | ||
8644 | #define TSSI_TC_OP_MASK (0x3 << TSSI_TC_OP_BIT) | ||
8645 | //////////////////#define TSSI_TC_OP_0 ( | ||
8646 | #define TSSI_TC_OPE (1 << 2) | ||
8647 | #define TSSI_TC_EME (1 << 1) | ||
8648 | #define TSSI_TC_APM (1 << 0) | ||
8649 | #ifndef __MIPS_ASSEMBLER | ||
8650 | |||
8651 | /************************************************************************* | ||
8652 | * TSSI MPEG 2-TS slave interface operation | ||
8653 | *************************************************************************/ | ||
8654 | #define __tssi_enable() ( REG_TSSI_ENA |= TSSI_ENA_ENA ) | ||
8655 | #define __tssi_disable() ( REG_TSSI_ENA &= ~TSSI_ENA_ENA ) | ||
8656 | #define __tssi_soft_reset() ( REG_TSSI_ENA |= TSSI_ENA_SFT_RST ) | ||
8657 | #define __tssi_filter_enable_pid0() ( REG_TSSI_ENA |= TSSI_ENA_PEN_0) | ||
8658 | #define __tssi_filter_disable_pid0() ( REG_TSSI_ENA &= ~TSSI_ENA_PEN_0) | ||
8659 | #define __tssi_dma_enable() ( REG_TSSI_ENA |= TSSI_ENA_DMA_EN ) | ||
8660 | #define __tssi_dma_disable() ( REG_TSSI_ENA &= ~TSSI_ENA_DMA_EN ) | ||
8661 | #define __tssi_filter_enable() ( REG_TSSI_ENA |= TSSI_ENA_PID_EN ) | ||
8662 | #define __tssi_filter_disable() ( REG_TSSI_ENA &= ~TSSI_ENA_PID_EN ) | ||
8663 | |||
8664 | /* n = 4, 8, 16 */ | ||
8665 | #define __tssi_set_tigger_num(n) \ | ||
8666 | do { \ | ||
8667 | REG_TSSI_CFG &= ~TSSI_CFG_TRIG_MASK; \ | ||
8668 | REG_TSSI_CFG |= TSSI_CFG_TRIG_##n; \ | ||
8669 | } while (0) | ||
8670 | |||
8671 | #define __tssi_set_data0_mode(n) \ | ||
8672 | do { \ | ||
8673 | REG_TSSI_CFG &= ~ TSSI_CFG_TRANS_MD_MASK; \ | ||
8674 | REG_TSSI_CFG |= TSSI_CFG_TRANS_MD_##n; \ | ||
8675 | } while(0) | ||
8676 | |||
8677 | #define __tssi_set_wd_1() ( REG_TSSI_CFG |= TSSI_CFG_END_WD ) | ||
8678 | #define __tssi_set_wd_0() ( REG_TSSI_CFG &= ~TSSI_CFG_END_WD ) | ||
8679 | |||
8680 | #define __tssi_set_bt_1() ( REG_TSSI_CFG |= TSSI_CFG_END_BD ) | ||
8681 | #define __tssi_set_bt_0() ( REG_TSSI_CFG &= ~TSSI_CFG_END_BD ) | ||
8682 | |||
8683 | #define __tssi_set_data_pola_high() ( REG_TSSI_CFG |= TSSI_CFG_TSDI_H ) | ||
8684 | #define __tssi_set_data_pola_low() ( REG_TSSI_CFG &= ~TSSI_CFG_TSDI_H ) | ||
8685 | |||
8686 | #define __tssi_set_data_use_data0() ( REG_TSSI_CFG |= TSSI_CFG_USE_0 ) | ||
8687 | #define __tssi_set_data_use_data7() ( REG_TSSI_CFG &= ~TSSI_CFG_USE_0 ) | ||
8688 | |||
8689 | #define __tssi_select_clk_fast() ( REG_TSSI_CFG &= ~TSSI_CFG_TSCLK_CH ) | ||
8690 | #define __tssi_select_clk_slow() ( REG_TSSI_CFG |= TSSI_CFG_TSCLK_CH ) | ||
8691 | |||
8692 | #define __tssi_select_serail_mode() ( REG_TSSI_CFG &= ~TSSI_CFG_PARAL ) | ||
8693 | #define __tssi_select_paral_mode() ( REG_TSSI_CFG |= TSSI_CFG_PARAL ) | ||
8694 | |||
8695 | #define __tssi_select_clk_nega_edge() ( REG_TSSI_CFG &= ~TSSI_CFG_TSCLK_P ) | ||
8696 | #define __tssi_select_clk_posi_edge() ( REG_TSSI_CFG |= TSSI_CFG_TSCLK_P ) | ||
8697 | |||
8698 | #define __tssi_select_frm_act_high() ( REG_TSSI_CFG |= TSSI_CFG_TSFRM_H ) | ||
8699 | #define __tssi_select_frm_act_low() ( REG_TSSI_CFG &= ~TSSI_CFG_TSFRM_H ) | ||
8700 | |||
8701 | #define __tssi_select_str_act_high() ( REG_TSSI_CFG |= TSSI_CFG_TSSTR_H ) | ||
8702 | #define __tssi_select_str_act_low() ( REG_TSSI_CFG &= ~TSSI_CFG_TSSTR_H ) | ||
8703 | |||
8704 | #define __tssi_select_fail_act_high() ( REG_TSSI_CFG |= TSSI_CFG_TSFAIL_H ) | ||
8705 | #define __tssi_select_fail_act_low() ( REG_TSSI_CFG &= ~TSSI_CFG_TSFAIL_H ) | ||
8706 | |||
8707 | #define __tssi_enable_data_trigger_irq() (REG_TSSI_CTRL &= ~TSSI_CTRL_DTRM) | ||
8708 | #define __tssi_disable_data_trigger_irq() (REG_TSSI_CTRL |= TSSI_CTRL_DTRM) | ||
8709 | |||
8710 | #define __tssi_enable_ovrn_irq() ( REG_TSSI_CTRL &= ~TSSI_CTRL_OVRNM ) | ||
8711 | #define __tssi_disable_ovrn_irq() ( REG_TSSI_CTRL |= TSSI_CTRL_OVRNM ) | ||
8712 | |||
8713 | #define __tssi_enable_trig_irq() ( REG_TSSI_CTRL &= ~TSSI_CTRL_TRIGM ) | ||
8714 | #define __tssi_disable_trig_irq() ( REG_TSSI_CTRL |= TSSI_CTRL_TRIGM ) | ||
8715 | |||
8716 | #define __tssi_state_is_dtr() ( REG_TSSI_STAT & TSSI_STAT_DTR ) | ||
8717 | #define __tssi_state_is_overrun() ( REG_TSSI_STAT & TSSI_STAT_OVRN ) | ||
8718 | #define __tssi_state_trigger_meet() ( REG_TSSI_STAT & TSSI_STAT_TRIG ) | ||
8719 | #define __tssi_clear_state() ( REG_TSSI_STAT = 0 ) /* write 0??? */ | ||
8720 | #define __tssi_state_clear_overrun() ( REG_TSSI_STAT = TSSI_STAT_OVRN ) //??????? xyma | ||
8721 | |||
8722 | //#define __tssi_enable_filte_pid0() ( REG_TSSI_PEN |= TSSI_PEN_PID0 ) | ||
8723 | //#define __tssi_disable_filte_pid0() ( REG_TSSI_PEN &= ~TSSI_PEN_PID0 ) | ||
8724 | |||
8725 | /* m = 0, ..., 31 */ | ||
8726 | ////////////////??????????????????????????????????????????????????????????? | ||
8727 | |||
8728 | #define __tssi_enable_pid_filter(m) \ | ||
8729 | do { \ | ||
8730 | int n = (m); \ | ||
8731 | if ( n>=0 && n <(TSSI_PID_MAX*2) ) { \ | ||
8732 | REG_TSSI_PEN |= ( 1 << n ); \ | ||
8733 | } \ | ||
8734 | } while (0) | ||
8735 | |||
8736 | /* m = 0, ..., 31 */ | ||
8737 | #define __tssi_disable_pid_filter(m) \ | ||
8738 | do { \ | ||
8739 | int n = (m); \ | ||
8740 | if ( n>=0 && n <(TSSI_PID_MAX*2) ) { \ | ||
8741 | REG_TSSI_PEN &= ~( 1 << n ); \ | ||
8742 | } \ | ||
8743 | } while (0) | ||
8744 | |||
8745 | /* n = 0, ..., 15 */ | ||
8746 | #define __tssi_set_pid0(n, pid0) \ | ||
8747 | do { \ | ||
8748 | REG_TSSI_PID(n) &= ~TSSI_PID_PID0_MASK; \ | ||
8749 | REG_TSSI_PID(n) |= ((pid0)<<TSSI_PID_PID0_BIT)&TSSI_PID_PID0_MASK; \ | ||
8750 | }while (0) | ||
8751 | /* n = 0, ..., 15 */ | ||
8752 | #define __tssi_set_pid1(n, pid1) \ | ||
8753 | do { \ | ||
8754 | REG_TSSI_PID(n) &= ~TSSI_PID_PID1_MASK; \ | ||
8755 | REG_TSSI_PID(n) |= ((pid1)<<TSSI_PID_PID1_BIT)&TSSI_PID_PID1_MASK; \ | ||
8756 | }while (0) | ||
8757 | |||
8758 | /* n = 0, ..., 15 */ | ||
8759 | #define __tssi_set_pid(n, pid) \ | ||
8760 | do { \ | ||
8761 | if ( n>=0 && n < TSSI_PID_MAX*2) { \ | ||
8762 | if ( n < TSSI_PID_MAX ) \ | ||
8763 | __tssi_set_pid0(n, pid); \ | ||
8764 | else \ | ||
8765 | __tssi_set_pid1(n-TSSI_PID_MAX, pid); \ | ||
8766 | } \ | ||
8767 | }while (0) | ||
8768 | |||
8769 | #endif /* __MIPS_ASSEMBLER */ | ||
8770 | |||
8771 | #define TVE_BASE 0xB3050100 | ||
8772 | |||
8773 | /************************************************************************* | ||
8774 | * TVE (TV Encoder Controller) | ||
8775 | *************************************************************************/ | ||
8776 | #define TVE_CTRL (TVE_BASE + 0x40) /* TV Encoder Control register */ | ||
8777 | #define TVE_FRCFG (TVE_BASE + 0x44) /* Frame configure register */ | ||
8778 | #define TVE_SLCFG1 (TVE_BASE + 0x50) /* TV signal level configure register 1 */ | ||
8779 | #define TVE_SLCFG2 (TVE_BASE + 0x54) /* TV signal level configure register 2*/ | ||
8780 | #define TVE_SLCFG3 (TVE_BASE + 0x58) /* TV signal level configure register 3*/ | ||
8781 | #define TVE_LTCFG1 (TVE_BASE + 0x60) /* Line timing configure register 1 */ | ||
8782 | #define TVE_LTCFG2 (TVE_BASE + 0x64) /* Line timing configure register 2 */ | ||
8783 | #define TVE_CFREQ (TVE_BASE + 0x70) /* Chrominance sub-carrier frequency configure register */ | ||
8784 | #define TVE_CPHASE (TVE_BASE + 0x74) /* Chrominance sub-carrier phase configure register */ | ||
8785 | #define TVE_CBCRCFG (TVE_BASE + 0x78) /* Chrominance filter configure register */ | ||
8786 | #define TVE_WSSCR (TVE_BASE + 0x80) /* Wide screen signal control register */ | ||
8787 | #define TVE_WSSCFG1 (TVE_BASE + 0x84) /* Wide screen signal configure register 1 */ | ||
8788 | #define TVE_WSSCFG2 (TVE_BASE + 0x88) /* Wide screen signal configure register 2 */ | ||
8789 | #define TVE_WSSCFG3 (TVE_BASE + 0x8c) /* Wide screen signal configure register 3 */ | ||
8790 | |||
8791 | #define REG_TVE_CTRL REG32(TVE_CTRL) | ||
8792 | #define REG_TVE_FRCFG REG32(TVE_FRCFG) | ||
8793 | #define REG_TVE_SLCFG1 REG32(TVE_SLCFG1) | ||
8794 | #define REG_TVE_SLCFG2 REG32(TVE_SLCFG2) | ||
8795 | #define REG_TVE_SLCFG3 REG32(TVE_SLCFG3) | ||
8796 | #define REG_TVE_LTCFG1 REG32(TVE_LTCFG1) | ||
8797 | #define REG_TVE_LTCFG2 REG32(TVE_LTCFG2) | ||
8798 | #define REG_TVE_CFREQ REG32(TVE_CFREQ) | ||
8799 | #define REG_TVE_CPHASE REG32(TVE_CPHASE) | ||
8800 | #define REG_TVE_CBCRCFG REG32(TVE_CBCRCFG) | ||
8801 | #define REG_TVE_WSSCR REG32(TVE_WSSCR) | ||
8802 | #define REG_TVE_WSSCFG1 REG32(TVE_WSSCFG1) | ||
8803 | #define REG_TVE_WSSCFG2 REG32(TVE_WSSCFG2) | ||
8804 | #define REG_TVE_WSSCFG3 REG32(TVE_WSSCFG3) | ||
8805 | |||
8806 | /* TV Encoder Control register */ | ||
8807 | #define TVE_CTRL_EYCBCR (1 << 25) /* YCbCr_enable */ | ||
8808 | #define TVE_CTRL_ECVBS (1 << 24) /* 1: cvbs_enable 0: s-video*/ | ||
8809 | #define TVE_CTRL_DAPD3 (1 << 23) /* DAC 3 power down */ | ||
8810 | #define TVE_CTRL_DAPD2 (1 << 22) /* DAC 2 power down */ | ||
8811 | #define TVE_CTRL_DAPD1 (1 << 21) /* DAC 1 power down */ | ||
8812 | #define TVE_CTRL_DAPD (1 << 20) /* power down all DACs */ | ||
8813 | #define TVE_CTRL_YCDLY_BIT 16 | ||
8814 | #define TVE_CTRL_YCDLY_MASK (0x7 << TVE_CTRL_YCDLY_BIT) | ||
8815 | #define TVE_CTRL_CGAIN_BIT 14 | ||
8816 | #define TVE_CTRL_CGAIN_MASK (0x3 << TVE_CTRL_CGAIN_BIT) | ||
8817 | #define TVE_CTRL_CGAIN_FULL (0 << TVE_CTRL_CGAIN_BIT) /* gain = 1 */ | ||
8818 | #define TVE_CTRL_CGAIN_QUTR (1 << TVE_CTRL_CGAIN_BIT) /* gain = 1/4 */ | ||
8819 | #define TVE_CTRL_CGAIN_HALF (2 << TVE_CTRL_CGAIN_BIT) /* gain = 1/2 */ | ||
8820 | #define TVE_CTRL_CGAIN_THREE_QURT (3 << TVE_CTRL_CGAIN_BIT) /* gain = 3/4 */ | ||
8821 | #define TVE_CTRL_CBW_BIT 12 | ||
8822 | #define TVE_CTRL_CBW_MASK (0x3 << TVE_CTRL_CBW_BIT) | ||
8823 | #define TVE_CTRL_CBW_NARROW (0 << TVE_CTRL_CBW_BIT) /* Narrow band */ | ||
8824 | #define TVE_CTRL_CBW_WIDE (1 << TVE_CTRL_CBW_BIT) /* Wide band */ | ||
8825 | #define TVE_CTRL_CBW_EXTRA (2 << TVE_CTRL_CBW_BIT) /* Extra wide band */ | ||
8826 | #define TVE_CTRL_CBW_ULTRA (3 << TVE_CTRL_CBW_BIT) /* Ultra wide band */ | ||
8827 | #define TVE_CTRL_SYNCT (1 << 9) | ||
8828 | #define TVE_CTRL_PAL (1 << 8) /* 1: PAL, 0: NTSC */ | ||
8829 | #define TVE_CTRL_FINV (1 << 7) /* invert_top:1-invert top and bottom fields. */ | ||
8830 | #define TVE_CTRL_ZBLACK (1 << 6) /* bypass_yclamp:1-Black of luminance (Y) input is 0.*/ | ||
8831 | #define TVE_CTRL_CR1ST (1 << 5) /* uv_order:0-Cb before Cr,1-Cr before Cb */ | ||
8832 | #define TVE_CTRL_CLBAR (1 << 4) /* Color bar mode:0-Output input video to TV,1-Output color bar to TV */ | ||
8833 | #define TVE_CTRL_SWRST (1 << 0) /* Software reset:1-TVE is reset */ | ||
8834 | |||
8835 | /* Signal level configure register 1 */ | ||
8836 | #define TVE_SLCFG1_BLACKL_BIT 0 | ||
8837 | #define TVE_SLCFG1_BLACKL_MASK (0x3ff << TVE_SLCFG1_BLACKL_BIT) | ||
8838 | #define TVE_SLCFG1_WHITEL_BIT 16 | ||
8839 | #define TVE_SLCFG1_WHITEL_MASK (0x3ff << TVE_SLCFG1_WHITEL_BIT) | ||
8840 | |||
8841 | /* Signal level configure register 2 */ | ||
8842 | #define TVE_SLCFG2_BLANKL_BIT 0 | ||
8843 | #define TVE_SLCFG2_BLANKL_MASK (0x3ff << TVE_SLCFG2_BLANKL_BIT) | ||
8844 | #define TVE_SLCFG2_VBLANKL_BIT 16 | ||
8845 | #define TVE_SLCFG2_VBLANKL_MASK (0x3ff << TVE_SLCFG2_VBLANKL_BIT) | ||
8846 | |||
8847 | /* Signal level configure register 3 */ | ||
8848 | #define TVE_SLCFG3_SYNCL_BIT 0 | ||
8849 | #define TVE_SLCFG3_SYNCL_MASK (0xff << TVE_SLCFG3_SYNCL_BIT) | ||
8850 | |||
8851 | /* Line timing configure register 1 */ | ||
8852 | #define TVE_LTCFG1_BACKP_BIT 0 | ||
8853 | #define TVE_LTCFG1_BACKP_MASK (0x7f << TVE_LTCFG1_BACKP_BIT) | ||
8854 | #define TVE_LTCFG1_HSYNCW_BIT 8 | ||
8855 | #define TVE_LTCFG1_HSYNCW_MASK (0x7f << TVE_LTCFG1_HSYNCW_BIT) | ||
8856 | #define TVE_LTCFG1_FRONTP_BIT 16 | ||
8857 | #define TVE_LTCFG1_FRONTP_MASK (0x1f << TVE_LTCFG1_FRONTP_BIT) | ||
8858 | |||
8859 | /* Line timing configure register 2 */ | ||
8860 | #define TVE_LTCFG2_BURSTW_BIT 0 | ||
8861 | #define TVE_LTCFG2_BURSTW_MASK (0x3f << TVE_LTCFG2_BURSTW_BIT) | ||
8862 | #define TVE_LTCFG2_PREBW_BIT 8 | ||
8863 | #define TVE_LTCFG2_PREBW_MASK (0x1f << TVE_LTCFG2_PREBW_BIT) | ||
8864 | #define TVE_LTCFG2_ACTLIN_BIT 16 | ||
8865 | #define TVE_LTCFG2_ACTLIN_MASK (0x7ff << TVE_LTCFG2_ACTLIN_BIT) | ||
8866 | |||
8867 | /* Chrominance sub-carrier phase configure register */ | ||
8868 | #define TVE_CPHASE_CCRSTP_BIT 0 | ||
8869 | #define TVE_CPHASE_CCRSTP_MASK (0x3 << TVE_CPHASE_CCRSTP_BIT) | ||
8870 | #define TVE_CPHASE_CCRSTP_8 (0 << TVE_CPHASE_CCRSTP_BIT) /* Every 8 field */ | ||
8871 | #define TVE_CPHASE_CCRSTP_4 (1 << TVE_CPHASE_CCRSTP_BIT) /* Every 4 field */ | ||
8872 | #define TVE_CPHASE_CCRSTP_2 (2 << TVE_CPHASE_CCRSTP_BIT) /* Every 2 lines */ | ||
8873 | #define TVE_CPHASE_CCRSTP_0 (3 << TVE_CPHASE_CCRSTP_BIT) /* Never */ | ||
8874 | #define TVE_CPHASE_ACTPH_BIT 16 | ||
8875 | #define TVE_CPHASE_ACTPH_MASK (0xff << TVE_CPHASE_ACTPH_BIT) | ||
8876 | #define TVE_CPHASE_INITPH_BIT 24 | ||
8877 | #define TVE_CPHASE_INITPH_MASK (0xff << TVE_CPHASE_INITPH_BIT) | ||
8878 | |||
8879 | /* Chrominance filter configure register */ | ||
8880 | #define TVE_CBCRCFG_CRGAIN_BIT 0 | ||
8881 | #define TVE_CBCRCFG_CRGAIN_MASK (0xff << TVE_CBCRCFG_CRGAIN_BIT) | ||
8882 | #define TVE_CBCRCFG_CBGAIN_BIT 8 | ||
8883 | #define TVE_CBCRCFG_CBGAIN_MASK (0xff << TVE_CBCRCFG_CBGAIN_BIT) | ||
8884 | #define TVE_CBCRCFG_CRBA_BIT 16 | ||
8885 | #define TVE_CBCRCFG_CRBA_MASK (0xff << TVE_CBCRCFG_CRBA_BIT) | ||
8886 | #define TVE_CBCRCFG_CBBA_BIT 24 | ||
8887 | #define TVE_CBCRCFG_CBBA_MASK (0xff << TVE_CBCRCFG_CBBA_BIT) | ||
8888 | |||
8889 | /* Frame configure register */ | ||
8890 | #define TVE_FRCFG_NLINE_BIT 0 | ||
8891 | #define TVE_FRCFG_NLINE_MASK (0x3ff << TVE_FRCFG_NLINE_BIT) | ||
8892 | #define TVE_FRCFG_L1ST_BIT 16 | ||
8893 | #define TVE_FRCFG_L1ST_MASK (0xff << TVE_FRCFG_L1ST_BIT) | ||
8894 | |||
8895 | /* Wide screen signal control register */ | ||
8896 | #define TVE_WSSCR_EWSS0_BIT 0 | ||
8897 | #define TVE_WSSCR_EWSS1_BIT 1 | ||
8898 | #define TVE_WSSCR_WSSTP_BIT 2 | ||
8899 | #define TVE_WSSCR_WSSCKBP_BIT 3 | ||
8900 | #define TVE_WSSCR_WSSEDGE_BIT 4 | ||
8901 | #define TVE_WSSCR_WSSEDGE_MASK (0x7 << TVE_WSSCR_WSSEDGE_BIT) | ||
8902 | #define TVE_WSSCR_ENCH_BIT 8 | ||
8903 | #define TVE_WSSCR_NCHW_BIT 9 | ||
8904 | #define TVE_WSSCR_NCHFREQ_BIT 12 | ||
8905 | #define TVE_WSSCR_NCHFREQ_MASK (0x7 << TVE_WSSCR_NCHFREQ_BIT) | ||
8906 | |||
8907 | #ifndef __MIPS_ASSEMBLER | ||
8908 | |||
8909 | /************************************************************************* | ||
8910 | * TVE (TV Encoder Controller) ops | ||
8911 | *************************************************************************/ | ||
8912 | /* TV Encoder Control register ops */ | ||
8913 | #define __tve_soft_reset() (REG_TVE_CTRL |= TVE_CTRL_SWRST) | ||
8914 | |||
8915 | #define __tve_output_colorbar() (REG_TVE_CTRL |= TVE_CTRL_CLBAR) | ||
8916 | #define __tve_output_video() (REG_TVE_CTRL &= ~TVE_CTRL_CLBAR) | ||
8917 | |||
8918 | #define __tve_input_cr_first() (REG_TVE_CTRL |= TVE_CTRL_CR1ST) | ||
8919 | #define __tve_input_cb_first() (REG_TVE_CTRL &= ~TVE_CTRL_CR1ST) | ||
8920 | |||
8921 | #define __tve_set_0_as_black() (REG_TVE_CTRL |= TVE_CTRL_ZBLACK) | ||
8922 | #define __tve_set_16_as_black() (REG_TVE_CTRL &= ~TVE_CTRL_ZBLACK) | ||
8923 | |||
8924 | #define __tve_ena_invert_top_bottom() (REG_TVE_CTRL |= TVE_CTRL_FINV) | ||
8925 | #define __tve_dis_invert_top_bottom() (REG_TVE_CTRL &= ~TVE_CTRL_FINV) | ||
8926 | |||
8927 | #define __tve_set_pal_mode() (REG_TVE_CTRL |= TVE_CTRL_PAL) | ||
8928 | #define __tve_set_ntsc_mode() (REG_TVE_CTRL &= ~TVE_CTRL_PAL) | ||
8929 | |||
8930 | #define __tve_set_pal_dura() (REG_TVE_CTRL |= TVE_CTRL_SYNCT) | ||
8931 | #define __tve_set_ntsc_dura() (REG_TVE_CTRL &= ~TVE_CTRL_SYNCT) | ||
8932 | |||
8933 | /* n = 0 ~ 3 */ | ||
8934 | #define __tve_set_c_bandwidth(n) \ | ||
8935 | do {\ | ||
8936 | REG_TVE_CTRL &= ~TVE_CTRL_CBW_MASK;\ | ||
8937 | REG_TVE_CTRL |= (n) << TVE_CTRL_CBW_BIT; \ | ||
8938 | }while(0) | ||
8939 | |||
8940 | /* n = 0 ~ 3 */ | ||
8941 | #define __tve_set_c_gain(n) \ | ||
8942 | do {\ | ||
8943 | REG_TVE_CTRL &= ~TVE_CTRL_CGAIN_MASK;\ | ||
8944 | (REG_TVE_CTRL |= (n) << TVE_CTRL_CGAIN_BIT; \ | ||
8945 | }while(0) | ||
8946 | |||
8947 | /* n = 0 ~ 7 */ | ||
8948 | #define __tve_set_yc_delay(n) \ | ||
8949 | do { \ | ||
8950 | REG_TVE_CTRL &= ~TVE_CTRL_YCDLY_MASK \ | ||
8951 | REG_TVE_CTRL |= ((n) << TVE_CTRL_YCDLY_BIT); \ | ||
8952 | } while(0) | ||
8953 | |||
8954 | #define __tve_disable_all_dacs() (REG_TVE_CTRL |= TVE_CTRL_DAPD) | ||
8955 | #define __tve_disable_dac1() (REG_TVE_CTRL |= TVE_CTRL_DAPD1) | ||
8956 | #define __tve_enable_dac1() (REG_TVE_CTRL &= ~TVE_CTRL_DAPD1) | ||
8957 | #define __tve_disable_dac2() (REG_TVE_CTRL |= TVE_CTRL_DAPD2) | ||
8958 | #define __tve_enable_dac2() (REG_TVE_CTRL &= ~TVE_CTRL_DAPD2) | ||
8959 | #define __tve_disable_dac3() (REG_TVE_CTRL |= TVE_CTRL_DAPD3) | ||
8960 | #define __tve_enable_dac3() (REG_TVE_CTRL &= ~TVE_CTRL_DAPD3) | ||
8961 | |||
8962 | #define __tve_enable_svideo_fmt() (REG_TVE_CTRL |= TVE_CTRL_ECVBS) | ||
8963 | #define __tve_enable_cvbs_fmt() (REG_TVE_CTRL &= ~TVE_CTRL_ECVBS) | ||
8964 | |||
8965 | /* TV Encoder Frame Configure register ops */ | ||
8966 | /* n = 0 ~ 255 */ | ||
8967 | #define __tve_set_first_video_line(n) \ | ||
8968 | do {\ | ||
8969 | REG_TVE_FRCFG &= ~TVE_FRCFG_L1ST_MASK;\ | ||
8970 | REG_TVE_FRCFG |= (n) << TVE_FRCFG_L1ST_BIT;\ | ||
8971 | } while(0) | ||
8972 | /* n = 0 ~ 1023 */ | ||
8973 | #define __tve_set_line_num_per_frm(n) \ | ||
8974 | do {\ | ||
8975 | REG_TVE_FRCFG &= ~TVE_FRCFG_NLINE_MASK;\ | ||
8976 | REG_TVE_CFG |= (n) << TVE_FRCFG_NLINE_BIT;\ | ||
8977 | } while(0) | ||
8978 | #define __tve_get_video_line_num()\ | ||
8979 | (((REG_TVE_FRCFG & TVE_FRCFG_NLINE_MASK) >> TVE_FRCFG_NLINE_BIT) - 1 - 2 * ((REG_TVE_FRCFG & TVE_FRCFG_L1ST_MASK) >> TVE_FRCFG_L1ST_BIT)) | ||
8980 | |||
8981 | /* TV Encoder Signal Level Configure register ops */ | ||
8982 | /* n = 0 ~ 1023 */ | ||
8983 | #define __tve_set_white_level(n) \ | ||
8984 | do {\ | ||
8985 | REG_TVE_SLCFG1 &= ~TVE_SLCFG1_WHITEL_MASK;\ | ||
8986 | REG_TVE_SLCFG1 |= (n) << TVE_SLCFG1_WHITEL_BIT;\ | ||
8987 | } while(0) | ||
8988 | /* n = 0 ~ 1023 */ | ||
8989 | #define __tve_set_black_level(n) \ | ||
8990 | do {\ | ||
8991 | REG_TVE_SLCFG1 &= ~TVE_SLCFG1_BLACKL_MASK;\ | ||
8992 | REG_TVE_SLCFG1 |= (n) << TVE_SLCFG1_BLACKL_BIT;\ | ||
8993 | } while(0) | ||
8994 | /* n = 0 ~ 1023 */ | ||
8995 | #define __tve_set_blank_level(n) \ | ||
8996 | do {\ | ||
8997 | REG_TVE_SLCFG2 &= ~TVE_SLCFG2_BLANKL_MASK;\ | ||
8998 | REG_TVE_SLCFG2 |= (n) << TVE_SLCFG2_BLANKL_BIT;\ | ||
8999 | } while(0) | ||
9000 | /* n = 0 ~ 1023 */ | ||
9001 | #define __tve_set_vbi_blank_level(n) \ | ||
9002 | do {\ | ||
9003 | REG_TVE_SLCFG2 &= ~TVE_SLCFG2_VBLANKL_MASK;\ | ||
9004 | REG_TVE_SLCFG2 |= (n) << TVE_SLCFG2_VBLANKL_BIT;\ | ||
9005 | } while(0) | ||
9006 | /* n = 0 ~ 1023 */ | ||
9007 | #define __tve_set_sync_level(n) \ | ||
9008 | do {\ | ||
9009 | REG_TVE_SLCFG3 &= ~TVE_SLCFG3_SYNCL_MASK;\ | ||
9010 | REG_TVE_SLCFG3 |= (n) << TVE_SLCFG3_SYNCL_BIT;\ | ||
9011 | } while(0) | ||
9012 | |||
9013 | /* TV Encoder Signal Level Configure register ops */ | ||
9014 | /* n = 0 ~ 31 */ | ||
9015 | #define __tve_set_front_porch(n) \ | ||
9016 | do {\ | ||
9017 | REG_TVE_LTCFG1 &= ~TVE_LTCFG1_FRONTP_MASK;\ | ||
9018 | REG_TVE_LTCFG1 |= (n) << TVE_LTCFG1_FRONTP_BIT; \ | ||
9019 | } while(0) | ||
9020 | /* n = 0 ~ 127 */ | ||
9021 | #define __tve_set_hsync_width(n) \ | ||
9022 | do {\ | ||
9023 | REG_TVE_LTCFG1 &= ~TVE_LTCFG1_HSYNCW_MASK;\ | ||
9024 | REG_TVE_LTCFG1 |= (n) << TVE_LTCFG1_HSYNCW_BIT; \ | ||
9025 | } while(0) | ||
9026 | /* n = 0 ~ 127 */ | ||
9027 | #define __tve_set_back_porch(n) \ | ||
9028 | do {\ | ||
9029 | REG_TVE_LTCFG1 &= ~TVE_LTCFG1_BACKP_MASK;\ | ||
9030 | REG_TVE_LTCFG1 |= (n) << TVE_LTCFG1_BACKP_BIT; \ | ||
9031 | } while(0) | ||
9032 | /* n = 0 ~ 2047 */ | ||
9033 | #define __tve_set_active_linec(n) \ | ||
9034 | do {\ | ||
9035 | REG_TVE_LTCFG2 &= ~TVE_LTCFG2_ACTLIN_MASK;\ | ||
9036 | REG_TVE_LTCFG2 |= (n) << TVE_LTCFG2_ACTLIN_BIT; \ | ||
9037 | } while(0) | ||
9038 | /* n = 0 ~ 31 */ | ||
9039 | #define __tve_set_breezy_way(n) \ | ||
9040 | do {\ | ||
9041 | REG_TVE_LTCFG2 &= ~TVE_LTCFG2_PREBW_MASK;\ | ||
9042 | REG_TVE_LTCFG2 |= (n) << TVE_LTCFG2_PREBW_BIT; \ | ||
9043 | } while(0) | ||
9044 | |||
9045 | /* n = 0 ~ 127 */ | ||
9046 | #define __tve_set_burst_width(n) \ | ||
9047 | do {\ | ||
9048 | REG_TVE_LTCFG2 &= ~TVE_LTCFG2_BURSTW_MASK;\ | ||
9049 | REG_TVE_LTCFG2 |= (n) << TVE_LTCFG2_BURSTW_BIT; \ | ||
9050 | } while(0) | ||
9051 | |||
9052 | /* TV Encoder Chrominance filter and Modulation register ops */ | ||
9053 | /* n = 0 ~ (2^32-1) */ | ||
9054 | #define __tve_set_c_sub_carrier_freq(n) REG_TVE_CFREQ = (n) | ||
9055 | /* n = 0 ~ 255 */ | ||
9056 | #define __tve_set_c_sub_carrier_init_phase(n) \ | ||
9057 | do { \ | ||
9058 | REG_TVE_CPHASE &= ~TVE_CPHASE_INITPH_MASK; \ | ||
9059 | REG_TVE_CPHASE |= (n) << TVE_CPHASE_INITPH_BIT; \ | ||
9060 | } while(0) | ||
9061 | /* n = 0 ~ 255 */ | ||
9062 | #define __tve_set_c_sub_carrier_act_phase(n) \ | ||
9063 | do { \ | ||
9064 | REG_TVE_CPHASE &= ~TVE_CPHASE_ACTPH_MASK; \ | ||
9065 | REG_TVE_CPHASE |= (n) << TVE_CPHASE_ACTPH_BIT; \ | ||
9066 | } while(0) | ||
9067 | /* n = 0 ~ 255 */ | ||
9068 | #define __tve_set_c_phase_rst_period(n) \ | ||
9069 | do { \ | ||
9070 | REG_TVE_CPHASE &= ~TVE_CPHASE_CCRSTP_MASK; \ | ||
9071 | REG_TVE_CPHASE |= (n) << TVE_CPHASE_CCRSTP_BIT; \ | ||
9072 | } while(0) | ||
9073 | /* n = 0 ~ 255 */ | ||
9074 | #define __tve_set_cb_burst_amp(n) \ | ||
9075 | do { \ | ||
9076 | REG_TVE_CBCRCFG &= ~TVE_CBCRCFG_CBBA_MASK; \ | ||
9077 | REG_TVE_CBCRCFG |= (n) << TVE_CBCRCFG_CBBA_BIT; \ | ||
9078 | } while(0) | ||
9079 | /* n = 0 ~ 255 */ | ||
9080 | #define __tve_set_cr_burst_amp(n) \ | ||
9081 | do { \ | ||
9082 | REG_TVE_CBCRCFG &= ~TVE_CBCRCFG_CRBA_MASK; \ | ||
9083 | REG_TVE_CBCRCFG |= (n) << TVE_CBCRCFG_CRBA_BIT; \ | ||
9084 | } while(0) | ||
9085 | /* n = 0 ~ 255 */ | ||
9086 | #define __tve_set_cb_gain_amp(n) \ | ||
9087 | do { \ | ||
9088 | REG_TVE_CBCRCFG &= ~TVE_CBCRCFG_CBGAIN_MASK; \ | ||
9089 | REG_TVE_CBCRCFG |= (n) << TVE_CBCRCFG_CBGAIN_BIT; \ | ||
9090 | } while(0) | ||
9091 | /* n = 0 ~ 255 */ | ||
9092 | #define __tve_set_cr_gain_amp(n) \ | ||
9093 | do { \ | ||
9094 | REG_TVE_CBCRCFG &= ~TVE_CBCRCFG_CRGAIN_MASK; \ | ||
9095 | REG_TVE_CBCRCFG |= (n) << TVE_CBCRCFG_CRGAIN_BIT; \ | ||
9096 | } while(0) | ||
9097 | |||
9098 | /* TV Encoder Wide Screen Signal Control register ops */ | ||
9099 | /* n = 0 ~ 7 */ | ||
9100 | #define __tve_set_notch_freq(n) \ | ||
9101 | do { \ | ||
9102 | REG_TVE_WSSCR &= ~TVE_WSSCR_NCHFREQ_MASK; \ | ||
9103 | REG_TVE_WSSCR |= (n) << TVE_WSSCR_NCHFREQ_BIT; \ | ||
9104 | } while(0) | ||
9105 | /* n = 0 ~ 7 */ | ||
9106 | #define __tve_set_notch_width() (REG_TVE_WSSCR |= TVE_WSSCR_NCHW_BIT) | ||
9107 | #define __tve_clear_notch_width() (REG_TVE_WSSCR &= ~TVE_WSSCR_NCHW_BIT) | ||
9108 | #define __tve_enable_notch() (REG_TVE_WSSCR |= TVE_WSSCR_ENCH_BIT) | ||
9109 | #define __tve_disable_notch() (REG_TVE_WSSCR &= ~TVE_WSSCR_ENCH_BIT) | ||
9110 | /* n = 0 ~ 7 */ | ||
9111 | #define __tve_set_wss_edge(n) \ | ||
9112 | do { \ | ||
9113 | REG_TVE_WSSCR &= ~TVE_WSSCR_WSSEDGE_MASK; \ | ||
9114 | REG_TVE_WSSCR |= (n) << TVE_WSSCR_WSSEDGE_BIT; \ | ||
9115 | } while(0) | ||
9116 | #define __tve_set_wss_clkbyp() (REG_TVE_WSSCR |= TVE_WSSCR_WSSCKBP_BIT) | ||
9117 | #define __tve_set_wss_type() (REG_TVE_WSSCR |= TVE_WSSCR_WSSTP_BIT) | ||
9118 | #define __tve_enable_wssf1() (REG_TVE_WSSCR |= TVE_WSSCR_EWSS1_BIT) | ||
9119 | #define __tve_enable_wssf0() (REG_TVE_WSSCR |= TVE_WSSCR_EWSS0_BIT) | ||
9120 | |||
9121 | /* TV Encoder Wide Screen Signal Configure register 1, 2 and 3 ops */ | ||
9122 | /* n = 0 ~ 1023 */ | ||
9123 | #define __tve_set_wss_level(n) \ | ||
9124 | do { \ | ||
9125 | REG_TVE_WSSCFG1 &= ~TVE_WSSCFG1_WSSL_MASK; \ | ||
9126 | REG_TVE_WSSCFG1 |= (n) << TVE_WSSCFG1_WSSL_BIT; \ | ||
9127 | } while(0) | ||
9128 | /* n = 0 ~ 4095 */ | ||
9129 | #define __tve_set_wss_freq(n) \ | ||
9130 | do { \ | ||
9131 | REG_TVE_WSSCFG1 &= ~TVE_WSSCFG1_WSSFREQ_MASK; \ | ||
9132 | REG_TVE_WSSCFG1 |= (n) << TVE_WSSCFG1_WSSFREQ_BIT; \ | ||
9133 | } while(0) | ||
9134 | /* n = 0, 1; l = 0 ~ 255 */ | ||
9135 | #define __tve_set_wss_line(n,v) \ | ||
9136 | do { \ | ||
9137 | REG_TVE_WSSCFG##n &= ~TVE_WSSCFG_WSSLINE_MASK; \ | ||
9138 | REG_TVE_WSSCFG##n |= (v) << TVE_WSSCFG_WSSLINE_BIT; \ | ||
9139 | } while(0) | ||
9140 | /* n = 0, 1; d = 0 ~ (2^20-1) */ | ||
9141 | #define __tve_set_wss_data(n, v) \ | ||
9142 | do { \ | ||
9143 | REG_TVE_WSSCFG##n &= ~TVE_WSSCFG_WSSLINE_MASK; \ | ||
9144 | REG_TVE_WSSCFG##n |= (v) << TVE_WSSCFG_WSSLINE_BIT; \ | ||
9145 | } while(0) | ||
9146 | |||
9147 | #endif /* __MIPS_ASSEMBLER */ | ||
9148 | |||
9149 | #define UART0_BASE 0xB0030000 | ||
9150 | #define UART1_BASE 0xB0031000 | ||
9151 | #define UART2_BASE 0xB0032000 | ||
9152 | #define UART3_BASE 0xB0033000 | ||
9153 | |||
9154 | /************************************************************************* | ||
9155 | * UART | ||
9156 | *************************************************************************/ | ||
9157 | |||
9158 | #define IRDA_BASE UART0_BASE | ||
9159 | #define UART_BASE UART0_BASE | ||
9160 | #define UART_OFF 0x1000 | ||
9161 | |||
9162 | /* Register Offset */ | ||
9163 | #define OFF_RDR (0x00) /* R 8b H'xx */ | ||
9164 | #define OFF_TDR (0x00) /* W 8b H'xx */ | ||
9165 | #define OFF_DLLR (0x00) /* RW 8b H'00 */ | ||
9166 | #define OFF_DLHR (0x04) /* RW 8b H'00 */ | ||
9167 | #define OFF_IER (0x04) /* RW 8b H'00 */ | ||
9168 | #define OFF_ISR (0x08) /* R 8b H'01 */ | ||
9169 | #define OFF_FCR (0x08) /* W 8b H'00 */ | ||
9170 | #define OFF_LCR (0x0C) /* RW 8b H'00 */ | ||
9171 | #define OFF_MCR (0x10) /* RW 8b H'00 */ | ||
9172 | #define OFF_LSR (0x14) /* R 8b H'00 */ | ||
9173 | #define OFF_MSR (0x18) /* R 8b H'00 */ | ||
9174 | #define OFF_SPR (0x1C) /* RW 8b H'00 */ | ||
9175 | #define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */ | ||
9176 | #define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */ | ||
9177 | #define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */ | ||
9178 | |||
9179 | /* Register Address */ | ||
9180 | #define UART0_RDR (UART0_BASE + OFF_RDR) | ||
9181 | #define UART0_TDR (UART0_BASE + OFF_TDR) | ||
9182 | #define UART0_DLLR (UART0_BASE + OFF_DLLR) | ||
9183 | #define UART0_DLHR (UART0_BASE + OFF_DLHR) | ||
9184 | #define UART0_IER (UART0_BASE + OFF_IER) | ||
9185 | #define UART0_ISR (UART0_BASE + OFF_ISR) | ||
9186 | #define UART0_FCR (UART0_BASE + OFF_FCR) | ||
9187 | #define UART0_LCR (UART0_BASE + OFF_LCR) | ||
9188 | #define UART0_MCR (UART0_BASE + OFF_MCR) | ||
9189 | #define UART0_LSR (UART0_BASE + OFF_LSR) | ||
9190 | #define UART0_MSR (UART0_BASE + OFF_MSR) | ||
9191 | #define UART0_SPR (UART0_BASE + OFF_SPR) | ||
9192 | #define UART0_SIRCR (UART0_BASE + OFF_SIRCR) | ||
9193 | #define UART0_UMR (UART0_BASE + OFF_UMR) | ||
9194 | #define UART0_UACR (UART0_BASE + OFF_UACR) | ||
9195 | |||
9196 | #define UART1_RDR (UART1_BASE + OFF_RDR) | ||
9197 | #define UART1_TDR (UART1_BASE + OFF_TDR) | ||
9198 | #define UART1_DLLR (UART1_BASE + OFF_DLLR) | ||
9199 | #define UART1_DLHR (UART1_BASE + OFF_DLHR) | ||
9200 | #define UART1_IER (UART1_BASE + OFF_IER) | ||
9201 | #define UART1_ISR (UART1_BASE + OFF_ISR) | ||
9202 | #define UART1_FCR (UART1_BASE + OFF_FCR) | ||
9203 | #define UART1_LCR (UART1_BASE + OFF_LCR) | ||
9204 | #define UART1_MCR (UART1_BASE + OFF_MCR) | ||
9205 | #define UART1_LSR (UART1_BASE + OFF_LSR) | ||
9206 | #define UART1_MSR (UART1_BASE + OFF_MSR) | ||
9207 | #define UART1_SPR (UART1_BASE + OFF_SPR) | ||
9208 | #define UART1_SIRCR (UART1_BASE + OFF_SIRCR) | ||
9209 | |||
9210 | #define UART2_RDR (UART2_BASE + OFF_RDR) | ||
9211 | #define UART2_TDR (UART2_BASE + OFF_TDR) | ||
9212 | #define UART2_DLLR (UART2_BASE + OFF_DLLR) | ||
9213 | #define UART2_DLHR (UART2_BASE + OFF_DLHR) | ||
9214 | #define UART2_IER (UART2_BASE + OFF_IER) | ||
9215 | #define UART2_ISR (UART2_BASE + OFF_ISR) | ||
9216 | #define UART2_FCR (UART2_BASE + OFF_FCR) | ||
9217 | #define UART2_LCR (UART2_BASE + OFF_LCR) | ||
9218 | #define UART2_MCR (UART2_BASE + OFF_MCR) | ||
9219 | #define UART2_LSR (UART2_BASE + OFF_LSR) | ||
9220 | #define UART2_MSR (UART2_BASE + OFF_MSR) | ||
9221 | #define UART2_SPR (UART2_BASE + OFF_SPR) | ||
9222 | #define UART2_SIRCR (UART2_BASE + OFF_SIRCR) | ||
9223 | |||
9224 | #define UART3_RDR (UART3_BASE + OFF_RDR) | ||
9225 | #define UART3_TDR (UART3_BASE + OFF_TDR) | ||
9226 | #define UART3_DLLR (UART3_BASE + OFF_DLLR) | ||
9227 | #define UART3_DLHR (UART3_BASE + OFF_DLHR) | ||
9228 | #define UART3_IER (UART3_BASE + OFF_IER) | ||
9229 | #define UART3_ISR (UART3_BASE + OFF_ISR) | ||
9230 | #define UART3_FCR (UART3_BASE + OFF_FCR) | ||
9231 | #define UART3_LCR (UART3_BASE + OFF_LCR) | ||
9232 | #define UART3_MCR (UART3_BASE + OFF_MCR) | ||
9233 | #define UART3_LSR (UART3_BASE + OFF_LSR) | ||
9234 | #define UART3_MSR (UART3_BASE + OFF_MSR) | ||
9235 | #define UART3_SPR (UART3_BASE + OFF_SPR) | ||
9236 | #define UART3_SIRCR (UART3_BASE + OFF_SIRCR) | ||
9237 | |||
9238 | /* | ||
9239 | * Define macros for UARTIER | ||
9240 | * UART Interrupt Enable Register | ||
9241 | */ | ||
9242 | #define UARTIER_RIE (1 << 0) /* 0: receive fifo full interrupt disable */ | ||
9243 | #define UARTIER_TIE (1 << 1) /* 0: transmit fifo empty interrupt disable */ | ||
9244 | #define UARTIER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ | ||
9245 | #define UARTIER_MIE (1 << 3) /* 0: modem status interrupt disable */ | ||
9246 | #define UARTIER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ | ||
9247 | |||
9248 | /* | ||
9249 | * Define macros for UARTISR | ||
9250 | * UART Interrupt Status Register | ||
9251 | */ | ||
9252 | #define UARTISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ | ||
9253 | #define UARTISR_IID (7 << 1) /* Source of Interrupt */ | ||
9254 | #define UARTISR_IID_MSI (0 << 1) /* Modem status interrupt */ | ||
9255 | #define UARTISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ | ||
9256 | #define UARTISR_IID_RDI (2 << 1) /* Receiver data interrupt */ | ||
9257 | #define UARTISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ | ||
9258 | #define UARTISR_IID_RTO (6 << 1) /* Receive timeout */ | ||
9259 | #define UARTISR_FFMS (3 << 6) /* FIFO mode select, set when UARTFCR.FE is set to 1 */ | ||
9260 | #define UARTISR_FFMS_NO_FIFO (0 << 6) | ||
9261 | #define UARTISR_FFMS_FIFO_MODE (3 << 6) | ||
9262 | |||
9263 | /* | ||
9264 | * Define macros for UARTFCR | ||
9265 | * UART FIFO Control Register | ||
9266 | */ | ||
9267 | #define UARTFCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ | ||
9268 | #define UARTFCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ | ||
9269 | #define UARTFCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ | ||
9270 | #define UARTFCR_DMS (1 << 3) /* 0: disable DMA mode */ | ||
9271 | #define UARTFCR_UUE (1 << 4) /* 0: disable UART */ | ||
9272 | #define UARTFCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ | ||
9273 | #define UARTFCR_RTRG_1 (0 << 6) | ||
9274 | #define UARTFCR_RTRG_4 (1 << 6) | ||
9275 | #define UARTFCR_RTRG_8 (2 << 6) | ||
9276 | #define UARTFCR_RTRG_15 (3 << 6) | ||
9277 | |||
9278 | /* | ||
9279 | * Define macros for UARTLCR | ||
9280 | * UART Line Control Register | ||
9281 | */ | ||
9282 | #define UARTLCR_WLEN (3 << 0) /* word length */ | ||
9283 | #define UARTLCR_WLEN_5 (0 << 0) | ||
9284 | #define UARTLCR_WLEN_6 (1 << 0) | ||
9285 | #define UARTLCR_WLEN_7 (2 << 0) | ||
9286 | #define UARTLCR_WLEN_8 (3 << 0) | ||
9287 | #define UARTLCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 | ||
9288 | 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ | ||
9289 | #define UARTLCR_STOP1 (0 << 2) | ||
9290 | #define UARTLCR_STOP2 (1 << 2) | ||
9291 | #define UARTLCR_PE (1 << 3) /* 0: parity disable */ | ||
9292 | #define UARTLCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ | ||
9293 | #define UARTLCR_SPAR (1 << 5) /* 0: sticky parity disable */ | ||
9294 | #define UARTLCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ | ||
9295 | #define UARTLCR_DLAB (1 << 7) /* 0: access UARTRDR/TDR/IER 1: access UARTDLLR/DLHR */ | ||
9296 | |||
9297 | /* | ||
9298 | * Define macros for UARTLSR | ||
9299 | * UART Line Status Register | ||
9300 | */ | ||
9301 | #define UARTLSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */ | ||
9302 | #define UARTLSR_ORER (1 << 1) /* 0: no overrun error */ | ||
9303 | #define UARTLSR_PER (1 << 2) /* 0: no parity error */ | ||
9304 | #define UARTLSR_FER (1 << 3) /* 0; no framing error */ | ||
9305 | #define UARTLSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */ | ||
9306 | #define UARTLSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */ | ||
9307 | #define UARTLSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */ | ||
9308 | #define UARTLSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */ | ||
9309 | |||
9310 | /* | ||
9311 | * Define macros for UARTMCR | ||
9312 | * UART Modem Control Register | ||
9313 | */ | ||
9314 | #define UARTMCR_RTS (1 << 1) /* 0: RTS_ output high, 1: RTS_ output low */ | ||
9315 | #define UARTMCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ | ||
9316 | #define UARTMCR_FCM (1 << 6) /* 0: software 1: hardware */ | ||
9317 | #define UARTMCR_MCE (1 << 7) /* 0: modem function is disable */ | ||
9318 | |||
9319 | /* | ||
9320 | * Define macros for UARTMSR | ||
9321 | * UART Modem Status Register | ||
9322 | */ | ||
9323 | #define UARTMSR_CCTS (1 << 0) /* 1: a change on CTS_ pin */ | ||
9324 | #define UARTMSR_CTS (1 << 4) /* 0: CTS_ pin is high */ | ||
9325 | |||
9326 | /* | ||
9327 | * Define macros for SIRCR | ||
9328 | * Slow IrDA Control Register | ||
9329 | */ | ||
9330 | #define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: SIR mode */ | ||
9331 | #define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: SIR mode */ | ||
9332 | #define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length | ||
9333 | 1: 0 pulse width is 1.6us for 115.2Kbps */ | ||
9334 | #define SIRCR_TDPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ | ||
9335 | #define SIRCR_RDPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ | ||
9336 | |||
9337 | #ifndef __MIPS_ASSEMBLER | ||
9338 | |||
9339 | /*************************************************************************** | ||
9340 | * UART | ||
9341 | ***************************************************************************/ | ||
9342 | #define __jtag_as_uart3() \ | ||
9343 | do { \ | ||
9344 | REG_GPIO_PXSELC(0) = 0x40000000; \ | ||
9345 | REG_GPIO_PXSELS(0) = 0x80000000; \ | ||
9346 | } while(0) | ||
9347 | |||
9348 | #define __uart_enable(n) \ | ||
9349 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) |= UARTFCR_UUE | UARTFCR_FE ) | ||
9350 | #define __uart_disable(n) \ | ||
9351 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = ~UARTFCR_UUE ) | ||
9352 | |||
9353 | #define __uart_enable_transmit_irq(n) \ | ||
9354 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_TIE ) | ||
9355 | #define __uart_disable_transmit_irq(n) \ | ||
9356 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~UARTIER_TIE ) | ||
9357 | |||
9358 | #define __uart_enable_receive_irq(n) \ | ||
9359 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE ) | ||
9360 | #define __uart_disable_receive_irq(n) \ | ||
9361 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) ) | ||
9362 | |||
9363 | #define __uart_enable_loopback(n) \ | ||
9364 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) |= UARTMCR_LOOP ) | ||
9365 | #define __uart_disable_loopback(n) \ | ||
9366 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) &= ~UARTMCR_LOOP ) | ||
9367 | |||
9368 | #define __uart_set_8n1(n) \ | ||
9369 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) = UARTLCR_WLEN_8 ) | ||
9370 | |||
9371 | #define __uart_set_baud(n, devclk, baud) \ | ||
9372 | do { \ | ||
9373 | REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) |= UARTLCR_DLAB; \ | ||
9374 | REG8(UART_BASE + UART_OFF*(n) + OFF_DLLR) = (devclk / 16 / baud) & 0xff; \ | ||
9375 | REG8(UART_BASE + UART_OFF*(n) + OFF_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \ | ||
9376 | REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) &= ~UARTLCR_DLAB; \ | ||
9377 | } while (0) | ||
9378 | |||
9379 | #define __uart_parity_error(n) \ | ||
9380 | ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_PER) != 0 ) | ||
9381 | |||
9382 | #define __uart_clear_errors(n) \ | ||
9383 | ( REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) ) | ||
9384 | |||
9385 | #define __uart_transmit_fifo_empty(n) \ | ||
9386 | ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TDRQ) != 0 ) | ||
9387 | |||
9388 | #define __uart_transmit_end(n) \ | ||
9389 | ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TEMT) != 0 ) | ||
9390 | |||
9391 | #define __uart_transmit_char(n, ch) \ | ||
9392 | REG8(UART_BASE + UART_OFF*(n) + OFF_TDR) = (ch) | ||
9393 | |||
9394 | #define __uart_receive_fifo_full(n) \ | ||
9395 | ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 ) | ||
9396 | |||
9397 | #define __uart_receive_ready(n) \ | ||
9398 | ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 ) | ||
9399 | |||
9400 | #define __uart_receive_char(n) \ | ||
9401 | REG8(UART_BASE + UART_OFF*(n) + OFF_RDR) | ||
9402 | |||
9403 | #define __uart_disable_irda() \ | ||
9404 | ( REG8(IRDA_BASE + OFF_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) ) | ||
9405 | #define __uart_enable_irda() \ | ||
9406 | /* Tx high pulse as 0, Rx low pulse as 0 */ \ | ||
9407 | ( REG8(IRDA_BASE + OFF_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS ) | ||
9408 | |||
9409 | #endif /* __MIPS_ASSEMBLER */ | ||
9410 | |||
9411 | /* | ||
9412 | * Watchdog timer module(WDT) address definition | ||
9413 | */ | ||
9414 | #define WDT_BASE 0xb0002000 | ||
9415 | |||
9416 | /* | ||
9417 | * WDT registers offset address definition | ||
9418 | */ | ||
9419 | #define WDT_WDR_OFFSET (0x00) /* rw, 16, 0x???? */ | ||
9420 | #define WDT_WCER_OFFSET (0x04) /* rw, 8, 0x00 */ | ||
9421 | #define WDT_WCNT_OFFSET (0x08) /* rw, 16, 0x???? */ | ||
9422 | #define WDT_WCSR_OFFSET (0x0c) /* rw, 16, 0x0000 */ | ||
9423 | |||
9424 | /* | ||
9425 | * WDT registers address definition | ||
9426 | */ | ||
9427 | #define WDT_WDR (WDT_BASE + WDT_WDR_OFFSET) | ||
9428 | #define WDT_WCER (WDT_BASE + WDT_WCER_OFFSET) | ||
9429 | #define WDT_WCNT (WDT_BASE + WDT_WCNT_OFFSET) | ||
9430 | #define WDT_WCSR (WDT_BASE + WDT_WCSR_OFFSET) | ||
9431 | |||
9432 | /* | ||
9433 | * WDT registers common define | ||
9434 | */ | ||
9435 | |||
9436 | /* Watchdog counter enable register(WCER) */ | ||
9437 | #define WCER_TCEN BIT0 | ||
9438 | |||
9439 | /* Watchdog control register(WCSR) */ | ||
9440 | #define WCSR_PRESCALE_LSB 3 | ||
9441 | #define WCSR_PRESCALE_MASK BITS_H2L(5, WCSR_PRESCALE_LSB) | ||
9442 | #define WCSR_PRESCALE1 (0x0 << WCSR_PRESCALE_LSB) | ||
9443 | #define WCSR_PRESCALE4 (0x1 << WCSR_PRESCALE_LSB) | ||
9444 | #define WCSR_PRESCALE16 (0x2 << WCSR_PRESCALE_LSB) | ||
9445 | #define WCSR_PRESCALE64 (0x3 << WCSR_PRESCALE_LSB) | ||
9446 | #define WCSR_PRESCALE256 (0x4 << WCSR_PRESCALE_LSB) | ||
9447 | #define WCSR_PRESCALE1024 (0x5 << WCSR_PRESCALE_LSB) | ||
9448 | |||
9449 | #define WCSR_CLKIN_LSB 0 | ||
9450 | #define WCSR_CLKIN_MASK BITS_H2L(2, WCSR_CLKIN_LSB) | ||
9451 | #define WCSR_CLKIN_PCK (0x1 << WCSR_CLKIN_LSB) | ||
9452 | #define WCSR_CLKIN_RTC (0x2 << WCSR_CLKIN_LSB) | ||
9453 | #define WCSR_CLKIN_EXT (0x4 << WCSR_CLKIN_LSB) | ||
9454 | |||
9455 | #ifndef __MIPS_ASSEMBLER | ||
9456 | |||
9457 | #define REG_WDT_WDR REG16(WDT_WDR) | ||
9458 | #define REG_WDT_WCER REG8(WDT_WCER) | ||
9459 | #define REG_WDT_WCNT REG16(WDT_WCNT) | ||
9460 | #define REG_WDT_WCSR REG16(WDT_WCSR) | ||
9461 | |||
9462 | #endif /* __MIPS_ASSEMBLER */ | ||
9463 | |||
9464 | /* | ||
9465 | * Operating system timer module(OST) address definition | ||
9466 | */ | ||
9467 | #define OST_BASE 0xb0002000 | ||
9468 | |||
9469 | /* | ||
9470 | * OST registers offset address definition | ||
9471 | */ | ||
9472 | #define OST_OSTDR_OFFSET (0xe0) /* rw, 32, 0x???????? */ | ||
9473 | #define OST_OSTCNT_OFFSET (0xe4) /* rw, 32, 0x???????? */ | ||
9474 | #define OST_OSTCNTL_OFFSET (0xe4) /* rw, 32, 0x???????? */ | ||
9475 | #define OST_OSTCNTH_OFFSET (0xe8) /* rw, 32, 0x???????? */ | ||
9476 | #define OST_OSTCSR_OFFSET (0xec) /* rw, 16, 0x0000 */ | ||
9477 | #define OST_OSTCNTHBUF_OFFSET (0xfc) /* r, 32, 0x???????? */ | ||
9478 | |||
9479 | /* | ||
9480 | * OST registers address definition | ||
9481 | */ | ||
9482 | #define OST_OSTDR (OST_BASE + OST_OSTDR_OFFSET) | ||
9483 | #define OST_OSTCNT (OST_BASE + OST_OSTCNT_OFFSET) | ||
9484 | #define OST_OSTCNTL (OST_BASE + OST_OSTCNTL_OFFSET) | ||
9485 | #define OST_OSTCNTH (OST_BASE + OST_OSTCNTH_OFFSET) | ||
9486 | #define OST_OSTCSR (OST_BASE + OST_OSTCSR_OFFSET) | ||
9487 | #define OST_OSTCNTHBUF (OST_BASE + OST_OSTCNTHBUF_OFFSET) | ||
9488 | |||
9489 | /* | ||
9490 | * OST registers common define | ||
9491 | */ | ||
9492 | |||
9493 | /* Operating system control register(OSTCSR) */ | ||
9494 | #define OSTCSR_CNT_MD BIT15 | ||
9495 | #define OSTCSR_SD BIT9 | ||
9496 | #define OSTCSR_EXT_EN BIT2 | ||
9497 | #define OSTCSR_RTC_EN BIT1 | ||
9498 | #define OSTCSR_PCK_EN BIT0 | ||
9499 | |||
9500 | #define OSTCSR_PRESCALE_LSB 3 | ||
9501 | #define OSTCSR_PRESCALE_MASK BITS_H2L(5, OSTCSR_PRESCALE_LSB) | ||
9502 | #define OSTCSR_PRESCALE1 (0x0 << OSTCSR_PRESCALE_LSB) | ||
9503 | #define OSTCSR_PRESCALE4 (0x1 << OSTCSR_PRESCALE_LSB) | ||
9504 | #define OSTCSR_PRESCALE16 (0x2 << OSTCSR_PRESCALE_LSB) | ||
9505 | #define OSTCSR_PRESCALE64 (0x3 << OSTCSR_PRESCALE_LSB) | ||
9506 | #define OSTCSR_PRESCALE256 (0x4 << OSTCSR_PRESCALE_LSB) | ||
9507 | #define OSTCSR_PRESCALE1024 (0x5 << OSTCSR_PRESCALE_LSB) | ||
9508 | |||
9509 | #ifndef __MIPS_ASSEMBLER | ||
9510 | |||
9511 | #define REG_OST_OSTDR REG32(OST_OSTDR) | ||
9512 | #define REG_OST_OSTCNT REG32(OST_OSTCNT) | ||
9513 | #define REG_OST_OSTCNTL REG32(OST_OSTCNTL) | ||
9514 | #define REG_OST_OSTCNTH REG32(OST_OSTCNTH) | ||
9515 | #define REG_OST_OSTCSR REG16(OST_OSTCSR) | ||
9516 | #define REG_OST_OSTCNTHBUF REG32(OST_OSTCNTHBUF) | ||
9517 | |||
9518 | #endif /* __MIPS_ASSEMBLER */ | ||
9519 | |||
9520 | #define AOSD_BASE 0xB3070000 | ||
9521 | |||
9522 | /************************************************************************* | ||
9523 | * OSD (On Screen Display) | ||
9524 | *************************************************************************/ | ||
9525 | #define AOSD_ADDR0 (AOSD_BASE + 0x00) | ||
9526 | #define AOSD_ADDR1 (AOSD_BASE + 0x04) | ||
9527 | #define AOSD_ADDR2 (AOSD_BASE + 0x08) | ||
9528 | #define AOSD_ADDR3 (AOSD_BASE + 0x0C) | ||
9529 | #define AOSD_WADDR (AOSD_BASE + 0x10) | ||
9530 | #define AOSD_ADDRLEN (AOSD_BASE + 0x14) | ||
9531 | #define AOSD_ALPHA_VALUE (AOSD_BASE + 0x18) | ||
9532 | #define AOSD_CTRL (AOSD_BASE + 0x1C) | ||
9533 | #define AOSD_INT (AOSD_BASE + 0x20) | ||
9534 | |||
9535 | #define REG_AOSD_ADDR0 REG32(AOSD_ADDR0) | ||
9536 | #define REG_AOSD_ADDR1 REG32(AOSD_ADDR1) | ||
9537 | #define REG_AOSD_ADDR2 REG32(AOSD_ADDR2) | ||
9538 | #define REG_AOSD_ADDR3 REG32(AOSD_ADDR3) | ||
9539 | #define REG_AOSD_WADDR REG32(AOSD_WADDR) | ||
9540 | #define REG_AOSD_ADDRLEN REG32(AOSD_ADDRLEN) | ||
9541 | #define REG_AOSD_ALPHA_VALUE REG32(AOSD_ALPHA_VALUE) | ||
9542 | #define REG_AOSD_CTRL REG32(AOSD_CTRL) | ||
9543 | #define REG_AOSD_INT REG32(AOSD_INT) | ||
9544 | |||
9545 | #define AOSD_CTRL_FRMLV_MASK (0x3 << 18) | ||
9546 | #define AOSD_CTRL_FRMLV_2 (0x1 << 18) | ||
9547 | #define AOSD_CTRL_FRMLV_3 (0x2 << 18) | ||
9548 | #define AOSD_CTRL_FRMLV_4 (0x3 << 18) | ||
9549 | |||
9550 | #define AOSD_CTRL_FRM_END (1 << 17) | ||
9551 | #define AOSD_CTRL_ALPHA_START (1 << 16) | ||
9552 | #define AOSD_CTRL_INT_MAKS (1 << 15) | ||
9553 | #define AOSD_CTRL_CHANNEL_LEVEL_BIT 7 | ||
9554 | #define AOSD_CTRL_CHANNEL_LEVEL_MASK (0xff << AOSD_CTRL_CHANNEL_LEVEL_BIT) | ||
9555 | #define AOSD_CTRL_ALPHA_MODE_BIT 3 | ||
9556 | #define AOSD_CTRL_ALPHA_MODE_MASK (0xf << AOSD_CTRL_ALPHA_MODE_BIT) | ||
9557 | #define AOSD_CTRL_ALPHA_PIXEL_MODE 0 | ||
9558 | #define AOSD_CTRL_ALPHA_FRAME_MODE 1 | ||
9559 | |||
9560 | #define AOSD_CTRL_FORMAT_MODE_BIT 1 | ||
9561 | #define AOSD_CTRL_FORMAT_MODE_MASK (0x3 << 1) | ||
9562 | #define AOSD_CTRL_RGB565_FORMAT_MODE (0 << AOSD_CTRL_FORMAT_MODE_BIT) | ||
9563 | #define AOSD_CTRL_RGB555_FORMAT_MODE (1 << AOSD_CTRL_FORMAT_MODE_BIT) | ||
9564 | #define AOSD_CTRL_RGB8888_FORMAT_MODE (2 << AOSD_CTRL_FORMAT_MODE_BIT) | ||
9565 | |||
9566 | #define AOSD_ALPHA_ENABLE (1 << 0) | ||
9567 | |||
9568 | #define AOSD_INT_COMPRESS_END (1 << 1) | ||
9569 | #define AOSD_INT_AOSD_END (1 << 0) | ||
9570 | |||
9571 | #define __osd_enable_alpha() (REG_AOSD_CTRL |= AOSD_ALPHA_ENABLE) | ||
9572 | #define __osd_alpha_start() (REG_AOSD_CTRL |= AOSD_CTRL_ALPHA_START) | ||
9573 | |||
9574 | /************************************************************************* | ||
9575 | * COMPRESS | ||
9576 | *************************************************************************/ | ||
9577 | #define COMPRESS_SCR_ADDR (AOSD_BASE + 0x00) | ||
9578 | #define COMPRESS_DES_ADDR (AOSD_BASE + 0x10) | ||
9579 | #define COMPRESS_DST_OFFSET (AOSD_BASE + 0x34) | ||
9580 | #define COMPRESS_FRAME_SIZE (AOSD_BASE + 0x38) | ||
9581 | #define COMPRESS_CTRL (AOSD_BASE + 0x3C) | ||
9582 | #define COMPRESS_RATIO (AOSD_BASE + 0x40) | ||
9583 | #define COMPRESS_SRC_OFFSET (AOSD_BASE + 0x44) | ||
9584 | |||
9585 | #define REG_COMPRESS_SCR_ADDR REG32(COMPRESS_SCR_ADDR) | ||
9586 | #define REG_COMPRESS_DES_ADDR REG32(COMPRESS_DES_ADDR) | ||
9587 | #define REG_COMPRESS_DST_OFFSET REG32(COMPRESS_DST_OFFSET) | ||
9588 | #define REG_COMPRESS_FRAME_SIZE REG32(COMPRESS_FRAME_SIZE) | ||
9589 | #define REG_COMPRESS_CTRL REG32(COMPRESS_CTRL) | ||
9590 | #define REG_COMPRESS_RATIO REG32(COMPRESS_RATIO) | ||
9591 | #define REG_COMPRESS_SRC_OFFSET REG32(COMPRESS_SRC_OFFSET) | ||
9592 | |||
9593 | #define COMPRESS_CTRL_WITHOUT_ALPHA (1 << 4) | ||
9594 | #define COMPRESS_CTRL_WITH_ALPHA (0 << 4) | ||
9595 | #define COMPRESS_CTRL_COMP_START (1 << 3) | ||
9596 | #define COMPRESS_CTRL_COMP_END (1 << 2) | ||
9597 | #define COMPRESS_CTRL_INT_MASK (1 << 1) | ||
9598 | #define COMPRESS_CTRL_COMP_ENABLE (1 << 0) | ||
9599 | |||
9600 | #define COMPRESS_RATIO_FRM_BYPASS (1 << 31) | ||
9601 | #define COMPRESS_BYPASS_ROW (1 << 12) | ||
9602 | #define COMPRESS_ROW_QUARTER (1 << 0) | ||
9603 | |||
9604 | #define COMPRESS_CTRL_ALIGNED_MODE_BIT (31) | ||
9605 | #define COMPRESS_CTRL_ALIGNED_16_WORD (0 << COMPRESS_CTRL_ALIGNED_MODE_BIT) | ||
9606 | #define COMPRESS_CTRL_ALIGNED_64_WORD (1 << COMPRESS_CTRL_ALIGNED_MODE_BIT) | ||
9607 | |||
9608 | #define __compress_enable() (REG_COMPRESS_CTRL |= COMPRESS_INT_AOSD_END) | ||
9609 | #define __compress_start() (REG_COMPRESS_CTRL |= COMPRESS_CTRL_COMP_START) | ||
9610 | #define __compress_with_alpha() (REG_COMPRESS_CTRL |= COMPRESS_CTRL_ALPHA_EN) | ||
9611 | |||
9612 | #endif /* __JZ4760B_H__ */ | ||
9613 | |||