diff options
Diffstat (limited to 'utils/atj2137/adfuload/test_binary')
7 files changed, 3764 insertions, 0 deletions
diff --git a/utils/atj2137/adfuload/test_binary/timer_no_irq/Makefile b/utils/atj2137/adfuload/test_binary/timer_no_irq/Makefile new file mode 100644 index 0000000000..f3bd76686b --- /dev/null +++ b/utils/atj2137/adfuload/test_binary/timer_no_irq/Makefile | |||
@@ -0,0 +1,40 @@ | |||
1 | |||
2 | TARGET = test_timer_noirq | ||
3 | |||
4 | TOOLCHAIN = mipsel-elf- | ||
5 | |||
6 | CC = $(TOOLCHAIN)gcc | ||
7 | CPP = $(TOOLCHAIN)cpp | ||
8 | LD = $(TOOLCHAIN)gcc | ||
9 | AS = $(TOOLCHAIN)as | ||
10 | OBJCOPY = $(TOOLCHAIN)objcopy | ||
11 | OBJDUMP = $(TOOLCHAIN)objdump | ||
12 | |||
13 | CFLAGS = -Wundef -march=4kec -nostdlib -Os -c | ||
14 | |||
15 | OBJS = crt0.o test_timer_noirq.o | ||
16 | LDSCRIPT= test.lds | ||
17 | |||
18 | LDFLAGS = -Wundef -march=4kec -T$(LDSCRIPT) -nostartfiles \ | ||
19 | -nostdlib -Xlinker -Map=$(TARGET).map | ||
20 | |||
21 | all : $(TARGET).bin | ||
22 | ls -ls $(TARGET).bin | ||
23 | |||
24 | %.o : %.c | ||
25 | $(CC) $(CPPFLAGS) $(CFLAGS) $(INCDIRS) $< -o $@ | ||
26 | |||
27 | %.o : %.S | ||
28 | $(CC) $(CFLAGS) -c $< -o $@ | ||
29 | |||
30 | $(TARGET).elf : $(OBJS) | ||
31 | $(LD) $(LDFLAGS) $(OBJS) $(LIBDIRS) $(LIBS) -o $(TARGET).elf | ||
32 | |||
33 | $(TARGET).bin : $(TARGET).elf | ||
34 | $(OBJCOPY) -O binary $(TARGET).elf $(TARGET).bin | ||
35 | |||
36 | clean : | ||
37 | rm -f $(OBJS) | ||
38 | rm -f $(TARGET).elf | ||
39 | rm -f $(TARGET).bin | ||
40 | rm -f $(TARGET).map | ||
diff --git a/utils/atj2137/adfuload/test_binary/timer_no_irq/atj213x.h b/utils/atj2137/adfuload/test_binary/timer_no_irq/atj213x.h new file mode 100644 index 0000000000..46f537e39d --- /dev/null +++ b/utils/atj2137/adfuload/test_binary/timer_no_irq/atj213x.h | |||
@@ -0,0 +1,383 @@ | |||
1 | typedef unsigned int uint32_t; | ||
2 | |||
3 | #define PMU_BASE 0xB0000000 | ||
4 | #define PMU_CTL (*(volatile uint32_t *)(PMU_BASE + 0x00)) | ||
5 | #define PMU_CTL_BL_EN (1<<15) | ||
6 | #define PMU_LRADC (*(volatile uint32_t *)(PMU_BASE + 0x04)) | ||
7 | #define PMU_CHG (*(volatile uint32_t *)(PMU_BASE + 0x08)) | ||
8 | #define PMU_CHG_PBLS (1<<15) | ||
9 | #define PMU_CHG_PBLS_PWM (1<<15) | ||
10 | #define PMU_CHG_PBLS_BL_NDR (0<<15) | ||
11 | #define PMU_CHG_PPHS (1<<14) | ||
12 | #define PMU_CHG_PPHS_HIGH (1<<14) | ||
13 | #define PMU_CHG_PPHS_LOW (0<<14) | ||
14 | #define PMU_CHG_PDUT(x) (((x) & 0x1f) << 8) | ||
15 | #define PMU_CHG_PDOUT_MASK (0x1f << 8) | ||
16 | |||
17 | #define CMU_BASE 0xB0010000 | ||
18 | #define CMU_COREPLL (*(volatile uint32_t *)(CMU_BASE + 0x00)) | ||
19 | #define CMU_DSPPLL (*(volatile uint32_t *)(CMU_BASE + 0x04)) | ||
20 | #define CMU_AUDIOPLL (*(volatile uint32_t *)(CMU_BASE + 0x08)) | ||
21 | #define CMU_BUSCLK (*(volatile uint32_t *)(CMU_BASE + 0x0C)) | ||
22 | #define CMU_SDRCLK (*(volatile uint32_t *)(CMU_BASE + 0x10)) | ||
23 | #define CMU_ATACLK (*(volatile uint32_t *)(CMU_BASE + 0x04)) | ||
24 | #define CMU_NANDCLK (*(volatile uint32_t *)(CMU_BASE + 0x18)) | ||
25 | #define CMU_SDCLK (*(volatile uint32_t *)(CMU_BASE + 0x1C)) | ||
26 | #define CMU_MHACLK (*(volatile uint32_t *)(CMU_BASE + 0x20)) | ||
27 | #define CMU_BTCLK (*(volatile uint32_t *)(CMU_BASE + 0x24)) | ||
28 | #define CMU_IRCLK (*(volatile uint32_t *)(CMU_BASE + 0x28)) | ||
29 | #define CMU_UART2CLK (*(volatile uint32_t *)(CMU_BASE + 0x2C)) | ||
30 | #define CMU_DMACLK (*(volatile uint32_t *)(CMU_BASE + 0x30)) | ||
31 | #define CMU_FMCLK (*(volatile uint32_t *)(CMU_BASE + 0x34)) | ||
32 | #define CMU_FMCLK_BCKE (1<<5) | ||
33 | #define CMI_FMCLK_BCKS (1<<4) | ||
34 | #define CMU_FMCLK_BCKS_32K (0<<4) | ||
35 | #define CMU_FMCLK_BCKS_3M (1<<4) | ||
36 | |||
37 | #define CMU_FMCLK_BCLK_MASK (CMI_FMCLK_BCKS | (3<<2)) | ||
38 | #define CMU_FMCLK_BCLK_3M (CMU_FMCLK_BCKS_3M | (0<<2)) | ||
39 | #define CMU_FMCLK_BCLK_1_5M (CMU_FMCLK_BCKS_3M | (1<<2)) | ||
40 | #define CMU_FMCLK_BCLK_750K (CMU_FMCLK_BCKS_3M | (2<<2)) | ||
41 | #define CMU_FMCLK_BCLK_375K (CMU_FMCLK_BCKS_3M | (3<<2)) | ||
42 | |||
43 | #define CMU_FMCLK_BCLK_32K (0<<2) | ||
44 | #define CMU_FMCLK_BCLK_16K (1<<2) | ||
45 | #define CMU_FMCLK_BCLK_8K (2<<2) | ||
46 | #define CMU_FMCLK_BCLK_4K (3<<2) | ||
47 | |||
48 | #define CMU_MCACLK (*(volatile uint32_t *)(CMU_BASE + 0x38)) | ||
49 | |||
50 | #define CMU_DEVCLKEN (*(volatile uint32_t *)(CMU_BASE + 0x80)) | ||
51 | #define CMU_DEVRST (*(volatile uint32_t *)(CMU_BASE + 0x84)) | ||
52 | |||
53 | #define RTC_BASE 0xB0018000 | ||
54 | #define RTC_CTL (*(volatile uint32_t *)(RTC_BASE + 0x00)) | ||
55 | #define RTC_DHMS (*(volatile uint32_t *)(RTC_BASE + 0x04)) | ||
56 | #define RTC_YMD (*(volatile uint32_t *)(RTC_BASE + 0x08)) | ||
57 | #define RTC_DHMSALM (*(volatile uint32_t *)(RTC_BASE + 0x0C)) | ||
58 | #define RTC_YMDALM (*(volatile uint32_t *)(RTC_BASE + 0x10)) | ||
59 | #define RTC_WDCTL (*(volatile uint32_t *)(RTC_BASE + 0x14)) | ||
60 | #define RTC_WDCTL_CLR (1<<0) | ||
61 | |||
62 | #define RTC_T0CTL (*(volatile uint32_t *)(RTC_BASE + 0x18)) | ||
63 | #define RTC_T0 (*(volatile uint32_t *)(RTC_BASE + 0x1C)) | ||
64 | #define RTC_T1CTL (*(volatile uint32_t *)(RTC_BASE + 0x20)) | ||
65 | #define RTC_T1 (*(volatile uint32_t *)(RTC_BASE + 0x24)) | ||
66 | |||
67 | #define INTC_BASE 0xB0020000 | ||
68 | #define INTC_PD (*(volatile uint32_t *)(INTC_BASE + 0x00)) | ||
69 | #define INTC_MSK (*(volatile uint32_t *)(INTC_BASE + 0x04)) | ||
70 | #define INTC_CFG0 (*(volatile uint32_t *)(INTC_BASE + 0x08)) | ||
71 | #define INTC_CFG1 (*(volatile uint32_t *)(INTC_BASE + 0x0C)) | ||
72 | #define INTC_CFG2 (*(volatile uint32_t *)(INTC_BASE + 0x10)) | ||
73 | #define INTC_EXTCTL (*(volatile uint32_t *)(INTC_BASE + 0x14)) | ||
74 | |||
75 | #define SRAMOC_BASE 0xB0030000 | ||
76 | #define SRAMOC_CTL (*(volatile uint32_t *)(SRAMOC_BASE + 0x00)) | ||
77 | #define SRAMOC_STAT (*(volatile uint32_t *)(SRAMOC_BASE + 0x04)) | ||
78 | |||
79 | #define BOOT_BASE 0xB00380000 | ||
80 | #define BOOT_NORCTL (*(volatile uint32_t *)(BOOT_BASE + 0x00)) | ||
81 | #define BOOT_BROMCTL (*(volatile uint32_t *)(BOOT_BASE + 0x04)) | ||
82 | #define BOOT_CHIPID (*(volatile uint32_t *)(BOOT_BASE + 0x08)) | ||
83 | |||
84 | #define PCNT_BASE 0xB0040000 | ||
85 | #define PCNT_CTL (*(volatile uint32_t *)(PCNT_BASE + 0x00)) | ||
86 | #define PCNT_PC0 (*(volatile uint32_t *)(PCNT_BASE + 0x04)) | ||
87 | #define PCNT_PC1 (*(volatile uint32_t *)(PCNT_BASE + 0x08)) | ||
88 | |||
89 | #define DSP_BASE 0xB0050000 | ||
90 | #define DSP_HDR0 (*(volatile uint32_t *)(DSP_BASE + 0x00)) | ||
91 | #define DSP_HDR1 (*(volatile uint32_t *)(DSP_BASE + 0x04)) | ||
92 | #define DSP_HDR2 (*(volatile uint32_t *)(DSP_BASE + 0x08)) | ||
93 | #define DSP_HDR3 (*(volatile uint32_t *)(DSP_BASE + 0x0C)) | ||
94 | #define DSP_HDR4 (*(volatile uint32_t *)(DSP_BASE + 0x10)) | ||
95 | #define DSP_HDR5 (*(volatile uint32_t *)(DSP_BASE + 0x14)) | ||
96 | #define DSP_HSR6 (*(volatile uint32_t *)(DSP_BASE + 0x18)) | ||
97 | #define DSP_HSR7 (*(volatile uint32_t *)(DSP_BASE + 0x1C)) | ||
98 | #define DSP_CTL (*(volatile uint32_t *)(DSP_BASE + 0x20)) | ||
99 | |||
100 | #define DMAC_BASE(n) (0xB0060000 + (n<<5)) | ||
101 | #define DMAC_CTL (*(volatile uint32_t *)(DMAC_BASE(0) + 0x00)) | ||
102 | #define DMAC_IRQEN (*(volatile uint32_t *)(DMAC_BASE(0) + 0x04)) | ||
103 | #define DMAC_IRQPD (*(volatile uint32_t *)(DMAC_BASE(0) + 0x08)) | ||
104 | |||
105 | /* n in range 0-7 */ | ||
106 | #define DMA_MODE(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x100)) | ||
107 | #define DMA_SRC(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x104)) | ||
108 | #define DMA_DST(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x108)) | ||
109 | #define DMA_CNT(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x10C)) | ||
110 | #define DMA_REM(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x110)) | ||
111 | #define DMA_CMD(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x114)) | ||
112 | |||
113 | #define SDR_BASE 0xB0070000 | ||
114 | #define SDR_CTL (*(volatile uint32_t *)(SDR_BASE + 0x00)) | ||
115 | #define SDR_ADDRCFG (*(volatile uint32_t *)(SDR_BASE + 0x04)) | ||
116 | #define SDR_EN (*(volatile uint32_t *)(SDR_BASE + 0x08)) | ||
117 | #define SDR_CMD (*(volatile uint32_t *)(SDR_BASE + 0x0C)) | ||
118 | #define SDR_STAT (*(volatile uint32_t *)(SDR_BASE + 0x10)) | ||
119 | #define SDR_RFSH (*(volatile uint32_t *)(SDR_BASE + 0x14)) | ||
120 | #define SDR_MODE (*(volatile uint32_t *)(SDR_BASE + 0x18)) | ||
121 | #define SDR_MOBILE (*(volatile uint32_t *)(SDR_BASE + 0x1C)) | ||
122 | |||
123 | #define MCA_BASE 0xB0080000 | ||
124 | #define MCA_CTL (*(volatile uint32_t *)(MCA_BASE + 0x00)) | ||
125 | |||
126 | #define ATA_BASE 0xB0090000 | ||
127 | #define ATA_CONFIG (*(volatile uint32_t *)(ATA_BASE + 0x00)) | ||
128 | #define ATA_UDMACTL (*(volatile uint32_t *)(ATA_BASE + 0x04)) | ||
129 | #define ATA_DATA (*(volatile uint32_t *)(ATA_BASE + 0x08)) | ||
130 | #define ATA_FEATURE (*(volatile uint32_t *)(ATA_BASE + 0x0C)) | ||
131 | #define ATA_SECCNT (*(volatile uint32_t *)(ATA_BASE + 0x10)) | ||
132 | #define ATA_SECNUM (*(volatile uint32_t *)(ATA_BASE + 0x14)) | ||
133 | #define ATA_CLDLOW (*(volatile uint32_t *)(ATA_BASE + 0x18)) | ||
134 | #define ATA_CLDHI (*(volatile uint32_t *)(ATA_BASE + 0x1C)) | ||
135 | #define ATA_HEAD (*(volatile uint32_t *)(ATA_BASE + 0x20)) | ||
136 | #define ATA_CMD (*(volatile uint32_t *)(ATA_BASE + 0x24)) | ||
137 | #define ATA_BYTECNT (*(volatile uint32_t *)(ATA_BASE + 0x28)) | ||
138 | #define ATA_FIFOCTL (*(volatile uint32_t *)(ATA_BASE + 0x2C)) | ||
139 | #define ATA_FIFOCFG (*(volatile uint32_t *)(ATA_BASE + 0x30)) | ||
140 | #define ATA_ADDRDEC (*(volatile uint32_t *)(ATA_BASE + 0x34)) | ||
141 | #define ATA_IRQCTL (*(volatile uint32_t *)(ATA_BASE + 0x38)) | ||
142 | |||
143 | #define NAND_BASE 0xB00A0000 | ||
144 | #define NAND_CTL (*(volatile uint32_t *)(NAND_BASE + 0x00)) | ||
145 | #define NAND_STATUS (*(volatile uint32_t *)(NAND_BASE + 0x04)) | ||
146 | #define NAND_FIFOTIM (*(volatile uint32_t *)(NAND_BASE + 0x08)) | ||
147 | #define NAND_CLKCTL (*(volatile uint32_t *)(NAND_BASE + 0x0C)) | ||
148 | #define NAND_BYTECNT (*(volatile uint32_t *)(NAND_BASE + 0x10)) | ||
149 | #define NAND_ADDRLO1234 (*(volatile uint32_t *)(NAND_BASE + 0x14)) | ||
150 | #define NAND_ADDRLO56 (*(volatile uint32_t *)(NAND_BASE + 0x18)) | ||
151 | #define NAND_ADDRHI1234 (*(volatile uint32_t *)(NAND_BASE + 0x1C)) | ||
152 | #define NAND_ADDRHI56 (*(volatile uint32_t *)(NAND_BASE + 0x20)) | ||
153 | #define NAND_BUF0 (*(volatile uint32_t *)(NAND_BASE + 0x24)) | ||
154 | #define NAND_BUF1 (*(volatile uint32_t *)(NAND_BASE + 0x28)) | ||
155 | #define NAND_CMD (*(volatile uint32_t *)(NAND_BASE + 0x2C)) | ||
156 | #define NAND_ECCCTL (*(volatile uint32_t *)(NAND_BASE + 0x30)) | ||
157 | #define NAND_HAMECC0 (*(volatile uint32_t *)(NAND_BASE + 0x34)) | ||
158 | #define NAND_HAMECC1 (*(volatile uint32_t *)(NAND_BASE + 0x38)) | ||
159 | #define NAND_HAMECC2 (*(volatile uint32_t *)(NAND_BASE + 0x3C)) | ||
160 | #define NAND_HAMCEC (*(volatile uint32_t *)(NAND_BASE + 0x40)) | ||
161 | #define NAND_RSE0 (*(volatile uint32_t *)(NAND_BASE + 0x44)) | ||
162 | #define NAND_RSE1 (*(volatile uint32_t *)(NAND_BASE + 0x48)) | ||
163 | #define NAND_RSE2 (*(volatile uint32_t *)(NAND_BASE + 0x4C)) | ||
164 | #define NAND_RSE3 (*(volatile uint32_t *)(NAND_BASE + 0x50)) | ||
165 | #define NAND_RSPS0 (*(volatile uint32_t *)(NAND_BASE + 0x54)) | ||
166 | #define NAND_RSPS1 (*(volatile uint32_t *)(NAND_BASE + 0x58)) | ||
167 | #define NAND_RSPS2 (*(volatile uint32_t *)(NAND_BASE + 0x5C)) | ||
168 | #define NAND_FIFODATA (*(volatile uint32_t *)(NAND_BASE + 0x60)) | ||
169 | #define NAND_DEBUG (*(volatile uint32_t *)(NAND_BASE + 0x70)) | ||
170 | |||
171 | #define SD_BASE 0xB00B0000 | ||
172 | #define SD_CTL (*(volatile uint32_t *)(SD_BASE + 0x00)) | ||
173 | #define SD_CMDRSP (*(volatile uint32_t *)(SD_BASE + 0x04)) | ||
174 | #define SD_RW (*(volatile uint32_t *)(SD_BASE + 0x08)) | ||
175 | #define SD_FIFOCTL (*(volatile uint32_t *)(SD_BASE + 0x0C)) | ||
176 | #define SD_CMD (*(volatile uint32_t *)(SD_BASE + 0x10)) | ||
177 | #define SD_ARG (*(volatile uint32_t *)(SD_BASE + 0x14)) | ||
178 | #define SD_CRC7 (*(volatile uint32_t *)(SD_BASE + 0x18)) | ||
179 | #define SD_RSPBUF0 (*(volatile uint32_t *)(SD_BASE + 0x1C)) | ||
180 | #define SD_RSPBUF1 (*(volatile uint32_t *)(SD_BASE + 0x20)) | ||
181 | #define SD_RSPBUF2 (*(volatile uint32_t *)(SD_BASE + 0x24)) | ||
182 | #define SD_RSPBUF3 (*(volatile uint32_t *)(SD_BASE + 0x28)) | ||
183 | #define SD_RSPBUF4 (*(volatile uint32_t *)(SD_BASE + 0x2C)) | ||
184 | #define SD_DAT (*(volatile uint32_t *)(SD_BASE + 0x30)) | ||
185 | #define SD_CLK (*(volatile uint32_t *)(SD_BASE + 0x34)) | ||
186 | #define SD_BYTECNT (*(volatile uint32_t *)(SD_BASE + 0x38)) | ||
187 | |||
188 | #define MHA_BASE 0xB00C0000 | ||
189 | #define MHA_CTL (*(volatile uint32_t *)(MHA_BASE + 0x00)) | ||
190 | #define MHA_CFG (*(volatile uint32_t *)(MHA_BASE + 0x04)) | ||
191 | #define MHA_DCSCL01 (*(volatile uint32_t *)(MHA_BASE + 0x10)) | ||
192 | #define MHA_DCSCL23 (*(volatile uint32_t *)(MHA_BASE + 0x14)) | ||
193 | #define MHA_DCSCL45 (*(volatile uint32_t *)(MHA_BASE + 0x18)) | ||
194 | #define MHA_DCSCL67 (*(volatile uint32_t *)(MHA_BASE + 0x1C)) | ||
195 | #define MHA_QSCL (*(volatile uint32_t *)(MHA_BASE + 0x20)) | ||
196 | |||
197 | #define BT_BASE 0xB00D0000 | ||
198 | #define BT_MODESEL (*(volatile uint32_t *)(BT_BASE + 0x00)) | ||
199 | #define BT_FIFODAT (*(volatile uint32_t *)(BT_BASE + 0x04)) | ||
200 | |||
201 | /* video Encoder */ | ||
202 | #define BT_VEICTL (*(volatile uint32_t *)(BT_BASE + 0x08)) | ||
203 | #define BT_VEIVSEPOF (*(volatile uint32_t *)(BT_BASE + 0x14)) | ||
204 | #define BT_VEIVSEPEF (*(volatile uint32_t *)(BT_BASE + 0x18)) | ||
205 | #define BT_VEIFTP (*(volatile uint32_t *)(BT_BASE + 0x24)) | ||
206 | #define BT_VEIFIFOCTL (*(volatile uint32_t *)(BT_BASE + 0x30)) | ||
207 | |||
208 | /* Video Decoder */ | ||
209 | #define BT_VDICTL (*(volatile uint32_t *)(BT_BASE + 0x08)) | ||
210 | #define BT_VDIHSPOS (*(volatile uint32_t *)(BT_BASE + 0x0C)) | ||
211 | #define BT_VDIHEPOS (*(volatile uint32_t *)(BT_BASE + 0x10)) | ||
212 | #define BT_VDIVSEPOF (*(volatile uint32_t *)(BT_BASE + 0x14)) | ||
213 | #define BT_VDIVSEPEF (*(volatile uint32_t *)(BT_BASE + 0x18)) | ||
214 | #define BT_VDIIRQSTA (*(volatile uint32_t *)(BT_BASE + 0x28)) | ||
215 | #define BT_VDIXYDAT (*(volatile uint32_t *)(BT_BASE + 0x2C)) | ||
216 | #define BT_VDIFIFOCTL (*(volatile uint32_t *)(BT_BASE + 0x30)) | ||
217 | |||
218 | /* CMOS Sensor Interface */ | ||
219 | #define BT_CSICTL (*(volatile uint32_t *)(BT_BASE + 0x08)) | ||
220 | #define BT_CSIHSPOS (*(volatile uint32_t *)(BT_BASE + 0x0C)) | ||
221 | #define BT_CSIHEPOS (*(volatile uint32_t *)(BT_BASE + 0x10)) | ||
222 | #define BT_CSIVSPOS (*(volatile uint32_t *)(BT_BASE + 0x1C)) | ||
223 | #define BT_CSIVEPOS (*(volatile uint32_t *)(BT_BASE + 0x20)) | ||
224 | #define BT_CSIIRQSTA (*(volatile uint32_t *)(BT_BASE + 0x28)) | ||
225 | #define BT_CSIXYDAT (*(volatile uint32_t *)(BT_BASE + 0x2C)) | ||
226 | #define BT_CSIFIFOCTL (*(volatile uint32_t *)(BT_BASE + 0x30)) | ||
227 | |||
228 | /* TS */ | ||
229 | #define BT_TSICTL (*(volatile uint32_t *)(BT_BASE + 0x08)) | ||
230 | #define BT_TSIFIFOCTL (*(volatile uint32_t *)(BT_BASE + 0x30)) | ||
231 | |||
232 | /* Integrated Video Encoder */ | ||
233 | #define BT_IVECTL (*(volatile uint32_t *)(BT_BASE + 0x34)) | ||
234 | #define BT_IVEOUTCTL (*(volatile uint32_t *)(BT_BASE + 0x38)) | ||
235 | #define BT_IVECOTCTL (*(volatile uint32_t *)(BT_BASE + 0x3C)) | ||
236 | #define BT_IVEBRGCTL (*(volatile uint32_t *)(BT_BASE + 0x40)) | ||
237 | #define BT_IVECSATCTL (*(volatile uint32_t *)(BT_BASE + 0x44)) | ||
238 | #define BT_IVECBURCTL (*(volatile uint32_t *)(BT_BASE + 0x48)) | ||
239 | #define BT_IVESYNCAMCTL (*(volatile uint32_t *)(BT_BASE + 0x4C)) | ||
240 | |||
241 | #define OTG_BASE 0xB00E0000 | ||
242 | #define OTG_OUT0BC (*(volatile uint8_t *)(OTG_BASE + 0x00)) // ok (byte count?) | ||
243 | #define OTG_IN0BC (*(volatile uint8_t *)(OTG_BASE + 0x01)) // ok (byte count?) | ||
244 | #define OTG_EP0CS (*(volatile uint8_t *)(OTG_BASE + 0x02)) // ok | ||
245 | #define EP_NAK (1<<1) // from rt source | ||
246 | #define EP0_IN_BUSY (1<<2) | ||
247 | #define EP0_OUT_BUSY (1<<3) | ||
248 | |||
249 | #define OTG_OUT1CON (*(volatile uint8_t *)(OTG_BASE + 0x0A)) // ok | ||
250 | #define OTG_OUT1CS (*(volatile uint8_t *)(OTG_BASE + 0x0B)) // missing in rt | ||
251 | |||
252 | #define OTG_OUT2CON (*(volatile uint8_t *)(OTG_BASE + 0x12)) // missing in sdk | ||
253 | #define OTG_OUT2CS (*(volatile uint8_t *)(OTG_BASE + 0x13)) // deduced | ||
254 | |||
255 | #define OTG_IN2BCL (*(volatile uint8_t *)(OTG_BASE + 0x14)) // missing in rt | ||
256 | #define OTG_IN2BCH (*(volatile uint8_t *)(OTG_BASE + 0x15)) // missing in rt | ||
257 | #define OTG_IN2CON (*(volatile uint8_t *)(OTG_BASE + 0x16)) // ok | ||
258 | #define OTG_IN2CS (*(volatile uint8_t *)(OTG_BASE + 0x17)) // | ||
259 | |||
260 | #define OTG_FIFO1DAT (*(volatile uint32_t *)(OTG_BASE + 0x84)) // missing in rt | ||
261 | #define OTG_FIFO2DAT (*(volatile uint32_t *)(OTG_BASE + 0x88)) // missing in rt | ||
262 | |||
263 | #define OTG_EP0INDAT (*(volatile uint8_t *)(OTG_BASE + 0x100) // ok | ||
264 | |||
265 | #define OTG_EP0OUTDAT (*(volatile uint8_t *)(OTG_BASE + 0x140) // ok | ||
266 | |||
267 | #define OTG_SETUPDAT (*(volatile uint8_t *)(OTG_BASE + 0x180) // ok | ||
268 | #define OTG_USBIRQ (*(volatile uint8_t *)(OTG_BASE + 0x18C) // ok | ||
269 | |||
270 | #define OTG_USBIEN (*(volatile uint8_t *)(OTG_BASE + 0x198)) // ok | ||
271 | |||
272 | #define OTG_IVECT (*(volatile uint8_t *)(OTG_BASE + 0x1A0)) // missing in rt | ||
273 | #define OTG_ENDPRST (*(volatile uint8_t *)(OTG_BASE + 0x1A2)) // ok | ||
274 | #define OTG_USBCS (*(volatile uint8_t *)(OTG_BASE + 0x1A3)) // ok | ||
275 | #define SOFT_DISCONN (1<<6) // set for soft disconnect | ||
276 | |||
277 | #define OTG_FIFOCTL (*(volatile uint8_t *)(OTG_BASE + 0x1A8)) // ok | ||
278 | |||
279 | |||
280 | #define OTG_OTGIRQ (*(volatile uint8_t *)(OTG_BASE + 0x1BC)) | ||
281 | #define OTG_FSMSTAT (*(volatile uint8_t *)(OTG_BASE + 0x1BD)) | ||
282 | #define OTG_CTRL (*(volatile uint8_t *)(OTG_BASE + 0x1BE)) | ||
283 | #define OTG_STAT (*(volatile uint8_t *)(OTG_BASE + 0x1BF)) | ||
284 | #define OTG_OTGIEN (*(volatile uint8_t *)(OTG_BASE + 0x1C0)) | ||
285 | |||
286 | #define OTG_TAAIDLBDIS (*(volatile uint8_t *)(OTG_BASE + 0x1C1)) | ||
287 | #define OTG_TAWAITBCON (*(volatile uint8_t *)(OTG_BASE + 0x1C2)) | ||
288 | #define OTG_TBVBUSPLS (*(volatile uint8_t *)(OTG_BASE + 0x1C3)) | ||
289 | #define OTG_TBVBUSDISPLS (*(volatile uint8_t *)(OTG_BASE + 0x1C7)) | ||
290 | |||
291 | #define OTG_HCIN1MAXPCKL (*(volatile uint8_t *)(OTG_BASE + 0x1E2)) | ||
292 | #define OTG_HCIN1MAXPCKH (*(volatile uint8_t *)(OTG_BASE + 0x1E3)) | ||
293 | |||
294 | #define OTG_OUT1STADDR ((*(volatile uint8_t *)(OTG_BASE + 0x304)) | ||
295 | |||
296 | #define OTG_IN2STADDR ((*(volatile uint8_t *)(OTG_BASE + 0x348)) | ||
297 | |||
298 | #define OTG_HCOUT2MAXPCKL ((*(volatile uint8_t *)(OTG_BASE + 0x3E4)) | ||
299 | #define OTG_HCOUT2MAXPCKH ((*(volatile uint8_t *)(OTG_BASE + 0x3E5)) | ||
300 | |||
301 | #define OTG_USBEIRQ ((*(volatile uint8_t *)(OTG_BASE + 0x400)) | ||
302 | |||
303 | #define OTG_DMAEPSEL ((*(volatile uint8_t *)(OTG_BASE + 0x40C)) | ||
304 | |||
305 | #define YUV2RGB_BASE 0xB00F0000 | ||
306 | #define YUV2RGB_CTL (*(volatile uint32_t *)(YUV2RGB_BASE + 0x00)) | ||
307 | #define YUV2RGB_FIFODATA (*(volatile uint32_t *)(YUV2RGB_BASE + 0x04)) | ||
308 | #define YUV2RGB_CLKCTL (*(volatile uint32_t *)(YUV2RGB_BASE + 0x08)) | ||
309 | #define YUV2RGB_FRAMECOUNT (*(volatile uint32_t *)(YUV2RGB_BASE + 0x0C)) | ||
310 | |||
311 | #define DAC_BASE 0xB0100000 | ||
312 | #define DAC_CTL (*(volatile uint32_t *)(DAC_BASE + 0x00)) | ||
313 | #define DAC_FIFOCTL (*(volatile uint32_t *)(DAC_BASE + 0x04)) | ||
314 | #define DAC_DAT (*(volatile uint32_t *)(DAC_BASE + 0x08)) | ||
315 | #define DAC_DEBUG (*(volatile uint32_t *)(DAC_BASE + 0x0C)) | ||
316 | #define DAC_ANALOG (*(volatile uint32_t *)(DAC_BASE + 0x10)) | ||
317 | |||
318 | #define ADC_BASE 0xB0110000 | ||
319 | #define ADC_CTL (*(volatile uint32_t *)(ADC_BASE + 0x00)) | ||
320 | #define ADC_FIFOCTL (*(volatile uint32_t *)(ADC_BASE + 0x04)) | ||
321 | #define ADC_DAT (*(volatile uint32_t *)(ADC_BASE + 0x08)) | ||
322 | #define ADC_DEBUG (*(volatile uint32_t *)(ADC_BASE + 0x0C)) | ||
323 | #define ADC_ANALOG (*(volatile uint32_t *)(ADC_BASE + 0x10)) | ||
324 | |||
325 | #define TP_BASE 0xB0120000 | ||
326 | #define TP_CTL (*(volatile uint32_t *)(TP_BASE + 0x00)) | ||
327 | #define TP_DAT (*(volatile uint32_t *)(TP_BASE + 0x04)) | ||
328 | |||
329 | #define SPDIF_BASE 0xB0140000 | ||
330 | #define SPDIF_CTL (*(volatile uint32_t *)(SPDIF_BASE + 0x00)) | ||
331 | #define SPDIF_STAT (*(volatile uint32_t *)(SPDIF_BASE + 0x04)) | ||
332 | #define SPDIF_TXDAT (*(volatile uint32_t *)(SPDIF_BASE + 0x08)) | ||
333 | #define SPDIF_RXDAT (*(volatile uint32_t *)(SPDIF_BASE + 0x0C)) | ||
334 | #define SPDIF_TXCSTAT (*(volatile uint32_t *)(SPDIF_BASE + 0x10)) | ||
335 | #define SPDIF_RXCSTAT (*(volatile uint32_t *)(SPDIF_BASE + 0x14)) | ||
336 | |||
337 | #define PCM_BASE 0xB0150000 | ||
338 | #define PCM_CTL (*(volatile uint32_t *)(PCM_BASE + 0x00)) | ||
339 | #define PCM_STAT (*(volatile uint32_t *)(PCM_BASE + 0x04)) | ||
340 | #define PCM_RXDAT (*(volatile uint32_t *)(PCM_BASE + 0x08)) | ||
341 | #define PCM_TXDAT (*(volatile uint32_t *)(PCM_BASE + 0x0C)) | ||
342 | |||
343 | /* n = 0,1 */ | ||
344 | #define UART_BASE(n) (0xB0160000 + (n<<5)) | ||
345 | #define UART_CTL(n) (*(volatile uint32_t *)(UART_BASE(n) + 0x00)) | ||
346 | #define UART_RXDAT(n) (*(volatile uint32_t *)(UART_BASE(n) + 0x04)) | ||
347 | #define UART_TXDAT(n) (*(volatile uint32_t *)(UART_BASE(n) + 0x08)) | ||
348 | #define UART_STAT(n) (*(volatile uint32_t *)(UART_BASE(n) + 0x0C)) | ||
349 | |||
350 | #define IR_PL (*(volatile uint32_t *)(UART_BASE(0) + 0x10)) | ||
351 | #define IR_RBC (*(volatile uint32_t *)(UART_BASE(0) + 0x14)) | ||
352 | |||
353 | /* n = 0,1 */ | ||
354 | #define I2C_BASE(n) (0xB0180000 + (n<<5)) | ||
355 | #define I2C_CTL(n) (*(volatile uint32_t *)(I2C_BASE(n) + 0x00)) | ||
356 | #define I2C_CLKDIV(n) (*(volatile uint32_t *)(I2C_BASE(n) + 0x04)) | ||
357 | #define I2C_STAT(n) (*(volatile uint32_t *)(I2C_BASE(n) + 0x08)) | ||
358 | #define I2C_ADDR(n) (*(volatile uint32_t *)(I2C_BASE(n) + 0x0C)) | ||
359 | #define I2C_DAT(n) (*(volatile uint32_t *)(I2C_BASE(n) + 0x10)) | ||
360 | |||
361 | #define SPI_BASE 0xB0190000 | ||
362 | #define SPI_CTL (*(volatile uint32_t *)(SPI_BASE + 0x00)) | ||
363 | #define SPI_CLKDIV (*(volatile uint32_t *)(SPI_BASE + 0x04)) | ||
364 | #define SPI_STAT (*(volatile uint32_t *)(SPI_BASE + 0x08)) | ||
365 | #define SPI_RXDAT (*(volatile uint32_t *)(SPI_BASE + 0x0C)) | ||
366 | #define SPI_TXDAT (*(volatile uint32_t *)(SPI_BASE + 0x10)) | ||
367 | |||
368 | #define KEY_BASE 0xB01A0000 | ||
369 | #define KEY_CTL (*(volatile uint32_t *)(KEY_BASE + 0x00)) | ||
370 | #define KEY_DAT0 (*(volatile uint32_t *)(KEY_BASE + 0x04)) | ||
371 | #define KEY_DAT1 (*(volatile uint32_t *)(KEY_BASE + 0x08)) | ||
372 | #define KEY_DAT2 (*(volatile uint32_t *)(KEY_BASE + 0x0C)) | ||
373 | #define KEY_DAT3 (*(volatile uint32_t *)(KEY_BASE + 0x10)) | ||
374 | |||
375 | #define GPIO_BASE 0xB01C0000 | ||
376 | #define GPIO_AOUTEN (*(volatile uint32_t *)(GPIO_BASE + 0x00)) | ||
377 | #define GPIO_AINEN (*(volatile uint32_t *)(GPIO_BASE + 0x04)) | ||
378 | #define GPIO_ADAT (*(volatile uint32_t *)(GPIO_BASE + 0x08)) | ||
379 | #define GPIO_BOUTEN (*(volatile uint32_t *)(GPIO_BASE + 0x0C)) | ||
380 | #define GPIO_BINEN (*(volatile uint32_t *)(GPIO_BASE + 0x10)) | ||
381 | #define GPIO_BDAT (*(volatile uint32_t *)(GPIO_BASE + 0x14)) | ||
382 | #define GPIO_MFCTL0 (*(volatile uint32_t *)(GPIO_BASE + 0x18)) | ||
383 | #define GPIO_MFCTL1 (*(volatile uint32_t *)(GPIO_BASE + 0x1C)) | ||
diff --git a/utils/atj2137/adfuload/test_binary/timer_no_irq/crt0.S b/utils/atj2137/adfuload/test_binary/timer_no_irq/crt0.S new file mode 100644 index 0000000000..e03b8b5439 --- /dev/null +++ b/utils/atj2137/adfuload/test_binary/timer_no_irq/crt0.S | |||
@@ -0,0 +1,79 @@ | |||
1 | #include "mips.h" | ||
2 | |||
3 | .extern main | ||
4 | .global start | ||
5 | |||
6 | .set mips32r2 | ||
7 | .set noreorder | ||
8 | .set noat | ||
9 | |||
10 | .section .init.text,"ax",%progbits | ||
11 | |||
12 | start: | ||
13 | di # disable interrupts | ||
14 | bltzal zero, load_addr # ra = PC + 8, branch not taken | ||
15 | nop | ||
16 | |||
17 | load_addr: | ||
18 | addiu v0, ra, -12 # calc real load address | ||
19 | # account for branch delay slot | ||
20 | # and very first 'di' instruction | ||
21 | la t0, relocstart | ||
22 | la t1, relocend | ||
23 | beq t0, v0, entry_point # no relocation needed | ||
24 | nop | ||
25 | |||
26 | reloc_loop: | ||
27 | lw t2, 0(v0) # src | ||
28 | addiu v0, 4 # inc src addr | ||
29 | sw t2, 0(t0) # dst | ||
30 | bne t0, t1, reloc_loop | ||
31 | addiu t0, 4 # inc dst addr | ||
32 | |||
33 | entry_point_jump: | ||
34 | la t0, entry_point | ||
35 | jr t0 | ||
36 | nop | ||
37 | |||
38 | entry_point: | ||
39 | # setup caches | ||
40 | # 4-way, 256 sets, 16 bytes cacheline I/D | ||
41 | li t0, 3 # enable cache for kseg0 accesses | ||
42 | mtc0 t0, C0_CONFIG | ||
43 | |||
44 | la t0, 0x80000000 # an idx op should use an unmappable address | ||
45 | ori t1, t0, 0x4000 # 16kB cache | ||
46 | mtc0 zero, C0_TAGLO | ||
47 | mtc0 zero, C0_TAGHI | ||
48 | |||
49 | cache_init_loop: | ||
50 | cache 8, 0(t0) # index store icache tag | ||
51 | cache 9, 0(t0) # index store dcache tag | ||
52 | bne t0, t1, cache_init_loop | ||
53 | addiu t0, t0, 0x10 | ||
54 | |||
55 | # clear bss | ||
56 | la t0, bssbegin | ||
57 | la t1, bssend | ||
58 | |||
59 | clear_bss_loop: | ||
60 | sw zero, 0(t0) | ||
61 | bne t0, t1, clear_bss_loop | ||
62 | addiu t0, 4 | ||
63 | |||
64 | # setup stack | ||
65 | la sp, stackend | ||
66 | la t0, stackbegin | ||
67 | li t1, 0xdeadbeef | ||
68 | |||
69 | stack_munge_loop: | ||
70 | sw t1, 0(t0) | ||
71 | bne t0, sp, stack_munge_loop | ||
72 | addiu t0, 4 | ||
73 | |||
74 | # jump to C code | ||
75 | j main | ||
76 | nop | ||
77 | |||
78 | .set at | ||
79 | .set reorder | ||
diff --git a/utils/atj2137/adfuload/test_binary/timer_no_irq/mips-archdefs.h b/utils/atj2137/adfuload/test_binary/timer_no_irq/mips-archdefs.h new file mode 100644 index 0000000000..5b13a81a46 --- /dev/null +++ b/utils/atj2137/adfuload/test_binary/timer_no_irq/mips-archdefs.h | |||
@@ -0,0 +1,2356 @@ | |||
1 | /************************************************************************** | ||
2 | * * | ||
3 | * PROJECT : MIPS port for uC/OS-II * | ||
4 | * * | ||
5 | * MODULE : ARCHDEFS.h * | ||
6 | * * | ||
7 | * AUTHOR : Michael Anburaj * | ||
8 | * URL : http://geocities.com/michaelanburaj/ * | ||
9 | * EMAIL: michaelanburaj@hotmail.com * | ||
10 | * * | ||
11 | * PROCESSOR : MIPS 4Kc (32 bit RISC) - ATLAS board * | ||
12 | * * | ||
13 | * TOOL-CHAIN : SDE & Cygnus * | ||
14 | * * | ||
15 | * DESCRIPTION : * | ||
16 | * Architecture definitions. * | ||
17 | * * | ||
18 | **************************************************************************/ | ||
19 | |||
20 | |||
21 | #ifndef __ARCHDEFS_H__ | ||
22 | #define __ARCHDEFS_H__ | ||
23 | |||
24 | |||
25 | /* ********************************************************************* */ | ||
26 | /* Module configuration */ | ||
27 | |||
28 | |||
29 | /* ********************************************************************* */ | ||
30 | /* Interface macro & data definition */ | ||
31 | |||
32 | /* | ||
33 | * Utility defines for cross platform handling of 64bit constants. | ||
34 | */ | ||
35 | |||
36 | #if !defined(Append) | ||
37 | #define Append(c,s) (c##s) | ||
38 | #endif | ||
39 | |||
40 | #if !defined(__assembler) && !defined(MIPSAVPENV) | ||
41 | #if defined(NT) | ||
42 | #if !defined(UNS64Const) | ||
43 | #define UNS64Const(c) Append(c,ui64) | ||
44 | #endif | ||
45 | |||
46 | #if !defined(INT64Const) | ||
47 | #define INT64Const(c) Append(c,i64) | ||
48 | #endif | ||
49 | #else | ||
50 | #if !defined(UNS64Const) | ||
51 | #define UNS64Const(c) Append(c,ull) | ||
52 | #endif | ||
53 | |||
54 | #if !defined(INT64Const) | ||
55 | #define INT64Const(c) Append(c,ll) | ||
56 | #endif | ||
57 | #endif | ||
58 | #else /* Not C or C++ */ | ||
59 | #if !defined(UNS64Const) | ||
60 | #define UNS64Const(c) c | ||
61 | #endif | ||
62 | |||
63 | #if !defined(INT64Const) | ||
64 | #define INT64Const(c) c | ||
65 | #endif | ||
66 | #endif /* C or C++ */ | ||
67 | |||
68 | |||
69 | /* | ||
70 | ************************************************************************ | ||
71 | * I N S T R U C T I O N F O R M A T S * | ||
72 | ************************************************************************ | ||
73 | * | ||
74 | * The following definitions describe each field in an instruction. There | ||
75 | * is one diagram for each type of instruction, with field definitions | ||
76 | * following the diagram for that instruction. Note that if a field of | ||
77 | * the same name and position is defined in an earlier diagram, it is | ||
78 | * not defined again in the subsequent diagram. Only new fields are | ||
79 | * defined for each diagram. | ||
80 | * | ||
81 | * R-Type (operate) | ||
82 | * | ||
83 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
84 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
85 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
86 | * | | rs | rt | rd | sa | | | ||
87 | * | Opcode | | | Tcode | func | | ||
88 | * | | Bcode | | sel | | ||
89 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
90 | */ | ||
91 | |||
92 | #define S_InstnOpcode 26 | ||
93 | #define M_InstnOpcode (0x3f << S_InstnOpcode) | ||
94 | #define S_InstnRS 21 | ||
95 | #define M_InstnRS (0x1f << S_InstnRS) | ||
96 | #define S_InstnRT 16 | ||
97 | #define M_InstnRT (0x1f << S_InstnRT) | ||
98 | #define S_InstnRD 11 | ||
99 | #define M_InstnRD (0x1f << S_InstnRD) | ||
100 | #define S_InstnSA 6 | ||
101 | #define M_InstnSA (0x1f << S_InstnSA) | ||
102 | #define S_InstnTcode 6 | ||
103 | #define M_InstnTcode (0x3ff << S_InstnTcode) | ||
104 | #define S_InstnBcode 6 | ||
105 | #define M_InstnBcode (0xfffff << S_InstnBcode) | ||
106 | #define S_InstnFunc 0 | ||
107 | #define M_InstnFunc (0x3f << S_InstnFunc) | ||
108 | #define S_InstnSel 0 | ||
109 | #define M_InstnSel (0x7 << S_InstnSel) | ||
110 | |||
111 | /* | ||
112 | * I-Type (load, store, branch, immediate) | ||
113 | * | ||
114 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
115 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
116 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
117 | * | Opcode | rs | rt | Offset | | ||
118 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
119 | */ | ||
120 | |||
121 | #define S_InstnOffset 0 | ||
122 | #define M_InstnOffset (0xffff << S_InstnOffset) | ||
123 | |||
124 | /* | ||
125 | * I-Type (pref) | ||
126 | * | ||
127 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
128 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
129 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
130 | * | Opcode | rs | hint | Offset | | ||
131 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
132 | */ | ||
133 | |||
134 | #define S_InstnHint S_InstnRT | ||
135 | #define M_InstnHint M_InstnRT | ||
136 | |||
137 | /* | ||
138 | * J-Type (jump) | ||
139 | * | ||
140 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
141 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
142 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
143 | * | Opcode | JIndex | | ||
144 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
145 | */ | ||
146 | |||
147 | #define S_InstnJIndex 0 | ||
148 | #define M_InstnJIndex (0x03ffffff << S_InstnJIndex) | ||
149 | |||
150 | /* | ||
151 | * FP R-Type (operate) | ||
152 | * | ||
153 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
154 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
155 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
156 | * | Opcode | fmt | ft | fs | fd | func | | ||
157 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
158 | */ | ||
159 | |||
160 | #define S_InstnFmt S_InstnRS | ||
161 | #define M_InstnFmt M_InstnRS | ||
162 | #define S_InstnFT S_InstnRT | ||
163 | #define M_InstnFT M_InstnRT | ||
164 | #define S_InstnFS S_InstnRD | ||
165 | #define M_InstnFS M_InstnRD | ||
166 | #define S_InstnFD S_InstnSA | ||
167 | #define M_InstnFD M_InstnSA | ||
168 | |||
169 | /* | ||
170 | * FP R-Type (cpu <-> cpu data movement)) | ||
171 | * | ||
172 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
173 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
174 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
175 | * | Opcode | sub | rt | fs | 0 | | ||
176 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
177 | */ | ||
178 | |||
179 | #define S_InstnSub S_InstnRS | ||
180 | #define M_InstnSub M_InstnRS | ||
181 | |||
182 | /* | ||
183 | * FP R-Type (compare) | ||
184 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
185 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
186 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
187 | * | | | | | | |C| | | ||
188 | * | Opcode | fmt | ft | fs | cc |0|A| func | | ||
189 | * | | | | | | |B| | | ||
190 | * | | | | | | |S| | | ||
191 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
192 | */ | ||
193 | |||
194 | #define S_InstnCCcmp 8 | ||
195 | #define M_InstnCCcmp (0x7 << S_InstnCCcmp) | ||
196 | #define S_InstnCABS 6 | ||
197 | #define M_InstnCABS (0x1 << S_InstnCABS) | ||
198 | |||
199 | /* | ||
200 | * FP R-Type (FPR conditional move on FP cc) | ||
201 | * | ||
202 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
203 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
204 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
205 | * | Opcode | fmt | cc |n|t| fs | fd | func | | ||
206 | * | | | |d|f| | | | | ||
207 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
208 | */ | ||
209 | |||
210 | #define S_InstnCC 18 | ||
211 | #define M_InstnCC (0x7 << S_InstnCC) | ||
212 | #define S_InstnND 17 | ||
213 | #define M_InstnND (0x1 << S_InstnND) | ||
214 | #define S_InstnTF 16 | ||
215 | #define M_InstnTF (0x1 << S_InstnTF) | ||
216 | |||
217 | /* | ||
218 | * FP R-Type (3-operand operate) | ||
219 | * | ||
220 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
221 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
222 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
223 | * | Opcode | fr | ft | fs | fd | op4 | fmt3| | ||
224 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
225 | */ | ||
226 | |||
227 | #define S_InstnFR S_InstnRS | ||
228 | #define M_InstnFR M_InstnRS | ||
229 | #define S_InstnOp4 3 | ||
230 | #define M_InstnOp4 (0x7 << S_InstnOp4) | ||
231 | #define S_InstnFmt3 0 | ||
232 | #define M_InstnFmt3 (0x7 << S_InstnFmt3) | ||
233 | |||
234 | /* | ||
235 | * FP R-Type (Indexed load, store) | ||
236 | * | ||
237 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
238 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
239 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
240 | * | Opcode | rs | rt | 0 | fd | func | | ||
241 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
242 | */ | ||
243 | /* | ||
244 | * FP R-Type (prefx) | ||
245 | * | ||
246 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
247 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
248 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
249 | * | Opcode | rs | rt | hint | 0 | func | | ||
250 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
251 | */ | ||
252 | |||
253 | #define S_InstnHintX S_InstnRD | ||
254 | #define M_InstnHintX M_InstnRD | ||
255 | |||
256 | /* | ||
257 | * FP R-Type (GPR conditional move on FP cc) | ||
258 | * | ||
259 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
260 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
261 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
262 | * | Opcode | rs | cc |n|t| rd | 0 | func | | ||
263 | * | | | |d|f| | | | | ||
264 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
265 | */ | ||
266 | |||
267 | /* | ||
268 | * FP I-Type (load, store) | ||
269 | * | ||
270 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
271 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
272 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
273 | * | Opcode | rs | ft | Offset | | ||
274 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
275 | */ | ||
276 | |||
277 | /* | ||
278 | * FP I-Type (branch) | ||
279 | * | ||
280 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
281 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
282 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
283 | * | Opcode | fmt | cc |n|t| Offset | | ||
284 | * | | | |d|f| | | ||
285 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
286 | */ | ||
287 | |||
288 | |||
289 | /* | ||
290 | ************************************************************************* | ||
291 | * V I R T U A L A D D R E S S D E F I N I T I O N S * | ||
292 | ************************************************************************* | ||
293 | */ | ||
294 | |||
295 | #ifdef MIPSADDR64 | ||
296 | #define A_K0BASE UNS64Const(0xffffffff80000000) | ||
297 | #define A_K1BASE UNS64Const(0xffffffffa0000000) | ||
298 | #define A_K2BASE UNS64Const(0xffffffffc0000000) | ||
299 | #define A_K3BASE UNS64Const(0xffffffffe0000000) | ||
300 | #define A_REGION UNS64Const(0xc000000000000000) | ||
301 | #define A_XKPHYS_ATTR UNS64Const(0x3800000000000000) | ||
302 | #else | ||
303 | #define A_K0BASE 0x80000000 | ||
304 | #define A_K1BASE 0xa0000000 | ||
305 | #define A_K2BASE 0xc0000000 | ||
306 | #define A_K3BASE 0xe0000000 | ||
307 | #endif | ||
308 | #define M_KMAPPED 0x40000000 /* KnSEG address is mapped if bit is one */ | ||
309 | |||
310 | |||
311 | #ifdef MIPS_Model64 | ||
312 | |||
313 | #define S_VMAP64 62 | ||
314 | #define M_VMAP64 UNS64Const(0xc000000000000000) | ||
315 | |||
316 | #define K_VMode11 3 | ||
317 | #define K_VMode10 2 | ||
318 | #define K_VMode01 1 | ||
319 | #define K_VMode00 0 | ||
320 | |||
321 | #define S_KSEG3 29 | ||
322 | #define M_KSEG3 (0x7 << S_KSEG3) | ||
323 | #define K_KSEG3 7 | ||
324 | |||
325 | #define S_SSEG 29 | ||
326 | #define M_SSEG (0x7 << S_KSEG3) | ||
327 | #define K_SSEG 6 | ||
328 | |||
329 | #define S_KSSEG 29 | ||
330 | #define M_KSSEG (0x7 << S_KSEG3) | ||
331 | #define K_KSSEG 6 | ||
332 | |||
333 | #define S_KSEG1 29 | ||
334 | #define M_KSEG1 (0x7 << S_KSEG3) | ||
335 | #define K_KSEG1 5 | ||
336 | |||
337 | #define S_KSEG0 29 | ||
338 | #define M_KSEG0 (0x7 << S_KSEG3) | ||
339 | #define K_KSEG0 4 | ||
340 | |||
341 | #define S_XKSEG 29 | ||
342 | #define M_XKSEG (0x7 << S_KSEG3) | ||
343 | #define K_XKSEG 3 | ||
344 | |||
345 | #define S_USEG 31 | ||
346 | #define M_USEG (0x1 << S_USEG) | ||
347 | #define K_USEG 0 | ||
348 | |||
349 | #define S_EjtagProbeMem 20 | ||
350 | #define M_EjtagProbeMem (0x1 << S_EjtagProbeMem) | ||
351 | #define K_EjtagProbeMem 0 | ||
352 | |||
353 | |||
354 | |||
355 | #else | ||
356 | |||
357 | #define S_KSEG3 29 | ||
358 | #define M_KSEG3 (0x7 << S_KSEG3) | ||
359 | #define K_KSEG3 7 | ||
360 | |||
361 | #define S_KSSEG 29 | ||
362 | #define M_KSSEG (0x7 << S_KSSEG) | ||
363 | #define K_KSSEG 6 | ||
364 | |||
365 | #define S_SSEG 29 | ||
366 | #define M_SSEG (0x7 << S_SSEG) | ||
367 | #define K_SSEG 6 | ||
368 | |||
369 | #define S_KSEG1 29 | ||
370 | #define M_KSEG1 (0x7 << S_KSEG1) | ||
371 | #define K_KSEG1 5 | ||
372 | |||
373 | #define S_KSEG0 29 | ||
374 | #define M_KSEG0 (0x7 << S_KSEG0) | ||
375 | #define K_KSEG0 4 | ||
376 | |||
377 | #define S_KUSEG 31 | ||
378 | #define M_KUSEG (0x1 << S_KUSEG) | ||
379 | #define K_KUSEG 0 | ||
380 | |||
381 | #define S_SUSEG 31 | ||
382 | #define M_SUSEG (0x1 << S_SUSEG) | ||
383 | #define K_SUSEG 0 | ||
384 | |||
385 | #define S_USEG 31 | ||
386 | #define M_USEG (0x1 << S_USEG) | ||
387 | #define K_USEG 0 | ||
388 | |||
389 | #define K_EjtagLower 0xff200000 | ||
390 | #define K_EjtagUpper 0xff3fffff | ||
391 | |||
392 | #define S_EjtagProbeMem 20 | ||
393 | #define M_EjtagProbeMem (0x1 << S_EjtagProbeMem) | ||
394 | #define K_EjtagProbeMem 0 | ||
395 | |||
396 | #endif | ||
397 | |||
398 | |||
399 | |||
400 | /* | ||
401 | ************************************************************************* | ||
402 | * C A C H E I N S T R U C T I O N O P E R A T I O N C O D E S * | ||
403 | ************************************************************************* | ||
404 | */ | ||
405 | |||
406 | /* | ||
407 | * Cache encodings | ||
408 | */ | ||
409 | #define K_CachePriI 0 /* Primary Icache */ | ||
410 | #define K_CachePriD 1 /* Primary Dcache */ | ||
411 | #define K_CachePriU 1 /* Unified primary */ | ||
412 | #define K_CacheTerU 2 /* Unified Tertiary */ | ||
413 | #define K_CacheSecU 3 /* Unified secondary */ | ||
414 | |||
415 | |||
416 | /* | ||
417 | * Function encodings | ||
418 | */ | ||
419 | #define S_CacheFunc 2 /* Amount to shift function encoding within 5-bit field */ | ||
420 | #define K_CacheIndexInv 0 /* Index invalidate */ | ||
421 | #define K_CacheIndexWBInv 0 /* Index writeback invalidate */ | ||
422 | #define K_CacheIndexLdTag 1 /* Index load tag */ | ||
423 | #define K_CacheIndexStTag 2 /* Index store tag */ | ||
424 | #define K_CacheHitInv 4 /* Hit Invalidate */ | ||
425 | #define K_CacheFill 5 /* Fill (Icache only) */ | ||
426 | #define K_CacheHitWBInv 5 /* Hit writeback invalidate */ | ||
427 | #define K_CacheHitWB 6 /* Hit writeback */ | ||
428 | #define K_CacheFetchLock 7 /* Fetch and lock */ | ||
429 | |||
430 | #define ICIndexInv ((K_CacheIndexInv << S_CacheFunc) | K_CachePriI) | ||
431 | #define DCIndexWBInv ((K_CacheIndexWBInv << S_CacheFunc) | K_CachePriD) | ||
432 | #define DCIndexInv DCIndexWBInv | ||
433 | #define ICIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriI) | ||
434 | #define DCIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriD) | ||
435 | #define ICIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriI) | ||
436 | #define DCIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriD) | ||
437 | #define ICHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriI) | ||
438 | #define DCHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriD) | ||
439 | #define ICFill ((K_CacheFill << S_CacheFunc) | K_CachePriI) | ||
440 | #define DCHitWBInv ((K_CacheHitWBInv << S_CacheFunc) | K_CachePriD) | ||
441 | #define DCHitWB ((K_CacheHitWB << S_CacheFunc) | K_CachePriD) | ||
442 | #define ICFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriI) | ||
443 | #define DCFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriD) | ||
444 | |||
445 | |||
446 | /* | ||
447 | ************************************************************************* | ||
448 | * P R E F E T C H I N S T R U C T I O N H I N T S * | ||
449 | ************************************************************************* | ||
450 | */ | ||
451 | |||
452 | #define PrefLoad 0 | ||
453 | #define PrefStore 1 | ||
454 | #define PrefLoadStreamed 4 | ||
455 | #define PrefStoreStreamed 5 | ||
456 | #define PrefLoadRetained 6 | ||
457 | #define PrefStoreRetained 7 | ||
458 | #define PrefWBInval 25 | ||
459 | #define PrefNudge 25 | ||
460 | |||
461 | |||
462 | /* | ||
463 | ************************************************************************* | ||
464 | * C P U R E G I S T E R D E F I N I T I O N S * | ||
465 | ************************************************************************* | ||
466 | */ | ||
467 | |||
468 | |||
469 | /* | ||
470 | ************************************************************************* | ||
471 | * S O F T W A R E G P R N A M E S * | ||
472 | ************************************************************************* | ||
473 | */ | ||
474 | |||
475 | #define zero $0 | ||
476 | #define AT $1 | ||
477 | #define v0 $2 | ||
478 | #define v1 $3 | ||
479 | #define a0 $4 | ||
480 | #define a1 $5 | ||
481 | #define a2 $6 | ||
482 | #define a3 $7 | ||
483 | #define t0 $8 | ||
484 | #define t1 $9 | ||
485 | #define t2 $10 | ||
486 | #define t3 $11 | ||
487 | #define t4 $12 | ||
488 | #define t5 $13 | ||
489 | #define t6 $14 | ||
490 | #define t7 $15 | ||
491 | #define s0 $16 | ||
492 | #define s1 $17 | ||
493 | #define s2 $18 | ||
494 | #define s3 $19 | ||
495 | #define s4 $20 | ||
496 | #define s5 $21 | ||
497 | #define s6 $22 | ||
498 | #define s7 $23 | ||
499 | #define t8 $24 | ||
500 | #define t9 $25 | ||
501 | #define k0 $26 | ||
502 | #define k1 $27 | ||
503 | #define gp $28 | ||
504 | #define sp $29 | ||
505 | #define fp $30 | ||
506 | #define ra $31 | ||
507 | |||
508 | /* | ||
509 | * The following registers are used by the AVP environment and | ||
510 | * are not part of the normal software definitions. | ||
511 | */ | ||
512 | |||
513 | #ifdef MIPSAVPENV | ||
514 | #define repc $25 /* Expected exception PC */ | ||
515 | #define tid $30 /* Current test case address */ | ||
516 | #endif | ||
517 | |||
518 | |||
519 | /* | ||
520 | ************************************************************************* | ||
521 | * H A R D W A R E G P R N A M E S * | ||
522 | ************************************************************************* | ||
523 | * | ||
524 | * In the AVP environment, several of the `r' names are removed from the | ||
525 | * name space because they are used by the kernel for special purposes. | ||
526 | * Removing them causes assembly rather than runtime errors for tests that | ||
527 | * use the `r' names. | ||
528 | * | ||
529 | * - r25 (repc) is used as the expected PC on an exception | ||
530 | * - r26-r27 (k0, k1) are used in the exception handler | ||
531 | * - r30 (tid) is used as the current test address | ||
532 | */ | ||
533 | |||
534 | #define r0 $0 | ||
535 | #define r1 $1 | ||
536 | #define r2 $2 | ||
537 | #define r3 $3 | ||
538 | #define r4 $4 | ||
539 | #define r5 $5 | ||
540 | #define r6 $6 | ||
541 | #define r7 $7 | ||
542 | #define r8 $8 | ||
543 | #define r9 $9 | ||
544 | #define r10 $10 | ||
545 | #define r11 $11 | ||
546 | #define r12 $12 | ||
547 | #define r13 $13 | ||
548 | #define r14 $14 | ||
549 | #define r15 $15 | ||
550 | #define r16 $16 | ||
551 | #define r17 $17 | ||
552 | #define r18 $18 | ||
553 | #define r19 $19 | ||
554 | #define r20 $20 | ||
555 | #define r21 $21 | ||
556 | #define r22 $22 | ||
557 | #define r23 $23 | ||
558 | #define r24 $24 | ||
559 | #ifdef MIPSAVPENV | ||
560 | #define r25 r25_unknown | ||
561 | #define r26 r26_unknown | ||
562 | #define r27 r27_unknown | ||
563 | #else | ||
564 | #define r25 $25 | ||
565 | #define r26 $26 | ||
566 | #define r27 $27 | ||
567 | #endif | ||
568 | #define r28 $28 | ||
569 | #define r29 $29 | ||
570 | #ifdef MIPSAVPENV | ||
571 | #define r30 r30_unknown | ||
572 | #else | ||
573 | #define r30 $30 | ||
574 | #endif | ||
575 | #define r31 $31 | ||
576 | |||
577 | |||
578 | /* | ||
579 | ************************************************************************* | ||
580 | * H A R D W A R E G P R I N D I C E S * | ||
581 | ************************************************************************* | ||
582 | * | ||
583 | * These definitions provide the index (number) of the GPR, as opposed | ||
584 | * to the assembler register name ($n). | ||
585 | */ | ||
586 | |||
587 | #define R_r0 0 | ||
588 | #define R_r1 1 | ||
589 | #define R_r2 2 | ||
590 | #define R_r3 3 | ||
591 | #define R_r4 4 | ||
592 | #define R_r5 5 | ||
593 | #define R_r6 6 | ||
594 | #define R_r7 7 | ||
595 | #define R_r8 8 | ||
596 | #define R_r9 9 | ||
597 | #define R_r10 10 | ||
598 | #define R_r11 11 | ||
599 | #define R_r12 12 | ||
600 | #define R_r13 13 | ||
601 | #define R_r14 14 | ||
602 | #define R_r15 15 | ||
603 | #define R_r16 16 | ||
604 | #define R_r17 17 | ||
605 | #define R_r18 18 | ||
606 | #define R_r19 19 | ||
607 | #define R_r20 20 | ||
608 | #define R_r21 21 | ||
609 | #define R_r22 22 | ||
610 | #define R_r23 23 | ||
611 | #define R_r24 24 | ||
612 | #define R_r25 25 | ||
613 | #define R_r26 26 | ||
614 | #define R_r27 27 | ||
615 | #define R_r28 28 | ||
616 | #define R_r29 29 | ||
617 | #define R_r30 30 | ||
618 | #define R_r31 31 | ||
619 | #define R_hi 32 /* Hi register */ | ||
620 | #define R_lo 33 /* Lo register */ | ||
621 | |||
622 | |||
623 | /* | ||
624 | ************************************************************************* | ||
625 | * S O F T W A R E G P R M A S K S * | ||
626 | ************************************************************************* | ||
627 | * | ||
628 | * These definitions provide the bit mask corresponding to the GPR number | ||
629 | */ | ||
630 | |||
631 | #define M_AT (1<<1) | ||
632 | #define M_v0 (1<<2) | ||
633 | #define M_v1 (1<<3) | ||
634 | #define M_a0 (1<<4) | ||
635 | #define M_a1 (1<<5) | ||
636 | #define M_a2 (1<<6) | ||
637 | #define M_a3 (1<<7) | ||
638 | #define M_t0 (1<<8) | ||
639 | #define M_t1 (1<<9) | ||
640 | #define M_t2 (1<<10) | ||
641 | #define M_t3 (1<<11) | ||
642 | #define M_t4 (1<<12) | ||
643 | #define M_t5 (1<<13) | ||
644 | #define M_t6 (1<<14) | ||
645 | #define M_t7 (1<<15) | ||
646 | #define M_s0 (1<<16) | ||
647 | #define M_s1 (1<<17) | ||
648 | #define M_s2 (1<<18) | ||
649 | #define M_s3 (1<<19) | ||
650 | #define M_s4 (1<<20) | ||
651 | #define M_s5 (1<<21) | ||
652 | #define M_s6 (1<<22) | ||
653 | #define M_s7 (1<<23) | ||
654 | #define M_t8 (1<<24) | ||
655 | #define M_t9 (1<<25) | ||
656 | #define M_k0 (1<<26) | ||
657 | #define M_k1 (1<<27) | ||
658 | #define M_gp (1<<28) | ||
659 | #define M_sp (1<<29) | ||
660 | #define M_fp (1<<30) | ||
661 | #define M_ra (1<<31) | ||
662 | |||
663 | |||
664 | /* | ||
665 | ************************************************************************* | ||
666 | * C P 0 R E G I S T E R D E F I N I T I O N S * | ||
667 | ************************************************************************* | ||
668 | * Each register has the following definitions: | ||
669 | * | ||
670 | * C0_rrr The register number (as a $n value) | ||
671 | * R_C0_rrr The register index (as an integer corresponding | ||
672 | * to the register number) | ||
673 | * | ||
674 | * Each field in a register has the following definitions: | ||
675 | * | ||
676 | * S_rrrfff The shift count required to right-justify | ||
677 | * the field. This corresponds to the bit | ||
678 | * number of the right-most bit in the field. | ||
679 | * M_rrrfff The Mask required to isolate the field. | ||
680 | * | ||
681 | * Register diagrams included below as comments correspond to the | ||
682 | * MIPS32 and MIPS64 architecture specifications. Refer to other | ||
683 | * sources for register diagrams for older architectures. | ||
684 | */ | ||
685 | |||
686 | |||
687 | /* | ||
688 | ************************************************************************ | ||
689 | * I N D E X R E G I S T E R ( 0 ) * | ||
690 | ************************************************************************ | ||
691 | * | ||
692 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
693 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
694 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
695 | * |P| 0 | Index | Index | ||
696 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
697 | */ | ||
698 | |||
699 | #define C0_Index $0 | ||
700 | #define R_C0_Index 0 | ||
701 | #define C0_INX C0_Index /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
702 | |||
703 | #define S_IndexP 31 /* Probe failure (R)*/ | ||
704 | #define M_IndexP (0x1 << S_IndexP) | ||
705 | |||
706 | #define S_IndexIndex 0 /* TLB index (R/W)*/ | ||
707 | #define M_IndexIndex (0x3f << S_IndexIndex) | ||
708 | |||
709 | #define M_Index0Fields 0x7fffffc0 | ||
710 | #define M_IndexRFields 0x80000000 | ||
711 | |||
712 | |||
713 | /* | ||
714 | ************************************************************************ | ||
715 | * R A N D O M R E G I S T E R ( 1 ) * | ||
716 | ************************************************************************ | ||
717 | * | ||
718 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
719 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
720 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
721 | * | 0 | Index | Random | ||
722 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
723 | */ | ||
724 | |||
725 | #define C0_Random $1 | ||
726 | #define R_C0_Random 1 | ||
727 | #define C0_RAND $1 /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
728 | |||
729 | #define S_RandomIndex 0 /* TLB random index (R)*/ | ||
730 | #define M_RandomIndex (0x3f << S_RandomIndex) | ||
731 | |||
732 | #define M_Random0Fields 0xffffffc0 | ||
733 | #define M_RandomRFields 0x0000003f | ||
734 | |||
735 | |||
736 | /* | ||
737 | ************************************************************************ | ||
738 | * E N T R Y L O 0 R E G I S T E R ( 2 ) * | ||
739 | ************************************************************************ | ||
740 | * | ||
741 | * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
742 | * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
743 | * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
744 | * | Fill (0) //| 0 | PFN | C |D|V|G| EntryLo0 | ||
745 | * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
746 | */ | ||
747 | |||
748 | #define C0_EntryLo0 $2 | ||
749 | #define R_C0_EntryLo0 2 | ||
750 | #define C0_TLBLO_0 C0_EntryLo0 /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
751 | |||
752 | #define S_EntryLoPFN 6 /* PFN (R/W) */ | ||
753 | #define M_EntryLoPFN (0xffffff << S_EntryLoPFN) | ||
754 | #define S_EntryLoC 3 /* Coherency attribute (R/W) */ | ||
755 | #define M_EntryLoC (0x7 << S_EntryLoC) | ||
756 | #define S_EntryLoD 2 /* Dirty (R/W) */ | ||
757 | #define M_EntryLoD (0x1 << S_EntryLoD) | ||
758 | #define S_EntryLoV 1 /* Valid (R/W) */ | ||
759 | #define M_EntryLoV (0x1 << S_EntryLoV) | ||
760 | #define S_EntryLoG 0 /* Global (R/W) */ | ||
761 | #define M_EntryLoG (0x1 << S_EntryLoG) | ||
762 | #define M_EntryLoOddPFN (0x1 << S_EntryLoPFN) /* Odd PFN bit */ | ||
763 | #define S_EntryLo_RS K_PageAlign /* Right-justify PFN */ | ||
764 | #define S_EntryLo_LS S_EntryLoPFN /* Position PFN to appropriate position */ | ||
765 | |||
766 | #define M_EntryLo0Fields 0x00000000 | ||
767 | #define M_EntryLoRFields 0xc0000000 | ||
768 | #define M_EntryLo0Fields64 UNS64Const(0x0000000000000000) | ||
769 | #define M_EntryLoRFields64 UNS64Const(0xffffffffc0000000) | ||
770 | |||
771 | /* | ||
772 | * Cache attribute values in the C field of EntryLo and the | ||
773 | * K0 field of Config | ||
774 | */ | ||
775 | #define K_CacheAttrCWTnWA 0 /* Cacheable, write-thru, no write allocate */ | ||
776 | #define K_CacheAttrCWTWA 1 /* Cacheable, write-thru, write allocate */ | ||
777 | #define K_CacheAttrU 2 /* Uncached */ | ||
778 | #define K_CacheAttrC 3 /* Cacheable */ | ||
779 | #define K_CacheAttrCN 3 /* Cacheable, non-coherent */ | ||
780 | #define K_CacheAttrCCE 4 /* Cacheable, coherent, exclusive */ | ||
781 | #define K_CacheAttrCCS 5 /* Cacheable, coherent, shared */ | ||
782 | #define K_CacheAttrCCU 6 /* Cacheable, coherent, update */ | ||
783 | #define K_CacheAttrUA 7 /* Uncached accelerated */ | ||
784 | |||
785 | |||
786 | /* | ||
787 | ************************************************************************ | ||
788 | * E N T R Y L O 1 R E G I S T E R ( 3 ) * | ||
789 | ************************************************************************ | ||
790 | * | ||
791 | * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
792 | * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
793 | * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
794 | * | Fill (0) //| 0 | PFN | C |D|V|G| EntryLo1 | ||
795 | * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
796 | */ | ||
797 | |||
798 | #define C0_EntryLo1 $3 | ||
799 | #define R_C0_EntryLo1 3 | ||
800 | #define C0_TLBLO_1 C0_EntryLo1 /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
801 | |||
802 | /* | ||
803 | * Field definitions are as given for EntryLo0 above | ||
804 | */ | ||
805 | |||
806 | |||
807 | /* | ||
808 | ************************************************************************ | ||
809 | * C O N T E X T R E G I S T E R ( 4 ) * | ||
810 | ************************************************************************ | ||
811 | * | ||
812 | * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
813 | * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
814 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
815 | * | // PTEBase | BadVPN<31:13> | 0 | Context | ||
816 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
817 | */ | ||
818 | |||
819 | #define C0_Context $4 | ||
820 | #define R_C0_Context 4 | ||
821 | #define C0_CTXT C0_Context /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
822 | |||
823 | #define S_ContextPTEBase 23 /* PTE base (R/W) */ | ||
824 | #define M_ContextPTEBase (0x1ff << S_ContextPTEBase) | ||
825 | #define S_ContextBadVPN 4 /* BadVPN2 (R) */ | ||
826 | #define M_ContextBadVPN (0x7ffff << S_ContextBadVPN) | ||
827 | #define S_ContextBadVPN_LS 9 /* Position BadVPN to bit 31 */ | ||
828 | #define S_ContextBadVPN_RS 13 /* Right-justify shifted BadVPN field */ | ||
829 | |||
830 | #define M_Context0Fields 0x0000000f | ||
831 | #define M_ContextRFields 0x007ffff0 | ||
832 | #define M_Context0Fields64 UNS64Const(0x000000000000000f) | ||
833 | #define M_ContextRFields64 UNS64Const(0x00000000007ffff0) | ||
834 | |||
835 | |||
836 | /* | ||
837 | ************************************************************************ | ||
838 | * P A G E M A S K R E G I S T E R ( 5 ) * | ||
839 | ************************************************************************ | ||
840 | * | ||
841 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
842 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
843 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
844 | * | 0 | Mask | 0 | PageMask | ||
845 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
846 | */ | ||
847 | |||
848 | #define C0_PageMask $5 | ||
849 | #define R_C0_PageMask 5 /* Mask (R/W) */ | ||
850 | #define C0_PGMASK C0_PageMask /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
851 | |||
852 | #define S_PageMaskMask 13 | ||
853 | #define M_PageMaskMask (0xfff << S_PageMaskMask) | ||
854 | |||
855 | #define M_PageMask0Fields 0xfe001fff | ||
856 | #define M_PageMaskRFields 0x00000000 | ||
857 | |||
858 | /* | ||
859 | * Values in the Mask field | ||
860 | */ | ||
861 | #define K_PageMask4K 0x000 /* K_PageMasknn values are values for use */ | ||
862 | #define K_PageMask16K 0x003 /* with KReqPageAttributes or KReqPageMask macros */ | ||
863 | #define K_PageMask64K 0x00f | ||
864 | #define K_PageMask256K 0x03f | ||
865 | #define K_PageMask1M 0x0ff | ||
866 | #define K_PageMask4M 0x3ff | ||
867 | #define K_PageMask16M 0xfff | ||
868 | |||
869 | #define M_PageMask4K (K_PageMask4K << S_PageMaskMask) /* M_PageMasknn values are masks */ | ||
870 | #define M_PageMask16K (K_PageMask16K << S_PageMaskMask) /* in position in the PageMask register */ | ||
871 | #define M_PageMask64K (K_PageMask64K << S_PageMaskMask) | ||
872 | #define M_PageMask256K (K_PageMask256K << S_PageMaskMask) | ||
873 | #define M_PageMask1M (K_PageMask1M << S_PageMaskMask) | ||
874 | #define M_PageMask4M (K_PageMask4M << S_PageMaskMask) | ||
875 | #define M_PageMask16M (K_PageMask16M << S_PageMaskMask) | ||
876 | |||
877 | |||
878 | /* | ||
879 | ************************************************************************ | ||
880 | * W I R E D R E G I S T E R ( 6 ) * | ||
881 | ************************************************************************ | ||
882 | * | ||
883 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
884 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
885 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
886 | * | 0 | Index | Wired | ||
887 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
888 | */ | ||
889 | |||
890 | #define C0_Wired $6 | ||
891 | #define R_C0_Wired 6 | ||
892 | #define C0_TLBWIRED C0_Wired /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
893 | |||
894 | #define S_WiredIndex 0 /* TLB wired boundary (R/W) */ | ||
895 | #define M_WiredIndex (0x3f << S_WiredIndex) | ||
896 | |||
897 | #define M_Wired0Fields 0xffffffc0 | ||
898 | #define M_WiredRFields 0x00000000 | ||
899 | |||
900 | |||
901 | /* | ||
902 | ************************************************************************ | ||
903 | * B A D V A D D R R E G I S T E R ( 8 ) * | ||
904 | ************************************************************************ | ||
905 | * | ||
906 | * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
907 | * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
908 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
909 | * | // Bad Virtual Address | BadVAddr | ||
910 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
911 | */ | ||
912 | |||
913 | #define C0_BadVAddr $8 | ||
914 | #define R_C0_BadVAddr 8 | ||
915 | #define C0_BADVADDR C0_BadVAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
916 | |||
917 | #define M_BadVAddrOddPage K_PageSize /* Even/Odd VA bit for pair of PAs */ | ||
918 | |||
919 | #define M_BadVAddr0Fields 0x00000000 | ||
920 | #define M_BadVAddrRFields 0xffffffff | ||
921 | #define M_BadVAddr0Fields64 UNS64Const(0x0000000000000000) | ||
922 | #define M_BadVAddrRFields64 UNS64Const(0xffffffffffffffff) | ||
923 | |||
924 | /* | ||
925 | ************************************************************************ | ||
926 | * C O U N T R E G I S T E R ( 9 ) * | ||
927 | ************************************************************************ | ||
928 | * | ||
929 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
930 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
931 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
932 | * | Count Value | Count | ||
933 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
934 | */ | ||
935 | |||
936 | #define C0_Count $9 | ||
937 | #define R_C0_Count 9 | ||
938 | #define C0_COUNT C0_Count /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
939 | |||
940 | #define M_Count0Fields 0x00000000 | ||
941 | #define M_CountRFields 0x00000000 | ||
942 | |||
943 | |||
944 | /* | ||
945 | ************************************************************************ | ||
946 | * E N T R Y H I R E G I S T E R ( 1 0 ) * | ||
947 | ************************************************************************ | ||
948 | * | ||
949 | * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
950 | * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
951 | * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
952 | * | R | Fill // VPN2 | 0 | ASID | EntryHi | ||
953 | * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
954 | */ | ||
955 | |||
956 | #define C0_EntryHi $10 | ||
957 | #define R_C0_EntryHi 10 | ||
958 | #define C0_TLBHI C0_EntryHi /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
959 | |||
960 | #define S_EntryHiR64 62 /* Region (R/W) */ | ||
961 | #define M_EntryHiR64 UNS64Const(0xc000000000000000) | ||
962 | #define S_EntryHiVPN2 13 /* VPN/2 (R/W) */ | ||
963 | #define M_EntryHiVPN2 (0x7ffff << S_EntryHiVPN2) | ||
964 | #define M_EntryHiVPN264 UNS64Const(0x000000ffffffe000) | ||
965 | #define S_EntryHiASID 0 /* ASID (R/W) */ | ||
966 | #define M_EntryHiASID (0xff << S_EntryHiASID) | ||
967 | #define S_EntryHiVPN_Shf S_EntryHiVPN2 | ||
968 | |||
969 | #define M_EntryHi0Fields 0x00001f00 | ||
970 | #define M_EntryHiRFields 0x00000000 | ||
971 | #define M_EntryHi0Fields64 UNS64Const(0x0000000000001f00) | ||
972 | #define M_EntryHiRFields64 UNS64Const(0x3fffff0000000000) | ||
973 | |||
974 | |||
975 | /* | ||
976 | ************************************************************************ | ||
977 | * C O M P A R E R E G I S T E R ( 1 1 ) * | ||
978 | ************************************************************************ | ||
979 | * | ||
980 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
981 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
982 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
983 | * | Compare Value | Compare | ||
984 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
985 | */ | ||
986 | |||
987 | #define C0_Compare $11 | ||
988 | #define R_C0_Compare 11 | ||
989 | #define C0_COMPARE C0_Compare /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
990 | |||
991 | #define M_Compare0Fields 0x00000000 | ||
992 | #define M_CompareRFields 0x00000000 | ||
993 | |||
994 | |||
995 | /* | ||
996 | ************************************************************************ | ||
997 | * S T A T U S R E G I S T E R ( 1 2 ) * | ||
998 | ************************************************************************ | ||
999 | * | ||
1000 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1001 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1002 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1003 | * |C|C|C|C|R|F|R|M|P|B|T|S|M| | R |I|I|I|I|I|I|I|I|K|S|U|U|R|E|E|I| | ||
1004 | * |U|U|U|U|P|R|E|X|X|E|S|R|M| | s |M|M|M|M|M|M|M|M|X|X|X|M|s|R|X|E| Status | ||
1005 | * |3|2|1|0| | | | | |V| | |I| | v |7|6|5|4|3|2|1|0| | | | |v|L|L| | | ||
1006 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1007 | */ | ||
1008 | |||
1009 | #define C0_Status $12 | ||
1010 | #define R_C0_Status 12 | ||
1011 | #define C0_SR C0_Status /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1012 | |||
1013 | #define S_StatusCU 28 /* Coprocessor enable (R/W) */ | ||
1014 | #define M_StatusCU (0xf << S_StatusCU) | ||
1015 | #define S_StatusCU3 31 | ||
1016 | #define M_StatusCU3 (0x1 << S_StatusCU3) | ||
1017 | #define S_StatusCU2 30 | ||
1018 | #define M_StatusCU2 (0x1 << S_StatusCU2) | ||
1019 | #define S_StatusCU1 29 | ||
1020 | #define M_StatusCU1 (0x1 << S_StatusCU1) | ||
1021 | #define S_StatusCU0 28 | ||
1022 | #define M_StatusCU0 (0x1 << S_StatusCU0) | ||
1023 | #define S_StatusRP 27 /* Enable reduced power mode (R/W) */ | ||
1024 | #define M_StatusRP (0x1 << S_StatusRP) | ||
1025 | #define S_StatusFR 26 /* Enable 64-bit FPRs (MIPS64 only) (R/W) */ | ||
1026 | #define M_StatusFR (0x1 << S_StatusFR) | ||
1027 | #define S_StatusRE 25 /* Enable reverse endian (R/W) */ | ||
1028 | #define M_StatusRE (0x1 << S_StatusRE) | ||
1029 | #define S_StatusMX 24 /* Enable access to MDMX resources (MIPS64 only) (R/W) */ | ||
1030 | #define M_StatusMX (0x1 << S_StatusMX) | ||
1031 | #define S_StatusPX 23 /* Enable access to 64-bit instructions/data (MIPS64 only) (R/W) */ | ||
1032 | #define M_StatusPX (0x1 << S_StatusPX) | ||
1033 | #define S_StatusBEV 22 /* Enable Boot Exception Vectors (R/W) */ | ||
1034 | #define M_StatusBEV (0x1 << S_StatusBEV) | ||
1035 | #define S_StatusTS 21 /* Denote TLB shutdown (R/W) */ | ||
1036 | #define M_StatusTS (0x1 << S_StatusTS) | ||
1037 | #define S_StatusSR 20 /* Denote soft reset (R/W) */ | ||
1038 | #define M_StatusSR (0x1 << S_StatusSR) | ||
1039 | #define S_StatusNMI 19 | ||
1040 | #define M_StatusNMI (0x1 << S_StatusNMI) /* Denote NMI (R/W) */ | ||
1041 | #define S_StatusIM 8 /* Interrupt mask (R/W) */ | ||
1042 | #define M_StatusIM (0xff << S_StatusIM) | ||
1043 | #define S_StatusIM7 15 | ||
1044 | #define M_StatusIM7 (0x1 << S_StatusIM7) | ||
1045 | #define S_StatusIM6 14 | ||
1046 | #define M_StatusIM6 (0x1 << S_StatusIM6) | ||
1047 | #define S_StatusIM5 13 | ||
1048 | #define M_StatusIM5 (0x1 << S_StatusIM5) | ||
1049 | #define S_StatusIM4 12 | ||
1050 | #define M_StatusIM4 (0x1 << S_StatusIM4) | ||
1051 | #define S_StatusIM3 11 | ||
1052 | #define M_StatusIM3 (0x1 << S_StatusIM3) | ||
1053 | #define S_StatusIM2 10 | ||
1054 | #define M_StatusIM2 (0x1 << S_StatusIM2) | ||
1055 | #define S_StatusIM1 9 | ||
1056 | #define M_StatusIM1 (0x1 << S_StatusIM1) | ||
1057 | #define S_StatusIM0 8 | ||
1058 | #define M_StatusIM0 (0x1 << S_StatusIM0) | ||
1059 | #define S_StatusKX 7 /* Enable access to extended kernel addresses (MIPS64 only) (R/W) */ | ||
1060 | #define M_StatusKX (0x1 << S_StatusKX) | ||
1061 | #define S_StatusSX 6 /* Enable access to extended supervisor addresses (MIPS64 only) (R/W) */ | ||
1062 | #define M_StatusSX (0x1 << S_StatusSX) | ||
1063 | #define S_StatusUX 5 /* Enable access to extended user addresses (MIPS64 only) (R/W) */ | ||
1064 | #define M_StatusUX (0x1 << S_StatusUX) | ||
1065 | #define S_StatusKSU 3 /* Two-bit current mode (R/W) */ | ||
1066 | #define M_StatusKSU (0x3 << S_StatusKSU) | ||
1067 | #define S_StatusUM 4 /* User mode if supervisor mode not implemented (R/W) */ | ||
1068 | #define M_StatusUM (0x1 << S_StatusUM) | ||
1069 | #define S_StatusSM 3 /* Supervisor mode (R/W) */ | ||
1070 | #define M_StatusSM (0x1 << S_StatusSM) | ||
1071 | #define S_StatusERL 2 /* Denotes error level (R/W) */ | ||
1072 | #define M_StatusERL (0x1 << S_StatusERL) | ||
1073 | #define S_StatusEXL 1 /* Denotes exception level (R/W) */ | ||
1074 | #define M_StatusEXL (0x1 << S_StatusEXL) | ||
1075 | #define S_StatusIE 0 /* Enables interrupts (R/W) */ | ||
1076 | #define M_StatusIE (0x1 << S_StatusIE) | ||
1077 | |||
1078 | #define M_Status0Fields 0x00040000 | ||
1079 | #define M_StatusRFields 0x058000e0 /* FR, MX, PX, KX, SX, UX unused in MIPS32 */ | ||
1080 | #define M_Status0Fields64 0x00040000 | ||
1081 | #define M_StatusRFields64 0x00000000 | ||
1082 | |||
1083 | /* | ||
1084 | * Values in the KSU field | ||
1085 | */ | ||
1086 | #define K_StatusKSU_U 2 /* User mode in KSU field */ | ||
1087 | #define K_StatusKSU_S 1 /* Supervisor mode in KSU field */ | ||
1088 | #define K_StatusKSU_K 0 /* Kernel mode in KSU field */ | ||
1089 | |||
1090 | |||
1091 | /* | ||
1092 | ************************************************************************ | ||
1093 | * C A U S E R E G I S T E R ( 1 3 ) * | ||
1094 | ************************************************************************ | ||
1095 | * | ||
1096 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1097 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1098 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1099 | * |B| | C | |I|W| |I|I|I|I|I|I|I|I| | | R | | ||
1100 | * |D| | E | Rsvd |V|P| Rsvd |P|P|P|P|P|P|P|P| | ExcCode | s | Cause | ||
1101 | * | | | | | | | |7|6|5|4|3|2|1|0| | | v | | ||
1102 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1103 | */ | ||
1104 | |||
1105 | #define C0_Cause $13 | ||
1106 | #define R_C0_Cause 13 | ||
1107 | #define C0_CAUSE C0_Cause /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1108 | |||
1109 | #define S_CauseBD 31 | ||
1110 | #define M_CauseBD (0x1 << S_CauseBD) | ||
1111 | #define S_CauseCE 28 | ||
1112 | #define M_CauseCE (0x3<< S_CauseCE) | ||
1113 | #define S_CauseIV 23 | ||
1114 | #define M_CauseIV (0x1 << S_CauseIV) | ||
1115 | #define S_CauseWP 22 | ||
1116 | #define M_CauseWP (0x1 << S_CauseWP) | ||
1117 | #define S_CauseIP 8 | ||
1118 | #define M_CauseIP (0xff << S_CauseIP) | ||
1119 | #define S_CauseIPEXT 10 | ||
1120 | #define M_CauseIPEXT (0x3f << S_CauseIPEXT) | ||
1121 | #define S_CauseIP7 15 | ||
1122 | #define M_CauseIP7 (0x1 << S_CauseIP7) | ||
1123 | #define S_CauseIP6 14 | ||
1124 | #define M_CauseIP6 (0x1 << S_CauseIP6) | ||
1125 | #define S_CauseIP5 13 | ||
1126 | #define M_CauseIP5 (0x1 << S_CauseIP5) | ||
1127 | #define S_CauseIP4 12 | ||
1128 | #define M_CauseIP4 (0x1 << S_CauseIP4) | ||
1129 | #define S_CauseIP3 11 | ||
1130 | #define M_CauseIP3 (0x1 << S_CauseIP3) | ||
1131 | #define S_CauseIP2 10 | ||
1132 | #define M_CauseIP2 (0x1 << S_CauseIP2) | ||
1133 | #define S_CauseIP1 9 | ||
1134 | #define M_CauseIP1 (0x1 << S_CauseIP1) | ||
1135 | #define S_CauseIP0 8 | ||
1136 | #define M_CauseIP0 (0x1 << S_CauseIP0) | ||
1137 | #define S_CauseExcCode 2 | ||
1138 | #define M_CauseExcCode (0x1f << S_CauseExcCode) | ||
1139 | |||
1140 | #define M_Cause0Fields 0x4f3f0083 | ||
1141 | #define M_CauseRFields 0xb000fc7c | ||
1142 | |||
1143 | /* | ||
1144 | * Values in the CE field | ||
1145 | */ | ||
1146 | #define K_CauseCE0 0 /* Coprocessor 0 in the CE field */ | ||
1147 | #define K_CauseCE1 1 /* Coprocessor 1 in the CE field */ | ||
1148 | #define K_CauseCE2 2 /* Coprocessor 2 in the CE field */ | ||
1149 | #define K_CauseCE3 3 /* Coprocessor 3 in the CE field */ | ||
1150 | |||
1151 | /* | ||
1152 | * Values in the ExcCode field | ||
1153 | */ | ||
1154 | #define EX_INT 0 /* Interrupt */ | ||
1155 | #define EXC_INT (EX_INT << S_CauseExcCode) | ||
1156 | #define EX_MOD 1 /* TLB modified */ | ||
1157 | #define EXC_MOD (EX_MOD << S_CauseExcCode) | ||
1158 | #define EX_TLBL 2 /* TLB exception (load or ifetch) */ | ||
1159 | #define EXC_TLBL (EX_TLBL << S_CauseExcCode) | ||
1160 | #define EX_TLBS 3 /* TLB exception (store) */ | ||
1161 | #define EXC_TLBS (EX_TLBS << S_CauseExcCode) | ||
1162 | #define EX_ADEL 4 /* Address error (load or ifetch) */ | ||
1163 | #define EXC_ADEL (EX_ADEL << S_CauseExcCode) | ||
1164 | #define EX_ADES 5 /* Address error (store) */ | ||
1165 | #define EXC_ADES (EX_ADES << S_CauseExcCode) | ||
1166 | #define EX_IBE 6 /* Instruction Bus Error */ | ||
1167 | #define EXC_IBE (EX_IBE << S_CauseExcCode) | ||
1168 | #define EX_DBE 7 /* Data Bus Error */ | ||
1169 | #define EXC_DBE (EX_DBE << S_CauseExcCode) | ||
1170 | #define EX_SYS 8 /* Syscall */ | ||
1171 | #define EXC_SYS (EX_SYS << S_CauseExcCode) | ||
1172 | #define EX_SYSCALL EX_SYS | ||
1173 | #define EXC_SYSCALL EXC_SYS | ||
1174 | #define EX_BP 9 /* Breakpoint */ | ||
1175 | #define EXC_BP (EX_BP << S_CauseExcCode) | ||
1176 | #define EX_BREAK EX_BP | ||
1177 | #define EXC_BREAK EXC_BP | ||
1178 | #define EX_RI 10 /* Reserved instruction */ | ||
1179 | #define EXC_RI (EX_RI << S_CauseExcCode) | ||
1180 | #define EX_CPU 11 /* CoProcessor Unusable */ | ||
1181 | #define EXC_CPU (EX_CPU << S_CauseExcCode) | ||
1182 | #define EX_OV 12 /* OVerflow */ | ||
1183 | #define EXC_OV (EX_OV << S_CauseExcCode) | ||
1184 | #define EX_TR 13 /* Trap instruction */ | ||
1185 | #define EXC_TR (EX_TR << S_CauseExcCode) | ||
1186 | #define EX_TRAP EX_TR | ||
1187 | #define EXC_TRAP EXC_TR | ||
1188 | #define EX_FPE 15 /* floating point exception */ | ||
1189 | #define EXC_FPE (EX_FPE << S_CauseExcCode) | ||
1190 | #define EX_C2E 18 /* COP2 exception */ | ||
1191 | #define EXC_C2E (EX_C2E << S_CauseExcCode) | ||
1192 | #define EX_MDMX 22 /* MDMX exception */ | ||
1193 | #define EXC_MDMX (EX_MDMX << S_CauseExcCode) | ||
1194 | #define EX_WATCH 23 /* Watch exception */ | ||
1195 | #define EXC_WATCH (EX_WATCH << S_CauseExcCode) | ||
1196 | #define EX_MCHECK 24 /* Machine check exception */ | ||
1197 | #define EXC_MCHECK (EX_MCHECK << S_CauseExcCode) | ||
1198 | #define EX_CacheErr 30 /* Cache error caused re-entry to Debug Mode */ | ||
1199 | #define EXC_CacheErr (EX_CacheErr << S_CauseExcCode) | ||
1200 | |||
1201 | |||
1202 | /* | ||
1203 | ************************************************************************ | ||
1204 | * E P C R E G I S T E R ( 1 4 ) * | ||
1205 | ************************************************************************ | ||
1206 | * | ||
1207 | * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1208 | * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1209 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1210 | * | // Exception PC | EPC | ||
1211 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1212 | */ | ||
1213 | |||
1214 | #define C0_EPC $14 | ||
1215 | #define R_C0_EPC 14 | ||
1216 | |||
1217 | #define M_EPC0Fields 0x00000000 | ||
1218 | #define M_EPCRFields 0x00000000 | ||
1219 | #define M_EPC0Fields64 UNS64Const(0x0000000000000000) | ||
1220 | #define M_EPCRFields64 UNS64Const(0x0000000000000000) | ||
1221 | |||
1222 | /* | ||
1223 | ************************************************************************ | ||
1224 | * P R I D R E G I S T E R ( 1 5 ) * | ||
1225 | ************************************************************************ | ||
1226 | * | ||
1227 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1228 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1229 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1230 | * | Company Opts | Company ID | Procesor ID | Revision | PRId | ||
1231 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1232 | */ | ||
1233 | |||
1234 | #define C0_PRId $15 | ||
1235 | #define R_C0_PRId 15 | ||
1236 | #define C0_PRID C0_PRID /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1237 | |||
1238 | #define S_PRIdCoOpt 24 /* Company options (R) */ | ||
1239 | #define M_PRIdCoOpt (0xff << S_PRIdCoOpt) | ||
1240 | #define S_PRIdCoID 16 /* Company ID (R) */ | ||
1241 | #define M_PRIdCoID (0xff << S_PRIdCoID) | ||
1242 | #define S_PRIdImp 8 /* Implementation ID (R) */ | ||
1243 | #define M_PRIdImp (0xff << S_PRIdImp) | ||
1244 | #define S_PRIdRev 0 /* Revision (R) */ | ||
1245 | #define M_PRIdRev (0xff << S_PRIdRev) | ||
1246 | |||
1247 | #define M_PRId0Fields 0x00000000 | ||
1248 | #define M_PRIdRFields 0xffffffff | ||
1249 | /* | ||
1250 | * Values in the Company ID field | ||
1251 | */ | ||
1252 | #define K_PRIdCoID_MIPS 1 | ||
1253 | #define K_PRIdCoID_Broadcom 2 | ||
1254 | #define K_PRIdCoID_Alchemy 3 | ||
1255 | #define K_PRIdCoID_SiByte 4 | ||
1256 | #define K_PRIdCoID_SandCraft 5 | ||
1257 | #define K_PRIdCoID_Philips 6 | ||
1258 | #define K_PRIdCoID_NextAvailable 7 /* Next available encoding */ | ||
1259 | |||
1260 | |||
1261 | /* | ||
1262 | * Values in the implementation number field | ||
1263 | */ | ||
1264 | #define K_PRIdImp_Jade 0x80 | ||
1265 | #define K_PRIdImp_Opal 0x81 | ||
1266 | #define K_PRIdImp_Ruby 0x82 | ||
1267 | #define K_PRIdImp_JadeLite 0x83 | ||
1268 | #define K_PRIdImp_4KEc 0x84 /* Emerald with TLB MMU */ | ||
1269 | #define K_PRIdImp_4KEmp 0x85 /* Emerald with FM MMU */ | ||
1270 | #define K_PRIdImp_4KSc 0x86 /* Coral */ | ||
1271 | |||
1272 | #define K_PRIdImp_R3000 0x01 | ||
1273 | #define K_PRIdImp_R4000 0x04 | ||
1274 | #define K_PRIdImp_R10000 0x09 | ||
1275 | #define K_PRIdImp_R4300 0x0b | ||
1276 | #define K_PRIdImp_R5000 0x23 | ||
1277 | #define K_PRIdImp_R5200 0x28 | ||
1278 | #define K_PRIdImp_R5400 0x54 | ||
1279 | |||
1280 | /* | ||
1281 | ************************************************************************ | ||
1282 | * C O N F I G R E G I S T E R ( 1 6 ) * | ||
1283 | ************************************************************************ | ||
1284 | * | ||
1285 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1286 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1287 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1288 | * |M| |B| A | A | | K | Config | ||
1289 | * | | Reserved for Implementations|E| T | R | Reserved | 0 | | ||
1290 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1291 | */ | ||
1292 | |||
1293 | #define C0_Config $16 | ||
1294 | #define R_C0_Config 16 | ||
1295 | #define C0_CONFIG C0_Config /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1296 | |||
1297 | #define S_ConfigMore 31 /* Additional config registers present (R) */ | ||
1298 | #define M_ConfigMore (0x1 << S_ConfigMore) | ||
1299 | #define S_ConfigImpl 16 /* Implementation-specific fields */ | ||
1300 | #define M_ConfigImpl (0x7fff << S_ConfigImpl) | ||
1301 | #define S_ConfigBE 15 /* Denotes big-endian operation (R) */ | ||
1302 | #define M_ConfigBE (0x1 << S_ConfigBE) | ||
1303 | #define S_ConfigAT 13 /* Architecture type (R) */ | ||
1304 | #define M_ConfigAT (0x3 << S_ConfigAT) | ||
1305 | #define S_ConfigAR 10 /* Architecture revision (R) */ | ||
1306 | #define M_ConfigAR (0x7 << S_ConfigAR) | ||
1307 | #define S_ConfigMT 7 /* MMU Type (R) */ | ||
1308 | #define M_ConfigMT (0x7 << S_ConfigMT) | ||
1309 | #define S_ConfigK0 0 /* Kseg0 coherency algorithm (R/W) */ | ||
1310 | #define M_ConfigK0 (0x7 << S_ConfigK0) | ||
1311 | |||
1312 | /* | ||
1313 | * The following definitions are technically part of the "reserved for | ||
1314 | * implementations" field, but are the semi-standard definition used in | ||
1315 | * fixed-mapping MMUs to control the cacheability of kuseg and kseg2/3 | ||
1316 | * references. For that reason, they are included here, but may be | ||
1317 | * overridden by true implementation-specific definitions | ||
1318 | */ | ||
1319 | #define S_ConfigK23 28 /* Kseg2/3 coherency algorithm (FM MMU only) (R/W) */ | ||
1320 | #define M_ConfigK23 (0x7 << S_ConfigK23) | ||
1321 | #define S_ConfigKU 25 /* Kuseg coherency algorithm (FM MMU only) (R/W) */ | ||
1322 | #define M_ConfigKU (0x7 << S_ConfigKU) | ||
1323 | |||
1324 | #define M_Config0Fields 0x00000078 | ||
1325 | #define M_ConfigRFields 0x8000ff80 | ||
1326 | |||
1327 | /* | ||
1328 | * Values in the AT field | ||
1329 | */ | ||
1330 | #define K_ConfigAT_MIPS32 0 /* MIPS32 */ | ||
1331 | #define K_ConfigAT_MIPS64S 1 /* MIPS64 with 32-bit addresses */ | ||
1332 | #define K_ConfigAT_MIPS64 2 /* MIPS64 with 32/64-bit addresses */ | ||
1333 | |||
1334 | /* | ||
1335 | * Values in the MT field | ||
1336 | */ | ||
1337 | #define K_ConfigMT_NoMMU 0 /* No MMU */ | ||
1338 | #define K_ConfigMT_TLBMMU 1 /* Standard TLB MMU */ | ||
1339 | #define K_ConfigMT_BATMMU 2 /* Standard BAT MMU */ | ||
1340 | #define K_ConfigMT_FMMMU 3 /* Standard Fixed Mapping MMU */ | ||
1341 | |||
1342 | |||
1343 | /* | ||
1344 | ************************************************************************ | ||
1345 | * C O N F I G 1 R E G I S T E R ( 1 6, SELECT 1 ) * | ||
1346 | ************************************************************************ | ||
1347 | * | ||
1348 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1349 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1350 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1351 | * |M| MMU Size | IS | IL | IA | DS | DL | DA |C|M|P|W|C|E|F| Config1 | ||
1352 | * | | | | | | | | |2|D|C|R|A|P|P| | ||
1353 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1354 | */ | ||
1355 | |||
1356 | #define C0_Config1 $16,1 | ||
1357 | #define R_C0_Config1 16 | ||
1358 | |||
1359 | #define S_Config1More 31 /* Additional Config registers present (R) */ | ||
1360 | #define M_Config1More (0x1 << S_Config1More) | ||
1361 | #define S_Config1MMUSize 25 /* Number of MMU entries - 1 (R) */ | ||
1362 | #define M_Config1MMUSize (0x3f << S_Config1MMUSize) | ||
1363 | #define S_Config1IS 22 /* Icache sets per way (R) */ | ||
1364 | #define M_Config1IS (0x7 << S_Config1IS) | ||
1365 | #define S_Config1IL 19 /* Icache line size (R) */ | ||
1366 | #define M_Config1IL (0x7 << S_Config1IL) | ||
1367 | #define S_Config1IA 16 /* Icache associativity - 1 (R) */ | ||
1368 | #define M_Config1IA (0x7 << S_Config1IA) | ||
1369 | #define S_Config1DS 13 /* Dcache sets per way (R) */ | ||
1370 | #define M_Config1DS (0x7 << S_Config1DS) | ||
1371 | #define S_Config1DL 10 /* Dcache line size (R) */ | ||
1372 | #define M_Config1DL (0x7 << S_Config1DL) | ||
1373 | #define S_Config1DA 7 /* Dcache associativity (R) */ | ||
1374 | #define M_Config1DA (0x7 << S_Config1DA) | ||
1375 | #define S_Config1C2 6 /* Coprocessor 2 present (R) */ | ||
1376 | #define M_Config1C2 (0x1 << S_Config1C2) | ||
1377 | #define S_Config1MD 5 /* Denotes MDMX present (R) */ | ||
1378 | #define M_Config1MD (0x1 << S_Config1MD) | ||
1379 | #define S_Config1PC 4 /* Denotes performance counters present (R) */ | ||
1380 | #define M_Config1PC (0x1 << S_Config1PC) | ||
1381 | #define S_Config1WR 3 /* Denotes watch registers present (R) */ | ||
1382 | #define M_Config1WR (0x1 << S_Config1WR) | ||
1383 | #define S_Config1CA 2 /* Denotes MIPS-16 present (R) */ | ||
1384 | #define M_Config1CA (0x1 << S_Config1CA) | ||
1385 | #define S_Config1EP 1 /* Denotes EJTAG present (R) */ | ||
1386 | #define M_Config1EP (0x1 << S_Config1EP) | ||
1387 | #define S_Config1FP 0 /* Denotes floating point present (R) */ | ||
1388 | #define M_Config1FP (0x1 << S_Config1FP) | ||
1389 | |||
1390 | #define M_Config10Fields 0x00000060 | ||
1391 | #define M_Config1RFields 0x7fffff9f | ||
1392 | |||
1393 | /* | ||
1394 | * The following macro generates a table that is indexed | ||
1395 | * by the Icache or Dcache sets field in Config1 and | ||
1396 | * contains the decoded value of sets per way | ||
1397 | */ | ||
1398 | #define Config1CacheSets() \ | ||
1399 | HALF(64); \ | ||
1400 | HALF(128); \ | ||
1401 | HALF(256); \ | ||
1402 | HALF(512); \ | ||
1403 | HALF(1024); \ | ||
1404 | HALF(2048); \ | ||
1405 | HALF(4096); \ | ||
1406 | HALF(8192); | ||
1407 | |||
1408 | /* | ||
1409 | * The following macro generates a table that is indexed | ||
1410 | * by the Icache or Dcache line size field in Config1 and | ||
1411 | * contains the decoded value of the cache line size, in bytes | ||
1412 | */ | ||
1413 | #define Config1CacheLineSize() \ | ||
1414 | HALF(0); \ | ||
1415 | HALF(4); \ | ||
1416 | HALF(8); \ | ||
1417 | HALF(16); \ | ||
1418 | HALF(32); \ | ||
1419 | HALF(64); \ | ||
1420 | HALF(128); \ | ||
1421 | HALF(256); | ||
1422 | |||
1423 | |||
1424 | /* | ||
1425 | ************************************************************************ | ||
1426 | * C O N F I G 2 R E G I S T E R ( 1 6, SELECT 2 ) * | ||
1427 | ************************************************************************ | ||
1428 | * | ||
1429 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1430 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1431 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1432 | * |M| | | | | | | | | | | | |S|T| Config1 | ||
1433 | * | | | | | | | | | | | | | |M|L| | ||
1434 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1435 | */ | ||
1436 | |||
1437 | #define C0_Config2 $16,2 | ||
1438 | #define R_C0_Config2 16 | ||
1439 | |||
1440 | #define S_Config2More 31 /* Additional Config registers present (R) */ | ||
1441 | #define M_Config2More (0x1 << S_Config2More) | ||
1442 | #define S_Config2SM 1 /* Denotes SmartMIPS ASE present (R) */ | ||
1443 | #define M_Config2SM (0x1 << S_Config2SM) | ||
1444 | #define S_Config2TL 0 /* Denotes Tracing Logic present (R) */ | ||
1445 | #define M_Config2TL (0x1 << S_Config2TL) | ||
1446 | |||
1447 | #define M_Config20Fields 0xfffffffc | ||
1448 | #define M_Config2RFields 0x00000003 | ||
1449 | |||
1450 | /* | ||
1451 | ************************************************************************ | ||
1452 | * L L A D D R R E G I S T E R ( 1 7 ) * | ||
1453 | ************************************************************************ | ||
1454 | * | ||
1455 | * 6 6 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1456 | * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1457 | * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1458 | * | // LL Physical Address | LLAddr | ||
1459 | * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1460 | */ | ||
1461 | |||
1462 | #define C0_LLAddr $17 | ||
1463 | #define R_C0_LLAddr 17 | ||
1464 | #define C0_LLADDR C0_LLAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1465 | |||
1466 | #define M_LLAddr0Fields 0x00000000 | ||
1467 | #define M_LLAddrRFields 0x00000000 | ||
1468 | #define M_LLAddr0Fields64 UNS64Const(0x0000000000000000) | ||
1469 | #define M_LLAddrRFields64 UNS64Const(0x0000000000000000) | ||
1470 | |||
1471 | |||
1472 | /* | ||
1473 | ************************************************************************ | ||
1474 | * W A T C H L O R E G I S T E R ( 1 8 ) * | ||
1475 | ************************************************************************ | ||
1476 | * | ||
1477 | * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1478 | * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1479 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1480 | * | // Watch Virtual Address |I|R|W| WatchLo | ||
1481 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1482 | */ | ||
1483 | |||
1484 | #define C0_WatchLo $18 | ||
1485 | #define R_C0_WatchLo 18 | ||
1486 | #define C0_WATCHLO C0_WatchLo /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1487 | |||
1488 | #define S_WatchLoVAddr 3 /* Watch virtual address (R/W) */ | ||
1489 | #define M_WatchLoVAddr (0x1fffffff << S_WatchLoVAddr) | ||
1490 | #define S_WatchLoI 2 /* Enable Istream watch (R/W) */ | ||
1491 | #define M_WatchLoI (0x1 << S_WatchLoI) | ||
1492 | #define S_WatchLoR 1 /* Enable data read watch (R/W) */ | ||
1493 | #define M_WatchLoR (0x1 << S_WatchLoR) | ||
1494 | #define S_WatchLoW 0 /* Enable data write watch (R/W) */ | ||
1495 | #define M_WatchLoW (0x1 << S_WatchLoW) | ||
1496 | |||
1497 | #define M_WatchLo0Fields 0x00000000 | ||
1498 | #define M_WatchLoRFields 0x00000000 | ||
1499 | #define M_WatchLo0Fields64 UNS64Const(0x0000000000000000) | ||
1500 | #define M_WatchLoRFields64 UNS64Const(0x0000000000000000) | ||
1501 | |||
1502 | #define M_WatchLoEnables (M_WatchLoI | M_WatchLoR | M_WatchLoW) | ||
1503 | |||
1504 | |||
1505 | /* | ||
1506 | ************************************************************************ | ||
1507 | * W A T C H H I R E G I S T E R ( 1 9 ) * | ||
1508 | ************************************************************************ | ||
1509 | * | ||
1510 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1511 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1512 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1513 | * |M|G| Rsvd | ASID | Rsvd | Mask | 0 | WatchHi | ||
1514 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1515 | */ | ||
1516 | |||
1517 | #define C0_WatchHi $19 | ||
1518 | #define R_C0_WatchHi 19 | ||
1519 | #define C0_WATCHHI C0_WatchHi /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1520 | |||
1521 | #define S_WatchHiM 31 /* Denotes additional Watch registers present (R) */ | ||
1522 | #define M_WatchHiM (0x1 << S_WatchHiM) | ||
1523 | #define S_WatchHiG 30 /* Enable ASID-independent Watch match (R/W) */ | ||
1524 | #define M_WatchHiG (0x1 << S_WatchHiG) | ||
1525 | #define S_WatchHiASID 16 /* ASID value to match (R/W) */ | ||
1526 | #define M_WatchHiASID (0xff << S_WatchHiASID) | ||
1527 | #define S_WatchHiMask 3 /* Address inhibit mask (R/W) */ | ||
1528 | #define M_WatchHiMask (0x1ff << S_WatchHiMask) | ||
1529 | |||
1530 | #define M_WatchHi0Fields 0x3f00f007 | ||
1531 | #define M_WatchHiRFields 0x80000000 | ||
1532 | |||
1533 | |||
1534 | /* | ||
1535 | ************************************************************************ | ||
1536 | * X C O N T E X T R E G I S T E R ( 2 0 ) * | ||
1537 | ************************************************************************ | ||
1538 | * | ||
1539 | * 6 // 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1540 | * 3 // 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1541 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1542 | * | // PTEBase | R | BadVPN2<39:13> | 0 | XContext | ||
1543 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1544 | */ | ||
1545 | |||
1546 | #define C0_XContext $20 | ||
1547 | #define R_C0_XContext 20 | ||
1548 | #define C0_EXTCTXT C0_XContext /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1549 | |||
1550 | #define S_XContextBadVPN2 4 /* BadVPN2 (R) */ | ||
1551 | #define S_XContextBadVPN S_XContextBadVPN2 | ||
1552 | |||
1553 | #define M_XContext0Fields 0x0000000f | ||
1554 | |||
1555 | |||
1556 | /* | ||
1557 | ************************************************************************ | ||
1558 | * D E B U G R E G I S T E R ( 2 3 ) * | ||
1559 | ************************************************************************ | ||
1560 | * | ||
1561 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1562 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1563 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1564 | * |D|D|N|L|D|H|C|I|M|C|D|I|D|D| | |N|S| |D|D|D|D|D|D| | ||
1565 | * |B|M|o|S|o|a|o|B|C|a|B|E|D|D|EJTAG|DExcCode |o|S| |I|I|D|D|B|S| | ||
1566 | * |D| |D|N|z|l|u|u|h|c|u|X|B|B| ver | |S|t| |N|B|B|B|p|S| | ||
1567 | * | | |C|M|e|t|n|s|e|h|s|I|S|L| | |S| | 0 |T| |S|L| | | Debug | ||
1568 | * | | |R| | | |t|E|c|e|E| |I|I| | |t| | | | | | | | | | ||
1569 | * | | | | | | |D|P|k|E|P| |m|m| | | | | | | | | | | | | ||
1570 | * | | | | | | |M| |P|P| | |p|p| | | | | | | | | | | | | ||
1571 | * | | | | | | | | | | | | |r|r| | | | | | | | | | | | | ||
1572 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1573 | */ | ||
1574 | |||
1575 | #define C0_Debug $23 /* EJTAG */ | ||
1576 | #define R_C0_Debug 23 | ||
1577 | |||
1578 | #define S_DebugDBD 31 /* Debug branch delay (R) */ | ||
1579 | #define M_DebugDBD (0x1 << S_DebugDBD) | ||
1580 | #define S_DebugDM 30 /* Debug mode (R) */ | ||
1581 | #define M_DebugDM (0x1 << S_DebugDM) | ||
1582 | #define S_DebugNoDCR 29 /* No debug control register present (R) */ | ||
1583 | #define M_DebugNoDCR (0x1 << S_DebugNoDCR) | ||
1584 | #define S_DebugLSNM 28 /* Load/Store Normal Memory (R/W) */ | ||
1585 | #define M_DebugLSNM (0x1 << S_DebugLSNM) | ||
1586 | #define S_DebugDoze 27 /* Doze (R) */ | ||
1587 | #define M_DebugDoze (0x1 << S_DebugDoze) | ||
1588 | #define S_DebugHalt 26 /* Halt (R) */ | ||
1589 | #define M_DebugHalt (0x1 << S_DebugHalt) | ||
1590 | #define S_DebugCountDM 25 /* Count register behavior in debug mode (R/W) */ | ||
1591 | #define M_DebugCountDM (0x1 << S_DebugCountDM) | ||
1592 | #define S_DebugIBusEP 24 /* Imprecise Instn Bus Error Pending (R/W) */ | ||
1593 | #define M_DebugIBusEP (0x1 << S_DebugIBusEP) | ||
1594 | #define S_DebugMCheckP 23 /* Imprecise Machine Check Pending (R/W) */ | ||
1595 | #define M_DebugMCheckP (0x1 << S_DebugMCheckP) | ||
1596 | #define S_DebugCacheEP 22 /* Imprecise Cache Error Pending (R/W) */ | ||
1597 | #define M_DebugCacheEP (0x1 << S_DebugCacheEP) | ||
1598 | #define S_DebugDBusEP 21 /* Imprecise Data Bus Error Pending (R/W) */ | ||
1599 | #define M_DebugDBusEP (0x1 << S_DebugDBusEP) | ||
1600 | #define S_DebugIEXI 20 /* Imprecise Exception Inhibit (R/W) */ | ||
1601 | #define M_DebugIEXI (0x1 << S_DebugIEXI) | ||
1602 | #define S_DebugDDBSImpr 19 /* Debug data break store imprecise (R) */ | ||
1603 | #define M_DebugDDBSImpr (0x1 << S_DebugDDBSImpr) | ||
1604 | #define S_DebugDDBLImpr 18 /* Debug data break load imprecise (R) */ | ||
1605 | #define M_DebugDDBLImpr (0x1 << S_DebugDDBLImpr) | ||
1606 | #define S_DebugEJTAGver 15 /* EJTAG version number (R) */ | ||
1607 | #define M_DebugEJTAGver (0x7 << S_DebugEJTAGver) | ||
1608 | #define S_DebugDExcCode 10 /* Debug exception code (R) */ | ||
1609 | #define M_DebugDExcCode (0x1f << S_DebugDExcCode) | ||
1610 | #define S_DebugNoSSt 9 /* No single step implemented (R) */ | ||
1611 | #define M_DebugNoSSt (0x1 << S_DebugNoSSt) | ||
1612 | #define S_DebugSSt 8 /* Single step enable (R/W) */ | ||
1613 | #define M_DebugSSt (0x1 << S_DebugSSt) | ||
1614 | #define S_DebugDINT 5 /* Debug interrupt (R) */ | ||
1615 | #define M_DebugDINT (0x1 << S_DebugDINT) | ||
1616 | #define S_DebugDIB 4 /* Debug instruction break (R) */ | ||
1617 | #define M_DebugDIB (0x1 << S_DebugDIB) | ||
1618 | #define S_DebugDDBS 3 /* Debug data break store (R) */ | ||
1619 | #define M_DebugDDBS (0x1 << S_DebugDDBS) | ||
1620 | #define S_DebugDDBL 2 /* Debug data break load (R) */ | ||
1621 | #define M_DebugDDBL (0x1 << S_DebugDDBL) | ||
1622 | #define S_DebugDBp 1 /* Debug breakpoint (R) */ | ||
1623 | #define M_DebugDBp (0x1 << S_DebugDBp) | ||
1624 | #define S_DebugDSS 0 /* Debug single step (R) */ | ||
1625 | #define M_DebugDSS (0x1 << S_DebugDSS) | ||
1626 | |||
1627 | #define M_Debug0Fields 0x01f000c0 | ||
1628 | #define M_DebugRFields 0xec0ffe3f | ||
1629 | |||
1630 | |||
1631 | /* | ||
1632 | ************************************************************************ | ||
1633 | * D E P C R E G I S T E R ( 2 4 ) * | ||
1634 | ************************************************************************ | ||
1635 | * | ||
1636 | * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1637 | * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1638 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1639 | * | // EJTAG Debug Exception PC | DEPC | ||
1640 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1641 | */ | ||
1642 | |||
1643 | |||
1644 | #define C0_DEPC $24 | ||
1645 | #define R_C0_DEPC 24 | ||
1646 | |||
1647 | #define M_DEEPC0Fields 0x00000000 | ||
1648 | #define M_DEEPCRFields 0x00000000 | ||
1649 | #define M_DEEPC0Fields64 UNS64Const(0x0000000000000000) | ||
1650 | #define M_DEEPCRFields64 UNS64Const(0x0000000000000000) | ||
1651 | |||
1652 | |||
1653 | /* | ||
1654 | ************************************************************************ | ||
1655 | * P E R F C N T R E G I S T E R ( 2 5 ) * | ||
1656 | ************************************************************************ | ||
1657 | * | ||
1658 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1659 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1660 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1661 | * | | | |I| | | |E| | ||
1662 | * |M| 0 | Event |E|U|S|K|X| PerfCnt | ||
1663 | * | | | | | | | |L| | ||
1664 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1665 | * | ||
1666 | * | ||
1667 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1668 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1669 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1670 | * | Event Count | PerfCnt | ||
1671 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1672 | */ | ||
1673 | |||
1674 | #define C0_PerfCnt $25 | ||
1675 | #define R_C0_PerfCnt 25 | ||
1676 | #define C0_PRFCNT0 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1677 | #define C0_PRFCNT1 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1678 | |||
1679 | #define S_PerfCntM 31 /* More performance counters exist (R) */ | ||
1680 | #define M_PerfCntM (1 << S_PerfCntM) | ||
1681 | #define S_PerfCntEvent 5 /* Enabled event (R/W) */ | ||
1682 | #define M_PerfCntEvent (0x3f << S_PerfCntEvent) | ||
1683 | #define S_PerfCntIE 4 /* Interrupt Enable (R/W) */ | ||
1684 | #define M_PerfCntIE (1 << S_PerfCntIE) | ||
1685 | #define S_PerfCntU 3 /* Enable counting in User Mode (R/W) */ | ||
1686 | #define M_PerfCntU (1 << S_PerfCntU) | ||
1687 | #define S_PerfCntS 2 /* Enable counting in Supervisor Mode (R/W) */ | ||
1688 | #define M_PerfCntS (1 << S_PerfCntS) | ||
1689 | #define S_PerfCntK 1 /* Enable counting in Kernel Mode (R/W) */ | ||
1690 | #define M_PerfCntK (1 << S_PerfCntK) | ||
1691 | #define S_PerfCntEXL 0 /* Enable counting while EXL==1 (R/W) */ | ||
1692 | #define M_PerfCntEXL (1 << S_PerfCntEXL) | ||
1693 | |||
1694 | #define M_PerfCnt0Fields 0x7ffff800 | ||
1695 | #define M_PerfCntRFields 0x80000000 | ||
1696 | |||
1697 | |||
1698 | /* | ||
1699 | ************************************************************************ | ||
1700 | * E R R C T L R E G I S T E R ( 2 6 ) * | ||
1701 | ************************************************************************ | ||
1702 | * | ||
1703 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1704 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1705 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1706 | * | Error Control | ErrCtl | ||
1707 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1708 | */ | ||
1709 | |||
1710 | #define C0_ErrCtl $26 | ||
1711 | #define R_C0_ErrCtl 26 | ||
1712 | #define C0_ECC $26 /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1713 | #define R_C0_ECC 26 /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1714 | |||
1715 | #define M_ErrCtl0Fields 0x00000000 | ||
1716 | #define M_ErrCtlRFields 0x00000000 | ||
1717 | |||
1718 | |||
1719 | /* | ||
1720 | ************************************************************************ | ||
1721 | * C A C H E E R R R E G I S T E R ( 2 7 ) * CacheErr | ||
1722 | ************************************************************************ | ||
1723 | * | ||
1724 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1725 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1726 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1727 | * | Cache Error Control | CacheErr | ||
1728 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1729 | */ | ||
1730 | |||
1731 | #define C0_CacheErr $27 | ||
1732 | #define R_C0_CacheErr 27 | ||
1733 | #define C0_CACHE_ERR C0_CacheErr /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1734 | |||
1735 | #define M_CacheErr0Fields 0x00000000 | ||
1736 | #define M_CachErrRFields 0x00000000 | ||
1737 | |||
1738 | |||
1739 | /* | ||
1740 | ************************************************************************ | ||
1741 | * T A G L O R E G I S T E R ( 2 8 ) * TagLo | ||
1742 | ************************************************************************ | ||
1743 | * | ||
1744 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1745 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1746 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1747 | * | TagLo | TagLo | ||
1748 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1749 | */ | ||
1750 | |||
1751 | #define C0_TagLo $28 | ||
1752 | #define R_C0_TagLo 28 | ||
1753 | #define C0_TAGLO C0_TagLo /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1754 | |||
1755 | /* | ||
1756 | * Some implementations use separate TagLo registers for the | ||
1757 | * instruction and data caches. In those cases, the following | ||
1758 | * definitions can be used in relevant code | ||
1759 | */ | ||
1760 | |||
1761 | #define C0_ITagLo $28,0 | ||
1762 | #define C0_DTagLo $28,2 | ||
1763 | |||
1764 | #define M_TagLo0Fields 0x00000000 | ||
1765 | #define M_TagLoRFields 0x00000000 | ||
1766 | |||
1767 | |||
1768 | /* | ||
1769 | ************************************************************************ | ||
1770 | * D A T A L O R E G I S T E R ( 2 8, SELECT 1 ) * DataLo | ||
1771 | ************************************************************************ | ||
1772 | * | ||
1773 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1774 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1775 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1776 | * | DataLo | DataLo | ||
1777 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1778 | */ | ||
1779 | |||
1780 | #define C0_DataLo $28,1 | ||
1781 | #define R_C0_DataLo 28 | ||
1782 | |||
1783 | /* | ||
1784 | * Some implementations use separate DataLo registers for the | ||
1785 | * instruction and data caches. In those cases, the following | ||
1786 | * definitions can be used in relevant code | ||
1787 | */ | ||
1788 | |||
1789 | #define C0_IDataLo $28,1 | ||
1790 | #define C0_DDataLo $28,3 | ||
1791 | |||
1792 | #define M_DataLo0Fields 0x00000000 | ||
1793 | #define M_DataLoRFields 0xffffffff | ||
1794 | |||
1795 | |||
1796 | /* | ||
1797 | ************************************************************************ | ||
1798 | * T A G H I R E G I S T E R ( 2 9 ) * TagHi | ||
1799 | ************************************************************************ | ||
1800 | * | ||
1801 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1802 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1803 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1804 | * | TagHi | TagHi | ||
1805 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1806 | */ | ||
1807 | |||
1808 | #define C0_TagHi $29 | ||
1809 | #define R_C0_TagHi 29 | ||
1810 | #define C0_TAGHI C0_TagHi /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1811 | |||
1812 | /* | ||
1813 | * Some implementations use separate TagHi registers for the | ||
1814 | * instruction and data caches. In those cases, the following | ||
1815 | * definitions can be used in relevant code | ||
1816 | */ | ||
1817 | |||
1818 | #define C0_ITagHi $29,0 | ||
1819 | #define C0_DTagHi $29,2 | ||
1820 | |||
1821 | #define M_TagHi0Fields 0x00000000 | ||
1822 | #define M_TagHiRFields 0x00000000 | ||
1823 | |||
1824 | |||
1825 | /* | ||
1826 | ************************************************************************ | ||
1827 | * D A T A H I R E G I S T E R ( 2 9, SELECT 1 ) * DataHi | ||
1828 | ************************************************************************ | ||
1829 | * | ||
1830 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1831 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1832 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1833 | * | DataHi | DataHi | ||
1834 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1835 | */ | ||
1836 | |||
1837 | #define C0_DataHi $29,1 | ||
1838 | #define R_C0_DataHi 29 | ||
1839 | |||
1840 | /* | ||
1841 | * Some implementations use separate DataHi registers for the | ||
1842 | * instruction and data caches. In those cases, the following | ||
1843 | * definitions can be used in relevant code | ||
1844 | */ | ||
1845 | |||
1846 | #define C0_IDataHi $29,1 | ||
1847 | #define C0_DDataHi $29,3 | ||
1848 | |||
1849 | #define M_DataHi0Fields 0x00000000 | ||
1850 | #define M_DataHiRFields 0xffffffff | ||
1851 | |||
1852 | |||
1853 | /* | ||
1854 | ************************************************************************ | ||
1855 | * E R R O R E P C R E G I S T E R ( 3 0 ) * | ||
1856 | ************************************************************************ | ||
1857 | * | ||
1858 | * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1859 | * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1860 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1861 | * | // Error PC | ErrorEPC | ||
1862 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1863 | */ | ||
1864 | |||
1865 | #define C0_ErrorEPC $30 | ||
1866 | #define R_C0_ErrorEPC 30 | ||
1867 | #define C0_ERROR_EPC C0_ErrorEPC /* OBSOLETE - DO NOT USE IN NEW CODE */ | ||
1868 | |||
1869 | #define M_ErrorEPC0Fields 0x00000000 | ||
1870 | #define M_ErrorEPCRFields 0x00000000 | ||
1871 | #define M_ErrorEPC0Fields64 UNS64Const(0x0000000000000000) | ||
1872 | #define M_ErrorEPCRFields64 UNS64Const(0x0000000000000000) | ||
1873 | |||
1874 | |||
1875 | /* | ||
1876 | ************************************************************************ | ||
1877 | * D E S A V E R E G I S T E R ( 3 1 ) * | ||
1878 | ************************************************************************ | ||
1879 | * | ||
1880 | * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
1881 | * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
1882 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1883 | * | // EJTAG Register Save Value | DESAVE | ||
1884 | * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
1885 | */ | ||
1886 | |||
1887 | #define C0_DESAVE $31 | ||
1888 | #define R_C0_DESAVE 31 | ||
1889 | |||
1890 | #define M_DESAVE0Fields 0x00000000 | ||
1891 | #define M_DESAVERFields 0x00000000 | ||
1892 | #define M_DESAVE0Fields64 UNS64Const(0x0000000000000000) | ||
1893 | #define M_DESAVERFields64 UNS64Const(0x0000000000000000) | ||
1894 | |||
1895 | |||
1896 | /* | ||
1897 | ************************************************************************* | ||
1898 | * C P 1 R E G I S T E R D E F I N I T I O N S * | ||
1899 | ************************************************************************* | ||
1900 | */ | ||
1901 | |||
1902 | |||
1903 | /* | ||
1904 | ************************************************************************* | ||
1905 | * H A R D W A R E F P R N A M E S * | ||
1906 | ************************************************************************* | ||
1907 | */ | ||
1908 | |||
1909 | #define fp0 $f0 | ||
1910 | #define fp1 $f1 | ||
1911 | #define fp2 $f2 | ||
1912 | #define fp3 $f3 | ||
1913 | #define fp4 $f4 | ||
1914 | #define fp5 $f5 | ||
1915 | #define fp6 $f6 | ||
1916 | #define fp7 $f7 | ||
1917 | #define fp8 $f8 | ||
1918 | #define fp9 $f9 | ||
1919 | #define fp10 $f10 | ||
1920 | #define fp11 $f11 | ||
1921 | #define fp12 $f12 | ||
1922 | #define fp13 $f13 | ||
1923 | #define fp14 $f14 | ||
1924 | #define fp15 $f15 | ||
1925 | #define fp16 $f16 | ||
1926 | #define fp17 $f17 | ||
1927 | #define fp18 $f18 | ||
1928 | #define fp19 $f19 | ||
1929 | #define fp20 $f20 | ||
1930 | #define fp21 $f21 | ||
1931 | #define fp22 $f22 | ||
1932 | #define fp23 $f23 | ||
1933 | #define fp24 $f24 | ||
1934 | #define fp25 $f25 | ||
1935 | #define fp26 $f26 | ||
1936 | #define fp27 $f27 | ||
1937 | #define fp28 $f28 | ||
1938 | #define fp29 $f29 | ||
1939 | #define fp30 $f30 | ||
1940 | #define fp31 $f31 | ||
1941 | |||
1942 | /* | ||
1943 | * The following definitions are used to convert an FPR name | ||
1944 | * into the corresponding even or odd name, respectively. | ||
1945 | * This is used in macro substitution in the AVPs. | ||
1946 | */ | ||
1947 | |||
1948 | #define fp1_even $f0 | ||
1949 | #define fp3_even $f2 | ||
1950 | #define fp5_even $f4 | ||
1951 | #define fp7_even $f6 | ||
1952 | #define fp9_even $f8 | ||
1953 | #define fp11_even $f10 | ||
1954 | #define fp13_even $f12 | ||
1955 | #define fp15_even $f14 | ||
1956 | #define fp17_even $f16 | ||
1957 | #define fp19_even $f18 | ||
1958 | #define fp21_even $f20 | ||
1959 | #define fp23_even $f22 | ||
1960 | #define fp25_even $f24 | ||
1961 | #define fp27_even $f26 | ||
1962 | #define fp29_even $f28 | ||
1963 | #define fp31_even $f30 | ||
1964 | |||
1965 | #define fp0_odd $f1 | ||
1966 | #define fp2_odd $f3 | ||
1967 | #define fp4_odd $f5 | ||
1968 | #define fp6_odd $f7 | ||
1969 | #define fp8_odd $f9 | ||
1970 | #define fp10_odd $f11 | ||
1971 | #define fp12_odd $f13 | ||
1972 | #define fp14_odd $f15 | ||
1973 | #define fp16_odd $f17 | ||
1974 | #define fp18_odd $f19 | ||
1975 | #define fp20_odd $f21 | ||
1976 | #define fp22_odd $f23 | ||
1977 | #define fp24_odd $f25 | ||
1978 | #define fp26_odd $f27 | ||
1979 | #define fp28_odd $f29 | ||
1980 | #define fp30_odd $f31 | ||
1981 | |||
1982 | |||
1983 | /* | ||
1984 | ************************************************************************* | ||
1985 | * H A R D W A R E F P R I N D I C E S * | ||
1986 | ************************************************************************* | ||
1987 | * | ||
1988 | * These definitions provide the index (number) of the FPR, as opposed | ||
1989 | * to the assembler register name ($n). | ||
1990 | */ | ||
1991 | |||
1992 | #define R_fp0 0 | ||
1993 | #define R_fp1 1 | ||
1994 | #define R_fp2 2 | ||
1995 | #define R_fp3 3 | ||
1996 | #define R_fp4 4 | ||
1997 | #define R_fp5 5 | ||
1998 | #define R_fp6 6 | ||
1999 | #define R_fp7 7 | ||
2000 | #define R_fp8 8 | ||
2001 | #define R_fp9 9 | ||
2002 | #define R_fp10 10 | ||
2003 | #define R_fp11 11 | ||
2004 | #define R_fp12 12 | ||
2005 | #define R_fp13 13 | ||
2006 | #define R_fp14 14 | ||
2007 | #define R_fp15 15 | ||
2008 | #define R_fp16 16 | ||
2009 | #define R_fp17 17 | ||
2010 | #define R_fp18 18 | ||
2011 | #define R_fp19 19 | ||
2012 | #define R_fp20 20 | ||
2013 | #define R_fp21 21 | ||
2014 | #define R_fp22 22 | ||
2015 | #define R_fp23 23 | ||
2016 | #define R_fp24 24 | ||
2017 | #define R_fp25 25 | ||
2018 | #define R_fp26 26 | ||
2019 | #define R_fp27 27 | ||
2020 | #define R_fp28 28 | ||
2021 | #define R_fp29 29 | ||
2022 | #define R_fp30 30 | ||
2023 | #define R_fp31 31 | ||
2024 | |||
2025 | |||
2026 | /* | ||
2027 | ************************************************************************* | ||
2028 | * H A R D W A R E F C R N A M E S * | ||
2029 | ************************************************************************* | ||
2030 | */ | ||
2031 | |||
2032 | #define fc0 $0 | ||
2033 | #define fc25 $25 | ||
2034 | #define fc26 $26 | ||
2035 | #define fc28 $28 | ||
2036 | #define fc31 $31 | ||
2037 | |||
2038 | |||
2039 | /* | ||
2040 | ************************************************************************* | ||
2041 | * H A R D W A R E F C R I N D I C E S * | ||
2042 | ************************************************************************* | ||
2043 | * | ||
2044 | * These definitions provide the index (number) of the FCR, as opposed | ||
2045 | * to the assembler register name ($n). | ||
2046 | */ | ||
2047 | |||
2048 | #define R_fc0 0 | ||
2049 | #define R_fc25 25 | ||
2050 | #define R_fc26 26 | ||
2051 | #define R_fc28 28 | ||
2052 | #define R_fc31 31 | ||
2053 | |||
2054 | |||
2055 | /* | ||
2056 | ************************************************************************* | ||
2057 | * H A R D W A R E F C C N A M E S * | ||
2058 | ************************************************************************* | ||
2059 | */ | ||
2060 | |||
2061 | #define cc0 $fcc0 | ||
2062 | #define cc1 $fcc1 | ||
2063 | #define cc2 $fcc2 | ||
2064 | #define cc3 $fcc3 | ||
2065 | #define cc4 $fcc4 | ||
2066 | #define cc5 $fcc5 | ||
2067 | #define cc6 $fcc6 | ||
2068 | #define cc7 $fcc7 | ||
2069 | |||
2070 | |||
2071 | /* | ||
2072 | ************************************************************************* | ||
2073 | * H A R D W A R E F C C I N D I C E S * | ||
2074 | ************************************************************************* | ||
2075 | * | ||
2076 | * These definitions provide the index (number) of the CC, as opposed | ||
2077 | * to the assembler register name ($n). | ||
2078 | */ | ||
2079 | |||
2080 | #define R_cc0 0 | ||
2081 | #define R_cc1 1 | ||
2082 | #define R_cc2 2 | ||
2083 | #define R_cc3 3 | ||
2084 | #define R_cc4 4 | ||
2085 | #define R_cc5 5 | ||
2086 | #define R_cc6 6 | ||
2087 | #define R_cc7 7 | ||
2088 | |||
2089 | |||
2090 | /* | ||
2091 | ************************************************************************ | ||
2092 | * I M P L E M E N T A T I O N R E G I S T E R * | ||
2093 | ************************************************************************ | ||
2094 | * | ||
2095 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
2096 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
2097 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
2098 | * |Reserved for Additional|3|P|D|S| Implementation| Revision | FIR | ||
2099 | * | Configuration Bits |D|S| | | | | | ||
2100 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
2101 | */ | ||
2102 | |||
2103 | #define C1_FIR $0 | ||
2104 | #define R_C1_FIR 0 | ||
2105 | |||
2106 | #define S_FIRConfigS 16 | ||
2107 | #define M_FIRConfigS (0x1 << S_FIRConfigS) | ||
2108 | #define S_FIRConfigD 17 | ||
2109 | #define M_FIRConfigD (0x1 << S_FIRConfigD) | ||
2110 | #define S_FIRConfigPS 18 | ||
2111 | #define M_FIRConfigPS (0x1 << S_FIRConfigPS) | ||
2112 | #define S_FIRConfig3D 19 | ||
2113 | #define M_FIRConfig3D (0x1 << S_FIRConfig3D) | ||
2114 | #define M_FIRConfigAll (M_FIRConfigS|M_FIRConfigD|M_FIRConfigPS|M_FIRConfig3D) | ||
2115 | |||
2116 | #define S_FIRImp 8 | ||
2117 | #define M_FIRImp (0xff << S_FIRImp) | ||
2118 | |||
2119 | #define S_FIRRev 0 | ||
2120 | #define M_FIRRev (0xff << S_FIRRev) | ||
2121 | |||
2122 | #define M_FIR0Fields 0xfff00000 | ||
2123 | #define M_FIRRFields 0x000fffff | ||
2124 | |||
2125 | /* | ||
2126 | ************************************************************************ | ||
2127 | * C O N D I T I O N C O D E S R E G I S T E R * | ||
2128 | ************************************************************************ | ||
2129 | * | ||
2130 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
2131 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
2132 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
2133 | * | 0 | CC | FCCR | ||
2134 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
2135 | */ | ||
2136 | |||
2137 | #define C1_FCCR $25 | ||
2138 | #define R_C1_FCCR 25 | ||
2139 | |||
2140 | #define S_FCCRCC 0 | ||
2141 | #define M_FCCRCC (0xff << S_FCCRCC) | ||
2142 | #define S_FCCRCC7 7 | ||
2143 | #define M_FCCRCC7 (0x1 << S_FCCRCC7) | ||
2144 | #define S_FCCRCC6 6 | ||
2145 | #define M_FCCRCC6 (0x1 << S_FCCRCC6) | ||
2146 | #define S_FCCRCC5 5 | ||
2147 | #define M_FCCRCC5 (0x1 << S_FCCRCC5) | ||
2148 | #define S_FCCRCC4 4 | ||
2149 | #define M_FCCRCC4 (0x1 << S_FCCRCC4) | ||
2150 | #define S_FCCRCC3 3 | ||
2151 | #define M_FCCRCC3 (0x1 << S_FCCRCC3) | ||
2152 | #define S_FCCRCC2 2 | ||
2153 | #define M_FCCRCC2 (0x1 << S_FCCRCC2) | ||
2154 | #define S_FCCRCC1 1 | ||
2155 | #define M_FCCRCC1 (0x1 << S_FCCRCC1) | ||
2156 | #define S_FCCRCC0 0 | ||
2157 | #define M_FCCRCC0 (0x1 << S_FCCRCC0) | ||
2158 | |||
2159 | #define M_FCCR0Fields 0xffffff00 | ||
2160 | #define M_FCCRRFields 0x000000ff | ||
2161 | |||
2162 | |||
2163 | /* | ||
2164 | ************************************************************************ | ||
2165 | * E X C E P T I O N S R E G I S T E R * | ||
2166 | ************************************************************************ | ||
2167 | * | ||
2168 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
2169 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
2170 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
2171 | * | 0 | Cause | 0 | Flags | 0 | FEXR | ||
2172 | * | |E|V|Z|O|U|I| |V|Z|O|U|I| | | ||
2173 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
2174 | */ | ||
2175 | |||
2176 | #define C1_FEXR $26 | ||
2177 | #define R_C1_FEXR 26 | ||
2178 | |||
2179 | #define S_FEXRExc 12 | ||
2180 | #define M_FEXRExc (0x3f << S_FEXRExc) | ||
2181 | #define S_FEXRExcE 17 | ||
2182 | #define M_FEXRExcE (0x1 << S_FEXRExcE) | ||
2183 | #define S_FEXRExcV 16 | ||
2184 | #define M_FEXRExcV (0x1 << S_FEXRExcV) | ||
2185 | #define S_FEXRExcZ 15 | ||
2186 | #define M_FEXRExcZ (0x1 << S_FEXRExcZ) | ||
2187 | #define S_FEXRExcO 14 | ||
2188 | #define M_FEXRExcO (0x1 << S_FEXRExcO) | ||
2189 | #define S_FEXRExcU 13 | ||
2190 | #define M_FEXRExcU (0x1 << S_FEXRExcU) | ||
2191 | #define S_FEXRExcI 12 | ||
2192 | #define M_FEXRExcI (0x1 << S_FEXRExcI) | ||
2193 | |||
2194 | #define S_FEXRFlg 2 | ||
2195 | #define M_FEXRFlg (0x1f << S_FEXRFlg) | ||
2196 | #define S_FEXRFlgV 6 | ||
2197 | #define M_FEXRFlgV (0x1 << S_FEXRFlgV) | ||
2198 | #define S_FEXRFlgZ 5 | ||
2199 | #define M_FEXRFlgZ (0x1 << S_FEXRFlgZ) | ||
2200 | #define S_FEXRFlgO 4 | ||
2201 | #define M_FEXRFlgO (0x1 << S_FEXRFlgO) | ||
2202 | #define S_FEXRFlgU 3 | ||
2203 | #define M_FEXRFlgU (0x1 << S_FEXRFlgU) | ||
2204 | #define S_FEXRFlgI 2 | ||
2205 | #define M_FEXRFlgI (0x1 << S_FEXRFlgI) | ||
2206 | |||
2207 | #define M_FEXR0Fields 0xfffc0f83 | ||
2208 | #define M_FEXRRFields 0x00000000 | ||
2209 | |||
2210 | |||
2211 | /* | ||
2212 | ************************************************************************ | ||
2213 | * E N A B L E S R E G I S T E R * | ||
2214 | ************************************************************************ | ||
2215 | * | ||
2216 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
2217 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
2218 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
2219 | * | 0 | Enables | 0 |F|RM | FENR | ||
2220 | * | |V|Z|O|U|I| |S| | | ||
2221 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
2222 | */ | ||
2223 | |||
2224 | #define C1_FENR $28 | ||
2225 | #define R_C1_FENR 28 | ||
2226 | |||
2227 | #define S_FENREna 7 | ||
2228 | #define M_FENREna (0x1f << S_FENREna) | ||
2229 | #define S_FENREnaV 11 | ||
2230 | #define M_FENREnaV (0x1 << S_FENREnaV) | ||
2231 | #define S_FENREnaZ 10 | ||
2232 | #define M_FENREnaZ (0x1 << S_FENREnaZ) | ||
2233 | #define S_FENREnaO 9 | ||
2234 | #define M_FENREnaO (0x1 << S_FENREnaO) | ||
2235 | #define S_FENREnaU 8 | ||
2236 | #define M_FENREnaU (0x1 << S_FENREnaU) | ||
2237 | #define S_FENREnaI 7 | ||
2238 | #define M_FENREnaI (0x1 << S_FENREnaI) | ||
2239 | |||
2240 | #define S_FENRFS 2 | ||
2241 | #define M_FENRFS (0x1 << S_FENRFS) | ||
2242 | |||
2243 | #define S_FENRRM 0 | ||
2244 | #define M_FENRRM (0x3 << S_FENRRM) | ||
2245 | |||
2246 | #define M_FENR0Fields 0xfffff078 | ||
2247 | #define M_FENRRFields 0x00000000 | ||
2248 | |||
2249 | |||
2250 | /* | ||
2251 | ************************************************************************ | ||
2252 | * C O N T R O L / S T A T U S R E G I S T E R * | ||
2253 | ************************************************************************ | ||
2254 | * | ||
2255 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | ||
2256 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | ||
2257 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
2258 | * | FCC |F|C|Imp| 0 | Cause | Enables | Flags | RM| FCSR | ||
2259 | * |7|6|5|4|3|2|1|S|C| | |E|V|Z|O|U|I|V|Z|O|U|I|V|Z|O|U|I| | | ||
2260 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | ||
2261 | */ | ||
2262 | |||
2263 | #define C1_FCSR $31 | ||
2264 | #define R_C1_FCSR 31 | ||
2265 | |||
2266 | #define S_FCSRFCC7_1 25 /* Floating point condition codes 7..1 (R/W) */ | ||
2267 | #define M_FCSRFCC7_1 (0x7f << S_FCSRFCC7_1) | ||
2268 | #define S_FCSRCC7 31 | ||
2269 | #define M_FCSRCC7 (0x1 << S_FCSRCC7) | ||
2270 | #define S_FCSRCC6 30 | ||
2271 | #define M_FCSRCC6 (0x1 << S_FCSRCC6) | ||
2272 | #define S_FCSRCC5 29 | ||
2273 | #define M_FCSRCC5 (0x1 << S_FCSRCC5) | ||
2274 | #define S_FCSRCC4 28 | ||
2275 | #define M_FCSRCC4 (0x1 << S_FCSRCC4) | ||
2276 | #define S_FCSRCC3 27 | ||
2277 | #define M_FCSRCC3 (0x1 << S_FCSRCC3) | ||
2278 | #define S_FCSRCC2 26 | ||
2279 | #define M_FCSRCC2 (0x1 << S_FCSRCC2) | ||
2280 | #define S_FCSRCC1 25 | ||
2281 | #define M_FCSRCC1 (0x1 << S_FCSRCC1) | ||
2282 | |||
2283 | #define S_FCSRFS 24 /* Flush denorms to zero (R/W) */ | ||
2284 | #define M_FCSRFS (0x1 << S_FCSRFS) | ||
2285 | |||
2286 | #define S_FCSRCC0 23 /* Floating point condition code 0 (R/W) */ | ||
2287 | #define M_FCSRCC0 (0x1 << S_FCSRCC0) | ||
2288 | #define S_FCSRCC S_FCSRCC0 | ||
2289 | #define M_FCSRCC M_FCSRCC0 | ||
2290 | |||
2291 | #define S_FCSRImpl 21 /* Implementation-specific control bits (R/W) */ | ||
2292 | #define M_FCSRImpl (0x3 << S_FCSRImpl) | ||
2293 | |||
2294 | #define S_FCSRExc 12 /* Exception cause (R/W) */ | ||
2295 | #define M_FCSRExc (0x3f << S_FCSRExc) | ||
2296 | #define S_FCSRExcE 17 | ||
2297 | #define M_FCSRExcE (0x1 << S_FCSRExcE) | ||
2298 | #define S_FCSRExcV 16 | ||
2299 | #define M_FCSRExcV (0x1 << S_FCSRExcV) | ||
2300 | #define S_FCSRExcZ 15 | ||
2301 | #define M_FCSRExcZ (0x1 << S_FCSRExcZ) | ||
2302 | #define S_FCSRExcO 14 | ||
2303 | #define M_FCSRExcO (0x1 << S_FCSRExcO) | ||
2304 | #define S_FCSRExcU 13 | ||
2305 | #define M_FCSRExcU (0x1 << S_FCSRExcU) | ||
2306 | #define S_FCSRExcI 12 | ||
2307 | #define M_FCSRExcI (0x1 << S_FCSRExcI) | ||
2308 | |||
2309 | #define S_FCSREna 7 /* Exception enable (R/W) */ | ||
2310 | #define M_FCSREna (0x1f << S_FCSREna) | ||
2311 | #define S_FCSREnaV 11 | ||
2312 | #define M_FCSREnaV (0x1 << S_FCSREnaV) | ||
2313 | #define S_FCSREnaZ 10 | ||
2314 | #define M_FCSREnaZ (0x1 << S_FCSREnaZ) | ||
2315 | #define S_FCSREnaO 9 | ||
2316 | #define M_FCSREnaO (0x1 << S_FCSREnaO) | ||
2317 | #define S_FCSREnaU 8 | ||
2318 | #define M_FCSREnaU (0x1 << S_FCSREnaU) | ||
2319 | #define S_FCSREnaI 7 | ||
2320 | #define M_FCSREnaI (0x1 << S_FCSREnaI) | ||
2321 | |||
2322 | #define S_FCSRFlg 2 /* Exception flags (R/W) */ | ||
2323 | #define M_FCSRFlg (0x1f << S_FCSRFlg) | ||
2324 | #define S_FCSRFlgV 6 | ||
2325 | #define M_FCSRFlgV (0x1 << S_FCSRFlgV) | ||
2326 | #define S_FCSRFlgZ 5 | ||
2327 | #define M_FCSRFlgZ (0x1 << S_FCSRFlgZ) | ||
2328 | #define S_FCSRFlgO 4 | ||
2329 | #define M_FCSRFlgO (0x1 << S_FCSRFlgO) | ||
2330 | #define S_FCSRFlgU 3 | ||
2331 | #define M_FCSRFlgU (0x1 << S_FCSRFlgU) | ||
2332 | #define S_FCSRFlgI 2 | ||
2333 | #define M_FCSRFlgI (0x1 << S_FCSRFlgI) | ||
2334 | |||
2335 | #define S_FCSRRM 0 /* Rounding mode (R/W) */ | ||
2336 | #define M_FCSRRM (0x3 << S_FCSRRM) | ||
2337 | |||
2338 | #define M_FCSR0Fields 0x001c0000 | ||
2339 | #define M_FCSRRFields 0x00000000 | ||
2340 | |||
2341 | /* | ||
2342 | * Values in the rounding mode field (of both FCSR and FCCR) | ||
2343 | */ | ||
2344 | #define K_FCSRRM_RN 0 | ||
2345 | #define K_FCSRRM_RZ 1 | ||
2346 | #define K_FCSRRM_RP 2 | ||
2347 | #define K_FCSRRM_RM 3 | ||
2348 | |||
2349 | |||
2350 | /* ********************************************************************* */ | ||
2351 | /* Interface function definition */ | ||
2352 | |||
2353 | |||
2354 | /* ********************************************************************* */ | ||
2355 | |||
2356 | #endif /* __ARCHDEFS_H__ */ | ||
diff --git a/utils/atj2137/adfuload/test_binary/timer_no_irq/mips.h b/utils/atj2137/adfuload/test_binary/timer_no_irq/mips.h new file mode 100644 index 0000000000..aef7bc9dd2 --- /dev/null +++ b/utils/atj2137/adfuload/test_binary/timer_no_irq/mips.h | |||
@@ -0,0 +1,820 @@ | |||
1 | /************************************************************************** | ||
2 | * * | ||
3 | * PROJECT : MIPS port for uC/OS-II * | ||
4 | * * | ||
5 | * MODULE : MIPS.h * | ||
6 | * * | ||
7 | * AUTHOR : Michael Anburaj * | ||
8 | * URL : http://geocities.com/michaelanburaj/ * | ||
9 | * EMAIL: michaelanburaj@hotmail.com * | ||
10 | * * | ||
11 | * PROCESSOR : MIPS 4Kc (32 bit RISC) - ATLAS board * | ||
12 | * * | ||
13 | * TOOL-CHAIN : SDE & Cygnus * | ||
14 | * * | ||
15 | * DESCRIPTION : * | ||
16 | * MIPS processor definitions. * | ||
17 | * The basic CPU definitions are found in the file archdefs.h, which * | ||
18 | * is included by mips.h. * | ||
19 | * * | ||
20 | * mips.h implements aliases for some of the definitions in archdefs.h * | ||
21 | * and adds various definitions. * | ||
22 | * * | ||
23 | **************************************************************************/ | ||
24 | |||
25 | |||
26 | #ifndef __MIPS_H__ | ||
27 | #define __MIPS_H__ | ||
28 | |||
29 | #include "mips-archdefs.h" | ||
30 | |||
31 | |||
32 | /* ********************************************************************* */ | ||
33 | /* Module configuration */ | ||
34 | |||
35 | |||
36 | /* ********************************************************************* */ | ||
37 | /* Interface macro & data definition */ | ||
38 | |||
39 | #ifndef MSK | ||
40 | #define MSK(n) ((1 << (n)) - 1) | ||
41 | #endif | ||
42 | |||
43 | /* CPU registers */ | ||
44 | #define SYS_CPUREG_ZERO 0 | ||
45 | #define SYS_CPUREG_AT 1 | ||
46 | #define SYS_CPUREG_V0 2 | ||
47 | #define SYS_CPUREG_V1 3 | ||
48 | #define SYS_CPUREG_A0 4 | ||
49 | #define SYS_CPUREG_A1 5 | ||
50 | #define SYS_CPUREG_A2 6 | ||
51 | #define SYS_CPUREG_A3 7 | ||
52 | #define SYS_CPUREG_T0 8 | ||
53 | #define SYS_CPUREG_T1 9 | ||
54 | #define SYS_CPUREG_T2 10 | ||
55 | #define SYS_CPUREG_T3 11 | ||
56 | #define SYS_CPUREG_T4 12 | ||
57 | #define SYS_CPUREG_T5 13 | ||
58 | #define SYS_CPUREG_T6 14 | ||
59 | #define SYS_CPUREG_T7 15 | ||
60 | #define SYS_CPUREG_S0 16 | ||
61 | #define SYS_CPUREG_S1 17 | ||
62 | #define SYS_CPUREG_S2 18 | ||
63 | #define SYS_CPUREG_S3 19 | ||
64 | #define SYS_CPUREG_S4 20 | ||
65 | #define SYS_CPUREG_S5 21 | ||
66 | #define SYS_CPUREG_S6 22 | ||
67 | #define SYS_CPUREG_S7 23 | ||
68 | #define SYS_CPUREG_T8 24 | ||
69 | #define SYS_CPUREG_T9 25 | ||
70 | #define SYS_CPUREG_K0 26 | ||
71 | #define SYS_CPUREG_K1 27 | ||
72 | #define SYS_CPUREG_GP 28 | ||
73 | #define SYS_CPUREG_SP 29 | ||
74 | #define SYS_CPUREG_S8 30 | ||
75 | #define SYS_CPUREG_FP SYS_CPUREG_S8 | ||
76 | #define SYS_CPUREG_RA 31 | ||
77 | |||
78 | |||
79 | /* CPU register fp ($30) has an alias s8 */ | ||
80 | #define s8 fp | ||
81 | |||
82 | |||
83 | /* Aliases for System Control Coprocessor (CP0) registers */ | ||
84 | #define C0_INDEX C0_Index | ||
85 | #define C0_RANDOM C0_Random | ||
86 | #define C0_ENTRYLO0 C0_EntryLo0 | ||
87 | #define C0_ENTRYLO1 C0_EntryLo1 | ||
88 | #define C0_CONTEXT C0_Context | ||
89 | #define C0_PAGEMASK C0_PageMask | ||
90 | #define C0_WIRED C0_Wired | ||
91 | #define C0_BADVADDR C0_BadVAddr | ||
92 | #define C0_COUNT C0_Count | ||
93 | #define C0_ENTRYHI C0_EntryHi | ||
94 | #define C0_COMPARE C0_Compare | ||
95 | #define C0_STATUS C0_Status | ||
96 | #define C0_CAUSE C0_Cause | ||
97 | |||
98 | #ifdef C0_PRID /* ArchDefs has an obsolete def. of C0_PRID */ | ||
99 | #undef C0_PRID | ||
100 | #endif | ||
101 | #define C0_PRID C0_PRId | ||
102 | |||
103 | #define C0_CONFIG C0_Config | ||
104 | #define C0_CONFIG1 C0_Config1 | ||
105 | #define C0_LLADDR C0_LLAddr | ||
106 | #define C0_WATCHLO C0_WatchLo | ||
107 | #define C0_WATCHHI C0_WatchHi | ||
108 | #define C0_DEBUG C0_Debug | ||
109 | #define C0_PERFCNT C0_PerfCnt | ||
110 | #define C0_ERRCTL C0_ErrCtl | ||
111 | #define C0_CACHEERR C0_CacheErr | ||
112 | #define C0_TAGLO C0_TagLo | ||
113 | #define C0_DATALO C0_DataLo | ||
114 | #define C0_TAGHI C0_TagHi | ||
115 | #define C0_DATAHI C0_DataHi | ||
116 | #define C0_ERROREPC C0_ErrorEPC | ||
117 | #if 0 | ||
118 | #define C0_DESAVE C0_DESAVE | ||
119 | #define C0_EPC C0_EPC | ||
120 | #define C0_DEPC C0_DEPC | ||
121 | #endif | ||
122 | |||
123 | /* System Control Coprocessor (CP0) registers select fields */ | ||
124 | #define C0_INDEX_SEL 0 /* TLB Index */ | ||
125 | #define C0_RANDOM_SEL 0 /* TLB Random */ | ||
126 | #define C0_TLBLO0_SEL 0 /* TLB EntryLo0 */ | ||
127 | #define C0_TLBLO1_SEL 0 /* TLB EntryLo1 */ | ||
128 | #define C0_CONTEXT_SEL 0 /* Context */ | ||
129 | #define C0_PAGEMASK_SEL 0 /* TLB PageMask */ | ||
130 | #define C0_WIRED_SEL 0 /* TLB Wired */ | ||
131 | #define C0_BADVADDR_SEL 0 /* Bad Virtual Address */ | ||
132 | #define C0_COUNT_SEL 0 /* Count */ | ||
133 | #define C0_ENTRYHI_SEL 0 /* TLB EntryHi */ | ||
134 | #define C0_COMPARE_SEL 0 /* Compare */ | ||
135 | #define C0_STATUS_SEL 0 /* Processor Status */ | ||
136 | #define C0_CAUSE_SEL 0 /* Exception Cause */ | ||
137 | #define C0_EPC_SEL 0 /* Exception PC */ | ||
138 | #define C0_PRID_SEL 0 /* Processor Revision Indentifier */ | ||
139 | #define C0_CONFIG_SEL 0 /* Config */ | ||
140 | #define C0_CONFIG1_SEL 1 /* Config1 */ | ||
141 | #define C0_LLADDR_SEL 0 /* LLAddr */ | ||
142 | #define C0_WATCHLO_SEL 0 /* WatchpointLo */ | ||
143 | #define C0_WATCHHI_SEL 0 /* WatchpointHi */ | ||
144 | #define C0_DEBUG_SEL 0 /* EJTAG Debug Register */ | ||
145 | #define C0_DEPC_SEL 0 /* Program counter at last EJTAG debug exception */ | ||
146 | #define C0_PERFCNT_SEL 0 /* Performance counter interface */ | ||
147 | #define C0_ERRCTL_SEL 0 /* ERRCTL */ | ||
148 | #define C0_CACHEERR_SEL 0 /* CacheErr */ | ||
149 | #define C0_TAGLO_SEL 0 /* TagLo */ | ||
150 | #define C0_DATALO_SEL 1 /* DataLo */ | ||
151 | #define C0_DTAGLO_SEL 2 /* DTagLo */ | ||
152 | #define C0_TAGHI_SEL 0 /* TagHi */ | ||
153 | #define C0_DATAHI_SEL 1 /* DataHi */ | ||
154 | #define C0_DTAGHI_SEL 2 /* DTagHi */ | ||
155 | #define C0_ERROREPC_SEL 0 /* ErrorEPC */ | ||
156 | #define C0_DESAVE_SEL 0 /* EJTAG dbg exc. save register */ | ||
157 | |||
158 | |||
159 | /* C0_CONFIG register encoding */ | ||
160 | |||
161 | #define C0_CONFIG_M_SHF S_ConfigMore | ||
162 | #define C0_CONFIG_M_MSK M_ConfigMore | ||
163 | #define C0_CONFIG_M_BIT C0_CONFIG_M_MSK | ||
164 | |||
165 | #define C0_CONFIG_BE_SHF S_ConfigBE | ||
166 | #define C0_CONFIG_BE_MSK M_ConfigBE | ||
167 | #define C0_CONFIG_BE_BIT C0_CONFIG_BE_MSK | ||
168 | |||
169 | #define C0_CONFIG_AT_SHF S_ConfigAT | ||
170 | #define C0_CONFIG_AT_MSK M_ConfigAT | ||
171 | #define C0_CONFIG_AT_MIPS32 K_ConfigAT_MIPS32 | ||
172 | #define C0_CONFIG_AT_MIPS64_32ADDR K_ConfigAT_MIPS64S | ||
173 | #define C0_CONFIG_AT_MIPS64 K_ConfigAT_MIPS64 | ||
174 | |||
175 | #define C0_CONFIG_AR_SHF S_ConfigAR | ||
176 | #define C0_CONFIG_AR_MSK M_ConfigAR | ||
177 | |||
178 | #define C0_CONFIG_MT_SHF S_ConfigMT | ||
179 | #define C0_CONFIG_MT_MSK M_ConfigMT | ||
180 | #define C0_CONFIG_MT_NONE K_ConfigMT_NoMMU | ||
181 | #define C0_CONFIG_MT_TLB K_ConfigMT_TLBMMU | ||
182 | #define C0_CONFIG_MT_BAT K_ConfigMT_BATMMU | ||
183 | #define C0_CONFIG_MT_NON_STD K_ConfigMT_FMMMU | ||
184 | |||
185 | #define C0_CONFIG_K0_SHF S_ConfigK0 | ||
186 | #define C0_CONFIG_K0_MSK M_ConfigK0 | ||
187 | #define C0_CONFIG_K0_WTHRU_NOALLOC K_CacheAttrCWTnWA | ||
188 | #define C0_CONFIG_K0_WTHRU_ALLOC K_CacheAttrCWTWA | ||
189 | #define C0_CONFIG_K0_UNCACHED K_CacheAttrU | ||
190 | #define C0_CONFIG_K0_NONCOHERENT K_CacheAttrCN | ||
191 | #define C0_CONFIG_K0_COHERENTXCL K_CacheAttrCCE | ||
192 | #define C0_CONFIG_K0_COHERENTXCLW K_CacheAttrCCS | ||
193 | #define C0_CONFIG_K0_COHERENTUPD K_CacheAttrCCU | ||
194 | #define C0_CONFIG_K0_UNCACHED_ACCEL K_CacheAttrUA | ||
195 | |||
196 | |||
197 | /* WC field. | ||
198 | * | ||
199 | * This feature is present specifically to support configuration | ||
200 | * testing of the core in a lead vehicle, and is not supported | ||
201 | * in any other environment. Attempting to use this feature | ||
202 | * outside of the scope of a lead vehicle is a violation of the | ||
203 | * MIPS Architecture, and may cause unpredictable operation of | ||
204 | * the processor. | ||
205 | */ | ||
206 | #define C0_CONFIG_WC_SHF 19 | ||
207 | #define C0_CONFIG_WC_MSK (MSK(1) << C0_CONFIG_WC_SHF) | ||
208 | #define C0_CONFIG_WC_BIT C0_CONFIG_WC_MSK | ||
209 | |||
210 | |||
211 | /* C0_CONFIG1 register encoding */ | ||
212 | |||
213 | #define C0_CONFIG1_MMUSIZE_SHF S_Config1MMUSize | ||
214 | #define C0_CONFIG1_MMUSIZE_MSK M_Config1MMUSize | ||
215 | |||
216 | #define C0_CONFIG1_IS_SHF S_Config1IS | ||
217 | #define C0_CONFIG1_IS_MSK M_Config1IS | ||
218 | |||
219 | #define C0_CONFIG1_IL_SHF S_Config1IL | ||
220 | #define C0_CONFIG1_IL_MSK M_Config1IL | ||
221 | |||
222 | #define C0_CONFIG1_IA_SHF S_Config1IA | ||
223 | #define C0_CONFIG1_IA_MSK M_Config1IA | ||
224 | |||
225 | #define C0_CONFIG1_DS_SHF S_Config1DS | ||
226 | #define C0_CONFIG1_DS_MSK M_Config1DS | ||
227 | |||
228 | #define C0_CONFIG1_DL_SHF S_Config1DL | ||
229 | #define C0_CONFIG1_DL_MSK M_Config1DL | ||
230 | |||
231 | #define C0_CONFIG1_DA_SHF S_Config1DA | ||
232 | #define C0_CONFIG1_DA_MSK M_Config1DA | ||
233 | |||
234 | #define C0_CONFIG1_WR_SHF S_Config1WR | ||
235 | #define C0_CONFIG1_WR_MSK M_Config1WR | ||
236 | #define C0_CONFIG1_WR_BIT C0_CONFIG1_WR_MSK | ||
237 | |||
238 | #define C0_CONFIG1_CA_SHF S_Config1CA | ||
239 | #define C0_CONFIG1_CA_MSK M_Config1CA | ||
240 | #define C0_CONFIG1_CA_BIT C0_CONFIG1_CA_MSK | ||
241 | |||
242 | #define C0_CONFIG1_EP_SHF S_Config1EP | ||
243 | #define C0_CONFIG1_EP_MSK M_Config1EP | ||
244 | #define C0_CONFIG1_EP_BIT C0_CONFIG1_EP_MSK | ||
245 | |||
246 | #define C0_CONFIG1_FP_SHF S_Config1FP | ||
247 | #define C0_CONFIG1_FP_MSK M_Config1FP | ||
248 | #define C0_CONFIG1_FP_BIT C0_CONFIG1_FP_MSK | ||
249 | |||
250 | |||
251 | /* C0_STATUS register encoding */ | ||
252 | |||
253 | #define C0_STATUS_CU3_SHF S_StatusCU3 | ||
254 | #define C0_STATUS_CU3_MSK M_StatusCU3 | ||
255 | #define C0_STATUS_CU3_BIT C0_STATUS_CU3_MSK | ||
256 | |||
257 | #define C0_STATUS_CU2_SHF S_StatusCU2 | ||
258 | #define C0_STATUS_CU2_MSK M_StatusCU2 | ||
259 | #define C0_STATUS_CU2_BIT C0_STATUS_CU2_MSK | ||
260 | |||
261 | #define C0_STATUS_CU1_SHF S_StatusCU1 | ||
262 | #define C0_STATUS_CU1_MSK M_StatusCU1 | ||
263 | #define C0_STATUS_CU1_BIT C0_STATUS_CU1_MSK | ||
264 | |||
265 | #define C0_STATUS_CU0_SHF S_StatusCU1 | ||
266 | #define C0_STATUS_CU0_MSK M_StatusCU1 | ||
267 | #define C0_STATUS_CU0_BIT C0_STATUS_CU0_MSK | ||
268 | |||
269 | #define C0_STATUS_RP_SHF S_StatusRP | ||
270 | #define C0_STATUS_RP_MSK M_StatusRP | ||
271 | #define C0_STATUS_RP_BIT C0_STATUS_RP_MSK | ||
272 | |||
273 | #define C0_STATUS_FR_SHF S_StatusFR | ||
274 | #define C0_STATUS_FR_MSK M_StatusFR | ||
275 | #define C0_STATUS_FR_BIT C0_STATUS_FR_MSK | ||
276 | |||
277 | #define C0_STATUS_RE_SHF S_StatusRE | ||
278 | #define C0_STATUS_RE_MSK M_StatusRE | ||
279 | #define C0_STATUS_RE_BIT C0_STATUS_RE_MSK | ||
280 | |||
281 | #define C0_STATUS_BEV_SHF S_StatusBEV | ||
282 | #define C0_STATUS_BEV_MSK M_StatusBEV | ||
283 | #define C0_STATUS_BEV_BIT C0_STATUS_BEV_MSK | ||
284 | |||
285 | #define C0_STATUS_TS_SHF S_StatusTS | ||
286 | #define C0_STATUS_TS_MSK M_StatusTS | ||
287 | #define C0_STATUS_TS_BIT C0_STATUS_TS_MSK | ||
288 | |||
289 | #define C0_STATUS_SR_SHF S_StatusSR | ||
290 | #define C0_STATUS_SR_MSK M_StatusSR | ||
291 | #define C0_STATUS_SR_BIT C0_STATUS_SR_MSK | ||
292 | |||
293 | #define C0_STATUS_NMI_SHF S_StatusNMI | ||
294 | #define C0_STATUS_NMI_MSK M_StatusNMI | ||
295 | #define C0_STATUS_NMI_BIT C0_STATUS_NMI_MSK | ||
296 | |||
297 | #define C0_STATUS_IM_SHF S_StatusIM | ||
298 | #define C0_STATUS_IM_MSK M_StatusIM | ||
299 | /* Note that the the definitions below indicate the interrupt number | ||
300 | * rather than the mask. | ||
301 | * (0..1 for SW interrupts and 2...7 for HW interrupts) | ||
302 | */ | ||
303 | #define C0_STATUS_IM_SW0 (S_StatusIM0 - S_StatusIM) | ||
304 | #define C0_STATUS_IM_SW1 (S_StatusIM1 - S_StatusIM) | ||
305 | #define C0_STATUS_IM_HW0 (S_StatusIM2 - S_StatusIM) | ||
306 | #define C0_STATUS_IM_HW1 (S_StatusIM3 - S_StatusIM) | ||
307 | #define C0_STATUS_IM_HW2 (S_StatusIM4 - S_StatusIM) | ||
308 | #define C0_STATUS_IM_HW3 (S_StatusIM5 - S_StatusIM) | ||
309 | #define C0_STATUS_IM_HW4 (S_StatusIM6 - S_StatusIM) | ||
310 | #define C0_STATUS_IM_HW5 (S_StatusIM7 - S_StatusIM) | ||
311 | |||
312 | /* Max interrupt code */ | ||
313 | #define C0_STATUS_IM_MAX C0_STATUS_IM_HW5 | ||
314 | |||
315 | #define C0_STATUS_KSU_SHF S_StatusKSU | ||
316 | #define C0_STATUS_KSU_MSK M_StatusKSU | ||
317 | |||
318 | #define C0_STATUS_UM_SHF S_StatusUM | ||
319 | #define C0_STATUS_UM_MSK M_StatusUM | ||
320 | #define C0_STATUS_UM_BIT C0_STATUS_UM_MSK | ||
321 | |||
322 | #define C0_STATUS_ERL_SHF S_StatusERL | ||
323 | #define C0_STATUS_ERL_MSK M_StatusERL | ||
324 | #define C0_STATUS_ERL_BIT C0_STATUS_ERL_MSK | ||
325 | |||
326 | #define C0_STATUS_EXL_SHF S_StatusEXL | ||
327 | #define C0_STATUS_EXL_MSK M_StatusEXL | ||
328 | #define C0_STATUS_EXL_BIT C0_STATUS_EXL_MSK | ||
329 | |||
330 | #define C0_STATUS_IE_SHF S_StatusIE | ||
331 | #define C0_STATUS_IE_MSK M_StatusIE | ||
332 | #define C0_STATUS_IE_BIT C0_STATUS_IE_MSK | ||
333 | |||
334 | |||
335 | /* C0_PRID register encoding */ | ||
336 | |||
337 | #define C0_PRID_OPT_SHF S_PRIdCoOpt | ||
338 | #define C0_PRID_OPT_MSK M_PRIdCoOpt | ||
339 | |||
340 | #define C0_PRID_COMP_SHF S_PRIdCoID | ||
341 | #define C0_PRID_COMP_MSK M_PRIdCoID | ||
342 | #define C0_PRID_COMP_MIPS K_PRIdCoID_MIPS | ||
343 | #define C0_PRID_COMP_NOT_MIPS32_64 0 | ||
344 | |||
345 | #define C0_PRID_PRID_SHF S_PRIdImp | ||
346 | #define C0_PRID_PRID_MSK M_PRIdImp | ||
347 | |||
348 | /* Jade */ | ||
349 | #define C0_PRID_PRID_4Kc K_PRIdImp_Jade | ||
350 | #define C0_PRID_PRID_4Kmp K_PRIdImp_JadeLite /* 4Km/4Kp */ | ||
351 | /* Emerald */ | ||
352 | #define C0_PRID_PRID_4KEc K_PRIdImp_4KEc | ||
353 | #define C0_PRID_PRID_4KEmp K_PRIdImp_4KEmp | ||
354 | /* Coral */ | ||
355 | #define C0_PRID_PRID_4KSc K_PRIdImp_4KSc | ||
356 | /* Opal */ | ||
357 | #define C0_PRID_PRID_5K K_PRIdImp_Opal | ||
358 | /* Ruby */ | ||
359 | #define C0_PRID_PRID_20Kc K_PRIdImp_Ruby | ||
360 | /* Other CPUs */ | ||
361 | #define C0_PRID_PRID_R4000 K_PRIdImp_R4000 | ||
362 | #define C0_PRID_PRID_RM52XX K_PRIdImp_R5200 | ||
363 | #define C0_PRID_PRID_RM70XX 0x27 | ||
364 | |||
365 | #define C0_PRID_REV_SHF S_PRIdRev | ||
366 | #define C0_PRID_REV_MSK M_PRIdRev | ||
367 | |||
368 | |||
369 | #define MIPS_4Kc ( (C0_PRID_COMP_MIPS << \ | ||
370 | C0_PRID_COMP_SHF) | \ | ||
371 | (C0_PRID_PRID_4Kc << \ | ||
372 | C0_PRID_PRID_SHF) \ | ||
373 | ) | ||
374 | |||
375 | #define MIPS_4Kmp ( (C0_PRID_COMP_MIPS << \ | ||
376 | C0_PRID_COMP_SHF) | \ | ||
377 | (C0_PRID_PRID_4Kmp << \ | ||
378 | C0_PRID_PRID_SHF) \ | ||
379 | ) | ||
380 | |||
381 | #define MIPS_4KEc ( (C0_PRID_COMP_MIPS << \ | ||
382 | C0_PRID_COMP_SHF) | \ | ||
383 | (C0_PRID_PRID_4KEc << \ | ||
384 | C0_PRID_PRID_SHF) \ | ||
385 | ) | ||
386 | |||
387 | #define MIPS_4KEmp ( (C0_PRID_COMP_MIPS << \ | ||
388 | C0_PRID_COMP_SHF) | \ | ||
389 | (C0_PRID_PRID_4KEmp << \ | ||
390 | C0_PRID_PRID_SHF) \ | ||
391 | ) | ||
392 | |||
393 | #define MIPS_4KSc ( (C0_PRID_COMP_MIPS << \ | ||
394 | C0_PRID_COMP_SHF) | \ | ||
395 | (C0_PRID_PRID_4KSc << \ | ||
396 | C0_PRID_PRID_SHF) \ | ||
397 | ) | ||
398 | |||
399 | #define MIPS_5K ( (C0_PRID_COMP_MIPS << \ | ||
400 | C0_PRID_COMP_SHF) | \ | ||
401 | (C0_PRID_PRID_5K << \ | ||
402 | C0_PRID_PRID_SHF) \ | ||
403 | ) | ||
404 | |||
405 | #define MIPS_20Kc ( (C0_PRID_COMP_MIPS << \ | ||
406 | C0_PRID_COMP_SHF) | \ | ||
407 | (C0_PRID_PRID_20Kc << \ | ||
408 | C0_PRID_PRID_SHF) \ | ||
409 | ) | ||
410 | |||
411 | #define QED_RM52XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \ | ||
412 | C0_PRID_COMP_SHF) | \ | ||
413 | (C0_PRID_PRID_RM52XX << \ | ||
414 | C0_PRID_PRID_SHF) \ | ||
415 | ) | ||
416 | |||
417 | #define QED_RM70XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \ | ||
418 | C0_PRID_COMP_SHF) | \ | ||
419 | (C0_PRID_PRID_RM70XX << \ | ||
420 | C0_PRID_PRID_SHF) \ | ||
421 | ) | ||
422 | |||
423 | /* C0_ENTRYHI register encoding */ | ||
424 | |||
425 | #define C0_ENTRYHI_VPN2_SHF S_EntryHiVPN2 | ||
426 | #define C0_ENTRYHI_VPN2_MSK M_EntryHiVPN2 | ||
427 | |||
428 | #define C0_ENTRYHI_ASID_SHF S_EntryHiASID | ||
429 | #define C0_ENTRYHI_ASID_MSK M_EntryHiASID | ||
430 | |||
431 | |||
432 | /* C0_CAUSE register encoding */ | ||
433 | |||
434 | #define C0_CAUSE_BD_SHF S_CauseBD | ||
435 | #define C0_CAUSE_BD_MSK M_CauseBD | ||
436 | #define C0_CAUSE_BD_BIT C0_CAUSE_BD_MSK | ||
437 | |||
438 | #define C0_CAUSE_CE_SHF S_CauseCE | ||
439 | #define C0_CAUSE_CE_MSK M_CauseCE | ||
440 | |||
441 | #define C0_CAUSE_IV_SHF S_CauseIV | ||
442 | #define C0_CAUSE_IV_MSK M_CauseIV | ||
443 | #define C0_CAUSE_IV_BIT C0_CAUSE_IV_MSK | ||
444 | |||
445 | #define C0_CAUSE_WP_SHF S_CauseWP | ||
446 | #define C0_CAUSE_WP_MSK M_CauseWP | ||
447 | #define C0_CAUSE_WP_BIT C0_CAUSE_WP_MSK | ||
448 | |||
449 | #define C0_CAUSE_IP_SHF S_CauseIP | ||
450 | #define C0_CAUSE_IP_MSK M_CauseIP | ||
451 | |||
452 | #define C0_CAUSE_CODE_SHF S_CauseExcCode | ||
453 | #define C0_CAUSE_CODE_MSK M_CauseExcCode | ||
454 | |||
455 | #define C0_CAUSE_CODE_INT EX_INT | ||
456 | #define C0_CAUSE_CODE_MOD EX_MOD | ||
457 | #define C0_CAUSE_CODE_TLBL EX_TLBL | ||
458 | #define C0_CAUSE_CODE_TLBS EX_TLBS | ||
459 | #define C0_CAUSE_CODE_ADEL EX_ADEL | ||
460 | #define C0_CAUSE_CODE_ADES EX_ADES | ||
461 | #define C0_CAUSE_CODE_IBE EX_IBE | ||
462 | #define C0_CAUSE_CODE_DBE EX_DBE | ||
463 | #define C0_CAUSE_CODE_SYS EX_SYS | ||
464 | #define C0_CAUSE_CODE_BP EX_BP | ||
465 | #define C0_CAUSE_CODE_RI EX_RI | ||
466 | #define C0_CAUSE_CODE_CPU EX_CPU | ||
467 | #define C0_CAUSE_CODE_OV EX_OV | ||
468 | #define C0_CAUSE_CODE_TR EV_TR | ||
469 | #define C0_CAUSE_CODE_FPE EX_FPE | ||
470 | #define C0_CAUSE_CODE_WATCH EX_WATCH | ||
471 | #define C0_CAUSE_CODE_MCHECK EX_MCHECK | ||
472 | |||
473 | /* Max cause code */ | ||
474 | #define C0_CAUSE_CODE_MAX EX_MCHECK | ||
475 | |||
476 | |||
477 | /* C0_PAGEMASK register encoding */ | ||
478 | #define C0_PAGEMASK_MASK_SHF S_PageMaskMask | ||
479 | #define C0_PAGEMASK_MASK_MSK M_PageMaskMask | ||
480 | #define C0_PAGEMASK_MASK_4K K_PageMask4K | ||
481 | #define C0_PAGEMASK_MASK_16K K_PageMask16K | ||
482 | #define C0_PAGEMASK_MASK_64K K_PageMask64K | ||
483 | #define C0_PAGEMASK_MASK_256K K_PageMask256K | ||
484 | #define C0_PAGEMASK_MASK_1M K_PageMask1M | ||
485 | #define C0_PAGEMASK_MASK_4M K_PageMask4M | ||
486 | #define C0_PAGEMASK_MASK_16M K_PageMask16M | ||
487 | |||
488 | |||
489 | /* C0_ENTRYLO0 register encoding (equiv. to C0_ENTRYLO1) */ | ||
490 | #define C0_ENTRYLO0_PFN_SHF S_EntryLoPFN | ||
491 | #define C0_ENTRYLO0_PFN_MSK M_EntryLoPFN | ||
492 | |||
493 | #define C0_ENTRYLO0_C_SHF S_EntryLoC | ||
494 | #define C0_ENTRYLO0_C_MSK M_EntryLoC | ||
495 | |||
496 | #define C0_ENTRYLO0_D_SHF S_EntryLoD | ||
497 | #define C0_ENTRYLO0_D_MSK M_EntryLoD | ||
498 | |||
499 | #define C0_ENTRYLO0_V_SHF S_EntryLoV | ||
500 | #define C0_ENTRYLO0_V_MSK M_EntryLoV | ||
501 | |||
502 | #define C0_ENTRYLO0_G_SHF S_EntryLoG | ||
503 | #define C0_ENTRYLO0_G_MSK M_EntryLoG | ||
504 | |||
505 | |||
506 | /* FPU (CP1) FIR register encoding */ | ||
507 | #define C1_FIR_3D_SHF S_FIRConfig3D | ||
508 | #define C1_FIR_3D_MSK M_FIRConfig3D | ||
509 | |||
510 | #define C1_FIR_PS_SHF S_FIRConfigPS | ||
511 | #define C1_FIR_PS_MSK M_FIRConfigPS | ||
512 | |||
513 | #define C1_FIR_D_SHF S_FIRConfigD | ||
514 | #define C1_FIR_D_MSK M_FIRConfigD | ||
515 | |||
516 | #define C1_FIR_S_SHF S_FIRConfigS | ||
517 | #define C1_FIR_S_MSK M_FIRConfigS | ||
518 | |||
519 | #define C1_FIR_PRID_SHF S_FIRImp | ||
520 | #define C1_FIR_PRID_MSK M_FIRImp | ||
521 | |||
522 | #define C1_FIR_REV_SHF S_FIRRev | ||
523 | #define C1_FIR_REV_MSK M_FIRRev | ||
524 | |||
525 | |||
526 | /* FPU (CP1) FCSR control/status register */ | ||
527 | #define C1_FCSR_FCC_SHF S_FCSRFCC7_1 | ||
528 | #define C1_FCSR_FCC_MSK M_FCSRFCC7_1 | ||
529 | |||
530 | #define C1_FCSR_FS_SHF S_FCSRFS | ||
531 | #define C1_FCSR_FS_MSK M_FCSRFS | ||
532 | #define C1_FCSR_FS_BIT C1_FCSR_FS_MSK | ||
533 | |||
534 | #define C1_FCSR_CC_SHF S_FCSRCC | ||
535 | #define C1_FCSR_CC_MSK M_FCSRCC | ||
536 | |||
537 | #define C1_FCSR_IMPL_SHF S_FCSRImpl | ||
538 | #define C1_FCSR_IMPL_MSK M_FCSRImpl | ||
539 | |||
540 | #define C1_FCSR_EXC_SHF S_FCSRExc | ||
541 | #define C1_FCSR_EXC_MSK M_FCSRExc | ||
542 | |||
543 | #define C1_FCSR_ENA_SHF S_FCSREna | ||
544 | #define C1_FCSR_ENA_MSK M_FCSREna | ||
545 | |||
546 | #define C1_FCSR_FLG_SHF S_FCSRFlg | ||
547 | #define C1_FCSR_FLG_MSK M_FCSRFlg | ||
548 | |||
549 | #define C1_FCSR_RM_SHF S_FCSRRM | ||
550 | #define C1_FCSR_RM_MSK M_FCSRRM | ||
551 | #define C1_FCSR_RM_RN K_FCSRRM_RN | ||
552 | #define C1_FCSR_RM_RZ K_FCSRRM_RZ | ||
553 | #define C1_FCSR_RM_RP K_FCSRRM_RP | ||
554 | #define C1_FCSR_RM_RM K_FCSRRM_RM | ||
555 | |||
556 | |||
557 | |||
558 | /* cache operations */ | ||
559 | |||
560 | #define CACHE_OP( code, type ) ( ((code) << 2) | (type) ) | ||
561 | |||
562 | #define ICACHE_INDEX_INVALIDATE CACHE_OP(0x0, 0) | ||
563 | #define ICACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 0) | ||
564 | #define ICACHE_INDEX_STORE_TAG CACHE_OP(0x2, 0) | ||
565 | #define DCACHE_INDEX_WRITEBACK_INVALIDATE CACHE_OP(0x0, 1) | ||
566 | #define DCACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 1) | ||
567 | #define DCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 1) | ||
568 | #define SCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 3) | ||
569 | |||
570 | #define ICACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 0) | ||
571 | #define ICACHE_ADDR_FILL CACHE_OP(0x5, 0) | ||
572 | #define ICACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 0) | ||
573 | #define DCACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 1) | ||
574 | #define DCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 1) | ||
575 | #define DCACHE_ADDR_HIT_WRITEBACK CACHE_OP(0x6, 1) | ||
576 | #define DCACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 1) | ||
577 | |||
578 | #define SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 3) | ||
579 | |||
580 | /* Workaround for bug in early revisions of MIPS 4K family of | ||
581 | * processors. Only relevant in early engineering samples of test | ||
582 | * chips (RTL revision <= 3.0). | ||
583 | * | ||
584 | * The bug is described in : | ||
585 | * | ||
586 | * MIPS32 4K(tm) Processor Core Family RTL Errata Sheet | ||
587 | * MIPS Document No: MD00003 | ||
588 | * | ||
589 | * The bug is identified as : C16 | ||
590 | */ | ||
591 | #ifndef SET_MIPS0 | ||
592 | #define SET_MIPS0() | ||
593 | #define SET_PUSH() | ||
594 | #define SET_POP() | ||
595 | #endif | ||
596 | #define ICACHE_INVALIDATE_WORKAROUND(reg) \ | ||
597 | SET_PUSH(); \ | ||
598 | SET_MIPS0(); \ | ||
599 | la reg, 999f; \ | ||
600 | SET_POP(); \ | ||
601 | cache ICACHE_ADDR_FILL, 0(reg); \ | ||
602 | sync; \ | ||
603 | nop; nop; nop; nop; \ | ||
604 | 999: | ||
605 | |||
606 | /* EMPTY_PIPELINE is used for the below cache invalidation operations. | ||
607 | * When $I is invalidated, there will still be operations in the | ||
608 | * pipeline. We make sure these are 'nop' operations. | ||
609 | */ | ||
610 | #define EMPTY_PIPELINE nop; nop; nop; nop | ||
611 | |||
612 | #define ICACHE_INDEX_INVALIDATE_OP(index,scratch) \ | ||
613 | ICACHE_INVALIDATE_WORKAROUND(scratch); \ | ||
614 | cache ICACHE_INDEX_INVALIDATE, 0(index); \ | ||
615 | EMPTY_PIPELINE | ||
616 | |||
617 | #define ICACHE_ADDR_INVALIDATE_OP(addr,scratch) \ | ||
618 | ICACHE_INVALIDATE_WORKAROUND(scratch); \ | ||
619 | cache ICACHE_ADDR_HIT_INVALIDATE, 0(addr); \ | ||
620 | EMPTY_PIPELINE | ||
621 | |||
622 | /* The sync used in the below macro is there in case we are installing | ||
623 | * a new instruction (flush $D, sync, invalidate $I sequence). | ||
624 | */ | ||
625 | #define SCACHE_ADDR_HIT_WB_INVALIDATE_OP(reg) \ | ||
626 | cache SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE, 0(reg); \ | ||
627 | sync; \ | ||
628 | EMPTY_PIPELINE | ||
629 | |||
630 | /* Config1 cache field decoding */ | ||
631 | #define CACHE_CALC_SPW(s) ( 64 << (s) ) | ||
632 | #define CACHE_CALC_LS(l) ( (l) ? 2 << (l) : 0 ) | ||
633 | #define CACHE_CALC_BPW(l,s) ( CACHE_CALC_LS(l) * CACHE_CALC_SPW(s) ) | ||
634 | #define CACHE_CALC_ASSOC(a) ( (a) + 1 ) | ||
635 | |||
636 | |||
637 | /**** Move from/to Coprocessor operations ****/ | ||
638 | |||
639 | /* We use ssnop instead of nop operations in order to handle | ||
640 | * superscalar CPUs. | ||
641 | * The "sll zero,zero,1" notation is compiler backwards compatible. | ||
642 | */ | ||
643 | #define SSNOP sll zero,zero,1 | ||
644 | #define NOPS SSNOP; SSNOP; SSNOP; SSNOP | ||
645 | |||
646 | #define MFLO(dst) \ | ||
647 | mflo dst;\ | ||
648 | NOPS | ||
649 | |||
650 | /* Workaround for bug in early revisions of MIPS 4K family of | ||
651 | * processors. | ||
652 | * | ||
653 | * This concerns the nop instruction before mtc0 in the | ||
654 | * MTC0 macro below. | ||
655 | * | ||
656 | * The bug is described in : | ||
657 | * | ||
658 | * MIPS32 4K(tm) Processor Core Family RTL Errata Sheet | ||
659 | * MIPS Document No: MD00003 | ||
660 | * | ||
661 | * The bug is identified as : C27 | ||
662 | */ | ||
663 | |||
664 | #define MTC0(src, dst) \ | ||
665 | nop; \ | ||
666 | mtc0 src,dst;\ | ||
667 | NOPS | ||
668 | |||
669 | #define DMTC0(src, dst) \ | ||
670 | nop; \ | ||
671 | dmtc0 src,dst;\ | ||
672 | NOPS | ||
673 | |||
674 | #define MFC0(dst, src) \ | ||
675 | mfc0 dst,src;\ | ||
676 | NOPS | ||
677 | |||
678 | #define DMFC0(dst, src) \ | ||
679 | dmfc0 dst,src;\ | ||
680 | NOPS | ||
681 | |||
682 | #define MFC0_SEL_OPCODE(dst, src, sel)\ | ||
683 | .##word (0x40000000 | ((dst)<<16) | ((src)<<11) | (sel));\ | ||
684 | NOPS | ||
685 | |||
686 | #define MTC0_SEL_OPCODE(dst, src, sel)\ | ||
687 | .##word (0x40800000 | ((dst)<<16) | ((src)<<11) | (sel));\ | ||
688 | NOPS | ||
689 | |||
690 | #define LDC1(dst, src, offs)\ | ||
691 | .##word (0xd4000000 | ((src)<<21) | ((dst)<<16) | (offs)) | ||
692 | |||
693 | #define SDC1(src, dst, offs)\ | ||
694 | .##word (0xf4000000 | ((dst)<<21) | ((src)<<16) | (offs)) | ||
695 | |||
696 | |||
697 | /* Instruction opcode fields */ | ||
698 | #define OPC_SPECIAL 0x0 | ||
699 | #define OPC_REGIM 0x1 | ||
700 | #define OPC_J 0x2 | ||
701 | #define OPC_JAL 0x3 | ||
702 | #define OPC_BEQ 0x4 | ||
703 | #define OPC_BNE 0x5 | ||
704 | #define OPC_BLEZ 0x6 | ||
705 | #define OPC_BGTZ 0x7 | ||
706 | #define OPC_COP1 0x11 | ||
707 | #define OPC_JALX 0x1D | ||
708 | #define OPC_BEQL 0x14 | ||
709 | #define OPC_BNEL 0x15 | ||
710 | #define OPC_BLEZL 0x16 | ||
711 | #define OPC_BGTZL 0x17 | ||
712 | |||
713 | /* Instruction function fields */ | ||
714 | #define FUNC_JR 0x8 | ||
715 | #define FUNC_JALR 0x9 | ||
716 | |||
717 | /* Instruction rt fields */ | ||
718 | #define RT_BLTZ 0x0 | ||
719 | #define RT_BGEZ 0x1 | ||
720 | #define RT_BLTZL 0x2 | ||
721 | #define RT_BGEZL 0x3 | ||
722 | #define RT_BLTZAL 0x10 | ||
723 | #define RT_BGEZAL 0x11 | ||
724 | #define RT_BLTZALL 0x12 | ||
725 | #define RT_BGEZALL 0x13 | ||
726 | |||
727 | /* Instruction rs fields */ | ||
728 | #define RS_BC1 0x08 | ||
729 | |||
730 | /* Access macros for instruction fields */ | ||
731 | #define MIPS_OPCODE( instr) ((instr) >> 26) | ||
732 | #define MIPS_FUNCTION(instr) ((instr) & MSK(6)) | ||
733 | #define MIPS_RT(instr) (((instr) >> 16) & MSK(5)) | ||
734 | #define MIPS_RS(instr) (((instr) >> 21) & MSK(5)) | ||
735 | #define MIPS_OFFSET(instr) ((instr) & 0xFFFF) | ||
736 | #define MIPS_TARGET(instr) ((instr) & MSK(26)) | ||
737 | |||
738 | /* Instructions */ | ||
739 | #define OPCODE_DERET 0x4200001f | ||
740 | #define OPCODE_BREAK 0x0005000d | ||
741 | #define OPCODE_NOP 0 | ||
742 | #define OPCODE_JUMP(addr) ( (OPC_J << 26) | (((addr) >> 2) & 0x3FFFFFF) ) | ||
743 | |||
744 | #define DERET .##word OPCODE_DERET | ||
745 | |||
746 | /* MIPS16e opcodes and instruction field access macros */ | ||
747 | |||
748 | #define MIPS16E_OPCODE(inst) (((inst) >> 11) & 0x1f) | ||
749 | #define MIPS16E_I8_FUNCTION(inst) (((inst) >> 8) & 0x7) | ||
750 | #define MIPS16E_X(inst) (((inst) >> 26) & 0x1) | ||
751 | #define MIPS16E_RR_FUNCTION(inst) (((inst) >> 0) & 0x1f) | ||
752 | #define MIPS16E_RY(inst) (((inst) >> 5) & 0x3) | ||
753 | #define MIPS16E_OPC_EXTEND 0x1e | ||
754 | #define MIPS16E_OPC_JAL_X 0x03 | ||
755 | #define MIPS16E_OPC_B 0x02 | ||
756 | #define MIPS16E_OPC_BEQZ 0x04 | ||
757 | #define MIPS16E_OPC_BNEZ 0x05 | ||
758 | #define MIPS16E_OPC_I8 0x0c | ||
759 | #define MIPS16E_I8_FUNC_BTEQZ 0x00 | ||
760 | #define MIPS16E_I8_FUNC_BTNEZ 0x01 | ||
761 | #define MIPS16E_X_JALX 0x01 | ||
762 | #define MIPS16E_OPC_RR 0x1d | ||
763 | #define MIPS16E_RR_FUNC_JALRC 0x00 | ||
764 | #define MIPS16E_RR_RY_JRRX 0x00 | ||
765 | #define MIPS16E_RR_RY_JRRA 0x01 | ||
766 | #define MIPS16E_RR_RY_JALR 0x02 | ||
767 | #define MIPS16E_RR_RY_JRCRX 0x04 | ||
768 | #define MIPS16E_RR_RY_JRCRA 0x05 | ||
769 | #define MIPS16E_RR_RY_JALRC 0x06 | ||
770 | |||
771 | #define MIPS16E_OPCODE_BREAK 0xE805 | ||
772 | #define MIPS16E_OPCODE_NOP 0x6500 | ||
773 | |||
774 | /* MIPS reset vector */ | ||
775 | #define MIPS_RESET_VECTOR 0x1fc00000 | ||
776 | |||
777 | /* Clock periods per count register increment */ | ||
778 | #define MIPS4K_COUNT_CLK_PER_CYCLE 2 | ||
779 | #define MIPS5K_COUNT_CLK_PER_CYCLE 2 | ||
780 | #define MIPS20Kc_COUNT_CLK_PER_CYCLE 1 | ||
781 | |||
782 | |||
783 | /**** MIPS 4K/5K families specific fields of CONFIG register ****/ | ||
784 | |||
785 | #define C0_CONFIG_MIPS4K5K_K23_SHF S_ConfigK23 | ||
786 | #define C0_CONFIG_MIPS4K5K_K23_MSK (MSK(3) << C0_CONFIG_MIPS4K5K_K23_SHF) | ||
787 | |||
788 | #define C0_CONFIG_MIPS4K5K_KU_SHF S_ConfigKU | ||
789 | #define C0_CONFIG_MIPS4K5K_KU_MSK (MSK(3) << C0_CONFIG_MIPS4K5K_KU_SHF) | ||
790 | |||
791 | |||
792 | /**** MIPS 20Kc specific fields of CONFIG register ****/ | ||
793 | |||
794 | #define C0_CONFIG_MIPS20KC_EC_SHF 28 | ||
795 | #define C0_CONFIG_MIPS20KC_EC_MSK (MSK(3) << C0_CONFIG_MIPS20KC_EC_SHF) | ||
796 | |||
797 | #define C0_CONFIG_MIPS20KC_DD_SHF 27 | ||
798 | #define C0_CONFIG_MIPS20KC_DD_MSK (MSK(1) << C0_CONFIG_MIPS20KC_DD_SHF) | ||
799 | #define C0_CONFIG_MIPS20KC_DD_BIT C0_CONFIG_MIPS20KC_DD_MSK | ||
800 | |||
801 | #define C0_CONFIG_MIPS20KC_LP_SHF 26 | ||
802 | #define C0_CONFIG_MIPS20KC_LP_MSK (MSK(1) << C0_CONFIG_MIPS20KC_LP_SHF) | ||
803 | #define C0_CONFIG_MIPS20KC_LP_BIT C0_CONFIG_MIPS20KC_LP_MSK | ||
804 | |||
805 | #define C0_CONFIG_MIPS20KC_SP_SHF 25 | ||
806 | #define C0_CONFIG_MIPS20KC_SP_MSK (MSK(1) << C0_CONFIG_MIPS20KC_SP_SHF) | ||
807 | #define C0_CONFIG_MIPS20KC_SP_BIT C0_CONFIG_MIPS20KC_SP_MSK | ||
808 | |||
809 | #define C0_CONFIG_MIPS20KC_TI_SHF 24 | ||
810 | #define C0_CONFIG_MIPS20KC_TI_MSK (MSK(1) << C0_CONFIG_MIPS20KC_TI_SHF) | ||
811 | #define C0_CONFIG_MIPS20KC_TI_BIT C0_CONFIG_MIPS20KC_TI_MSK | ||
812 | |||
813 | |||
814 | /* ********************************************************************* */ | ||
815 | /* Interface function definition */ | ||
816 | |||
817 | |||
818 | /* ********************************************************************* */ | ||
819 | |||
820 | #endif /* #ifndef __MIPS_H__ */ | ||
diff --git a/utils/atj2137/adfuload/test_binary/timer_no_irq/test.lds b/utils/atj2137/adfuload/test_binary/timer_no_irq/test.lds new file mode 100644 index 0000000000..744cad5175 --- /dev/null +++ b/utils/atj2137/adfuload/test_binary/timer_no_irq/test.lds | |||
@@ -0,0 +1,38 @@ | |||
1 | OUTPUT_ARCH(mips) | ||
2 | ENTRY(main) | ||
3 | |||
4 | SECTIONS | ||
5 | { | ||
6 | |||
7 | |||
8 | .text 0xa0001000 : | ||
9 | { | ||
10 | relocstart = .; | ||
11 | *(.init.text*) | ||
12 | *(.text*) | ||
13 | } | ||
14 | |||
15 | .data : | ||
16 | { | ||
17 | *(.rodata*) | ||
18 | *(.data*) | ||
19 | relocend = .; | ||
20 | } | ||
21 | |||
22 | .bss : | ||
23 | { | ||
24 | bssbegin = .; | ||
25 | *(.sbss*) | ||
26 | *(.bss*) | ||
27 | *(COMMON) | ||
28 | *(.scommon*) | ||
29 | bssend = .; | ||
30 | } | ||
31 | |||
32 | .stack (NOLOAD) : | ||
33 | { | ||
34 | stackbegin = .; | ||
35 | . += 0x2000; | ||
36 | stackend = .; | ||
37 | } | ||
38 | } | ||
diff --git a/utils/atj2137/adfuload/test_binary/timer_no_irq/test_timer_noirq.c b/utils/atj2137/adfuload/test_binary/timer_no_irq/test_timer_noirq.c new file mode 100644 index 0000000000..43aee07c00 --- /dev/null +++ b/utils/atj2137/adfuload/test_binary/timer_no_irq/test_timer_noirq.c | |||
@@ -0,0 +1,48 @@ | |||
1 | #include "atj213x.h" | ||
2 | |||
3 | static void backlight_set(int level) | ||
4 | { | ||
5 | /* set duty cycle in 1/32 units */ | ||
6 | PMU_CHG = ((PMU_CHG & ~PMU_CHG_PDOUT_MASK) | PMU_CHG_PDUT(level)); | ||
7 | } | ||
8 | |||
9 | static void wdt_feed(void) | ||
10 | { | ||
11 | RTC_WDCTL |= RTC_WDCTL_CLR; | ||
12 | } | ||
13 | |||
14 | int main(void) | ||
15 | { | ||
16 | int i = 0, j = 0; | ||
17 | |||
18 | /* backlight clock enable, select backlight clock as 32kHz */ | ||
19 | CMU_FMCLK = (CMU_FMCLK & ~(CMU_FMCLK_BCLK_MASK)) | CMU_FMCLK_BCKE | CMU_FMCLK_BCLK_32K; | ||
20 | |||
21 | /* baclight enable */ | ||
22 | PMU_CTL |= PMU_CTL_BL_EN; | ||
23 | |||
24 | /* pwm output, phase high, some initial duty cycle set as 24/32 */ | ||
25 | PMU_CHG = ((PMU_CHG & ~PMU_CHG_PDOUT_MASK)| PMU_CHG_PBLS_PWM | PMU_CHG_PPHS_HIGH | PMU_CHG_PDUT(24)); | ||
26 | |||
27 | /* ADEC_N63.BIN seems to setup P_CLK as 7.5MHz which is timer clk */ | ||
28 | RTC_T0 = (7500000*10/32); /* with this we should see transition every ~0.3125s and 'black' every ~10s */ | ||
29 | RTC_T0CTL = (1<<5) | (1<<2) | (1<<0); /* timer enable, timer reload, clear irq pending bit */ | ||
30 | |||
31 | while(1) | ||
32 | { | ||
33 | /* otherwise wdt will trigger reset */ | ||
34 | wdt_feed(); | ||
35 | |||
36 | /* check if irq pending bit is set */ | ||
37 | if (RTC_T0CTL & 1) | ||
38 | { | ||
39 | /* clear irq pending bit */ | ||
40 | RTC_T0CTL |= 1; | ||
41 | |||
42 | j++; | ||
43 | backlight_set(j); | ||
44 | } | ||
45 | } | ||
46 | |||
47 | return 0; | ||
48 | } | ||