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Diffstat (limited to 'utils/atj2137/adfuload/test_binary/timer_irq/atj213x.h')
-rw-r--r--utils/atj2137/adfuload/test_binary/timer_irq/atj213x.h383
1 files changed, 383 insertions, 0 deletions
diff --git a/utils/atj2137/adfuload/test_binary/timer_irq/atj213x.h b/utils/atj2137/adfuload/test_binary/timer_irq/atj213x.h
new file mode 100644
index 0000000000..46f537e39d
--- /dev/null
+++ b/utils/atj2137/adfuload/test_binary/timer_irq/atj213x.h
@@ -0,0 +1,383 @@
1typedef unsigned int uint32_t;
2
3#define PMU_BASE 0xB0000000
4#define PMU_CTL (*(volatile uint32_t *)(PMU_BASE + 0x00))
5#define PMU_CTL_BL_EN (1<<15)
6#define PMU_LRADC (*(volatile uint32_t *)(PMU_BASE + 0x04))
7#define PMU_CHG (*(volatile uint32_t *)(PMU_BASE + 0x08))
8#define PMU_CHG_PBLS (1<<15)
9#define PMU_CHG_PBLS_PWM (1<<15)
10#define PMU_CHG_PBLS_BL_NDR (0<<15)
11#define PMU_CHG_PPHS (1<<14)
12#define PMU_CHG_PPHS_HIGH (1<<14)
13#define PMU_CHG_PPHS_LOW (0<<14)
14#define PMU_CHG_PDUT(x) (((x) & 0x1f) << 8)
15#define PMU_CHG_PDOUT_MASK (0x1f << 8)
16
17#define CMU_BASE 0xB0010000
18#define CMU_COREPLL (*(volatile uint32_t *)(CMU_BASE + 0x00))
19#define CMU_DSPPLL (*(volatile uint32_t *)(CMU_BASE + 0x04))
20#define CMU_AUDIOPLL (*(volatile uint32_t *)(CMU_BASE + 0x08))
21#define CMU_BUSCLK (*(volatile uint32_t *)(CMU_BASE + 0x0C))
22#define CMU_SDRCLK (*(volatile uint32_t *)(CMU_BASE + 0x10))
23#define CMU_ATACLK (*(volatile uint32_t *)(CMU_BASE + 0x04))
24#define CMU_NANDCLK (*(volatile uint32_t *)(CMU_BASE + 0x18))
25#define CMU_SDCLK (*(volatile uint32_t *)(CMU_BASE + 0x1C))
26#define CMU_MHACLK (*(volatile uint32_t *)(CMU_BASE + 0x20))
27#define CMU_BTCLK (*(volatile uint32_t *)(CMU_BASE + 0x24))
28#define CMU_IRCLK (*(volatile uint32_t *)(CMU_BASE + 0x28))
29#define CMU_UART2CLK (*(volatile uint32_t *)(CMU_BASE + 0x2C))
30#define CMU_DMACLK (*(volatile uint32_t *)(CMU_BASE + 0x30))
31#define CMU_FMCLK (*(volatile uint32_t *)(CMU_BASE + 0x34))
32#define CMU_FMCLK_BCKE (1<<5)
33#define CMI_FMCLK_BCKS (1<<4)
34#define CMU_FMCLK_BCKS_32K (0<<4)
35#define CMU_FMCLK_BCKS_3M (1<<4)
36
37#define CMU_FMCLK_BCLK_MASK (CMI_FMCLK_BCKS | (3<<2))
38#define CMU_FMCLK_BCLK_3M (CMU_FMCLK_BCKS_3M | (0<<2))
39#define CMU_FMCLK_BCLK_1_5M (CMU_FMCLK_BCKS_3M | (1<<2))
40#define CMU_FMCLK_BCLK_750K (CMU_FMCLK_BCKS_3M | (2<<2))
41#define CMU_FMCLK_BCLK_375K (CMU_FMCLK_BCKS_3M | (3<<2))
42
43#define CMU_FMCLK_BCLK_32K (0<<2)
44#define CMU_FMCLK_BCLK_16K (1<<2)
45#define CMU_FMCLK_BCLK_8K (2<<2)
46#define CMU_FMCLK_BCLK_4K (3<<2)
47
48#define CMU_MCACLK (*(volatile uint32_t *)(CMU_BASE + 0x38))
49
50#define CMU_DEVCLKEN (*(volatile uint32_t *)(CMU_BASE + 0x80))
51#define CMU_DEVRST (*(volatile uint32_t *)(CMU_BASE + 0x84))
52
53#define RTC_BASE 0xB0018000
54#define RTC_CTL (*(volatile uint32_t *)(RTC_BASE + 0x00))
55#define RTC_DHMS (*(volatile uint32_t *)(RTC_BASE + 0x04))
56#define RTC_YMD (*(volatile uint32_t *)(RTC_BASE + 0x08))
57#define RTC_DHMSALM (*(volatile uint32_t *)(RTC_BASE + 0x0C))
58#define RTC_YMDALM (*(volatile uint32_t *)(RTC_BASE + 0x10))
59#define RTC_WDCTL (*(volatile uint32_t *)(RTC_BASE + 0x14))
60#define RTC_WDCTL_CLR (1<<0)
61
62#define RTC_T0CTL (*(volatile uint32_t *)(RTC_BASE + 0x18))
63#define RTC_T0 (*(volatile uint32_t *)(RTC_BASE + 0x1C))
64#define RTC_T1CTL (*(volatile uint32_t *)(RTC_BASE + 0x20))
65#define RTC_T1 (*(volatile uint32_t *)(RTC_BASE + 0x24))
66
67#define INTC_BASE 0xB0020000
68#define INTC_PD (*(volatile uint32_t *)(INTC_BASE + 0x00))
69#define INTC_MSK (*(volatile uint32_t *)(INTC_BASE + 0x04))
70#define INTC_CFG0 (*(volatile uint32_t *)(INTC_BASE + 0x08))
71#define INTC_CFG1 (*(volatile uint32_t *)(INTC_BASE + 0x0C))
72#define INTC_CFG2 (*(volatile uint32_t *)(INTC_BASE + 0x10))
73#define INTC_EXTCTL (*(volatile uint32_t *)(INTC_BASE + 0x14))
74
75#define SRAMOC_BASE 0xB0030000
76#define SRAMOC_CTL (*(volatile uint32_t *)(SRAMOC_BASE + 0x00))
77#define SRAMOC_STAT (*(volatile uint32_t *)(SRAMOC_BASE + 0x04))
78
79#define BOOT_BASE 0xB00380000
80#define BOOT_NORCTL (*(volatile uint32_t *)(BOOT_BASE + 0x00))
81#define BOOT_BROMCTL (*(volatile uint32_t *)(BOOT_BASE + 0x04))
82#define BOOT_CHIPID (*(volatile uint32_t *)(BOOT_BASE + 0x08))
83
84#define PCNT_BASE 0xB0040000
85#define PCNT_CTL (*(volatile uint32_t *)(PCNT_BASE + 0x00))
86#define PCNT_PC0 (*(volatile uint32_t *)(PCNT_BASE + 0x04))
87#define PCNT_PC1 (*(volatile uint32_t *)(PCNT_BASE + 0x08))
88
89#define DSP_BASE 0xB0050000
90#define DSP_HDR0 (*(volatile uint32_t *)(DSP_BASE + 0x00))
91#define DSP_HDR1 (*(volatile uint32_t *)(DSP_BASE + 0x04))
92#define DSP_HDR2 (*(volatile uint32_t *)(DSP_BASE + 0x08))
93#define DSP_HDR3 (*(volatile uint32_t *)(DSP_BASE + 0x0C))
94#define DSP_HDR4 (*(volatile uint32_t *)(DSP_BASE + 0x10))
95#define DSP_HDR5 (*(volatile uint32_t *)(DSP_BASE + 0x14))
96#define DSP_HSR6 (*(volatile uint32_t *)(DSP_BASE + 0x18))
97#define DSP_HSR7 (*(volatile uint32_t *)(DSP_BASE + 0x1C))
98#define DSP_CTL (*(volatile uint32_t *)(DSP_BASE + 0x20))
99
100#define DMAC_BASE(n) (0xB0060000 + (n<<5))
101#define DMAC_CTL (*(volatile uint32_t *)(DMAC_BASE(0) + 0x00))
102#define DMAC_IRQEN (*(volatile uint32_t *)(DMAC_BASE(0) + 0x04))
103#define DMAC_IRQPD (*(volatile uint32_t *)(DMAC_BASE(0) + 0x08))
104
105/* n in range 0-7 */
106#define DMA_MODE(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x100))
107#define DMA_SRC(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x104))
108#define DMA_DST(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x108))
109#define DMA_CNT(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x10C))
110#define DMA_REM(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x110))
111#define DMA_CMD(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x114))
112
113#define SDR_BASE 0xB0070000
114#define SDR_CTL (*(volatile uint32_t *)(SDR_BASE + 0x00))
115#define SDR_ADDRCFG (*(volatile uint32_t *)(SDR_BASE + 0x04))
116#define SDR_EN (*(volatile uint32_t *)(SDR_BASE + 0x08))
117#define SDR_CMD (*(volatile uint32_t *)(SDR_BASE + 0x0C))
118#define SDR_STAT (*(volatile uint32_t *)(SDR_BASE + 0x10))
119#define SDR_RFSH (*(volatile uint32_t *)(SDR_BASE + 0x14))
120#define SDR_MODE (*(volatile uint32_t *)(SDR_BASE + 0x18))
121#define SDR_MOBILE (*(volatile uint32_t *)(SDR_BASE + 0x1C))
122
123#define MCA_BASE 0xB0080000
124#define MCA_CTL (*(volatile uint32_t *)(MCA_BASE + 0x00))
125
126#define ATA_BASE 0xB0090000
127#define ATA_CONFIG (*(volatile uint32_t *)(ATA_BASE + 0x00))
128#define ATA_UDMACTL (*(volatile uint32_t *)(ATA_BASE + 0x04))
129#define ATA_DATA (*(volatile uint32_t *)(ATA_BASE + 0x08))
130#define ATA_FEATURE (*(volatile uint32_t *)(ATA_BASE + 0x0C))
131#define ATA_SECCNT (*(volatile uint32_t *)(ATA_BASE + 0x10))
132#define ATA_SECNUM (*(volatile uint32_t *)(ATA_BASE + 0x14))
133#define ATA_CLDLOW (*(volatile uint32_t *)(ATA_BASE + 0x18))
134#define ATA_CLDHI (*(volatile uint32_t *)(ATA_BASE + 0x1C))
135#define ATA_HEAD (*(volatile uint32_t *)(ATA_BASE + 0x20))
136#define ATA_CMD (*(volatile uint32_t *)(ATA_BASE + 0x24))
137#define ATA_BYTECNT (*(volatile uint32_t *)(ATA_BASE + 0x28))
138#define ATA_FIFOCTL (*(volatile uint32_t *)(ATA_BASE + 0x2C))
139#define ATA_FIFOCFG (*(volatile uint32_t *)(ATA_BASE + 0x30))
140#define ATA_ADDRDEC (*(volatile uint32_t *)(ATA_BASE + 0x34))
141#define ATA_IRQCTL (*(volatile uint32_t *)(ATA_BASE + 0x38))
142
143#define NAND_BASE 0xB00A0000
144#define NAND_CTL (*(volatile uint32_t *)(NAND_BASE + 0x00))
145#define NAND_STATUS (*(volatile uint32_t *)(NAND_BASE + 0x04))
146#define NAND_FIFOTIM (*(volatile uint32_t *)(NAND_BASE + 0x08))
147#define NAND_CLKCTL (*(volatile uint32_t *)(NAND_BASE + 0x0C))
148#define NAND_BYTECNT (*(volatile uint32_t *)(NAND_BASE + 0x10))
149#define NAND_ADDRLO1234 (*(volatile uint32_t *)(NAND_BASE + 0x14))
150#define NAND_ADDRLO56 (*(volatile uint32_t *)(NAND_BASE + 0x18))
151#define NAND_ADDRHI1234 (*(volatile uint32_t *)(NAND_BASE + 0x1C))
152#define NAND_ADDRHI56 (*(volatile uint32_t *)(NAND_BASE + 0x20))
153#define NAND_BUF0 (*(volatile uint32_t *)(NAND_BASE + 0x24))
154#define NAND_BUF1 (*(volatile uint32_t *)(NAND_BASE + 0x28))
155#define NAND_CMD (*(volatile uint32_t *)(NAND_BASE + 0x2C))
156#define NAND_ECCCTL (*(volatile uint32_t *)(NAND_BASE + 0x30))
157#define NAND_HAMECC0 (*(volatile uint32_t *)(NAND_BASE + 0x34))
158#define NAND_HAMECC1 (*(volatile uint32_t *)(NAND_BASE + 0x38))
159#define NAND_HAMECC2 (*(volatile uint32_t *)(NAND_BASE + 0x3C))
160#define NAND_HAMCEC (*(volatile uint32_t *)(NAND_BASE + 0x40))
161#define NAND_RSE0 (*(volatile uint32_t *)(NAND_BASE + 0x44))
162#define NAND_RSE1 (*(volatile uint32_t *)(NAND_BASE + 0x48))
163#define NAND_RSE2 (*(volatile uint32_t *)(NAND_BASE + 0x4C))
164#define NAND_RSE3 (*(volatile uint32_t *)(NAND_BASE + 0x50))
165#define NAND_RSPS0 (*(volatile uint32_t *)(NAND_BASE + 0x54))
166#define NAND_RSPS1 (*(volatile uint32_t *)(NAND_BASE + 0x58))
167#define NAND_RSPS2 (*(volatile uint32_t *)(NAND_BASE + 0x5C))
168#define NAND_FIFODATA (*(volatile uint32_t *)(NAND_BASE + 0x60))
169#define NAND_DEBUG (*(volatile uint32_t *)(NAND_BASE + 0x70))
170
171#define SD_BASE 0xB00B0000
172#define SD_CTL (*(volatile uint32_t *)(SD_BASE + 0x00))
173#define SD_CMDRSP (*(volatile uint32_t *)(SD_BASE + 0x04))
174#define SD_RW (*(volatile uint32_t *)(SD_BASE + 0x08))
175#define SD_FIFOCTL (*(volatile uint32_t *)(SD_BASE + 0x0C))
176#define SD_CMD (*(volatile uint32_t *)(SD_BASE + 0x10))
177#define SD_ARG (*(volatile uint32_t *)(SD_BASE + 0x14))
178#define SD_CRC7 (*(volatile uint32_t *)(SD_BASE + 0x18))
179#define SD_RSPBUF0 (*(volatile uint32_t *)(SD_BASE + 0x1C))
180#define SD_RSPBUF1 (*(volatile uint32_t *)(SD_BASE + 0x20))
181#define SD_RSPBUF2 (*(volatile uint32_t *)(SD_BASE + 0x24))
182#define SD_RSPBUF3 (*(volatile uint32_t *)(SD_BASE + 0x28))
183#define SD_RSPBUF4 (*(volatile uint32_t *)(SD_BASE + 0x2C))
184#define SD_DAT (*(volatile uint32_t *)(SD_BASE + 0x30))
185#define SD_CLK (*(volatile uint32_t *)(SD_BASE + 0x34))
186#define SD_BYTECNT (*(volatile uint32_t *)(SD_BASE + 0x38))
187
188#define MHA_BASE 0xB00C0000
189#define MHA_CTL (*(volatile uint32_t *)(MHA_BASE + 0x00))
190#define MHA_CFG (*(volatile uint32_t *)(MHA_BASE + 0x04))
191#define MHA_DCSCL01 (*(volatile uint32_t *)(MHA_BASE + 0x10))
192#define MHA_DCSCL23 (*(volatile uint32_t *)(MHA_BASE + 0x14))
193#define MHA_DCSCL45 (*(volatile uint32_t *)(MHA_BASE + 0x18))
194#define MHA_DCSCL67 (*(volatile uint32_t *)(MHA_BASE + 0x1C))
195#define MHA_QSCL (*(volatile uint32_t *)(MHA_BASE + 0x20))
196
197#define BT_BASE 0xB00D0000
198#define BT_MODESEL (*(volatile uint32_t *)(BT_BASE + 0x00))
199#define BT_FIFODAT (*(volatile uint32_t *)(BT_BASE + 0x04))
200
201/* video Encoder */
202#define BT_VEICTL (*(volatile uint32_t *)(BT_BASE + 0x08))
203#define BT_VEIVSEPOF (*(volatile uint32_t *)(BT_BASE + 0x14))
204#define BT_VEIVSEPEF (*(volatile uint32_t *)(BT_BASE + 0x18))
205#define BT_VEIFTP (*(volatile uint32_t *)(BT_BASE + 0x24))
206#define BT_VEIFIFOCTL (*(volatile uint32_t *)(BT_BASE + 0x30))
207
208/* Video Decoder */
209#define BT_VDICTL (*(volatile uint32_t *)(BT_BASE + 0x08))
210#define BT_VDIHSPOS (*(volatile uint32_t *)(BT_BASE + 0x0C))
211#define BT_VDIHEPOS (*(volatile uint32_t *)(BT_BASE + 0x10))
212#define BT_VDIVSEPOF (*(volatile uint32_t *)(BT_BASE + 0x14))
213#define BT_VDIVSEPEF (*(volatile uint32_t *)(BT_BASE + 0x18))
214#define BT_VDIIRQSTA (*(volatile uint32_t *)(BT_BASE + 0x28))
215#define BT_VDIXYDAT (*(volatile uint32_t *)(BT_BASE + 0x2C))
216#define BT_VDIFIFOCTL (*(volatile uint32_t *)(BT_BASE + 0x30))
217
218/* CMOS Sensor Interface */
219#define BT_CSICTL (*(volatile uint32_t *)(BT_BASE + 0x08))
220#define BT_CSIHSPOS (*(volatile uint32_t *)(BT_BASE + 0x0C))
221#define BT_CSIHEPOS (*(volatile uint32_t *)(BT_BASE + 0x10))
222#define BT_CSIVSPOS (*(volatile uint32_t *)(BT_BASE + 0x1C))
223#define BT_CSIVEPOS (*(volatile uint32_t *)(BT_BASE + 0x20))
224#define BT_CSIIRQSTA (*(volatile uint32_t *)(BT_BASE + 0x28))
225#define BT_CSIXYDAT (*(volatile uint32_t *)(BT_BASE + 0x2C))
226#define BT_CSIFIFOCTL (*(volatile uint32_t *)(BT_BASE + 0x30))
227
228/* TS */
229#define BT_TSICTL (*(volatile uint32_t *)(BT_BASE + 0x08))
230#define BT_TSIFIFOCTL (*(volatile uint32_t *)(BT_BASE + 0x30))
231
232/* Integrated Video Encoder */
233#define BT_IVECTL (*(volatile uint32_t *)(BT_BASE + 0x34))
234#define BT_IVEOUTCTL (*(volatile uint32_t *)(BT_BASE + 0x38))
235#define BT_IVECOTCTL (*(volatile uint32_t *)(BT_BASE + 0x3C))
236#define BT_IVEBRGCTL (*(volatile uint32_t *)(BT_BASE + 0x40))
237#define BT_IVECSATCTL (*(volatile uint32_t *)(BT_BASE + 0x44))
238#define BT_IVECBURCTL (*(volatile uint32_t *)(BT_BASE + 0x48))
239#define BT_IVESYNCAMCTL (*(volatile uint32_t *)(BT_BASE + 0x4C))
240
241#define OTG_BASE 0xB00E0000
242#define OTG_OUT0BC (*(volatile uint8_t *)(OTG_BASE + 0x00)) // ok (byte count?)
243#define OTG_IN0BC (*(volatile uint8_t *)(OTG_BASE + 0x01)) // ok (byte count?)
244#define OTG_EP0CS (*(volatile uint8_t *)(OTG_BASE + 0x02)) // ok
245#define EP_NAK (1<<1) // from rt source
246#define EP0_IN_BUSY (1<<2)
247#define EP0_OUT_BUSY (1<<3)
248
249#define OTG_OUT1CON (*(volatile uint8_t *)(OTG_BASE + 0x0A)) // ok
250#define OTG_OUT1CS (*(volatile uint8_t *)(OTG_BASE + 0x0B)) // missing in rt
251
252#define OTG_OUT2CON (*(volatile uint8_t *)(OTG_BASE + 0x12)) // missing in sdk
253#define OTG_OUT2CS (*(volatile uint8_t *)(OTG_BASE + 0x13)) // deduced
254
255#define OTG_IN2BCL (*(volatile uint8_t *)(OTG_BASE + 0x14)) // missing in rt
256#define OTG_IN2BCH (*(volatile uint8_t *)(OTG_BASE + 0x15)) // missing in rt
257#define OTG_IN2CON (*(volatile uint8_t *)(OTG_BASE + 0x16)) // ok
258#define OTG_IN2CS (*(volatile uint8_t *)(OTG_BASE + 0x17)) //
259
260#define OTG_FIFO1DAT (*(volatile uint32_t *)(OTG_BASE + 0x84)) // missing in rt
261#define OTG_FIFO2DAT (*(volatile uint32_t *)(OTG_BASE + 0x88)) // missing in rt
262
263#define OTG_EP0INDAT (*(volatile uint8_t *)(OTG_BASE + 0x100) // ok
264
265#define OTG_EP0OUTDAT (*(volatile uint8_t *)(OTG_BASE + 0x140) // ok
266
267#define OTG_SETUPDAT (*(volatile uint8_t *)(OTG_BASE + 0x180) // ok
268#define OTG_USBIRQ (*(volatile uint8_t *)(OTG_BASE + 0x18C) // ok
269
270#define OTG_USBIEN (*(volatile uint8_t *)(OTG_BASE + 0x198)) // ok
271
272#define OTG_IVECT (*(volatile uint8_t *)(OTG_BASE + 0x1A0)) // missing in rt
273#define OTG_ENDPRST (*(volatile uint8_t *)(OTG_BASE + 0x1A2)) // ok
274#define OTG_USBCS (*(volatile uint8_t *)(OTG_BASE + 0x1A3)) // ok
275#define SOFT_DISCONN (1<<6) // set for soft disconnect
276
277#define OTG_FIFOCTL (*(volatile uint8_t *)(OTG_BASE + 0x1A8)) // ok
278
279
280#define OTG_OTGIRQ (*(volatile uint8_t *)(OTG_BASE + 0x1BC))
281#define OTG_FSMSTAT (*(volatile uint8_t *)(OTG_BASE + 0x1BD))
282#define OTG_CTRL (*(volatile uint8_t *)(OTG_BASE + 0x1BE))
283#define OTG_STAT (*(volatile uint8_t *)(OTG_BASE + 0x1BF))
284#define OTG_OTGIEN (*(volatile uint8_t *)(OTG_BASE + 0x1C0))
285
286#define OTG_TAAIDLBDIS (*(volatile uint8_t *)(OTG_BASE + 0x1C1))
287#define OTG_TAWAITBCON (*(volatile uint8_t *)(OTG_BASE + 0x1C2))
288#define OTG_TBVBUSPLS (*(volatile uint8_t *)(OTG_BASE + 0x1C3))
289#define OTG_TBVBUSDISPLS (*(volatile uint8_t *)(OTG_BASE + 0x1C7))
290
291#define OTG_HCIN1MAXPCKL (*(volatile uint8_t *)(OTG_BASE + 0x1E2))
292#define OTG_HCIN1MAXPCKH (*(volatile uint8_t *)(OTG_BASE + 0x1E3))
293
294#define OTG_OUT1STADDR ((*(volatile uint8_t *)(OTG_BASE + 0x304))
295
296#define OTG_IN2STADDR ((*(volatile uint8_t *)(OTG_BASE + 0x348))
297
298#define OTG_HCOUT2MAXPCKL ((*(volatile uint8_t *)(OTG_BASE + 0x3E4))
299#define OTG_HCOUT2MAXPCKH ((*(volatile uint8_t *)(OTG_BASE + 0x3E5))
300
301#define OTG_USBEIRQ ((*(volatile uint8_t *)(OTG_BASE + 0x400))
302
303#define OTG_DMAEPSEL ((*(volatile uint8_t *)(OTG_BASE + 0x40C))
304
305#define YUV2RGB_BASE 0xB00F0000
306#define YUV2RGB_CTL (*(volatile uint32_t *)(YUV2RGB_BASE + 0x00))
307#define YUV2RGB_FIFODATA (*(volatile uint32_t *)(YUV2RGB_BASE + 0x04))
308#define YUV2RGB_CLKCTL (*(volatile uint32_t *)(YUV2RGB_BASE + 0x08))
309#define YUV2RGB_FRAMECOUNT (*(volatile uint32_t *)(YUV2RGB_BASE + 0x0C))
310
311#define DAC_BASE 0xB0100000
312#define DAC_CTL (*(volatile uint32_t *)(DAC_BASE + 0x00))
313#define DAC_FIFOCTL (*(volatile uint32_t *)(DAC_BASE + 0x04))
314#define DAC_DAT (*(volatile uint32_t *)(DAC_BASE + 0x08))
315#define DAC_DEBUG (*(volatile uint32_t *)(DAC_BASE + 0x0C))
316#define DAC_ANALOG (*(volatile uint32_t *)(DAC_BASE + 0x10))
317
318#define ADC_BASE 0xB0110000
319#define ADC_CTL (*(volatile uint32_t *)(ADC_BASE + 0x00))
320#define ADC_FIFOCTL (*(volatile uint32_t *)(ADC_BASE + 0x04))
321#define ADC_DAT (*(volatile uint32_t *)(ADC_BASE + 0x08))
322#define ADC_DEBUG (*(volatile uint32_t *)(ADC_BASE + 0x0C))
323#define ADC_ANALOG (*(volatile uint32_t *)(ADC_BASE + 0x10))
324
325#define TP_BASE 0xB0120000
326#define TP_CTL (*(volatile uint32_t *)(TP_BASE + 0x00))
327#define TP_DAT (*(volatile uint32_t *)(TP_BASE + 0x04))
328
329#define SPDIF_BASE 0xB0140000
330#define SPDIF_CTL (*(volatile uint32_t *)(SPDIF_BASE + 0x00))
331#define SPDIF_STAT (*(volatile uint32_t *)(SPDIF_BASE + 0x04))
332#define SPDIF_TXDAT (*(volatile uint32_t *)(SPDIF_BASE + 0x08))
333#define SPDIF_RXDAT (*(volatile uint32_t *)(SPDIF_BASE + 0x0C))
334#define SPDIF_TXCSTAT (*(volatile uint32_t *)(SPDIF_BASE + 0x10))
335#define SPDIF_RXCSTAT (*(volatile uint32_t *)(SPDIF_BASE + 0x14))
336
337#define PCM_BASE 0xB0150000
338#define PCM_CTL (*(volatile uint32_t *)(PCM_BASE + 0x00))
339#define PCM_STAT (*(volatile uint32_t *)(PCM_BASE + 0x04))
340#define PCM_RXDAT (*(volatile uint32_t *)(PCM_BASE + 0x08))
341#define PCM_TXDAT (*(volatile uint32_t *)(PCM_BASE + 0x0C))
342
343/* n = 0,1 */
344#define UART_BASE(n) (0xB0160000 + (n<<5))
345#define UART_CTL(n) (*(volatile uint32_t *)(UART_BASE(n) + 0x00))
346#define UART_RXDAT(n) (*(volatile uint32_t *)(UART_BASE(n) + 0x04))
347#define UART_TXDAT(n) (*(volatile uint32_t *)(UART_BASE(n) + 0x08))
348#define UART_STAT(n) (*(volatile uint32_t *)(UART_BASE(n) + 0x0C))
349
350#define IR_PL (*(volatile uint32_t *)(UART_BASE(0) + 0x10))
351#define IR_RBC (*(volatile uint32_t *)(UART_BASE(0) + 0x14))
352
353/* n = 0,1 */
354#define I2C_BASE(n) (0xB0180000 + (n<<5))
355#define I2C_CTL(n) (*(volatile uint32_t *)(I2C_BASE(n) + 0x00))
356#define I2C_CLKDIV(n) (*(volatile uint32_t *)(I2C_BASE(n) + 0x04))
357#define I2C_STAT(n) (*(volatile uint32_t *)(I2C_BASE(n) + 0x08))
358#define I2C_ADDR(n) (*(volatile uint32_t *)(I2C_BASE(n) + 0x0C))
359#define I2C_DAT(n) (*(volatile uint32_t *)(I2C_BASE(n) + 0x10))
360
361#define SPI_BASE 0xB0190000
362#define SPI_CTL (*(volatile uint32_t *)(SPI_BASE + 0x00))
363#define SPI_CLKDIV (*(volatile uint32_t *)(SPI_BASE + 0x04))
364#define SPI_STAT (*(volatile uint32_t *)(SPI_BASE + 0x08))
365#define SPI_RXDAT (*(volatile uint32_t *)(SPI_BASE + 0x0C))
366#define SPI_TXDAT (*(volatile uint32_t *)(SPI_BASE + 0x10))
367
368#define KEY_BASE 0xB01A0000
369#define KEY_CTL (*(volatile uint32_t *)(KEY_BASE + 0x00))
370#define KEY_DAT0 (*(volatile uint32_t *)(KEY_BASE + 0x04))
371#define KEY_DAT1 (*(volatile uint32_t *)(KEY_BASE + 0x08))
372#define KEY_DAT2 (*(volatile uint32_t *)(KEY_BASE + 0x0C))
373#define KEY_DAT3 (*(volatile uint32_t *)(KEY_BASE + 0x10))
374
375#define GPIO_BASE 0xB01C0000
376#define GPIO_AOUTEN (*(volatile uint32_t *)(GPIO_BASE + 0x00))
377#define GPIO_AINEN (*(volatile uint32_t *)(GPIO_BASE + 0x04))
378#define GPIO_ADAT (*(volatile uint32_t *)(GPIO_BASE + 0x08))
379#define GPIO_BOUTEN (*(volatile uint32_t *)(GPIO_BASE + 0x0C))
380#define GPIO_BINEN (*(volatile uint32_t *)(GPIO_BASE + 0x10))
381#define GPIO_BDAT (*(volatile uint32_t *)(GPIO_BASE + 0x14))
382#define GPIO_MFCTL0 (*(volatile uint32_t *)(GPIO_BASE + 0x18))
383#define GPIO_MFCTL1 (*(volatile uint32_t *)(GPIO_BASE + 0x1C))
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-24 12:28:18 +0000