diff options
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/target/arm/imx233/icoll-imx233.c | 18 | ||||
-rw-r--r-- | firmware/target/arm/imx233/icoll-imx233.h | 19 |
2 files changed, 9 insertions, 28 deletions
diff --git a/firmware/target/arm/imx233/icoll-imx233.c b/firmware/target/arm/imx233/icoll-imx233.c index 0d785337d0..1bd363e781 100644 --- a/firmware/target/arm/imx233/icoll-imx233.c +++ b/firmware/target/arm/imx233/icoll-imx233.c | |||
@@ -113,7 +113,7 @@ static uint32_t irq_count[INT_SRC_NR_SOURCES]; | |||
113 | struct imx233_icoll_irq_info_t imx233_icoll_get_irq_info(int src) | 113 | struct imx233_icoll_irq_info_t imx233_icoll_get_irq_info(int src) |
114 | { | 114 | { |
115 | struct imx233_icoll_irq_info_t info; | 115 | struct imx233_icoll_irq_info_t info; |
116 | info.enabled = !!(HW_ICOLL_INTERRUPT(src) & HW_ICOLL_INTERRUPT__ENABLE); | 116 | info.enabled = BF_RDn(ICOLL_INTERRUPTn, src, ENABLE); |
117 | info.freq = irq_count_old[src]; | 117 | info.freq = irq_count_old[src]; |
118 | return info; | 118 | return info; |
119 | } | 119 | } |
@@ -145,7 +145,7 @@ void irq_handler(void) | |||
145 | do_irq_stat(); | 145 | do_irq_stat(); |
146 | (*(isr_t *)HW_ICOLL_VECTOR)(); | 146 | (*(isr_t *)HW_ICOLL_VECTOR)(); |
147 | /* acknowledge completion of IRQ (all use the same priority 0) */ | 147 | /* acknowledge completion of IRQ (all use the same priority 0) */ |
148 | HW_ICOLL_LEVELACK = HW_ICOLL_LEVELACK__LEVEL0; | 148 | HW_ICOLL_LEVELACK = BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0; |
149 | } | 149 | } |
150 | 150 | ||
151 | void fiq_handler(void) | 151 | void fiq_handler(void) |
@@ -155,23 +155,21 @@ void fiq_handler(void) | |||
155 | void imx233_icoll_enable_interrupt(int src, bool enable) | 155 | void imx233_icoll_enable_interrupt(int src, bool enable) |
156 | { | 156 | { |
157 | if(enable) | 157 | if(enable) |
158 | __REG_SET(HW_ICOLL_INTERRUPT(src)) = HW_ICOLL_INTERRUPT__ENABLE; | 158 | BF_SETn(ICOLL_INTERRUPTn, src, ENABLE); |
159 | else | 159 | else |
160 | __REG_CLR(HW_ICOLL_INTERRUPT(src)) = HW_ICOLL_INTERRUPT__ENABLE; | 160 | BF_CLRn(ICOLL_INTERRUPTn, src, ENABLE); |
161 | } | 161 | } |
162 | 162 | ||
163 | void imx233_icoll_init(void) | 163 | void imx233_icoll_init(void) |
164 | { | 164 | { |
165 | imx233_reset_block(&HW_ICOLL_CTRL); | 165 | imx233_reset_block(&HW_ICOLL_CTRL); |
166 | /* disable all interrupts */ | 166 | /* disable all interrupts: |
167 | * priority = 0, disable, disable fiq */ | ||
167 | for(int i = 0; i < INT_SRC_NR_SOURCES; i++) | 168 | for(int i = 0; i < INT_SRC_NR_SOURCES; i++) |
168 | { | 169 | HW_ICOLL_INTERRUPTn(i) = 0; |
169 | /* priority = 0, disable, disable fiq */ | ||
170 | HW_ICOLL_INTERRUPT(i) = 0; | ||
171 | } | ||
172 | /* setup vbase as isr_table */ | 170 | /* setup vbase as isr_table */ |
173 | HW_ICOLL_VBASE = (uint32_t)&isr_table; | 171 | HW_ICOLL_VBASE = (uint32_t)&isr_table; |
174 | /* enable final irq bit */ | 172 | /* enable final irq bit */ |
175 | __REG_SET(HW_ICOLL_CTRL) = HW_ICOLL_CTRL__IRQ_FINAL_ENABLE; | 173 | BF_SET(ICOLL_CTRL, IRQ_FINAL_ENABLE); |
176 | } | 174 | } |
177 | 175 | ||
diff --git a/firmware/target/arm/imx233/icoll-imx233.h b/firmware/target/arm/imx233/icoll-imx233.h index d1bf8a18aa..e44b67f1d4 100644 --- a/firmware/target/arm/imx233/icoll-imx233.h +++ b/firmware/target/arm/imx233/icoll-imx233.h | |||
@@ -24,24 +24,7 @@ | |||
24 | #include "config.h" | 24 | #include "config.h" |
25 | #include "system.h" | 25 | #include "system.h" |
26 | 26 | ||
27 | /* Interrupt collector */ | 27 | #include "regs/regs-icoll.h" |
28 | #define HW_ICOLL_BASE 0x80000000 | ||
29 | |||
30 | #define HW_ICOLL_VECTOR (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x0)) | ||
31 | |||
32 | #define HW_ICOLL_LEVELACK (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x10)) | ||
33 | #define HW_ICOLL_LEVELACK__LEVEL0 0x1 | ||
34 | |||
35 | #define HW_ICOLL_CTRL (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x20)) | ||
36 | #define HW_ICOLL_CTRL__IRQ_FINAL_ENABLE (1 << 16) | ||
37 | #define HW_ICOLL_CTRL__ARM_RSE_MODE (1 << 18) | ||
38 | |||
39 | #define HW_ICOLL_VBASE (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x40)) | ||
40 | #define HW_ICOLL_INTERRUPT(i) (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x120 + (i) * 0x10)) | ||
41 | #define HW_ICOLL_INTERRUPT__PRIORITY_BM 0x3 | ||
42 | #define HW_ICOLL_INTERRUPT__ENABLE 0x4 | ||
43 | #define HW_ICOLL_INTERRUPT__SOFTIRQ 0x8 | ||
44 | #define HW_ICOLL_INTERRUPT__ENFIQ 0x10 | ||
45 | 28 | ||
46 | #define INT_SRC_SSP2_ERROR 2 | 29 | #define INT_SRC_SSP2_ERROR 2 |
47 | #define INT_SRC_VDD5V 3 | 30 | #define INT_SRC_VDD5V 3 |