diff options
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/SOURCES | 8 | ||||
-rw-r--r-- | firmware/drivers/serial.c | 172 | ||||
-rw-r--r-- | firmware/export/config/ipodmini2g.h | 13 | ||||
-rw-r--r-- | firmware/target/arm/pp/system-pp502x.c | 20 | ||||
-rw-r--r-- | firmware/target/arm/pp/uart-pp.c | 265 |
5 files changed, 292 insertions, 186 deletions
diff --git a/firmware/SOURCES b/firmware/SOURCES index e6c0b967d4..9c45808b66 100644 --- a/firmware/SOURCES +++ b/firmware/SOURCES | |||
@@ -595,10 +595,16 @@ target/arm/pp/wmcodec-pp.c | |||
595 | target/arm/pp/system-pp5002.c | 595 | target/arm/pp/system-pp5002.c |
596 | target/arm/pp/usb-fw-pp5002.c | 596 | target/arm/pp/usb-fw-pp5002.c |
597 | target/arm/pp/ata-pp5002.c | 597 | target/arm/pp/ata-pp5002.c |
598 | # ifdef HAVE_SERIAL | ||
599 | target/arm/pp/uart-pp.c | ||
600 | # endif /* HAVE_SERIAL */ | ||
598 | #elif defined CPU_PP502x | 601 | #elif defined CPU_PP502x |
599 | target/arm/pp/usb-fw-pp502x.c | 602 | target/arm/pp/usb-fw-pp502x.c |
600 | target/arm/pp/system-pp502x.c | 603 | target/arm/pp/system-pp502x.c |
601 | #endif | 604 | # ifdef HAVE_SERIAL |
605 | target/arm/pp/uart-pp.c | ||
606 | # endif /* HAVE_SERIAL */ | ||
607 | #endif /* (CONFIG_CPU==PP5002) || CPU_PP502x */ | ||
602 | #ifdef BOOTLOADER | 608 | #ifdef BOOTLOADER |
603 | #ifdef HAVE_BOOTLOADER_USB_MODE | 609 | #ifdef HAVE_BOOTLOADER_USB_MODE |
604 | target/arm/pp/crt0-pp502x-bl-usb.S | 610 | target/arm/pp/crt0-pp502x-bl-usb.S |
diff --git a/firmware/drivers/serial.c b/firmware/drivers/serial.c index a46342389d..0fab570fdc 100644 --- a/firmware/drivers/serial.c +++ b/firmware/drivers/serial.c | |||
@@ -21,179 +21,7 @@ | |||
21 | #include <stdio.h> | 21 | #include <stdio.h> |
22 | #include <stdlib.h> | 22 | #include <stdlib.h> |
23 | #include <stdarg.h> | 23 | #include <stdarg.h> |
24 | #include "button.h" | ||
25 | #include "config.h" | ||
26 | #include "cpu.h" | ||
27 | #include "system.h" | ||
28 | #include "kernel.h" | ||
29 | #include "lcd.h" | ||
30 | #include "serial.h" | 24 | #include "serial.h" |
31 | #include "iap.h" | ||
32 | |||
33 | #if defined(IPOD_ACCESSORY_PROTOCOL) | ||
34 | static int autobaud = 0; | ||
35 | |||
36 | static void set_bitrate(unsigned int rate) | ||
37 | { | ||
38 | unsigned int divisor; | ||
39 | |||
40 | divisor = 24000000L / rate / 16; | ||
41 | SER0_LCR = 0x80; /* Divisor latch enable */ | ||
42 | SER0_DLL = (divisor >> 0) & 0xFF; | ||
43 | SER0_LCR = 0x03; /* Divisor latch disable, 8-N-1 */ | ||
44 | } | ||
45 | |||
46 | void serial_setup (void) | ||
47 | { | ||
48 | int tmp; | ||
49 | |||
50 | #if defined(IPOD_COLOR) || defined(IPOD_4G) | ||
51 | /* Route the Tx/Rx pins. 4G Ipod??? */ | ||
52 | outl(0x70000018, inl(0x70000018) & ~0xc00); | ||
53 | #elif defined(IPOD_NANO) || defined(IPOD_VIDEO) | ||
54 | /* Route the Tx/Rx pins. 5G Ipod */ | ||
55 | (*(volatile unsigned long *)(0x7000008C)) &= ~0x0C; | ||
56 | GPO32_ENABLE &= ~0x0C; | ||
57 | #endif | ||
58 | |||
59 | DEV_EN = DEV_EN | DEV_SER0; | ||
60 | CPU_HI_INT_DIS = SER0_MASK; | ||
61 | |||
62 | DEV_RS |= DEV_SER0; | ||
63 | sleep(1); | ||
64 | DEV_RS &= ~DEV_SER0; | ||
65 | |||
66 | SER0_LCR = 0x80; /* Divisor latch enable */ | ||
67 | SER0_DLM = 0x00; | ||
68 | SER0_LCR = 0x03; /* Divisor latch disable, 8-N-1 */ | ||
69 | SER0_IER = 0x01; | ||
70 | |||
71 | SER0_FCR = 0x07; /* Tx+Rx FIFO reset and FIFO enable */ | ||
72 | |||
73 | CPU_INT_EN |= HI_MASK; | ||
74 | CPU_HI_INT_EN |= SER0_MASK; | ||
75 | tmp = SER0_RBR; | ||
76 | |||
77 | serial_bitrate(0); | ||
78 | } | ||
79 | |||
80 | void serial_bitrate(int rate) | ||
81 | { | ||
82 | if(rate == 0) | ||
83 | { | ||
84 | autobaud = 2; | ||
85 | set_bitrate(115200); | ||
86 | } | ||
87 | else | ||
88 | { | ||
89 | autobaud = 0; | ||
90 | set_bitrate(rate); | ||
91 | } | ||
92 | } | ||
93 | |||
94 | int tx_rdy(void) | ||
95 | { | ||
96 | if((SER0_LSR & 0x20)) | ||
97 | return 1; | ||
98 | else | ||
99 | return 0; | ||
100 | } | ||
101 | |||
102 | static int rx_rdy(void) | ||
103 | { | ||
104 | if((SER0_LSR & 0x1)) | ||
105 | return 1; | ||
106 | else | ||
107 | return 0; | ||
108 | } | ||
109 | |||
110 | void tx_writec(unsigned char c) | ||
111 | { | ||
112 | SER0_THR =(int) c; | ||
113 | } | ||
114 | |||
115 | static unsigned char rx_readc(void) | ||
116 | { | ||
117 | return (SER0_RBR & 0xFF); | ||
118 | } | ||
119 | |||
120 | void SERIAL0(void) | ||
121 | { | ||
122 | static int badbaud = 0; | ||
123 | static bool newpkt = true; | ||
124 | char temp; | ||
125 | |||
126 | while(rx_rdy()) | ||
127 | { | ||
128 | temp = rx_readc(); | ||
129 | if (newpkt && autobaud > 0) | ||
130 | { | ||
131 | if (autobaud == 1) | ||
132 | { | ||
133 | switch (temp) | ||
134 | { | ||
135 | case 0xFF: | ||
136 | case 0x55: | ||
137 | break; | ||
138 | case 0xFC: | ||
139 | set_bitrate(19200); | ||
140 | temp = 0xFF; | ||
141 | break; | ||
142 | case 0xE0: | ||
143 | set_bitrate(9600); | ||
144 | temp = 0xFF; | ||
145 | break; | ||
146 | default: | ||
147 | badbaud++; | ||
148 | if (badbaud >= 6) /* Switch baud detection mode */ | ||
149 | { | ||
150 | autobaud = 2; | ||
151 | set_bitrate(115200); | ||
152 | badbaud = 0; | ||
153 | } else { | ||
154 | set_bitrate(57600); | ||
155 | } | ||
156 | continue; | ||
157 | } | ||
158 | } else { | ||
159 | switch (temp) | ||
160 | { | ||
161 | case 0xFF: | ||
162 | case 0x55: | ||
163 | break; | ||
164 | case 0xFE: | ||
165 | set_bitrate(57600); | ||
166 | temp = 0xFF; | ||
167 | break; | ||
168 | case 0xFC: | ||
169 | set_bitrate(38400); | ||
170 | temp = 0xFF; | ||
171 | break; | ||
172 | case 0xE0: | ||
173 | set_bitrate(19200); | ||
174 | temp = 0xFF; | ||
175 | break; | ||
176 | default: | ||
177 | badbaud++; | ||
178 | if (badbaud >= 6) /* Switch baud detection */ | ||
179 | { | ||
180 | autobaud = 1; | ||
181 | set_bitrate(57600); | ||
182 | badbaud = 0; | ||
183 | } else { | ||
184 | set_bitrate(115200); | ||
185 | } | ||
186 | continue; | ||
187 | } | ||
188 | } | ||
189 | } | ||
190 | bool pkt = iap_getc(temp); | ||
191 | if(newpkt && !pkt) | ||
192 | autobaud = 0; /* Found good baud */ | ||
193 | newpkt = pkt; | ||
194 | } | ||
195 | } | ||
196 | #endif | ||
197 | 25 | ||
198 | void dprintf(const char * str, ... ) | 26 | void dprintf(const char * str, ... ) |
199 | { | 27 | { |
diff --git a/firmware/export/config/ipodmini2g.h b/firmware/export/config/ipodmini2g.h index 12f63f9e11..5e4731679f 100644 --- a/firmware/export/config/ipodmini2g.h +++ b/firmware/export/config/ipodmini2g.h | |||
@@ -18,6 +18,8 @@ | |||
18 | /* define this if you have recording possibility */ | 18 | /* define this if you have recording possibility */ |
19 | /*#define HAVE_RECORDING*/ | 19 | /*#define HAVE_RECORDING*/ |
20 | 20 | ||
21 | #define INPUT_SRC_CAPS (SRC_CAP_FMRADIO) | ||
22 | |||
21 | /* define the bitmask of hardware sample rates */ | 23 | /* define the bitmask of hardware sample rates */ |
22 | #define HW_SAMPR_CAPS (SAMPR_CAP_96 | SAMPR_CAP_88 | SAMPR_CAP_48 | \ | 24 | #define HW_SAMPR_CAPS (SAMPR_CAP_96 | SAMPR_CAP_88 | SAMPR_CAP_48 | \ |
23 | SAMPR_CAP_44 | SAMPR_CAP_32 | SAMPR_CAP_8) | 25 | SAMPR_CAP_44 | SAMPR_CAP_32 | SAMPR_CAP_8) |
@@ -156,6 +158,11 @@ | |||
156 | * if USB/MAIN power is discernable and hardware doesn't compel charging */ | 158 | * if USB/MAIN power is discernable and hardware doesn't compel charging */ |
157 | #define HAVE_USB_CHARGING_ENABLE | 159 | #define HAVE_USB_CHARGING_ENABLE |
158 | 160 | ||
161 | |||
162 | /* Define Apple remote tuner */ | ||
163 | #define CONFIG_TUNER IPOD_REMOTE_TUNER | ||
164 | #define HAVE_RDS_CAP | ||
165 | |||
159 | /* Define this if you have a PortalPlayer PP5022 */ | 166 | /* Define this if you have a PortalPlayer PP5022 */ |
160 | #define CONFIG_CPU PP5022 | 167 | #define CONFIG_CPU PP5022 |
161 | 168 | ||
@@ -166,7 +173,7 @@ | |||
166 | #define HAVE_ATA_POWER_OFF | 173 | #define HAVE_ATA_POWER_OFF |
167 | 174 | ||
168 | /* define this if the hardware can be powered off while charging */ | 175 | /* define this if the hardware can be powered off while charging */ |
169 | //#define HAVE_POWEROFF_WHILE_CHARGING | 176 | /*#define HAVE_POWEROFF_WHILE_CHARGING */ |
170 | 177 | ||
171 | /* The start address index for ROM builds */ | 178 | /* The start address index for ROM builds */ |
172 | #define ROM_START 0x00000000 | 179 | #define ROM_START 0x00000000 |
@@ -212,8 +219,10 @@ | |||
212 | 219 | ||
213 | #define ICODE_ATTR_TREMOR_NOT_MDCT | 220 | #define ICODE_ATTR_TREMOR_NOT_MDCT |
214 | 221 | ||
215 | #define IRAM_LCDFRAMEBUFFER IBSS_ATTR /* put the lcd frame buffer in IRAM */ | 222 | #define IPOD_ACCESSORY_PROTOCOL |
223 | #define HAVE_SERIAL | ||
216 | 224 | ||
225 | #define IRAM_LCDFRAMEBUFFER IBSS_ATTR /* put the lcd frame buffer in IRAM */ | ||
217 | 226 | ||
218 | /* DMA is used only for reading on PP502x because although reads are ~8x faster | 227 | /* DMA is used only for reading on PP502x because although reads are ~8x faster |
219 | * writes appear to be ~25% slower. | 228 | * writes appear to be ~25% slower. |
diff --git a/firmware/target/arm/pp/system-pp502x.c b/firmware/target/arm/pp/system-pp502x.c index d3331bf9f4..af2e6d7761 100644 --- a/firmware/target/arm/pp/system-pp502x.c +++ b/firmware/target/arm/pp/system-pp502x.c | |||
@@ -32,7 +32,7 @@ | |||
32 | #if !defined(BOOTLOADER) || defined(HAVE_BOOTLOADER_USB_MODE) | 32 | #if !defined(BOOTLOADER) || defined(HAVE_BOOTLOADER_USB_MODE) |
33 | extern void TIMER1(void); | 33 | extern void TIMER1(void); |
34 | extern void TIMER2(void); | 34 | extern void TIMER2(void); |
35 | extern void SERIAL0(void); | 35 | extern void SERIAL_ISR(void); |
36 | 36 | ||
37 | #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1) | 37 | #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1) |
38 | static struct corelock cpufreq_cl SHAREDBSS_ATTR; | 38 | static struct corelock cpufreq_cl SHAREDBSS_ATTR; |
@@ -126,7 +126,6 @@ void __attribute__((interrupt("IRQ"))) irq_handler(void) | |||
126 | button_int(); | 126 | button_int(); |
127 | if (GPIOD_INT_STAT & 0x80) | 127 | if (GPIOD_INT_STAT & 0x80) |
128 | headphones_int(); | 128 | headphones_int(); |
129 | |||
130 | } | 129 | } |
131 | else if (CPU_HI_INT_STAT & GPIO2_MASK) { | 130 | else if (CPU_HI_INT_STAT & GPIO2_MASK) { |
132 | if (GPIOL_INT_STAT & 0x04) | 131 | if (GPIOL_INT_STAT & 0x04) |
@@ -169,8 +168,8 @@ void __attribute__((interrupt("IRQ"))) irq_handler(void) | |||
169 | /* end PBELL_VIBE500 */ | 168 | /* end PBELL_VIBE500 */ |
170 | #endif | 169 | #endif |
171 | #ifdef IPOD_ACCESSORY_PROTOCOL | 170 | #ifdef IPOD_ACCESSORY_PROTOCOL |
172 | else if (CPU_HI_INT_STAT & SER0_MASK) { | 171 | else if (CPU_HI_INT_STAT & (SER0_MASK | SER1_MASK)) { |
173 | SERIAL0(); | 172 | SERIAL_ISR(); |
174 | } | 173 | } |
175 | #endif | 174 | #endif |
176 | } else { | 175 | } else { |
@@ -310,7 +309,7 @@ void set_cpu_frequency(long frequency) | |||
310 | #else | 309 | #else |
311 | static void pp_set_cpu_frequency(long frequency) | 310 | static void pp_set_cpu_frequency(long frequency) |
312 | #endif | 311 | #endif |
313 | { | 312 | { |
314 | #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1) | 313 | #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1) |
315 | corelock_lock(&cpufreq_cl); | 314 | corelock_lock(&cpufreq_cl); |
316 | #endif | 315 | #endif |
@@ -334,7 +333,7 @@ static void pp_set_cpu_frequency(long frequency) | |||
334 | PLL_CONTROL &= ~0x80000000; /* disable PLL */ | 333 | PLL_CONTROL &= ~0x80000000; /* disable PLL */ |
335 | DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */ | 334 | DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */ |
336 | break; | 335 | break; |
337 | 336 | ||
338 | case CPUFREQ_MAX: | 337 | case CPUFREQ_MAX: |
339 | cpu_frequency = CPUFREQ_MAX; | 338 | cpu_frequency = CPUFREQ_MAX; |
340 | DEV_INIT2 |= INIT_PLL; /* enable PLL power */ | 339 | DEV_INIT2 |= INIT_PLL; /* enable PLL power */ |
@@ -379,7 +378,7 @@ static void pp_set_cpu_frequency(long frequency) | |||
379 | DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */ | 378 | DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */ |
380 | break; | 379 | break; |
381 | #else /******** CPUFREQ_NORMAL = 30MHz with PLL ********/ | 380 | #else /******** CPUFREQ_NORMAL = 30MHz with PLL ********/ |
382 | case CPUFREQ_NORMAL: | 381 | case CPUFREQ_NORMAL: |
383 | cpu_frequency = CPUFREQ_NORMAL; | 382 | cpu_frequency = CPUFREQ_NORMAL; |
384 | DEV_INIT2 |= INIT_PLL; /* enable PLL power */ | 383 | DEV_INIT2 |= INIT_PLL; /* enable PLL power */ |
385 | PLL_CONTROL |= 0x88000000; /* enable PLL */ | 384 | PLL_CONTROL |= 0x88000000; /* enable PLL */ |
@@ -421,7 +420,7 @@ static void pp_set_cpu_frequency(long frequency) | |||
421 | DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */ | 420 | DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */ |
422 | break; | 421 | break; |
423 | } | 422 | } |
424 | 423 | ||
425 | #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1) | 424 | #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1) |
426 | corelock_unlock(&cpufreq_cl); | 425 | corelock_unlock(&cpufreq_cl); |
427 | #endif | 426 | #endif |
@@ -447,7 +446,7 @@ void system_init(void) | |||
447 | DEV_RS2 = 0xffffdfff; | 446 | DEV_RS2 = 0xffffdfff; |
448 | DEV_RS = 0x00000000; | 447 | DEV_RS = 0x00000000; |
449 | DEV_RS2 = 0x00000000; | 448 | DEV_RS2 = 0x00000000; |
450 | #elif defined (IPOD_VIDEO) | 449 | #elif defined (IPOD_VIDEO) |
451 | /* set minimum startup configuration */ | 450 | /* set minimum startup configuration */ |
452 | DEV_EN = 0xc2000124; | 451 | DEV_EN = 0xc2000124; |
453 | DEV_EN2 = 0x00000000; | 452 | DEV_EN2 = 0x00000000; |
@@ -461,7 +460,7 @@ void system_init(void) | |||
461 | DEV_RS2 = 0xffffffff; | 460 | DEV_RS2 = 0xffffffff; |
462 | DEV_RS = 0x00000000; | 461 | DEV_RS = 0x00000000; |
463 | DEV_RS2 = 0x00000000; | 462 | DEV_RS2 = 0x00000000; |
464 | #elif defined (IPOD_NANO) | 463 | #elif defined (IPOD_NANO) |
465 | /* set minimum startup configuration */ | 464 | /* set minimum startup configuration */ |
466 | DEV_EN = 0xc2000124; | 465 | DEV_EN = 0xc2000124; |
467 | DEV_EN2 = 0x00002000; | 466 | DEV_EN2 = 0x00002000; |
@@ -625,4 +624,3 @@ int system_memory_guard(int newmode) | |||
625 | (void)newmode; | 624 | (void)newmode; |
626 | return 0; | 625 | return 0; |
627 | } | 626 | } |
628 | |||
diff --git a/firmware/target/arm/pp/uart-pp.c b/firmware/target/arm/pp/uart-pp.c new file mode 100644 index 0000000000..612ffdf77c --- /dev/null +++ b/firmware/target/arm/pp/uart-pp.c | |||
@@ -0,0 +1,265 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2002 by Alan Korr & Nick Robinson | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #include <stdio.h> | ||
22 | #include <stdlib.h> | ||
23 | #include <stdarg.h> | ||
24 | #include "button.h" | ||
25 | #include "config.h" | ||
26 | #include "cpu.h" | ||
27 | #include "system.h" | ||
28 | #include "kernel.h" | ||
29 | #include "lcd.h" | ||
30 | #include "serial.h" | ||
31 | #include "iap.h" | ||
32 | |||
33 | #if defined(IPOD_ACCESSORY_PROTOCOL) | ||
34 | static int autobaud = 0; | ||
35 | volatile unsigned long * base_RBR, * base_THR, * base_LCR, * base_LSR, * base_DLL; | ||
36 | |||
37 | static void set_bitrate(unsigned int rate) | ||
38 | { | ||
39 | unsigned int divisor; | ||
40 | |||
41 | divisor = 24000000L / rate / 16; | ||
42 | *base_LCR = 0x80; /* Divisor latch enable */ | ||
43 | *base_DLL = (divisor >> 0) & 0xFF; | ||
44 | *base_LCR = 0x03; /* Divisor latch disable, 8-N-1 */ | ||
45 | } | ||
46 | |||
47 | void serial_setup (void) | ||
48 | { | ||
49 | int tmp; | ||
50 | |||
51 | #if defined(IPOD_COLOR) || defined(IPOD_4G) || defined(IPOD_MINI2G) | ||
52 | |||
53 | /* Route the Tx/Rx pins. 4G Ipod, ser1, dock connector */ | ||
54 | GPIO_CLEAR_BITWISE(GPIOD_ENABLE, 0x6); | ||
55 | GPIO_CLEAR_BITWISE(GPIOD_OUTPUT_EN, 0x6); | ||
56 | |||
57 | outl(0x70000018, inl(0x70000018) & ~0xc00); | ||
58 | |||
59 | base_RBR = &SER1_RBR; | ||
60 | base_THR = &SER1_THR; | ||
61 | base_LCR = &SER1_LCR; | ||
62 | base_LSR = &SER1_LSR; | ||
63 | base_DLL = &SER1_DLL; | ||
64 | |||
65 | DEV_EN |= DEV_SER1; | ||
66 | CPU_HI_INT_DIS = SER1_MASK; | ||
67 | |||
68 | DEV_RS |= DEV_SER1; | ||
69 | sleep(1); | ||
70 | DEV_RS &= ~DEV_SER1; | ||
71 | |||
72 | SER1_LCR = 0x80; /* Divisor latch enable */ | ||
73 | SER1_DLM = 0x00; | ||
74 | SER1_LCR = 0x03; /* Divisor latch disable, 8-N-1 */ | ||
75 | SER1_IER = 0x01; | ||
76 | |||
77 | SER1_FCR = 0x07; /* Tx+Rx FIFO reset and FIFO enable */ | ||
78 | |||
79 | CPU_INT_EN = HI_MASK; | ||
80 | CPU_HI_INT_EN = SER1_MASK; | ||
81 | tmp = SER1_RBR; | ||
82 | |||
83 | #elif defined(IPOD_NANO) || defined(IPOD_VIDEO) | ||
84 | /* Route the Tx/Rx pins. 5G Ipod */ | ||
85 | (*(volatile unsigned long *)(0x7000008C)) &= ~0x0C; | ||
86 | GPO32_ENABLE &= ~0x0C; | ||
87 | |||
88 | base_RBR = &SER0_RBR; | ||
89 | base_THR = &SER0_THR; | ||
90 | base_LCR = &SER0_LCR; | ||
91 | base_LSR = &SER0_LSR; | ||
92 | base_DLL = &SER0_DLL; | ||
93 | |||
94 | DEV_EN = DEV_EN | DEV_SER0; | ||
95 | CPU_HI_INT_DIS = SER0_MASK; | ||
96 | |||
97 | DEV_RS |= DEV_SER0; | ||
98 | sleep(1); | ||
99 | DEV_RS &= ~DEV_SER0; | ||
100 | |||
101 | SER0_LCR = 0x80; /* Divisor latch enable */ | ||
102 | SER0_DLM = 0x00; | ||
103 | SER0_LCR = 0x03; /* Divisor latch disable, 8-N-1 */ | ||
104 | SER0_IER = 0x01; | ||
105 | |||
106 | SER0_FCR = 0x07; /* Tx+Rx FIFO reset and FIFO enable */ | ||
107 | |||
108 | CPU_INT_EN = HI_MASK; | ||
109 | CPU_HI_INT_EN = SER0_MASK; | ||
110 | tmp = SER0_RBR; | ||
111 | |||
112 | #else | ||
113 | |||
114 | /* Default Route the Tx/Rx pins. 4G Ipod, ser0, top connector */ | ||
115 | |||
116 | GPIO_CLEAR_BITWISE(GPIOC_INT_EN, 0x8); | ||
117 | GPIO_CLEAR_BITWISE(GPIOC_INT_LEV, 0x8); | ||
118 | GPIOC_INT_CLR = 0x8; | ||
119 | |||
120 | base_RBR = &SER0_RBR; | ||
121 | base_THR = &SER0_THR; | ||
122 | base_LCR = &SER0_LCR; | ||
123 | base_LSR = &SER0_LSR; | ||
124 | base_DLL = &SER0_DLL; | ||
125 | |||
126 | DEV_EN |= DEV_SER0; | ||
127 | CPU_HI_INT_DIS = SER0_MASK; | ||
128 | |||
129 | DEV_RS |= DEV_SER0; | ||
130 | sleep(1); | ||
131 | DEV_RS &= ~DEV_SER0; | ||
132 | |||
133 | SER0_LCR = 0x80; /* Divisor latch enable */ | ||
134 | SER0_DLM = 0x00; | ||
135 | SER0_LCR = 0x03; /* Divisor latch disable, 8-N-1 */ | ||
136 | SER0_IER = 0x01; | ||
137 | |||
138 | SER0_FCR = 0x07; /* Tx+Rx FIFO reset and FIFO enable */ | ||
139 | |||
140 | CPU_INT_EN = HI_MASK; | ||
141 | CPU_HI_INT_EN = SER0_MASK; | ||
142 | tmp = SER0_RBR; | ||
143 | |||
144 | #endif | ||
145 | |||
146 | serial_bitrate(0); | ||
147 | } | ||
148 | |||
149 | void serial_bitrate(int rate) | ||
150 | { | ||
151 | if(rate == 0) | ||
152 | { | ||
153 | autobaud = 2; | ||
154 | set_bitrate(115200); | ||
155 | } | ||
156 | else | ||
157 | { | ||
158 | autobaud = 0; | ||
159 | set_bitrate(rate); | ||
160 | } | ||
161 | } | ||
162 | |||
163 | int tx_rdy(void) | ||
164 | { | ||
165 | if((*base_LSR & 0x20)) | ||
166 | return 1; | ||
167 | else | ||
168 | return 0; | ||
169 | } | ||
170 | |||
171 | static int rx_rdy(void) | ||
172 | { | ||
173 | if((*base_LSR & 0x1)) | ||
174 | return 1; | ||
175 | else | ||
176 | return 0; | ||
177 | } | ||
178 | |||
179 | void tx_writec(unsigned char c) | ||
180 | { | ||
181 | *base_THR =(int) c; | ||
182 | } | ||
183 | |||
184 | static unsigned char rx_readc(void) | ||
185 | { | ||
186 | return (*base_RBR & 0xFF); | ||
187 | } | ||
188 | |||
189 | void SERIAL_ISR(void) | ||
190 | { | ||
191 | static int badbaud = 0; | ||
192 | static bool newpkt = true; | ||
193 | char temp; | ||
194 | |||
195 | while(rx_rdy()) | ||
196 | { | ||
197 | temp = rx_readc(); | ||
198 | if (newpkt && autobaud > 0) | ||
199 | { | ||
200 | if (autobaud == 1) | ||
201 | { | ||
202 | switch (temp) | ||
203 | { | ||
204 | case 0xFF: | ||
205 | case 0x55: | ||
206 | break; | ||
207 | case 0xFC: | ||
208 | set_bitrate(19200); | ||
209 | temp = 0xFF; | ||
210 | break; | ||
211 | case 0xE0: | ||
212 | set_bitrate(9600); | ||
213 | temp = 0xFF; | ||
214 | break; | ||
215 | default: | ||
216 | badbaud++; | ||
217 | if (badbaud >= 6) /* Switch baud detection mode */ | ||
218 | { | ||
219 | autobaud = 2; | ||
220 | set_bitrate(115200); | ||
221 | badbaud = 0; | ||
222 | } else { | ||
223 | set_bitrate(57600); | ||
224 | } | ||
225 | continue; | ||
226 | } | ||
227 | } else { | ||
228 | switch (temp) | ||
229 | { | ||
230 | case 0xFF: | ||
231 | case 0x55: | ||
232 | break; | ||
233 | case 0xFE: | ||
234 | set_bitrate(57600); | ||
235 | temp = 0xFF; | ||
236 | break; | ||
237 | case 0xFC: | ||
238 | set_bitrate(38400); | ||
239 | temp = 0xFF; | ||
240 | break; | ||
241 | case 0xE0: | ||
242 | set_bitrate(19200); | ||
243 | temp = 0xFF; | ||
244 | break; | ||
245 | default: | ||
246 | badbaud++; | ||
247 | if (badbaud >= 6) /* Switch baud detection */ | ||
248 | { | ||
249 | autobaud = 1; | ||
250 | set_bitrate(57600); | ||
251 | badbaud = 0; | ||
252 | } else { | ||
253 | set_bitrate(115200); | ||
254 | } | ||
255 | continue; | ||
256 | } | ||
257 | } | ||
258 | } | ||
259 | bool pkt = iap_getc(temp); | ||
260 | if(newpkt && !pkt) | ||
261 | autobaud = 0; /* Found good baud */ | ||
262 | newpkt = pkt; | ||
263 | } | ||
264 | } | ||
265 | #endif | ||