2 files changed, 12 insertions, 0 deletions

diff --git a/firmware/target/arm/tms320dm320/app.lds b/firmware/target/arm/tms320dm320/app.lds
index 64610a3577..0a9aa85bc4 100644
--- a/firmware/target/arm/tms320dm320/app.lds
+++ b/firmware/target/arm/tms320dm320/app.lds
@@ -81,9 +81,13 @@ SECTIONS
         _vectorsstart = .;
         *(.vectors);
         _vectorsend = .;
+#ifndef CREATIVE_ZVx
     } > IRAM AT> DRAM
 
     _vectorscopy = LOADADDR(.vectors);
+#else
+    } > IRAM
+#endif
 
     .iram :
     {
@@ -93,9 +97,13 @@ SECTIONS
         *(.idata)
         . = ALIGN(0x4);
         _iramend = .;
+#ifndef CREATIVE_ZVx
     } > IRAM AT> DRAM
 
     _iramcopy = LOADADDR(.iram);
+#else
+    } > IRAM
+#endif
 
     .ibss (NOLOAD) :
     {
diff --git a/firmware/target/arm/tms320dm320/crt0.S b/firmware/target/arm/tms320dm320/crt0.S
index a0b5a5abfb..ba5daa9117 100755
--- a/firmware/target/arm/tms320dm320/crt0.S
+++ b/firmware/target/arm/tms320dm320/crt0.S
@@ -44,6 +44,7 @@ start:
 
     msr    cpsr, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
 
+#ifndef CREATIVE_ZVx
     /* Copy exception handler code to address 0 */
     ldr    r2, =_vectorsstart
     ldr    r3, =_vectorsend
@@ -53,6 +54,7 @@ start:
     ldrhi  r5, [r4], #4
     strhi  r5, [r2], #4
     bhi    1b
+#endif
 
     /* Disable data and instruction cache, high vectors (at 0xffff0000 instead of 0x00000000) */
     mrc    p15, 0, r0, c1, c0, 0
@@ -105,6 +107,7 @@ start:
     strhi  r4, [r2], #4
     bhi    1b
 
+#ifndef CREATIVE_ZVx
     /* Copy the IRAM */
     ldr    r2, =_iramcopy
     ldr    r3, =_iramstart
@@ -114,6 +117,7 @@ start:
     ldrhi  r5, [r2], #4
     strhi  r5, [r3], #4
     bhi    1b
+#endif
 #endif /* !BOOTLOADER,!STUB */
 
     /* Initialise bss section to zero */