diff options
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/export/jz4740.h | 102 | ||||
-rw-r--r-- | firmware/export/r61509.h | 1 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c | 71 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/lcd-target.h | 2 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c | 106 |
5 files changed, 177 insertions, 105 deletions
diff --git a/firmware/export/jz4740.h b/firmware/export/jz4740.h index cacdd1e488..b0f3f538a3 100644 --- a/firmware/export/jz4740.h +++ b/firmware/export/jz4740.h | |||
@@ -1305,10 +1305,10 @@ | |||
1305 | #define ICDC_CDCCR1_SUSPD (1 << 1) | 1305 | #define ICDC_CDCCR1_SUSPD (1 << 1) |
1306 | #define ICDC_CDCCR1_RST (1 << 0) | 1306 | #define ICDC_CDCCR1_RST (1 << 0) |
1307 | 1307 | ||
1308 | #define ICDC_CDCCR2_AINVOL(n) ((n & 5) << 16) | 1308 | #define ICDC_CDCCR2_AINVOL(n) ((n & 0x1F) << 16) |
1309 | #define ICDC_CDCCR2_SMPR(n) ((n & 4) << 8) | 1309 | #define ICDC_CDCCR2_SMPR(n) ((n & 0xF) << 8) |
1310 | #define ICDC_CDCCR2_MICBG(n) ((n & 2) << 4) | 1310 | #define ICDC_CDCCR2_MICBG(n) ((n & 0x3) << 4) |
1311 | #define ICDC_CDCCR2_HPVOL(n) ((n & 2) << 0) | 1311 | #define ICDC_CDCCR2_HPVOL(n) ((n & 0x3) << 0) |
1312 | 1312 | ||
1313 | #define ICDC_CDCCR2_AINVOL_DB(n) ((n+34.5)/1.5) | 1313 | #define ICDC_CDCCR2_AINVOL_DB(n) ((n+34.5)/1.5) |
1314 | 1314 | ||
@@ -1423,7 +1423,7 @@ | |||
1423 | #define SSI_CR1_MULTS (1 << 22) | 1423 | #define SSI_CR1_MULTS (1 << 22) |
1424 | #define SSI_CR1_FMAT_BIT 20 | 1424 | #define SSI_CR1_FMAT_BIT 20 |
1425 | #define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) | 1425 | #define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) |
1426 | #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */ | 1426 | #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */ |
1427 | #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ | 1427 | #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ |
1428 | #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ | 1428 | #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ |
1429 | #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ | 1429 | #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ |
@@ -4984,7 +4984,7 @@ do{ \ | |||
4984 | 4984 | ||
4985 | // IPU_REG_BASE | 4985 | // IPU_REG_BASE |
4986 | #define IPU_P_BASE 0x13080000 | 4986 | #define IPU_P_BASE 0x13080000 |
4987 | #define IPU__OFFSET 0x13080000 | 4987 | #define IPU_V_BASE 0xB3080000 |
4988 | #define IPU__SIZE 0x00001000 | 4988 | #define IPU__SIZE 0x00001000 |
4989 | 4989 | ||
4990 | struct ipu_module | 4990 | struct ipu_module |
@@ -5069,10 +5069,12 @@ struct Ration2m | |||
5069 | #define INFMT_YCbCr422 (5 << 0) | 5069 | #define INFMT_YCbCr422 (5 << 0) |
5070 | #define INFMT_YCbCr444 (6 << 0) | 5070 | #define INFMT_YCbCr444 (6 << 0) |
5071 | #define INFMT_YCbCr411 (7 << 0) | 5071 | #define INFMT_YCbCr411 (7 << 0) |
5072 | #define INFMT_MASK (7) | ||
5072 | 5073 | ||
5073 | #define OUTFMT_RGB555 (0 << 16) | 5074 | #define OUTFMT_RGB555 (0 << 16) |
5074 | #define OUTFMT_RGB565 (1 << 16) | 5075 | #define OUTFMT_RGB565 (1 << 16) |
5075 | #define OUTFMT_RGB888 (2 << 16) | 5076 | #define OUTFMT_RGB888 (2 << 16) |
5077 | #define OUTFMT_MASK (3 << 16) | ||
5076 | 5078 | ||
5077 | // REG_IN_FM_GS field define | 5079 | // REG_IN_FM_GS field define |
5078 | #define IN_FM_W(val) ((val) << 16) | 5080 | #define IN_FM_W(val) ((val) << 16) |
@@ -5086,7 +5088,6 @@ struct Ration2m | |||
5086 | #define U_STRIDE(val) ((val) << 16) | 5088 | #define U_STRIDE(val) ((val) << 16) |
5087 | #define V_STRIDE(val) ((val) << 0) | 5089 | #define V_STRIDE(val) ((val) << 0) |
5088 | 5090 | ||
5089 | |||
5090 | #define VE_IDX_SFT 0 | 5091 | #define VE_IDX_SFT 0 |
5091 | #define HE_IDX_SFT 16 | 5092 | #define HE_IDX_SFT 16 |
5092 | 5093 | ||
@@ -5099,53 +5100,106 @@ struct Ration2m | |||
5099 | #define W_COEF_MSK 0xFF | 5100 | #define W_COEF_MSK 0xFF |
5100 | 5101 | ||
5101 | // function about REG_CTRL | 5102 | // function about REG_CTRL |
5102 | #define IPU_STOP_IPU(IPU_V_BASE) \ | 5103 | #define IPU_STOP_IPU() \ |
5103 | REG32(IPU_V_BASE + REG_CTRL) &= ~IPU_EN; | 5104 | REG32(IPU_V_BASE + REG_CTRL) &= ~IPU_EN; |
5104 | 5105 | ||
5105 | #define IPU_RUN_IPU(IPU_V_BASE) \ | 5106 | #define IPU_RUN_IPU() \ |
5106 | REG32(IPU_V_BASE + REG_CTRL) |= IPU_EN; | 5107 | REG32(IPU_V_BASE + REG_CTRL) |= IPU_EN; |
5107 | 5108 | ||
5108 | #define IPU_RESET_IPU(IPU_V_BASE) \ | 5109 | #define IPU_RESET_IPU() \ |
5109 | REG32(IPU_V_BASE + REG_CTRL) |= IPU_RESET; | 5110 | REG32(IPU_V_BASE + REG_CTRL) |= IPU_RESET; |
5110 | 5111 | ||
5111 | #define IPU_DISABLE_IRQ(IPU_V_BASE) \ | 5112 | #define IPU_DISABLE_IRQ() \ |
5112 | REG32(IPU_V_BASE + REG_CTRL) &= ~FM_IRQ_EN; | 5113 | REG32(IPU_V_BASE + REG_CTRL) &= ~FM_IRQ_EN; |
5113 | 5114 | ||
5114 | #define IPU_DISABLE_RSIZE(IPU_V_BASE) \ | 5115 | #define IPU_DISABLE_RSIZE() \ |
5115 | REG32(IPU_V_BASE + REG_CTRL) &= ~RSZ_EN; | 5116 | REG32(IPU_V_BASE + REG_CTRL) &= ~RSZ_EN; |
5116 | 5117 | ||
5117 | #define IPU_ENABLE_RSIZE(IPU_V_BASE) \ | 5118 | #define IPU_ENABLE_RSIZE() \ |
5118 | REG32(IPU_V_BASE + REG_CTRL) |= RSZ_EN; | 5119 | REG32(IPU_V_BASE + REG_CTRL) |= RSZ_EN; |
5119 | 5120 | ||
5120 | #define IPU_IS_ENABLED(IPU_V_BASE) \ | 5121 | #define IPU_IS_ENABLED() \ |
5121 | (REG32(IPU_V_BASE + REG_CTRL) & IPU_EN) | 5122 | (REG32(IPU_V_BASE + REG_CTRL) & IPU_EN) |
5122 | 5123 | ||
5123 | // function about REG_STATUS | 5124 | // function about REG_STATUS |
5124 | #define IPU_CLEAR_END_FLAG(IPU_V_BASE) \ | 5125 | #define IPU_CLEAR_END_FLAG() \ |
5125 | REG32(IPU_V_BASE + REG_STATUS) &= ~OUT_END; | 5126 | REG32(IPU_V_BASE + REG_STATUS) &= ~OUT_END; |
5126 | 5127 | ||
5127 | #define IPU_POLLING_END_FLAG(IPU_V_BASE) \ | 5128 | #define IPU_POLLING_END_FLAG() \ |
5128 | (REG32(IPU_V_BASE + REG_STATUS) & OUT_END) | 5129 | (REG32(IPU_V_BASE + REG_STATUS) & OUT_END) |
5129 | 5130 | ||
5131 | #define IPU_SET_INFMT(fmt) \ | ||
5132 | REG32(IPU_V_BASE + REG_D_FMT) = (REG32(IPU_V_BASE + REG_D_FMT) & ~INFMT_MASK) | (fmt); | ||
5133 | |||
5134 | #define IPU_SET_OUTFMT(fmt) \ | ||
5135 | REG32(IPU_V_BASE + REG_D_FMT) = (REG32(IPU_V_BASE + REG_D_FMT) & ~OUTFMT_MASK) | (fmt); | ||
5136 | |||
5137 | #define IPU_SET_IN_FM(w, h) \ | ||
5138 | REG32(IPU_V_BASE + REG_IN_FM_GS) = IN_FM_W(w) | IN_FM_H(h); | ||
5139 | |||
5140 | #define IPU_SET_Y_STRIDE(stride) \ | ||
5141 | REG32(IPU_V_BASE + REG_Y_STRIDE) = (stride); | ||
5142 | |||
5143 | #define IPU_SET_UV_STRIDE(u, v) \ | ||
5144 | REG32(IPU_V_BASE + REG_UV_STRIDE) = U_STRIDE(u) | V_STRIDE(v); | ||
5145 | |||
5146 | #define IPU_SET_Y_ADDR(addr) \ | ||
5147 | REG32(IPU_V_BASE + REG_Y_ADDR) = (addr); | ||
5148 | |||
5149 | #define IPU_SET_U_ADDR(addr) \ | ||
5150 | REG32(IPU_V_BASE + REG_U_ADDR) = (addr); | ||
5151 | |||
5152 | #define IPU_SET_V_ADDR(addr) \ | ||
5153 | REG32(IPU_V_BASE + REG_V_ADDR) = (addr); | ||
5154 | |||
5155 | #define IPU_SET_OUT_ADDR(addr) \ | ||
5156 | REG32(IPU_V_BASE + REG_OUT_ADDR) = (addr); | ||
5157 | |||
5158 | #define IPU_SET_OUT_FM(w, h) \ | ||
5159 | REG32(IPU_V_BASE + REG_OUT_GS) = OUT_FM_W(w) | OUT_FM_H(h); | ||
5160 | |||
5161 | #define IPU_SET_OUT_STRIDE(stride) \ | ||
5162 | REG32(IPU_V_BASE + REG_OUT_STRIDE) = (stride); | ||
5163 | |||
5164 | #define IPU_SET_CSC_C0_COEF(coef) \ | ||
5165 | REG32(IPU_V_BASE + REG_CSC_C0_COEF) = (coef); | ||
5166 | |||
5167 | #define IPU_SET_CSC_C1_COEF(coef) \ | ||
5168 | REG32(IPU_V_BASE + REG_CSC_C1_COEF) = (coef); | ||
5169 | |||
5170 | #define IPU_SET_CSC_C2_COEF(coef) \ | ||
5171 | REG32(IPU_V_BASE + REG_CSC_C2_COEF) = (coef); | ||
5172 | |||
5173 | #define IPU_SET_CSC_C3_COEF(coef) \ | ||
5174 | REG32(IPU_V_BASE + REG_CSC_C3_COEF) = (coef); | ||
5175 | |||
5176 | #define IPU_SET_CSC_C4_COEF(coef) \ | ||
5177 | REG32(IPU_V_BASE + REG_CSC_C4_COEF) = (coef); | ||
5178 | |||
5179 | /* YCbCr */ | ||
5130 | /* parameter | 5180 | /* parameter |
5131 | R = 1.164 * (Y - 16) + 1.596 * (cr - 128) {C0, C1} | 5181 | R = 1.164 * (Y - 16) + 1.596 * (cr - 128) {C0, C1} |
5132 | G = 1.164 * (Y - 16) - 0.392 * (cb -128) - 0.813 * (cr - 128) {C0, C2, C3} | 5182 | G = 1.164 * (Y - 16) - 0.392 * (cb -128) - 0.813 * (cr - 128) {C0, C2, C3} |
5133 | B = 1.164 * (Y - 16) + 2.017 * (cb - 128) {C0, C4} | 5183 | B = 1.164 * (Y - 16) + 2.017 * (cb - 128) {C0, C4} |
5134 | */ | 5184 | */ |
5185 | #define YCBCR_CSC_C0 0x4A8 /* 1.164 * 1024 */ | ||
5186 | #define YCBCR_CSC_C1 0x662 /* 1.596 * 1024 */ | ||
5187 | #define YCBCR_CSC_C2 0x191 /* 0.392 * 1024 */ | ||
5188 | #define YCBCR_CSC_C3 0x341 /* 0.813 * 1024 */ | ||
5189 | #define YCBCR_CSC_C4 0x811 /* 2.017 * 1024 */ | ||
5135 | 5190 | ||
5136 | #if 1 | 5191 | |
5137 | #define YUV_CSC_C0 0x4A8 /* 1.164 * 1024 */ | 5192 | /* YUV */ |
5138 | #define YUV_CSC_C1 0x662 /* 1.596 * 1024 */ | 5193 | /* parameter |
5139 | #define YUV_CSC_C2 0x191 /* 0.392 * 1024 */ | 5194 | R = 1 * (Y – 0) + 1.4026 * (V - 128) {C0, C1} |
5140 | #define YUV_CSC_C3 0x341 /* 0.813 * 1024 */ | 5195 | G = 1 * (Y – 0) – 0.3444 * (U - 128) – 0.7144 * (V - 128) {C0, C2, C3} |
5141 | #define YUV_CSC_C4 0x811 /* 2.017 * 1024 */ | 5196 | B = 1 * (Y – 0) + 1.7730 * (U - 128) {C0, C4} |
5142 | #else | 5197 | */ |
5143 | #define YUV_CSC_C0 0x400 | 5198 | #define YUV_CSC_C0 0x400 |
5144 | #define YUV_CSC_C1 0x59C | 5199 | #define YUV_CSC_C1 0x59C |
5145 | #define YUV_CSC_C2 0x161 | 5200 | #define YUV_CSC_C2 0x161 |
5146 | #define YUV_CSC_C3 0x2DC | 5201 | #define YUV_CSC_C3 0x2DC |
5147 | #define YUV_CSC_C4 0x718 | 5202 | #define YUV_CSC_C4 0x718 |
5148 | #endif | ||
5149 | 5203 | ||
5150 | #endif /* _IPU_H_ */ | 5204 | #endif /* _IPU_H_ */ |
5151 | 5205 | ||
diff --git a/firmware/export/r61509.h b/firmware/export/r61509.h index 53f0440742..f61b620084 100644 --- a/firmware/export/r61509.h +++ b/firmware/export/r61509.h | |||
@@ -26,6 +26,7 @@ | |||
26 | #define __R61509_H | 26 | #define __R61509_H |
27 | 27 | ||
28 | /* Register list */ | 28 | /* Register list */ |
29 | #define REG_DEVICE_CODE 0x000 | ||
29 | #define REG_DRIVER_OUTPUT 0x001 | 30 | #define REG_DRIVER_OUTPUT 0x001 |
30 | #define REG_LCD_DR_WAVE_CTRL 0x002 | 31 | #define REG_LCD_DR_WAVE_CTRL 0x002 |
31 | #define REG_ENTRY_MODE 0x003 | 32 | #define REG_ENTRY_MODE 0x003 |
diff --git a/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c index 783621c88b..25265395b2 100644 --- a/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c | |||
@@ -71,7 +71,14 @@ bool lcd_active(void) | |||
71 | /* Update a fraction of the display. */ | 71 | /* Update a fraction of the display. */ |
72 | void lcd_update_rect(int x, int y, int width, int height) | 72 | void lcd_update_rect(int x, int y, int width, int height) |
73 | { | 73 | { |
74 | x=0;y=0;width=LCD_WIDTH;height=LCD_HEIGHT; /* HACK! */ | 74 | /* Currently only do full updates. |
75 | * DMA can't handle partial updates and CPU is too slow compared | ||
76 | * to full DMA updates */ | ||
77 | x = 0; | ||
78 | y = 0; | ||
79 | width = LCD_WIDTH; | ||
80 | height = LCD_HEIGHT; | ||
81 | |||
75 | mutex_lock(&lcd_mtx); | 82 | mutex_lock(&lcd_mtx); |
76 | 83 | ||
77 | __cpm_start_lcd(); | 84 | __cpm_start_lcd(); |
@@ -82,12 +89,12 @@ x=0;y=0;width=LCD_WIDTH;height=LCD_HEIGHT; /* HACK! */ | |||
82 | 89 | ||
83 | REG_DMAC_DCCSR(DMA_LCD_CHANNEL) = DMAC_DCCSR_NDES; | 90 | REG_DMAC_DCCSR(DMA_LCD_CHANNEL) = DMAC_DCCSR_NDES; |
84 | REG_DMAC_DSAR(DMA_LCD_CHANNEL) = PHYSADDR((unsigned long)&lcd_framebuffer[y][x]); | 91 | REG_DMAC_DSAR(DMA_LCD_CHANNEL) = PHYSADDR((unsigned long)&lcd_framebuffer[y][x]); |
85 | REG_DMAC_DRSR(DMA_LCD_CHANNEL) = DMAC_DRSR_RS_SLCD; /* source = SLCD */ | 92 | REG_DMAC_DRSR(DMA_LCD_CHANNEL) = DMAC_DRSR_RS_SLCD; |
86 | REG_DMAC_DTAR(DMA_LCD_CHANNEL) = PHYSADDR(SLCD_FIFO); | 93 | REG_DMAC_DTAR(DMA_LCD_CHANNEL) = PHYSADDR(SLCD_FIFO); |
87 | REG_DMAC_DTCR(DMA_LCD_CHANNEL) = width*height; | 94 | REG_DMAC_DTCR(DMA_LCD_CHANNEL) = (width * height) >> 3; |
88 | 95 | ||
89 | REG_DMAC_DCMD(DMA_LCD_CHANNEL) = ( DMAC_DCMD_SAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | 96 | REG_DMAC_DCMD(DMA_LCD_CHANNEL) = ( DMAC_DCMD_SAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 |
90 | | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BIT ); | 97 | | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BYTE ); |
91 | 98 | ||
92 | __dcache_writeback_all(); /* Size of framebuffer is way bigger than cache size. | 99 | __dcache_writeback_all(); /* Size of framebuffer is way bigger than cache size. |
93 | We need to find a way to make the framebuffer uncached, so this statement can get removed. */ | 100 | We need to find a way to make the framebuffer uncached, so this statement can get removed. */ |
@@ -101,7 +108,6 @@ x=0;y=0;width=LCD_WIDTH;height=LCD_HEIGHT; /* HACK! */ | |||
101 | wakeup_wait(&lcd_wkup, TIMEOUT_BLOCK); /* Sleeping in lcd_update() should be safe */ | 108 | wakeup_wait(&lcd_wkup, TIMEOUT_BLOCK); /* Sleeping in lcd_update() should be safe */ |
102 | 109 | ||
103 | REG_DMAC_DCCSR(DMA_LCD_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */ | 110 | REG_DMAC_DCCSR(DMA_LCD_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */ |
104 | |||
105 | dma_disable(); | 111 | dma_disable(); |
106 | 112 | ||
107 | while(REG_SLCD_STATE & SLCD_STATE_BUSY); | 113 | while(REG_SLCD_STATE & SLCD_STATE_BUSY); |
@@ -139,17 +145,54 @@ void lcd_update(void) | |||
139 | lcd_update_rect(0, 0, LCD_WIDTH, LCD_HEIGHT); | 145 | lcd_update_rect(0, 0, LCD_WIDTH, LCD_HEIGHT); |
140 | } | 146 | } |
141 | 147 | ||
142 | /* TODO: use IPU */ | 148 | /* (Mis)use LCD framebuffer as a temporary buffer */ |
143 | void lcd_blit_yuv(unsigned char * const src[3], | 149 | void lcd_blit_yuv(unsigned char * const src[3], |
144 | int src_x, int src_y, int stride, | 150 | int src_x, int src_y, int stride, |
145 | int x, int y, int width, int height) | 151 | int x, int y, int width, int height) |
146 | { | 152 | { |
147 | (void)src; | 153 | __dcache_writeback_all(); |
148 | (void)src_x; | 154 | |
149 | (void)src_y; | 155 | __cpm_start_ipu(); |
150 | (void)stride; | 156 | |
151 | (void)x; | 157 | IPU_STOP_IPU(); |
152 | (void)y; | 158 | IPU_RESET_IPU() |
153 | (void)width; | 159 | IPU_CLEAR_END_FLAG(); |
154 | (void)height; | 160 | |
161 | IPU_DISABLE_RSIZE(); | ||
162 | IPU_DISABLE_IRQ(); | ||
163 | |||
164 | IPU_SET_INFMT(INFMT_YUV420); | ||
165 | IPU_SET_OUTFMT(OUTFMT_RGB565); | ||
166 | |||
167 | IPU_SET_IN_FM(width, height); | ||
168 | IPU_SET_Y_STRIDE(stride); | ||
169 | IPU_SET_UV_STRIDE(stride, stride); | ||
170 | |||
171 | IPU_SET_Y_ADDR((unsigned long)src[0]); | ||
172 | IPU_SET_U_ADDR((unsigned long)src[2]); | ||
173 | IPU_SET_V_ADDR((unsigned long)src[3]); | ||
174 | IPU_SET_OUT_ADDR(PHYSADDR((unsigned long)&lcd_framebuffer[y][x])); | ||
175 | |||
176 | IPU_SET_OUT_FM(width, height); | ||
177 | IPU_SET_OUT_STRIDE(stride); | ||
178 | |||
179 | IPU_SET_CSC_C0_COEF(YUV_CSC_C0); | ||
180 | IPU_SET_CSC_C1_COEF(YUV_CSC_C1); | ||
181 | IPU_SET_CSC_C2_COEF(YUV_CSC_C2); | ||
182 | IPU_SET_CSC_C2_COEF(YUV_CSC_C3); | ||
183 | IPU_SET_CSC_C4_COEF(YUV_CSC_C4); | ||
184 | |||
185 | IPU_RUN_IPU(); | ||
186 | |||
187 | while(!(IPU_POLLING_END_FLAG()) && IPU_IS_ENABLED()); | ||
188 | |||
189 | IPU_CLEAR_END_FLAG(); | ||
190 | IPU_STOP_IPU(); | ||
191 | |||
192 | //__cpm_stop_ipu(); | ||
193 | |||
194 | __dcache_invalidate_all(); | ||
195 | |||
196 | /* YUV speed is limited by LCD speed */ | ||
197 | lcd_update_rect(x, y, width, height); | ||
155 | } | 198 | } |
diff --git a/firmware/target/mips/ingenic_jz47xx/lcd-target.h b/firmware/target/mips/ingenic_jz47xx/lcd-target.h index 95eecf7823..95ce7acbb5 100644 --- a/firmware/target/mips/ingenic_jz47xx/lcd-target.h +++ b/firmware/target/mips/ingenic_jz47xx/lcd-target.h | |||
@@ -29,7 +29,7 @@ void lcd_init_device(void); | |||
29 | 29 | ||
30 | 30 | ||
31 | void lcd_init_controller(void); | 31 | void lcd_init_controller(void); |
32 | void lcd_set_target(short x, short y, short width, short height); | 32 | void lcd_set_target(int x, int y, int width, int height); |
33 | void lcd_on(void); | 33 | void lcd_on(void); |
34 | void lcd_off(void); | 34 | void lcd_off(void); |
35 | 35 | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c b/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c index 85947eb66c..a2240e0f7d 100644 --- a/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c +++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c | |||
@@ -25,23 +25,22 @@ | |||
25 | #include "lcd.h" | 25 | #include "lcd.h" |
26 | #include "lcd-target.h" | 26 | #include "lcd-target.h" |
27 | 27 | ||
28 | #define PIN_CS_N (32*1+17) /* Chip select */ | 28 | #define PIN_CS_N (32*1+17) /* Chip select */ |
29 | #define PIN_RESET_N (32*1+18) /* Reset */ | 29 | #define PIN_RESET_N (32*1+18) /* Reset */ |
30 | #define LCD_PCLK (20000000) /* LCD PCLK */ | 30 | #define LCD_PCLK (20000000) /* LCD PCLK */ |
31 | 31 | ||
32 | #define my__gpio_as_lcd_16bit() \ | 32 | #define my__gpio_as_lcd_16bit() \ |
33 | do { \ | 33 | do { \ |
34 | REG_GPIO_PXFUNS(2) = 0x001cffff; \ | 34 | REG_GPIO_PXFUNS(2) = 0x001cffff; \ |
35 | REG_GPIO_PXSELC(2) = 0x001cffff; \ | 35 | REG_GPIO_PXSELC(2) = 0x001cffff; \ |
36 | REG_GPIO_PXPES(2) = 0x001cffff; \ | 36 | REG_GPIO_PXPES(2) = 0x001cffff; \ |
37 | } while (0) | 37 | } while (0) |
38 | 38 | ||
39 | 39 | ||
40 | #define SLEEP(x) for(i=0; i<x; i++) asm("nop"); asm("nop"); | 40 | #define SLEEP(x) { register int __i; for(__i=0; __i<x; __i++) {asm("nop"); asm("nop");} } |
41 | #define DELAY SLEEP(700000); | 41 | #define DELAY SLEEP(700000); |
42 | static void _display_pin_init(void) | 42 | static void _display_pin_init(void) |
43 | { | 43 | { |
44 | int i; | ||
45 | my__gpio_as_lcd_16bit(); | 44 | my__gpio_as_lcd_16bit(); |
46 | __gpio_as_output(PIN_CS_N); | 45 | __gpio_as_output(PIN_CS_N); |
47 | __gpio_as_output(PIN_RESET_N); | 46 | __gpio_as_output(PIN_RESET_N); |
@@ -61,8 +60,6 @@ static void _display_pin_init(void) | |||
61 | #define SLCD_SEND_COMMAND(cmd,val) SLCD_SET_COMMAND(cmd); SLCD_SET_DATA(val); | 60 | #define SLCD_SEND_COMMAND(cmd,val) SLCD_SET_COMMAND(cmd); SLCD_SET_DATA(val); |
62 | static void _display_init(void) | 61 | static void _display_init(void) |
63 | { | 62 | { |
64 | int i; | ||
65 | |||
66 | SLCD_SEND_COMMAND(REG_SOFT_RESET, SOFT_RESET(1)); | 63 | SLCD_SEND_COMMAND(REG_SOFT_RESET, SOFT_RESET(1)); |
67 | SLEEP(700000); | 64 | SLEEP(700000); |
68 | SLCD_SEND_COMMAND(REG_SOFT_RESET, SOFT_RESET(0)); | 65 | SLCD_SEND_COMMAND(REG_SOFT_RESET, SOFT_RESET(0)); |
@@ -72,9 +69,9 @@ static void _display_init(void) | |||
72 | SLCD_SEND_COMMAND(REG_DRIVER_OUTPUT, 0x100); | 69 | SLCD_SEND_COMMAND(REG_DRIVER_OUTPUT, 0x100); |
73 | SLCD_SEND_COMMAND(REG_LCD_DR_WAVE_CTRL, 0x100); | 70 | SLCD_SEND_COMMAND(REG_LCD_DR_WAVE_CTRL, 0x100); |
74 | #if CONFIG_ORIENTATION == SCREEN_PORTRAIT | 71 | #if CONFIG_ORIENTATION == SCREEN_PORTRAIT |
75 | SLCD_SEND_COMMAND(REG_ENTRY_MODE, (ENTRY_MODE_BGR | ENTRY_MODE_VID | ENTRY_MODE_HID | ENTRY_MODE_HWM)); | 72 | SLCD_SEND_COMMAND(REG_ENTRY_MODE, (ENTRY_MODE_BGR | ENTRY_MODE_VID | ENTRY_MODE_HID)); |
76 | #else | 73 | #else |
77 | SLCD_SEND_COMMAND(REG_ENTRY_MODE, (ENTRY_MODE_BGR | ENTRY_MODE_VID | ENTRY_MODE_AM | ENTRY_MODE_HWM)); | 74 | SLCD_SEND_COMMAND(REG_ENTRY_MODE, (ENTRY_MODE_BGR | ENTRY_MODE_VID | ENTRY_MODE_AM)); |
78 | #endif | 75 | #endif |
79 | SLCD_SEND_COMMAND(REG_DISP_CTRL2, 0x503); | 76 | SLCD_SEND_COMMAND(REG_DISP_CTRL2, 0x503); |
80 | SLCD_SEND_COMMAND(REG_DISP_CTRL3, 1); | 77 | SLCD_SEND_COMMAND(REG_DISP_CTRL3, 1); |
@@ -95,19 +92,6 @@ static void _display_init(void) | |||
95 | SLCD_SEND_COMMAND(REG_PWR_CTRL4, 0x2f00); | 92 | SLCD_SEND_COMMAND(REG_PWR_CTRL4, 0x2f00); |
96 | SLCD_SEND_COMMAND(REG_PWR_CTRL5, 0); | 93 | SLCD_SEND_COMMAND(REG_PWR_CTRL5, 0); |
97 | SLCD_SEND_COMMAND(REG_PWR_CTRL6, 1); | 94 | SLCD_SEND_COMMAND(REG_PWR_CTRL6, 1); |
98 | SLCD_SEND_COMMAND(REG_RAM_HADDR_SET, 0); /* set cursor at x_start */ | ||
99 | SLCD_SEND_COMMAND(REG_RAM_VADDR_SET, 0); /* set cursor at y_start */ | ||
100 | #if CONFIG_ORIENTATION == SCREEN_PORTRAIT | ||
101 | SLCD_SEND_COMMAND(REG_RAM_HADDR_START, 0); /* y_start*/ | ||
102 | SLCD_SEND_COMMAND(REG_RAM_HADDR_END, 239); /* y_end */ | ||
103 | SLCD_SEND_COMMAND(REG_RAM_VADDR_START, 0); /* x_start */ | ||
104 | SLCD_SEND_COMMAND(REG_RAM_VADDR_END, 399); /* x_end */ | ||
105 | #else | ||
106 | SLCD_SEND_COMMAND(REG_RAM_HADDR_START, 0); /* y_start*/ | ||
107 | SLCD_SEND_COMMAND(REG_RAM_HADDR_END, 399); /* y_end */ | ||
108 | SLCD_SEND_COMMAND(REG_RAM_VADDR_START, 0); /* x_start */ | ||
109 | SLCD_SEND_COMMAND(REG_RAM_VADDR_END, 239); /* x_end */ | ||
110 | #endif | ||
111 | SLCD_SEND_COMMAND(REG_RW_NVM, 0); | 95 | SLCD_SEND_COMMAND(REG_RW_NVM, 0); |
112 | SLCD_SEND_COMMAND(REG_VCOM_HVOLTAGE1, 6); | 96 | SLCD_SEND_COMMAND(REG_VCOM_HVOLTAGE1, 6); |
113 | SLCD_SEND_COMMAND(REG_VCOM_HVOLTAGE2, 0); | 97 | SLCD_SEND_COMMAND(REG_VCOM_HVOLTAGE2, 0); |
@@ -144,42 +128,34 @@ static void _display_init(void) | |||
144 | SLCD_SEND_COMMAND(0x7f5, 1); | 128 | SLCD_SEND_COMMAND(0x7f5, 1); |
145 | SLCD_SEND_COMMAND(0x7f0, 0); | 129 | SLCD_SEND_COMMAND(0x7f0, 0); |
146 | 130 | ||
147 | /* LCD ON: */ | 131 | /* LCD ON */ |
148 | SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_BASEE | DISP_CTRL1_VON | 132 | SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_BASEE | DISP_CTRL1_VON | |
149 | | DISP_CTRL1_GON | DISP_CTRL1_DTE | DISP_CTRL1_D(3)) | 133 | DISP_CTRL1_GON | DISP_CTRL1_DTE | DISP_CTRL1_D(3))); |
150 | ); | ||
151 | SLEEP(3500000); | 134 | SLEEP(3500000); |
152 | SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_BASEE | DISP_CTRL1_VON | 135 | SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_BASEE | DISP_CTRL1_VON | |
153 | | DISP_CTRL1_GON | DISP_CTRL1_DTE | DISP_CTRL1_D(2)) | 136 | DISP_CTRL1_GON | DISP_CTRL1_DTE | DISP_CTRL1_D(2))); |
154 | ); | ||
155 | SLEEP(3500000); | 137 | SLEEP(3500000); |
156 | SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_BASEE | DISP_CTRL1_VON | 138 | SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_BASEE | DISP_CTRL1_VON | |
157 | | DISP_CTRL1_GON | DISP_CTRL1_DTE | DISP_CTRL1_D(3)) | 139 | DISP_CTRL1_GON | DISP_CTRL1_DTE | DISP_CTRL1_D(3))); |
158 | ); | ||
159 | SLEEP(3500000); | 140 | SLEEP(3500000); |
160 | } | 141 | } |
161 | 142 | ||
162 | static void _display_on(void) | 143 | static void _display_on(void) |
163 | { | 144 | { |
164 | int i; | ||
165 | SLCD_SEND_COMMAND(REG_PWR_CTRL1, (PWR_CTRL1_SAPE | PWR_CTRL1_BT(6) | PWR_CTRL1_APE | PWR_CTRL1_AP(3))); | 145 | SLCD_SEND_COMMAND(REG_PWR_CTRL1, (PWR_CTRL1_SAPE | PWR_CTRL1_BT(6) | PWR_CTRL1_APE | PWR_CTRL1_AP(3))); |
166 | SLEEP(3500000); | 146 | SLEEP(3500000); |
167 | SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_VON | DISP_CTRL1_GON | 147 | SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_VON | DISP_CTRL1_GON | |
168 | | DISP_CTRL1_D(1)) | 148 | DISP_CTRL1_D(1))); |
169 | ); | ||
170 | SLEEP(3500000); | 149 | SLEEP(3500000); |
171 | SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_VON | DISP_CTRL1_GON | 150 | SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_VON | DISP_CTRL1_GON | |
172 | | DISP_CTRL1_DTE | DISP_CTRL1_D(3) | 151 | DISP_CTRL1_DTE | DISP_CTRL1_D(3) | |
173 | | DISP_CTRL1_BASEE) | 152 | DISP_CTRL1_BASEE)); |
174 | ); | ||
175 | } | 153 | } |
176 | 154 | ||
177 | static void _display_off(void) | 155 | static void _display_off(void) |
178 | { | 156 | { |
179 | int i; | 157 | SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_VON | DISP_CTRL1_GON | |
180 | SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_VON | DISP_CTRL1_GON | 158 | DISP_CTRL1_DTE | DISP_CTRL1_D(2))); |
181 | | DISP_CTRL1_DTE | DISP_CTRL1_D(2)) | ||
182 | ); | ||
183 | SLEEP(3500000); | 159 | SLEEP(3500000); |
184 | SLCD_SEND_COMMAND(REG_DISP_CTRL1, DISP_CTRL1_D(1)); | 160 | SLCD_SEND_COMMAND(REG_DISP_CTRL1, DISP_CTRL1_D(1)); |
185 | SLEEP(3500000); | 161 | SLEEP(3500000); |
@@ -193,9 +169,9 @@ static void _set_lcd_bus(void) | |||
193 | REG_LCD_CFG &= ~LCD_CFG_LCDPIN_MASK; | 169 | REG_LCD_CFG &= ~LCD_CFG_LCDPIN_MASK; |
194 | REG_LCD_CFG |= LCD_CFG_LCDPIN_SLCD; | 170 | REG_LCD_CFG |= LCD_CFG_LCDPIN_SLCD; |
195 | 171 | ||
196 | REG_SLCD_CFG = (SLCD_CFG_BURST_8_WORD | SLCD_CFG_DWIDTH_16 | SLCD_CFG_CWIDTH_16BIT | 172 | REG_SLCD_CFG = (SLCD_CFG_BURST_8_WORD | SLCD_CFG_DWIDTH_16 | SLCD_CFG_CWIDTH_16BIT | |
197 | | SLCD_CFG_CS_ACTIVE_LOW | SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING | 173 | SLCD_CFG_CS_ACTIVE_LOW | SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING | |
198 | | SLCD_CFG_TYPE_PARALLEL); | 174 | SLCD_CFG_TYPE_PARALLEL); |
199 | } | 175 | } |
200 | 176 | ||
201 | static void _set_lcd_clock(void) | 177 | static void _set_lcd_clock(void) |
@@ -204,8 +180,7 @@ static void _set_lcd_clock(void) | |||
204 | 180 | ||
205 | __cpm_stop_lcd(); | 181 | __cpm_stop_lcd(); |
206 | 182 | ||
207 | val = __cpm_get_pllout2() / LCD_PCLK; | 183 | val = (__cpm_get_pllout2() / LCD_PCLK) - 1; |
208 | val--; | ||
209 | if ( val > 0x1ff ) | 184 | if ( val > 0x1ff ) |
210 | val = 0x1ff; /* CPM_LPCDR is too large, set it to 0x1ff */ | 185 | val = 0x1ff; /* CPM_LPCDR is too large, set it to 0x1ff */ |
211 | __cpm_set_pixdiv(val); | 186 | __cpm_set_pixdiv(val); |
@@ -215,7 +190,6 @@ static void _set_lcd_clock(void) | |||
215 | 190 | ||
216 | void lcd_init_controller(void) | 191 | void lcd_init_controller(void) |
217 | { | 192 | { |
218 | int i; | ||
219 | _display_pin_init(); | 193 | _display_pin_init(); |
220 | _set_lcd_bus(); | 194 | _set_lcd_bus(); |
221 | _set_lcd_clock(); | 195 | _set_lcd_clock(); |
@@ -223,37 +197,37 @@ void lcd_init_controller(void) | |||
223 | _display_init(); | 197 | _display_init(); |
224 | } | 198 | } |
225 | 199 | ||
226 | void lcd_set_target(short x, short y, short width, short height) | 200 | void lcd_set_target(int x, int y, int width, int height) |
227 | { | 201 | { |
228 | #if CONFIG_ORIENTATION == SCREEN_PORTRAIT | 202 | #if CONFIG_ORIENTATION == SCREEN_PORTRAIT |
229 | SLCD_SEND_COMMAND(REG_RAM_HADDR_START, y); /* y_start */ | 203 | SLCD_SEND_COMMAND(REG_RAM_HADDR_START, x); |
230 | SLCD_SEND_COMMAND(REG_RAM_HADDR_END, y+width-1); /* y_end */ | 204 | SLCD_SEND_COMMAND(REG_RAM_HADDR_END, x + width - 1); |
231 | SLCD_SEND_COMMAND(REG_RAM_VADDR_START, x); /* x_start */ | 205 | SLCD_SEND_COMMAND(REG_RAM_VADDR_START, y); |
232 | SLCD_SEND_COMMAND(REG_RAM_VADDR_END, x+height-1); /* x_end */ | 206 | SLCD_SEND_COMMAND(REG_RAM_VADDR_END, y + height - 1); |
207 | SLCD_SEND_COMMAND(REG_RAM_HADDR_SET, x); | ||
208 | SLCD_SEND_COMMAND(REG_RAM_VADDR_SET, y); | ||
233 | #else | 209 | #else |
234 | SLCD_SEND_COMMAND(REG_RAM_HADDR_START, y); /* y_start */ | 210 | SLCD_SEND_COMMAND(REG_RAM_HADDR_START, y); |
235 | SLCD_SEND_COMMAND(REG_RAM_HADDR_END, y+height-1); /* y_end */ | 211 | SLCD_SEND_COMMAND(REG_RAM_HADDR_END, y + height - 1); |
236 | SLCD_SEND_COMMAND(REG_RAM_VADDR_START, x); /* x_start */ | 212 | SLCD_SEND_COMMAND(REG_RAM_VADDR_START, x); |
237 | SLCD_SEND_COMMAND(REG_RAM_VADDR_END, x+width-1); /* x_end */ | 213 | SLCD_SEND_COMMAND(REG_RAM_VADDR_END, x + width - 1); |
214 | SLCD_SEND_COMMAND(REG_RAM_HADDR_SET, y); | ||
215 | SLCD_SEND_COMMAND(REG_RAM_VADDR_SET, x); | ||
238 | #endif | 216 | #endif |
239 | SLCD_SEND_COMMAND(REG_RAM_HADDR_SET, y); /* set cursor at x_start */ | ||
240 | SLCD_SEND_COMMAND(REG_RAM_VADDR_SET, x); /* set cursor at y_start */ | ||
241 | SLCD_SET_COMMAND(REG_RW_GRAM); /* write data to GRAM */ | 217 | SLCD_SET_COMMAND(REG_RW_GRAM); /* write data to GRAM */ |
242 | } | 218 | } |
243 | 219 | ||
244 | void lcd_set_flip(bool yesno) | 220 | void lcd_set_flip(bool yesno) |
245 | { | 221 | { |
246 | int i; | ||
247 | |||
248 | __cpm_start_lcd(); | 222 | __cpm_start_lcd(); |
249 | #if CONFIG_ORIENTATION == SCREEN_PORTRAIT | 223 | #if CONFIG_ORIENTATION == SCREEN_PORTRAIT |
250 | if(yesno) | 224 | if(yesno) |
251 | { | 225 | { |
252 | SLCD_SEND_COMMAND(REG_ENTRY_MODE, (ENTRY_MODE_BGR | ENTRY_MODE_HWM)); | 226 | SLCD_SEND_COMMAND(REG_ENTRY_MODE, ENTRY_MODE_BGR); |
253 | } | 227 | } |
254 | else | 228 | else |
255 | { | 229 | { |
256 | SLCD_SEND_COMMAND(REG_ENTRY_MODE, (ENTRY_MODE_BGR | ENTRY_MODE_VID | ENTRY_MODE_HID | ENTRY_MODE_HWM)); | 230 | SLCD_SEND_COMMAND(REG_ENTRY_MODE, (ENTRY_MODE_BGR | ENTRY_MODE_VID | ENTRY_MODE_HID)); |
257 | } | 231 | } |
258 | #else | 232 | #else |
259 | if(yesno) | 233 | if(yesno) |