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-rw-r--r--firmware/SOURCES2
-rw-r--r--firmware/export/config-ondavx747.h2
-rw-r--r--firmware/export/jz4740.h33
-rw-r--r--firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c167
-rw-r--r--firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c16
-rw-r--r--firmware/target/mips/ingenic_jz47xx/codec-jz4740.c5
-rw-r--r--firmware/target/mips/ingenic_jz47xx/i2c-jz4740.c240
-rw-r--r--firmware/target/mips/ingenic_jz47xx/kernel-jz4740.c3
-rw-r--r--firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c8
-rw-r--r--firmware/target/mips/ingenic_jz47xx/onda_vx747/ata-sd-target.h19
-rw-r--r--firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c28
-rw-r--r--firmware/target/mips/ingenic_jz47xx/onda_vx747/power-onda_vx747.c43
-rw-r--r--firmware/target/mips/ingenic_jz47xx/onda_vx747/usb-target.h2
13 files changed, 467 insertions, 101 deletions
diff --git a/firmware/SOURCES b/firmware/SOURCES
index 8783c3a080..4df4fae9a2 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -1220,6 +1220,7 @@ target/mips/ingenic_jz47xx/ata-nand-jz4740.c
1220target/mips/ingenic_jz47xx/ata-sd-jz4740.c 1220target/mips/ingenic_jz47xx/ata-sd-jz4740.c
1221target/mips/ingenic_jz47xx/codec-jz4740.c 1221target/mips/ingenic_jz47xx/codec-jz4740.c
1222target/mips/ingenic_jz47xx/kernel-jz4740.c 1222target/mips/ingenic_jz47xx/kernel-jz4740.c
1223target/mips/ingenic_jz47xx/i2c-jz4740.c
1223target/mips/ingenic_jz47xx/lcd-jz4740.c 1224target/mips/ingenic_jz47xx/lcd-jz4740.c
1224target/mips/ingenic_jz47xx/pcm-jz4740.c 1225target/mips/ingenic_jz47xx/pcm-jz4740.c
1225target/mips/ingenic_jz47xx/system-jz4740.c 1226target/mips/ingenic_jz47xx/system-jz4740.c
@@ -1231,6 +1232,7 @@ drivers/nand_id.c
1231target/mips/ingenic_jz47xx/onda_vx747/backlight-onda_vx747.c 1232target/mips/ingenic_jz47xx/onda_vx747/backlight-onda_vx747.c
1232target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c 1233target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c
1233target/mips/ingenic_jz47xx/onda_vx747/sadc-onda_vx747.c 1234target/mips/ingenic_jz47xx/onda_vx747/sadc-onda_vx747.c
1235target/mips/ingenic_jz47xx/onda_vx747/power-onda_vx747.c
1234#endif 1236#endif
1235 1237
1236#ifdef ONDA_VX767 1238#ifdef ONDA_VX767
diff --git a/firmware/export/config-ondavx747.h b/firmware/export/config-ondavx747.h
index d4badf89cd..3646156ede 100644
--- a/firmware/export/config-ondavx747.h
+++ b/firmware/export/config-ondavx747.h
@@ -121,7 +121,7 @@
121#define BATTERY_TYPES_COUNT 1 /* only one type */ 121#define BATTERY_TYPES_COUNT 1 /* only one type */
122 122
123/* Hardware controlled charging with monitoring */ 123/* Hardware controlled charging with monitoring */
124//#define CONFIG_CHARGING CHARGING_MONITOR 124#define CONFIG_CHARGING CHARGING_MONITOR
125 125
126#ifndef SIMULATOR 126#ifndef SIMULATOR
127 127
diff --git a/firmware/export/jz4740.h b/firmware/export/jz4740.h
index 7910fbec92..f1060686f1 100644
--- a/firmware/export/jz4740.h
+++ b/firmware/export/jz4740.h
@@ -3381,13 +3381,17 @@ static __inline__ unsigned int __cpm_get_pllout(void)
3381 unsigned long m, n, no, pllout; 3381 unsigned long m, n, no, pllout;
3382 unsigned long cppcr = REG_CPM_CPPCR; 3382 unsigned long cppcr = REG_CPM_CPPCR;
3383 unsigned long od[4] = {1, 2, 2, 4}; 3383 unsigned long od[4] = {1, 2, 2, 4};
3384 if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) { 3384
3385 if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP))
3386 {
3385 m = __cpm_get_pllm() + 2; 3387 m = __cpm_get_pllm() + 2;
3386 n = __cpm_get_plln() + 2; 3388 n = __cpm_get_plln() + 2;
3387 no = od[__cpm_get_pllod()]; 3389 no = od[__cpm_get_pllod()];
3388 pllout = ((JZ_EXTAL) / (n * no)) * m; 3390 pllout = ((JZ_EXTAL) / (n * no)) * m;
3389 } else 3391 }
3392 else
3390 pllout = JZ_EXTAL; 3393 pllout = JZ_EXTAL;
3394
3391 return pllout; 3395 return pllout;
3392} 3396}
3393 3397
@@ -3447,23 +3451,19 @@ static __inline__ unsigned int __cpm_get_pixclk(void)
3447/* I2S clock */ 3451/* I2S clock */
3448static __inline__ unsigned int __cpm_get_i2sclk(void) 3452static __inline__ unsigned int __cpm_get_i2sclk(void)
3449{ 3453{
3450 if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) { 3454 if (REG_CPM_CPCCR & CPM_CPCCR_I2CS)
3451 return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1); 3455 return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1);
3452 } 3456 else
3453 else {
3454 return JZ_EXTAL; 3457 return JZ_EXTAL;
3455 }
3456} 3458}
3457 3459
3458/* USB clock */ 3460/* USB clock */
3459static __inline__ unsigned int __cpm_get_usbclk(void) 3461static __inline__ unsigned int __cpm_get_usbclk(void)
3460{ 3462{
3461 if (REG_CPM_CPCCR & CPM_CPCCR_UCS) { 3463 if (REG_CPM_CPCCR & CPM_CPCCR_UCS)
3462 return __cpm_get_pllout2() / (__cpm_get_udiv() + 1); 3464 return __cpm_get_pllout2() / (__cpm_get_udiv() + 1);
3463 } 3465 else
3464 else {
3465 return JZ_EXTAL; 3466 return JZ_EXTAL;
3466 }
3467} 3467}
3468 3468
3469/* MSC clock */ 3469/* MSC clock */
@@ -3492,12 +3492,10 @@ static inline void __cpm_select_msc_clk(int sd)
3492 unsigned int pllout2 = __cpm_get_pllout2(); 3492 unsigned int pllout2 = __cpm_get_pllout2();
3493 unsigned int div = 0; 3493 unsigned int div = 0;
3494 3494
3495 if (sd) { 3495 if (sd)
3496 div = pllout2 / 24000000; 3496 div = pllout2 / 24000000;
3497 } 3497 else
3498 else {
3499 div = pllout2 / 16000000; 3498 div = pllout2 / 16000000;
3500 }
3501 3499
3502 REG_CPM_MSCCDR = div - 1; 3500 REG_CPM_MSCCDR = div - 1;
3503} 3501}
@@ -3510,12 +3508,11 @@ static inline void __cpm_select_msc_hs_clk(int sd)
3510 unsigned int pllout2 = __cpm_get_pllout2(); 3508 unsigned int pllout2 = __cpm_get_pllout2();
3511 unsigned int div = 0; 3509 unsigned int div = 0;
3512 3510
3513 if (sd) { 3511 if (sd)
3514 div = pllout2 / 48000000; 3512 div = pllout2 / 48000000;
3515 } 3513 else
3516 else {
3517 div = pllout2 / 16000000; 3514 div = pllout2 / 16000000;
3518 } 3515
3519 REG_CPM_MSCCDR = div - 1; 3516 REG_CPM_MSCCDR = div - 1;
3520} 3517}
3521 3518
diff --git a/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c b/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c
index 851472bf62..c9ca85cfaf 100644
--- a/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c
@@ -85,21 +85,20 @@ struct nand_param
85 * 85 *
86 */ 86 */
87 87
88#define NAND_DATAPORT 0xB8000000 88static volatile unsigned long nand_address;
89#define NAND_ADDRPORT 0xB8010000 89#define NAND_DATAPORT (nand_address)
90#define NAND_COMMPORT 0xB8008000 90#define NAND_ADDRPORT (nand_address+0x10000)
91#define NAND_COMMPORT (nand_address+0x08000)
91 92
92#define ECC_BLOCK 512 93#define ECC_BLOCK 512
93#define ECC_POS 6 94#define ECC_POS 6
94#define PAR_SIZE 9 95#define PAR_SIZE 9
95 96
96#define __nand_cmd(n) (REG8(NAND_COMMPORT) = (n)) 97#define __nand_cmd(n) (REG8(NAND_COMMPORT) = (n))
97#define __nand_addr(n) (REG8(NAND_ADDRPORT) = (n)) 98#define __nand_addr(n) (REG8(NAND_ADDRPORT) = (n))
98#define __nand_data8() (REG8(NAND_DATAPORT)) 99#define __nand_data8() (REG8(NAND_DATAPORT))
99#define __nand_data16() (REG16(NAND_DATAPORT)) 100#define __nand_data16() (REG16(NAND_DATAPORT))
100 101
101#define __nand_enable() (REG_EMC_NFCSR |= EMC_NFCSR_NFE1 | EMC_NFCSR_NFCE1)
102#define __nand_disable() (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1))
103#define __nand_ecc_rs_encoding() \ 102#define __nand_ecc_rs_encoding() \
104 (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_ENCODING) 103 (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_ENCODING)
105#define __nand_ecc_rs_decoding() \ 104#define __nand_ecc_rs_decoding() \
@@ -111,6 +110,9 @@ struct nand_param
111/*--------------------------------------------------------------*/ 110/*--------------------------------------------------------------*/
112 111
113static struct nand_info* chip_info = NULL; 112static struct nand_info* chip_info = NULL;
113static struct nand_info* banks[4];
114static unsigned int nr_banks = 1;
115static unsigned long bank_size;
114static struct nand_param internal_param; 116static struct nand_param internal_param;
115#ifdef USE_DMA 117#ifdef USE_DMA
116static struct mutex nand_mtx; 118static struct mutex nand_mtx;
@@ -344,6 +346,9 @@ static int jz_nand_read_page(unsigned long page_addr, unsigned char *dst)
344 int i, j; 346 int i, j;
345 unsigned char *data_buf; 347 unsigned char *data_buf;
346 unsigned char oob_buf[nandp->oob_size]; 348 unsigned char oob_buf[nandp->oob_size];
349
350 if(nand_address == 0)
351 return -1;
347 352
348 page_size = nandp->page_size; 353 page_size = nandp->page_size;
349 oob_size = nandp->oob_size; 354 oob_size = nandp->oob_size;
@@ -463,44 +468,112 @@ static int jz_nand_read_page(unsigned long page_addr, unsigned char *dst)
463} 468}
464 469
465/* 470/*
471 * Disable NAND controller
472 */
473static void jz_nand_disable(void)
474{
475 REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1 | EMC_NFCSR_NFCE2 |
476 EMC_NFCSR_NFCE3 | EMC_NFCSR_NFCE4 |
477 EMC_NFCSR_NFE1 | EMC_NFCSR_NFE2 |
478 EMC_NFCSR_NFE3 | EMC_NFCSR_NFE4 );
479}
480
481/*
466 * Enable NAND controller 482 * Enable NAND controller
467 */ 483 */
468static void jz_nand_enable(void) 484static void jz_nand_enable(void)
485{
486#if 0
487 /* OF RE */
488 REG_GPIO_PXFUNS(1) = 0x1E018000; // __gpio_as_func0() start
489 REG_GPIO_PXSELC(1) = 0x1E018000; // __gpio_as_func0() end
490
491 REG_GPIO_PXFUNS(2) = 0x3000<<16; // __gpio_as_func0() start
492 REG_GPIO_PXSELC(2) = 0x3000<<16; // __gpio_as_func0() end
493
494 REG_GPIO_PXFUNC(2) = 0x4000<<16; // __gpio_port_as_input() start
495 REG_GPIO_PXSELC(2) = 0x4000<<16;
496 REG_GPIO_PXDIRC(2) = 0x4000<<16; // __gpio_port_as_input() end
497 REG_GPIO_PXPES(2) = 0x4000<<16; // __gpio_disable_pull()
498
499 REG_GPIO_PXFUNS(1) = 0x40<<16; // __gpio_as_func0() start
500 REG_GPIO_PXSELC(1) = 0x40<<16; // __gpio_as_func0() end
501
502 REG_EMC_SMCR1 = (REG_EMC_SMCR1 & 0xFF) | 0x4621200;
503 REG_EMC_SMCR2 = (REG_EMC_SMCR2 & 0xFF) | 0x4621200;
504 REG_EMC_SMCR3 = (REG_EMC_SMCR3 & 0xFF) | 0x4621200;
505 REG_EMC_SMCR4 = (REG_EMC_SMCR4 & 0xFF) | 0x4621200;
506
507 REG_EMC_SMCR1 = REG_EMC_SMCR2 = REG_EMC_SMCR3 = REG_EMC_SMCR4 = 0x6621200;
508#else
509 REG_EMC_SMCR1 = REG_EMC_SMCR2 = REG_EMC_SMCR3 = REG_EMC_SMCR4 = 0x04444400;
510#endif
511}
512
513static void jz_nand_select(int bank)
469{ 514{
470 __nand_enable(); 515 REG_EMC_NFCSR |= (EMC_NFCSR_NFE(bank+1) | EMC_NFCSR_NFCE(bank+1));
471 516
472 REG_EMC_SMCR1 = 0x04444400; 517 switch(bank)
518 {
519 case 0:
520 nand_address = 0xB8000000;
521 break;
522 case 1:
523 nand_address = 0xB4000000;
524 break;
525 case 2:
526 nand_address = 0xAC000000;
527 break;
528 case 3:
529 nand_address = 0xA8000000;
530 break;
531 }
473} 532}
474 533
475/* 534static void jz_nand_deselect(int bank)
476 * Disable NAND controller
477 */
478static void jz_nand_disable(void)
479{ 535{
480 __nand_disable(); 536 REG_EMC_NFCSR &= ~(EMC_NFCSR_NFE(bank+1) | EMC_NFCSR_NFCE(bank+1));
537 nand_address = 0;
481} 538}
482 539
483static int jz_nand_init(void) 540static int jz_nand_init(void)
484{ 541{
485 unsigned char cData[5]; 542 unsigned char cData[5];
543 int i;
486 544
487 jz_nand_enable(); 545 jz_nand_enable();
488 546
489 __nand_cmd(NAND_CMD_READID); 547 for(i=0; i<4; i++)
490 __nand_addr(NAND_CMD_READ0);
491 cData[0] = __nand_data8();
492 cData[1] = __nand_data8();
493 cData[2] = __nand_data8();
494 cData[3] = __nand_data8();
495 cData[4] = __nand_data8();
496
497 chip_info = nand_identify(cData);
498 if(chip_info == NULL)
499 { 548 {
500 panicf("Unknown NAND flash chip: 0x%x 0x%x 0x%x 0x%x 0x%x", cData[0], 549 jz_nand_select(i);
501 cData[1], cData[2], cData[3], cData[4]); 550
502 return -1; /* panicf() doesn't return though */ 551 __nand_cmd(NAND_CMD_READID);
552 __nand_addr(NAND_CMD_READ0);
553 cData[0] = __nand_data8();
554 cData[1] = __nand_data8();
555 cData[2] = __nand_data8();
556 cData[3] = __nand_data8();
557 cData[4] = __nand_data8();
558
559 jz_nand_deselect(i);
560
561 logf("NAND chip %d: 0x%x 0x%x 0x%x 0x%x 0x%x", i+1, cData[0], cData[1],
562 cData[2], cData[3], cData[4]);
563
564 banks[i] = nand_identify(cData);
565
566 if(banks[i] != NULL)
567 nr_banks++;
568
569 if(i == 0 && banks[i] == NULL)
570 {
571 panicf("Unknown NAND flash chip: 0x%x 0x%x 0x%x 0x%x 0x%x", cData[0],
572 cData[1], cData[2], cData[3], cData[4]);
573 return -1; /* panicf() doesn't return though */
574 }
503 } 575 }
576 chip_info = banks[0];
504 577
505 internal_param.bus_width = 8; 578 internal_param.bus_width = 8;
506 internal_param.row_cycle = chip_info->row_cycles; 579 internal_param.row_cycle = chip_info->row_cycles;
@@ -508,13 +581,17 @@ static int jz_nand_init(void)
508 internal_param.oob_size = chip_info->spare_size; 581 internal_param.oob_size = chip_info->spare_size;
509 internal_param.page_per_block = chip_info->pages_per_block; 582 internal_param.page_per_block = chip_info->pages_per_block;
510 583
584 bank_size = chip_info->page_size * chip_info->blocks_per_bank / 512 * chip_info->pages_per_block;
585
586 jz_nand_disable();
587
511 return 0; 588 return 0;
512} 589}
513 590
514static bool inited = false;
515int nand_init(void) 591int nand_init(void)
516{ 592{
517 int res = 0; 593 int res = 0;
594 static bool inited = false;
518 595
519 if(!inited) 596 if(!inited)
520 { 597 {
@@ -533,29 +610,37 @@ int nand_init(void)
533 610
534int nand_read_sectors(IF_MV2(int drive,) unsigned long start, int count, void* buf) 611int nand_read_sectors(IF_MV2(int drive,) unsigned long start, int count, void* buf)
535{ 612{
536 int i, ret = 0; 613 int i, ret = 0, chip_size = chip_info->page_size;
537 614
538 logf("nand_read_sectors(%ld, %d, 0x%x)", start, count, (int)buf); 615 logf("nand_read_sectors(%ld, %d, 0x%x)", start, count, (int)buf);
539 616
540 start *= 512; 617 start *= 512;
541 count *= 512; 618 count *= 512;
542 619
543 if(count <= chip_info->page_size) 620 if(count <= chip_size)
544 { 621 {
545 ret = jz_nand_read_page(start/chip_info->page_size, temp_page); 622 jz_nand_select(start / 512 / bank_size);
546 memcpy(buf, temp_page+(start%chip_info->page_size), count); 623
547 return ret; 624 ret = jz_nand_read_page(start/chip_size, temp_page);
625 memcpy(buf, temp_page+(start%chip_size), count);
626
627 jz_nand_deselect(start / 512 / bank_size);
548 } 628 }
549 else 629 else
550 { 630 {
551 for(i=0; i<count && ret==0; i+=chip_info->page_size) 631 for(i=0; i<count && ret==0; i+=chip_size)
552 { 632 {
553 ret = jz_nand_read_page((start+i)/chip_info->page_size, temp_page); 633 jz_nand_select((start/512+i) / bank_size);
554 memcpy(buf+i, temp_page+((start+i)%chip_info->page_size), 634
555 (count-i < chip_info->page_size ? count-i : chip_info->page_size)); 635 ret = jz_nand_read_page((start+i)/chip_size, temp_page);
636 memcpy(buf+i, temp_page+((start+i)%chip_size),
637 (count-i < chip_size ? count-i : chip_size));
638
639 jz_nand_deselect((start/512+i) / bank_size);
556 } 640 }
557 return ret;
558 } 641 }
642
643 return ret;
559} 644}
560 645
561/* TODO */ 646/* TODO */
@@ -605,6 +690,7 @@ void nand_enable(bool on)
605void nand_get_info(IF_MV2(int drive,) struct storage_info *info) 690void nand_get_info(IF_MV2(int drive,) struct storage_info *info)
606{ 691{
607 (void)drive; 692 (void)drive;
693
608 /* firmware version */ 694 /* firmware version */
609 info->revision="0.00"; 695 info->revision="0.00";
610 696
@@ -612,8 +698,7 @@ void nand_get_info(IF_MV2(int drive,) struct storage_info *info)
612 info->product="NAND Storage"; 698 info->product="NAND Storage";
613 699
614 /* blocks count */ 700 /* blocks count */
615 /* TODO: proper amount of sectors! */ 701 info->num_sectors = bank_size * nr_banks;
616 info->num_sectors = ((chip_info->page_size+chip_info->spare_size) / 512) * chip_info->pages_per_block * chip_info->blocks_per_bank;
617 info->sector_size = 512; 702 info->sector_size = 512;
618} 703}
619#endif 704#endif
diff --git a/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c
index 3bb9a27007..0b31e8e74d 100644
--- a/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c
@@ -38,9 +38,7 @@ static struct wakeup sd_wakeup;
38 38
39#define DEBUG(x...) logf(x); 39#define DEBUG(x...) logf(x);
40 40
41#ifdef MMC_CD_PIN
42#define MMC_INSERT_STATUS() __gpio_get_pin(MMC_CD_PIN) 41#define MMC_INSERT_STATUS() __gpio_get_pin(MMC_CD_PIN)
43#endif
44 42
45#define MMC_RESET() __msc_reset() 43#define MMC_RESET() __msc_reset()
46 44
@@ -367,7 +365,7 @@ struct mmc_request
367 365
368static int use_4bit; /* Use 4-bit data bus */ 366static int use_4bit; /* Use 4-bit data bus */
369static int num_6; 367static int num_6;
370static int sd2_0; 368static int sd2_0 = 1;
371 369
372/* Stop the MMC clock and wait while it happens */ 370/* Stop the MMC clock and wait while it happens */
373static inline int jz_mmc_stop_clock(void) 371static inline int jz_mmc_stop_clock(void)
@@ -766,7 +764,7 @@ static int jz_mmc_exec_cmd(struct mmc_request *request)
766 jz_mmc_stop_clock(); 764 jz_mmc_stop_clock();
767 765
768 /* mask all interrupts */ 766 /* mask all interrupts */
769 //REG_MSC_IMASK = 0xffff; 767 REG_MSC_IMASK = 0xffff;
770 /* clear status */ 768 /* clear status */
771 REG_MSC_IREG = 0xffff; 769 REG_MSC_IREG = 0xffff;
772 /*open interrupt */ 770 /*open interrupt */
@@ -812,7 +810,6 @@ static int jz_mmc_exec_cmd(struct mmc_request *request)
812 case 6: 810 case 6:
813 if (num_6 < 2) 811 if (num_6 < 2)
814 { 812 {
815
816#if defined(MMC_DMA_ENABLE) 813#if defined(MMC_DMA_ENABLE)
817 cmdat |= 814 cmdat |=
818 MSC_CMDAT_DATA_EN | MSC_CMDAT_READ | 815 MSC_CMDAT_DATA_EN | MSC_CMDAT_READ |
@@ -992,10 +989,7 @@ static int jz_mmc_exec_cmd(struct mmc_request *request)
992********************************************************************************************************************/ 989********************************************************************************************************************/
993static int jz_mmc_chkcard(void) 990static int jz_mmc_chkcard(void)
994{ 991{
995 if (MMC_INSERT_STATUS() == 0) 992 return (MMC_INSERT_STATUS() == 0 ? 1 : 0);
996 return 1; /* insert entirely */
997 else
998 return 0; /* not insert entirely */
999} 993}
1000 994
1001#if MMC_DMA_INTERRUPT 995#if MMC_DMA_INTERRUPT
@@ -1044,13 +1038,13 @@ void MSC(void)
1044static void jz_mmc_hardware_init(void) 1038static void jz_mmc_hardware_init(void)
1045{ 1039{
1046 mmc_init_gpio(); /* init GPIO */ 1040 mmc_init_gpio(); /* init GPIO */
1041 __cpm_start_msc(); /* enable mmc clock */
1047#ifdef MMC_POWER_ON 1042#ifdef MMC_POWER_ON
1048 MMC_POWER_ON(); /* turn on power of card */ 1043 MMC_POWER_ON(); /* turn on power of card */
1049#endif 1044#endif
1050 MMC_RESET(); /* reset mmc/sd controller */ 1045 MMC_RESET(); /* reset mmc/sd controller */
1051 MMC_IRQ_MASK(); /* mask all IRQs */ 1046 MMC_IRQ_MASK(); /* mask all IRQs */
1052 jz_mmc_stop_clock(); /* stop MMC/SD clock */ 1047 jz_mmc_stop_clock(); /* stop MMC/SD clock */
1053 __cpm_start_msc();
1054#ifdef MMC_DMA_ENABLE 1048#ifdef MMC_DMA_ENABLE
1055// __cpm_start_dmac(); 1049// __cpm_start_dmac();
1056// __dmac_enable_module(); 1050// __dmac_enable_module();
@@ -1101,7 +1095,7 @@ int _sd_init(void)
1101 1095
1102bool card_detect_target(void) 1096bool card_detect_target(void)
1103{ 1097{
1104 return jz_mmc_chkcard() == 1; 1098 return (jz_mmc_chkcard() == 1);
1105} 1099}
1106 1100
1107#ifdef HAVE_HOTSWAP 1101#ifdef HAVE_HOTSWAP
diff --git a/firmware/target/mips/ingenic_jz47xx/codec-jz4740.c b/firmware/target/mips/ingenic_jz47xx/codec-jz4740.c
index d144a03553..ef8c343035 100644
--- a/firmware/target/mips/ingenic_jz47xx/codec-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/codec-jz4740.c
@@ -28,7 +28,6 @@ static unsigned short codec_base_gain;
28static unsigned short codec_mic_gain; 28static unsigned short codec_mic_gain;
29static bool HP_on_off_flag; 29static bool HP_on_off_flag;
30static int HP_register_value; 30static int HP_register_value;
31static int IS_WRITE_PCM;
32 31
33static void i2s_codec_set_samplerate(unsigned short rate); 32static void i2s_codec_set_samplerate(unsigned short rate);
34 33
@@ -44,6 +43,9 @@ static void i2s_codec_reset(void)
44 43
45static void i2s_codec_init(void) 44static void i2s_codec_init(void)
46{ 45{
46 __cpm_start_aic1();
47 __cpm_start_aic2();
48
47 __aic_enable(); 49 __aic_enable();
48 50
49 __i2s_internal_codec(); 51 __i2s_internal_codec();
@@ -185,7 +187,6 @@ static unsigned short i2s_codec_get_volume(void)
185static void i2s_codec_set_samplerate(unsigned short rate) 187static void i2s_codec_set_samplerate(unsigned short rate)
186{ 188{
187 unsigned short speed = 0; 189 unsigned short speed = 0;
188 unsigned short val = 0;
189 190
190 switch (rate) 191 switch (rate)
191 { 192 {
diff --git a/firmware/target/mips/ingenic_jz47xx/i2c-jz4740.c b/firmware/target/mips/ingenic_jz47xx/i2c-jz4740.c
new file mode 100644
index 0000000000..1fbf1fc19e
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/i2c-jz4740.c
@@ -0,0 +1,240 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2009 by Maurus Cuelenaere
11 *
12 * based on linux/arch/mips/jz4740/i2c.c
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version 2
17 * of the License, or (at your option) any later version.
18 *
19 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
20 * KIND, either express or implied.
21 *
22 ****************************************************************************/
23
24/*
25 * Jz4740 I2C routines.
26 *
27 * Copyright (C) 2005,2006 Ingenic Semiconductor Inc.
28 * Author: <lhhuang@ingenic.cn>
29 *
30 * This program is free software; you can distribute it and/or modify it
31 * under the terms of the GNU General Public License (Version 2) as
32 * published by the Free Software Foundation.
33 *
34 * This program is distributed in the hope it will be useful, but WITHOUT
35 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
36 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
37 * for more details.
38 *
39 * You should have received a copy of the GNU General Public License along
40 * with this program; if not, write to the Free Software Foundation, Inc.,
41 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
42 *
43 */
44
45#include "config.h"
46#include "system.h"
47#include "jz4740.h"
48#include "logf.h"
49#include "generic_i2c.h"
50
51
52/* I2C protocol */
53#define I2C_READ 1
54#define I2C_WRITE 0
55
56#define TIMEOUT 1000
57
58/*
59 * I2C bus protocol basic routines
60 */
61static int i2c_put_data(unsigned char data)
62{
63 unsigned int timeout = TIMEOUT*10;
64
65 __i2c_write(data);
66 __i2c_set_drf();
67 while (__i2c_check_drf() != 0);
68 while (!__i2c_transmit_ended());
69 while (!__i2c_received_ack() && timeout)
70 timeout--;
71
72 if (timeout)
73 return 0;
74 else
75 return -1;
76}
77
78static int i2c_put_data_nack(unsigned char data)
79{
80 unsigned int timeout = TIMEOUT*10;
81
82 __i2c_write(data);
83 __i2c_set_drf();
84 while (__i2c_check_drf() != 0);
85 while (!__i2c_transmit_ended());
86 while (timeout--);
87
88 return 0;
89}
90
91static int i2c_get_data(unsigned char *data, int ack)
92{
93 int timeout = TIMEOUT*10;
94
95 if (!ack)
96 __i2c_send_nack();
97 else
98 __i2c_send_ack();
99
100 while (__i2c_check_drf() == 0 && timeout)
101 timeout--;
102
103 if (timeout)
104 {
105 if (!ack)
106 __i2c_send_stop();
107 *data = __i2c_read();
108 __i2c_clear_drf();
109 return 0;
110 }
111 else
112 return -1;
113}
114
115/*
116 * I2C interface
117 */
118void i2c_open(void)
119{
120 /* TODO */
121 //__i2c_set_clk(jz_clocks.extalclk, 10000); /* default 10 KHz */
122 __i2c_enable();
123}
124
125void i2c_close(void)
126{
127 udelay(300); /* wait for STOP goes over. */
128 __i2c_disable();
129}
130
131void i2c_setclk(unsigned int i2cclk)
132{
133 /* TODO */
134 //__i2c_set_clk(jz_clocks.extalclk, i2cclk);
135}
136
137int i2c_read(int device, unsigned char *buf, int count)
138{
139 int cnt = count;
140 int timeout = 5;
141
142 device &= 0xFF;
143
144L_try_again:
145 if (timeout < 0)
146 goto L_timeout;
147
148 __i2c_send_nack(); /* Master does not send ACK, slave sends it */
149
150 __i2c_send_start();
151 if (i2c_put_data( (device << 1) | I2C_READ ) < 0)
152 goto device_err;
153
154 __i2c_send_ack(); /* Master sends ACK for continue reading */
155
156 while (cnt)
157 {
158 if (cnt == 1)
159 {
160 if (i2c_get_data(buf, 0) < 0)
161 break;
162 }
163 else
164 {
165 if (i2c_get_data(buf, 1) < 0)
166 break;
167 }
168 cnt--;
169 buf++;
170 }
171
172 __i2c_send_stop();
173 return count - cnt;
174
175device_err:
176 timeout--;
177 __i2c_send_stop();
178 goto L_try_again;
179
180L_timeout:
181 __i2c_send_stop();
182 logf("Read I2C device 0x%2x failed.", device);
183 return -1;
184}
185
186int i2c_write(int device, unsigned char *buf, int count)
187{
188 int cnt = count;
189 int timeout = 5;
190
191 device &= 0xFF;
192
193 __i2c_send_nack(); /* Master does not send ACK, slave sends it */
194
195W_try_again:
196 if (timeout < 0)
197 goto W_timeout;
198
199 cnt = count;
200
201 __i2c_send_start();
202 if (i2c_put_data( (device << 1) | I2C_WRITE ) < 0)
203 goto device_err;
204
205#if 0 //CONFIG_JZ_TPANEL_ATA2508
206 if (address == 0xff)
207 {
208 while (cnt)
209 {
210 if (i2c_put_data_nack(*buf) < 0)
211 break;
212 cnt--;
213 buf++;
214 }
215 }
216 else
217#endif
218 {
219 while (cnt)
220 {
221 if (i2c_put_data(*buf) < 0)
222 break;
223 cnt--;
224 buf++;
225 }
226 }
227
228 __i2c_send_stop();
229 return count - cnt;
230
231device_err:
232 timeout--;
233 __i2c_send_stop();
234 goto W_try_again;
235
236W_timeout:
237 logf("Write I2C device 0x%2x failed.", device);
238 __i2c_send_stop();
239 return -1;
240}
diff --git a/firmware/target/mips/ingenic_jz47xx/kernel-jz4740.c b/firmware/target/mips/ingenic_jz47xx/kernel-jz4740.c
index 431af490da..2ef66a1d19 100644
--- a/firmware/target/mips/ingenic_jz47xx/kernel-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/kernel-jz4740.c
@@ -39,7 +39,8 @@ void tick_start(unsigned int interval_in_ms)
39 __tcu_select_extalclk(0); 39 __tcu_select_extalclk(0);
40 __tcu_select_clk_div4(0); 40 __tcu_select_clk_div4(0);
41 41
42 latch = (JZ_EXTAL / 4 + (interval_in_ms>>1)) / interval_in_ms; 42 /* 12Mhz / 4 = 3Mhz */
43 latch = interval_in_ms*1000 * 3;
43 44
44 REG_TCU_TCNT(0) = 0; 45 REG_TCU_TCNT(0) = 0;
45 REG_TCU_TDFR(0) = latch; 46 REG_TCU_TDFR(0) = latch;
diff --git a/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c
index cc2c84c6b4..317da8413e 100644
--- a/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c
@@ -69,14 +69,6 @@ bool lcd_enabled(void)
69/* Update a fraction of the display. */ 69/* Update a fraction of the display. */
70void lcd_update_rect(int x, int y, int width, int height) 70void lcd_update_rect(int x, int y, int width, int height)
71{ 71{
72#if 1
73 /* This is an ugly HACK until partial LCD drawing works.. */
74 width = LCD_WIDTH;
75 height = LCD_HEIGHT;
76 x = 0;
77 y = 0;
78#endif
79
80 mutex_lock(&lcd_mtx); 72 mutex_lock(&lcd_mtx);
81 73
82 __cpm_start_lcd(); 74 __cpm_start_lcd();
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/ata-sd-target.h b/firmware/target/mips/ingenic_jz47xx/onda_vx747/ata-sd-target.h
index ba324c1dcb..aed2b9cfea 100644
--- a/firmware/target/mips/ingenic_jz47xx/onda_vx747/ata-sd-target.h
+++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/ata-sd-target.h
@@ -39,29 +39,12 @@ int _sd_write_sectors(unsigned long start, int count, const void* buf);
39int _sd_init(void); 39int _sd_init(void);
40 40
41#define MMC_CD_PIN (29 + 1 * 32) /* Pin to check card insertion */ 41#define MMC_CD_PIN (29 + 1 * 32) /* Pin to check card insertion */
42//#define MMC_POWER_PIN (22 + 2 * 32) /* Pin to enable/disable card power */
43
44#ifdef MMC_POWER_PIN
45#define MMC_POWER_OFF() \
46do { \
47 __gpio_clear_pin(MMC_POWER_PIN); \
48} while (0)
49
50#define MMC_POWER_ON() \
51do { \
52 __gpio_set_pin(MMC_POWER_PIN); \
53} while (0)
54#endif
55 42
56static inline void mmc_init_gpio(void) 43static inline void mmc_init_gpio(void)
57{ 44{
58 __gpio_as_msc(); 45 __gpio_as_msc();
59 __gpio_as_input(MMC_CD_PIN); 46 __gpio_as_input(MMC_CD_PIN);
60#ifdef MMC_POWER_PIN 47 //__gpio_enable_pull(32*3+29);
61 __gpio_as_func0(MMC_POWER_PIN);
62 __gpio_as_output(MMC_POWER_PIN);
63#endif
64 __gpio_enable_pull(32*3+29);
65 __gpio_enable_pull(32*3+10); 48 __gpio_enable_pull(32*3+10);
66 __gpio_enable_pull(32*3+11); 49 __gpio_enable_pull(32*3+11);
67 __gpio_enable_pull(32*3+12); 50 __gpio_enable_pull(32*3+12);
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c b/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c
index faed5ecda2..c07a191bbe 100644
--- a/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c
+++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c
@@ -240,6 +240,34 @@ void lcd_set_target(short x, short y, short width, short height)
240 SLCD_SET_COMMAND(REG_RW_GRAM); /* write data to GRAM */ 240 SLCD_SET_COMMAND(REG_RW_GRAM); /* write data to GRAM */
241} 241}
242 242
243void lcd_set_flip(bool yesno)
244{
245 int i;
246
247 __cpm_start_lcd();
248#if CONFIG_ORIENTATION == SCREEN_PORTRAIT
249 if(yesno)
250 {
251 SLCD_SEND_COMMAND(REG_ENTRY_MODE, (ENTRY_MODE_BGR | ENTRY_MODE_HWM));
252 }
253 else
254 {
255 SLCD_SEND_COMMAND(REG_ENTRY_MODE, (ENTRY_MODE_BGR | ENTRY_MODE_VID | ENTRY_MODE_HID | ENTRY_MODE_HWM));
256 }
257#else
258 if(yesno)
259 {
260 SLCD_SEND_COMMAND(REG_ENTRY_MODE, (ENTRY_MODE_BGR | ENTRY_MODE_HID | ENTRY_MODE_AM));
261 }
262 else
263 {
264 SLCD_SEND_COMMAND(REG_ENTRY_MODE, (ENTRY_MODE_BGR | ENTRY_MODE_VID | ENTRY_MODE_AM));
265 }
266#endif
267 DELAY;
268 __cpm_stop_lcd();
269}
270
243void lcd_on(void) 271void lcd_on(void)
244{ 272{
245 _display_on(); 273 _display_on();
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/power-onda_vx747.c b/firmware/target/mips/ingenic_jz47xx/onda_vx747/power-onda_vx747.c
new file mode 100644
index 0000000000..374bc110d6
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/power-onda_vx747.c
@@ -0,0 +1,43 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2009 by Maurus Cuelenaere
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21
22#include "config.h"
23#include "power.h"
24#include "jz4740.h"
25
26/* TQ7051 chip */
27#define USB_CHARGER_GPIO (32*1+30) /* STAT port */
28
29/* Detect which power sources are present. */
30unsigned int power_input_status(void)
31{
32 unsigned int status = 0;
33
34 if (__gpio_get_pin(USB_CHARGER_GPIO))
35 status |= POWER_INPUT_USB_CHARGER;
36
37 return status;
38}
39
40void power_init(void)
41{
42 __gpio_as_input(USB_CHARGER_GPIO);
43}
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/usb-target.h b/firmware/target/mips/ingenic_jz47xx/onda_vx747/usb-target.h
index fbb14b7ac4..0b17bebfc2 100644
--- a/firmware/target/mips/ingenic_jz47xx/onda_vx747/usb-target.h
+++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/usb-target.h
@@ -24,7 +24,7 @@
24 24
25#include "config.h" 25#include "config.h"
26 26
27#define GPIO_UDC_DETE (32 * 3 + 28) 27#define GPIO_UDC_DETE (32 * 3 + 28) /* A18 = ADP_CHK */
28#define IRQ_GPIO_UDC_DETE (IRQ_GPIO_0 + GPIO_UDC_DETE) 28#define IRQ_GPIO_UDC_DETE (IRQ_GPIO_0 + GPIO_UDC_DETE)
29#define USB_GPIO_IRQ GPIO124 29#define USB_GPIO_IRQ GPIO124
30 30
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-05 14:26:56 +0000