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-rw-r--r--firmware/export/as3525v2.h2
-rw-r--r--firmware/export/imx31l.h1
-rw-r--r--firmware/export/tcc77x.h2
-rw-r--r--firmware/export/tcc780x.h2
4 files changed, 6 insertions, 1 deletions
diff --git a/firmware/export/as3525v2.h b/firmware/export/as3525v2.h
index c5c9c0504f..5cff4d6f75 100644
--- a/firmware/export/as3525v2.h
+++ b/firmware/export/as3525v2.h
@@ -26,6 +26,8 @@
26 26
27/* insert differences here */ 27/* insert differences here */
28 28
29#define CACHEALIGN_BITS (5)
30
29#ifndef IRAM_SIZE /* protect in case the define name changes */ 31#ifndef IRAM_SIZE /* protect in case the define name changes */
30# error IRAM_SIZE not defined ! 32# error IRAM_SIZE not defined !
31#endif 33#endif
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h
index 7cb452d3cb..bf1a05b6ec 100644
--- a/firmware/export/imx31l.h
+++ b/firmware/export/imx31l.h
@@ -38,7 +38,6 @@
38#define FRAME ((void *)(FRAME_PHYS_ADDR+0x100000-CSD0_BASE_ADDR)) 38#define FRAME ((void *)(FRAME_PHYS_ADDR+0x100000-CSD0_BASE_ADDR))
39 39
40#define CACHEALIGN_BITS 5 40#define CACHEALIGN_BITS 5
41#define CACHEALIGN_SIZE 32
42#define NOCACHE_BASE CSD0_BASE_ADDR 41#define NOCACHE_BASE CSD0_BASE_ADDR
43 42
44/* USBOTG */ 43/* USBOTG */
diff --git a/firmware/export/tcc77x.h b/firmware/export/tcc77x.h
index db128b68f6..3c457c5b38 100644
--- a/firmware/export/tcc77x.h
+++ b/firmware/export/tcc77x.h
@@ -21,6 +21,8 @@
21#ifndef __TCC77X_H__ 21#ifndef __TCC77X_H__
22#define __TCC77X_H__ 22#define __TCC77X_H__
23 23
24#define CACHEALIGN_BITS (5)
25
24/* General-purpose IO */ 26/* General-purpose IO */
25 27
26#define GPIOA (*(volatile unsigned long *)0x80000300) 28#define GPIOA (*(volatile unsigned long *)0x80000300)
diff --git a/firmware/export/tcc780x.h b/firmware/export/tcc780x.h
index aca3bec2bd..8706fbbf6d 100644
--- a/firmware/export/tcc780x.h
+++ b/firmware/export/tcc780x.h
@@ -21,6 +21,8 @@
21#ifndef __TCC780X_H__ 21#ifndef __TCC780X_H__
22#define __TCC780X_H__ 22#define __TCC780X_H__
23 23
24#define CACHEALIGN_BITS (5)
25
24#define TTB_SIZE (0x4000) 26#define TTB_SIZE (0x4000)
25/* must be 16Kb (0x4000) aligned */ 27/* must be 16Kb (0x4000) aligned */
26#define TTB_BASE_ADDR (0x20000000 + (MEMORYSIZE*1024*1024) - TTB_SIZE) 28#define TTB_BASE_ADDR (0x20000000 + (MEMORYSIZE*1024*1024) - TTB_SIZE)