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-rw-r--r--firmware/app.lds95
-rw-r--r--firmware/backlight.c6
-rw-r--r--firmware/crt0.S123
-rw-r--r--firmware/drivers/adc.c46
-rw-r--r--firmware/drivers/ata.c130
-rw-r--r--firmware/drivers/button.c34
-rw-r--r--firmware/drivers/i2c.c28
-rw-r--r--firmware/drivers/lcd-recorder.c59
-rw-r--r--firmware/drivers/led.c6
-rw-r--r--firmware/drivers/power.c20
-rw-r--r--firmware/drivers/serial.c4
-rw-r--r--firmware/export/button.h23
-rw-r--r--firmware/export/config-gmini120.h86
-rw-r--r--firmware/export/config-gminisp.h77
-rw-r--r--firmware/export/config.h32
-rw-r--r--firmware/export/cpu.h3
-rw-r--r--firmware/export/system.h66
-rw-r--r--firmware/export/tcc730.h107
-rw-r--r--firmware/export/thread.h7
-rw-r--r--firmware/hwcompat.c6
-rw-r--r--firmware/kernel.c57
-rw-r--r--firmware/rolo.c8
-rw-r--r--firmware/system.c238
-rw-r--r--firmware/thread.c64
-rw-r--r--firmware/usb.c39
25 files changed, 30 insertions, 1334 deletions
diff --git a/firmware/app.lds b/firmware/app.lds
index f2bd9dbb4e..a081536dfb 100644
--- a/firmware/app.lds
+++ b/firmware/app.lds
@@ -4,9 +4,6 @@ ENTRY(start)
4#ifdef CPU_COLDFIRE 4#ifdef CPU_COLDFIRE
5OUTPUT_FORMAT(elf32-m68k) 5OUTPUT_FORMAT(elf32-m68k)
6INPUT(target/coldfire/crt0.o) 6INPUT(target/coldfire/crt0.o)
7#elif CONFIG_CPU == TCC730
8OUTPUT_FORMAT(elf32-calmrisc16)
9INPUT(crt0.o)
10#elif defined(CPU_ARM) 7#elif defined(CPU_ARM)
11OUTPUT_FORMAT(elf32-littlearm) 8OUTPUT_FORMAT(elf32-littlearm)
12OUTPUT_ARCH(arm) 9OUTPUT_ARCH(arm)
@@ -20,100 +17,9 @@ OUTPUT_FORMAT(elf32-sh)
20INPUT(target/sh/crt0.o) 17INPUT(target/sh/crt0.o)
21#endif 18#endif
22 19
23#if CONFIG_CPU == TCC730
24MEMORY
25{
26 FIRMWARE : ORIGIN = LOADADDRESS, LENGTH = 256K
27 FLASH (RX) : ORIGIN = 0x000000, LENGTH = 1024K
28 ICMEM (RX) : ORIGIN = 0x3FC000, LENGTH = 32K
29 IMEM1 : ORIGIN = 0x200000, LENGTH = 32K
30 IMEM2 : ORIGIN = 0x210000, LENGTH = 16K
31 IMEM3 : ORIGIN = 0x220000, LENGTH = 32K
32 IMEM4 : ORIGIN = 0x230000, LENGTH = 16K
33
34 DRAM : ORIGIN = 0x000000, LENGTH = 0x3F0000
35}
36
37SECTIONS
38{
39.text LOADADDRESS : {
40 *(.init.text)
41 *(.text)
42 }> FLASH AT> FIRMWARE
43
44.icode 0x3FC040: {
45 *(.vectors)
46 *(.icode)
47 }> ICMEM AT> FIRMWARE
48
49/* We start at 0x2000, to avoid overwriting Archos' loader datasegment.
50 * If it turns out that we won't call back the loader, this can be set to 0.
51 */
52.bss 0x2000 : {
53 *(.bss)
54 . = ALIGN(2);
55 }> DRAM
56
57/* Data is put after BSS, to have all strings addresses > VIRT_PTR + VIRT_SIZE.
58 Strings are in rodata, so what we really assert is (.rodata > VIRT_PTR + VIRT_SIZE)
59 See settings.h for details */
60.data ALIGN(2): {
61 *(.data)
62 . = ALIGN(2);
63 *(.rodata)
64 . = ALIGN(2);
65 *(.rodata.str1.2)
66 . = ALIGN(2);
67 }> DRAM AT> FIRMWARE
68
69
70.stack ALIGN(2) : {
71 . = . + 0x2000;
72}> DRAM
73
74.idata 0x200000: {
75 *(.idata)
76}> IMEM1
77
78.idata2 0x220000: {
79 *(.idata2)
80}> IMEM3
81
82_codesize = SIZEOF(.text);
83
84_icodecopy = LOADADDR(.icode);
85_icodestart = ADDR(.icode);
86_icodesize = SIZEOF(.icode);
87
88_datacopy = LOADADDR(.data);
89_datastart = ADDR(.data);
90_datasize = SIZEOF(.data);
91
92
93_bssstart = ADDR(.bss);
94_bsssize = (SIZEOF(.bss) + 1) & ~ 1;
95
96_stackbegin = ADDR(.stack);
97_stackend = ADDR(.stack) + SIZEOF(.stack);
98
99_idatastart = ADDR(.idata);
100
101/* FIXME: Where to put audio buffer? */
102
103_audiobuffer = 0;
104_audiobufend = 0;
105
106/* Plugins are not supported on the Gmini*/
107
108_pluginbuf = 0;
109
110}
111#else
112
113#define PLUGINSIZE PLUGIN_BUFFER_SIZE 20#define PLUGINSIZE PLUGIN_BUFFER_SIZE
114#define CODECSIZE CODEC_SIZE 21#define CODECSIZE CODEC_SIZE
115 22
116
117#ifdef DEBUG 23#ifdef DEBUG
118#define STUBOFFSET 0x10000 24#define STUBOFFSET 0x10000
119#else 25#else
@@ -332,4 +238,3 @@ SECTIONS
332 } 238 }
333} 239}
334 240
335#endif
diff --git a/firmware/backlight.c b/firmware/backlight.c
index c7d1add605..8a07197426 100644
--- a/firmware/backlight.c
+++ b/firmware/backlight.c
@@ -73,8 +73,6 @@ static inline void __backlight_on(void)
73 or_b(0x40, &PAIORH); 73 or_b(0x40, &PAIORH);
74#elif CONFIG_BACKLIGHT == BL_PA14_HI /* Ondio */ 74#elif CONFIG_BACKLIGHT == BL_PA14_HI /* Ondio */
75 or_b(0x40, &PADRH); /* drive it high */ 75 or_b(0x40, &PADRH); /* drive it high */
76#elif CONFIG_BACKLIGHT == BL_GMINI
77 P1 |= 0x10;
78#endif 76#endif
79} 77}
80 78
@@ -87,8 +85,6 @@ static inline void __backlight_off(void)
87 and_b(~0x40, &PAIORH); /* let it float (up) */ 85 and_b(~0x40, &PAIORH); /* let it float (up) */
88#elif CONFIG_BACKLIGHT == BL_PA14_HI /* Ondio */ 86#elif CONFIG_BACKLIGHT == BL_PA14_HI /* Ondio */
89 and_b(~0x40, &PADRH); /* drive it low */ 87 and_b(~0x40, &PADRH); /* drive it low */
90#elif CONFIG_BACKLIGHT == BL_GMINI
91 P1 &= ~0x10;
92#endif 88#endif
93} 89}
94#endif 90#endif
@@ -568,8 +564,6 @@ void backlight_init(void)
568#elif CONFIG_BACKLIGHT == BL_PA14_LO || CONFIG_BACKLIGHT == BL_PA14_HI 564#elif CONFIG_BACKLIGHT == BL_PA14_LO || CONFIG_BACKLIGHT == BL_PA14_HI
569 PACR1 &= ~0x3000; /* Set PA14 (backlight control) to GPIO */ 565 PACR1 &= ~0x3000; /* Set PA14 (backlight control) to GPIO */
570 or_b(0x40, &PAIORH); /* ..and output */ 566 or_b(0x40, &PAIORH); /* ..and output */
571#elif CONFIG_BACKLIGHT == BL_GMINI
572 P1CON |= 0x10; /* P1.4 C-MOS output mode */
573#endif 567#endif
574 backlight_on(); 568 backlight_on();
575#ifdef HAVE_REMOTE_LCD 569#ifdef HAVE_REMOTE_LCD
diff --git a/firmware/crt0.S b/firmware/crt0.S
deleted file mode 100644
index 61a2d63f1e..0000000000
--- a/firmware/crt0.S
+++ /dev/null
@@ -1,123 +0,0 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2002 by Linus Nielsen Feltzing
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20/* Most of the code from this file has now been moved into the target trees */
21
22#include "config.h"
23#include "cpu.h"
24
25 .section .init.text,"ax",@progbits
26
27 .global start
28start:
29
30#if CONFIG_CPU == TCC730
31 /* Platform: Gmini 120/SP */
32 ;; disable all interrupts
33 clrsr fe
34 clrsr ie
35 clrsr te
36 ld a14, #0x3F0000
37
38 ld r5, 0xA5
39 ldb @[a14 + 6], r5 ; disable watchdog
40
41 ld a11, #(_datacopy) ; where the data section is in the flash
42 ld a8, #(_datastart) ; destination
43
44 ;; copy data section from flash to ram.
45 ld a9, #_datasize
46 ld r6, e9
47 cmp eq, r6, #0
48 brf .data_copy_loop
49 cmp eq, r9, #0
50 brt .data_copy_end
51.data_copy_loop:
52 ldc r2, @a11
53 ldw @[a8 + 0], r2
54 add a11, #0x2
55 add a8, #0x2
56 sub r9, #0x2
57 sbc r6, #0
58 cmp ugt, r6, #0
59 brt .data_copy_loop
60 cmp ugt, r9, #0
61 brt .data_copy_loop
62.data_copy_end:
63
64 ;; zero out bss
65 ld r2, #0
66 ld a8, #(_bssstart) ; destination
67 ld a9, #_bsssize
68 ld r6, e9
69
70 cmp eq, r6, #0
71 brf .bss_init_loop
72 cmp eq, r9, #0
73 brt .bss_init_end
74.bss_init_loop:
75 ldw @[a8 + 0], r2
76 add a8, #0x2
77 sub r9, #0x2
78 sbc r6, #0
79 cmp ugt, r6, #0
80 brt .bss_init_loop
81 cmp ugt, r9, #0
82 brt .bss_init_loop
83.bss_init_end:
84
85 ;; set stack pointer
86 ld a15, _stackend
87
88 ;; go!
89 jsr _main
90
91 ;; soft reset
92 ld a10, #0
93 ldc r10, @a10
94 jmp a10
95
96
97 .section .vectors, "ax"
98irq_handler:
99
100 push r0, r1
101 push r2, r3
102 push r4, r5
103 push r6, r7
104 push a8, a9
105 push a10, a11
106 push a12, a13
107 push a14
108 ld a13, #0x3f0000
109 ldb r0, @[a13 + 0x26]
110 add r0, r0
111 ld a10, #_interrupt_vector
112 ldw a13, @[a10 + r0]
113 jsr a13
114 pop a14
115 pop a13, a12
116 pop a11, a10
117 pop a9, a8
118 pop r7, r6
119 pop r5, r4
120 pop r3, r2
121 pop r1, r0
122 ret_irq
123#endif
diff --git a/firmware/drivers/adc.c b/firmware/drivers/adc.c
index adeace005b..f002be96b4 100644
--- a/firmware/drivers/adc.c
+++ b/firmware/drivers/adc.c
@@ -109,50 +109,4 @@ void adc_init(void)
109 sleep(2); /* Ensure valid readings when adc_init returns */ 109 sleep(2); /* Ensure valid readings when adc_init returns */
110} 110}
111 111
112#elif CONFIG_CPU == TCC730
113
114
115/**************************************************************************
116 **
117 ** Each channel will be updated HZ/CHANNEL_ORDER_SIZE times per second.
118 **
119 *************************************************************************/
120
121static int current_channel;
122static int current_channel_idx;
123static unsigned short adcdata[NUM_ADC_CHANNELS];
124
125#define CHANNEL_ORDER_SIZE 2
126static int channel_order[CHANNEL_ORDER_SIZE] = {6,7};
127
128static void adc_tick(void)
129{
130 if (ADCON & (1 << 3)) {
131 /* previous conversion finished? */
132 adcdata[current_channel] = ADDATA >> 6;
133 if (++current_channel_idx >= CHANNEL_ORDER_SIZE)
134 current_channel_idx = 0;
135 current_channel = channel_order[current_channel_idx];
136 int adcon = (current_channel << 4) | 1;
137 ADCON = adcon;
138 }
139}
140
141unsigned short adc_read(int channel)
142{
143 return adcdata[channel];
144}
145
146void adc_init(void)
147{
148 current_channel_idx = 0;
149 current_channel = channel_order[current_channel_idx];
150
151 ADCON = (current_channel << 4) | 1;
152
153 tick_add_task(adc_tick);
154
155 sleep(2); /* Ensure valid readings when adc_init returns */
156}
157
158#endif 112#endif
diff --git a/firmware/drivers/ata.c b/firmware/drivers/ata.c
index 4017d5f3f7..c882c22fe1 100644
--- a/firmware/drivers/ata.c
+++ b/firmware/drivers/ata.c
@@ -84,104 +84,6 @@
84#define SET_REG(reg,val) reg = (val) 84#define SET_REG(reg,val) reg = (val)
85#define SET_16BITREG(reg,val) reg = (val) 85#define SET_16BITREG(reg,val) reg = (val)
86 86
87#elif CONFIG_CPU == TCC730
88
89/* Plain C read & write loops */
90#define PREFER_C_READING
91#define PREFER_C_WRITING
92
93#define SWAP_WORDS
94
95#define ATA_DATA_IDX (0xD0)
96#define ATA_ERROR_IDX (0xD2)
97#define ATA_NSECTOR_IDX (0xD4)
98#define ATA_SECTOR_IDX (0xD6)
99#define ATA_LCYL_IDX (0xD8)
100#define ATA_HCYL_IDX (0xDA)
101#define ATA_SELECT_IDX (0xDC)
102#define ATA_COMMAND_IDX (0xDE)
103#define ATA_CONTROL_IDX (0xEC)
104
105#define ATA_FEATURE_IDX ATA_ERROR_IDX
106#define ATA_STATUS_IDX ATA_COMMAND_IDX
107#define ATA_ALT_STATUS_IDX ATA_CONTROL_IDX
108
109#define SET_REG(reg, value) (ide_write_register(reg ## _IDX, value))
110#define SET_16BITREG(reg, value) (ide_write_register(reg ## _IDX, value))
111#define GET_REG(reg) (ide_read_register(reg))
112
113#define ATA_DATA (GET_REG(ATA_DATA_IDX))
114#define ATA_ERROR (GET_REG(ATA_ERROR_IDX))
115#define ATA_NSECTOR (GET_REG(ATA_NSECTOR_IDX))
116#define ATA_SECTOR (GET_REG(ATA_SECTOR_IDX))
117#define ATA_LCYL (GET_REG(ATA_LCYL_IDX))
118#define ATA_HCYL (GET_REG(ATA_HCYL_IDX))
119#define ATA_SELECT (GET_REG(ATA_SELECT_IDX))
120#define ATA_COMMAND (GET_REG(ATA_COMMAND_IDX))
121
122#define ATA_CONTROL (GET_REG(ATA_CONTROL_IDX))
123
124#define STATUS_BSY 0x80
125#define STATUS_RDY 0x40
126#define STATUS_DF 0x20
127#define STATUS_DRQ 0x08
128#define STATUS_ERR 0x01
129
130#define ERROR_ABRT 0x04
131
132#define WRITE_PATTERN1 0xa5
133#define WRITE_PATTERN2 0x5a
134#define WRITE_PATTERN3 0xaa
135#define WRITE_PATTERN4 0x55
136
137#define READ_PATTERN1 0xa5
138#define READ_PATTERN2 0x5a
139#define READ_PATTERN3 0xaa
140#define READ_PATTERN4 0x55
141
142#define READ_PATTERN1_MASK 0xff
143#define READ_PATTERN2_MASK 0xff
144#define READ_PATTERN3_MASK 0xff
145#define READ_PATTERN4_MASK 0xff
146
147static unsigned char ide_sector_data[SECTOR_SIZE] __attribute__ ((section(".idata")));
148static unsigned ide_reg_temp __attribute__ ((section(".idata")));
149
150void ide_write_register(int reg, int value) {
151 /* Archos firmware code does (sometimes!) this:
152 set the RAM speed to 8 cycles.
153 MIUSCFG |= 0x7;
154 */
155
156 ide_reg_temp = value;
157
158 long extAddr = (long)reg << 16;
159 ddma_transfer(1, 1, &ide_reg_temp, extAddr, 2);
160
161 /* set the RAM speed to 6 cycles.
162 unsigned char miuscfg = MIUSCFG;
163 miuscfg = (miuscfg & ~7) | 5;
164 */
165}
166
167int ide_read_register(int reg) {
168 /* set the RAM speed to 6 cycles.
169 unsigned char miuscfg = MIUSCFG;
170 miuscfg = (miuscfg & ~7) | 5;
171 MIUSCFG = miuscfg; */
172
173 long extAddr = (long)reg << 16;
174 ddma_transfer(0, 1, &ide_reg_temp, extAddr, 2);
175
176 /* This is done like this in the archos firmware...
177 miuscfg = MIUSCFG;
178 miuscfg = (miuscfg & ~7) | 5;
179 MIUSCFG = miuscfg;
180 Though I'd expect MIUSCFG &= ~0x7; (1 cycle) */
181
182 return ide_reg_temp;
183}
184
185#endif 87#endif
186 88
187#ifndef NOINLINE_ATTR 89#ifndef NOINLINE_ATTR
@@ -349,16 +251,7 @@ static void copy_read_sectors(unsigned char* buf, int wordcount)
349 } while (++wbuf < wbufend); /* tail loop is faster */ 251 } while (++wbuf < wbufend); /* tail loop is faster */
350 } 252 }
351#else /* !PREFER_C_READING */ 253#else /* !PREFER_C_READING */
352#if CONFIG_CPU == TCC730 254#if defined(CPU_COLDFIRE)
353 int sectorcount = wordcount / 0x100;
354 do {
355 /* Slurp an entire sector with a single dma transfer */
356 ddma_transfer(0, 1, ide_sector_data, ATA_DATA_IDX << 16, SECTOR_SIZE);
357 memcpy(buf, ide_sector_data, SECTOR_SIZE);
358 buf += SECTOR_SIZE;
359 sectorcount--;
360 } while (sectorcount > 0);
361#elif defined(CPU_COLDFIRE)
362 unsigned char* bufend = buf + 2 * wordcount; 255 unsigned char* bufend = buf + 2 * wordcount;
363 /* coldfire asm reading, utilising line bursts */ 256 /* coldfire asm reading, utilising line bursts */
364 /* this assumes there is at least one full line to copy */ 257 /* this assumes there is at least one full line to copy */
@@ -1416,23 +1309,6 @@ int ata_hard_reset(void)
1416 /* state HRR1 */ 1309 /* state HRR1 */
1417 or_b(0x02, &PADRH); /* negate _RESET */ 1310 or_b(0x02, &PADRH); /* negate _RESET */
1418 sleep(1); /* > 2ms */ 1311 sleep(1); /* > 2ms */
1419#elif CONFIG_CPU == TCC730
1420
1421 P6 &= ~0x40;
1422 ddma_transfer(0, 1, ide_sector_data, 0xF00000, SECTOR_SIZE);
1423 P6 |= 0x40;
1424
1425 /*
1426 What can the following do?
1427 P1 |= 0x04;
1428 P10CON &= ~0x56;
1429 sleep(1);
1430
1431 P10CON |= 0x56;
1432 P10 &= ~0x56;
1433 P1 &= ~0x04;
1434 sleep(1);
1435 */
1436#endif 1312#endif
1437 1313
1438 /* state HRR2 */ 1314 /* state HRR2 */
@@ -1561,8 +1437,6 @@ void ata_enable(bool on)
1561 or_b(0x80, &PADRL); /* disable ATA */ 1437 or_b(0x80, &PADRL); /* disable ATA */
1562 1438
1563 or_b(0x80, &PAIORL); 1439 or_b(0x80, &PAIORL);
1564#elif CONFIG_CPU == TCC730
1565
1566#endif 1440#endif
1567} 1441}
1568#endif 1442#endif
@@ -1712,8 +1586,6 @@ int ata_init(void)
1712 int rc; 1586 int rc;
1713#ifdef TARGET_TREE 1587#ifdef TARGET_TREE
1714 bool coldstart = ata_is_coldstart(); 1588 bool coldstart = ata_is_coldstart();
1715#elif CONFIG_CPU == TCC730
1716 bool coldstart = (P1 & 0x80) == 0;
1717#else 1589#else
1718 bool coldstart = (PACR2 & 0x4000) != 0; 1590 bool coldstart = (PACR2 & 0x4000) != 0;
1719#endif 1591#endif
diff --git a/firmware/drivers/button.c b/firmware/drivers/button.c
index 561dc6ee14..01b9174dae 100644
--- a/firmware/drivers/button.c
+++ b/firmware/drivers/button.c
@@ -314,8 +314,6 @@ void button_init(void)
314 PAIOR &= ~0x0820; /* Inputs */ 314 PAIOR &= ~0x0820; /* Inputs */
315#elif CONFIG_KEYPAD == ONDIO_PAD 315#elif CONFIG_KEYPAD == ONDIO_PAD
316 /* nothing to initialize here */ 316 /* nothing to initialize here */
317#elif CONFIG_KEYPAD == GMINI100_PAD
318 /* nothing to initialize here */
319#endif /* CONFIG_KEYPAD */ 317#endif /* CONFIG_KEYPAD */
320 queue_init(&button_queue, true); 318 queue_init(&button_queue, true);
321 button_read(); 319 button_read();
@@ -599,38 +597,6 @@ static int button_read(void)
599 if(adc_read(ADC_BUTTON_ONOFF) < 0x120) /* active low */ 597 if(adc_read(ADC_BUTTON_ONOFF) < 0x120) /* active low */
600 btn |= BUTTON_OFF; 598 btn |= BUTTON_OFF;
601 599
602#elif CONFIG_KEYPAD == GMINI100_PAD
603 data = adc_read(7);
604 if (data < 0x38a)
605 {
606 if (data < 0x1c5)
607 if (data < 0xe3)
608 btn = BUTTON_LEFT;
609 else
610 btn = BUTTON_DOWN;
611 else
612 if (data < 0x2a2)
613 btn = BUTTON_RIGHT;
614 else
615 btn = BUTTON_UP;
616 }
617
618 data = adc_read(6);
619 if (data < 0x355)
620 {
621 if (data < 0x288)
622 if (data < 0x233)
623 btn |= BUTTON_OFF;
624 else
625 btn |= BUTTON_PLAY;
626 else
627 btn |= BUTTON_MENU;
628 }
629
630 data = P7;
631 if (data & 0x01)
632 btn |= BUTTON_ON;
633
634#endif /* CONFIG_KEYPAD */ 600#endif /* CONFIG_KEYPAD */
635 601
636#ifdef HAVE_LCD_BITMAP 602#ifdef HAVE_LCD_BITMAP
diff --git a/firmware/drivers/i2c.c b/firmware/drivers/i2c.c
index 2b439c23ad..83ac21fae8 100644
--- a/firmware/drivers/i2c.c
+++ b/firmware/drivers/i2c.c
@@ -24,26 +24,6 @@
24#include "system.h" 24#include "system.h"
25 25
26/* cute little functions, atomic read-modify-write */ 26/* cute little functions, atomic read-modify-write */
27#if CONFIG_I2C == I2C_GMINI
28
29/* This is done like this in the Archos' firmware.
30 * However, the TCC370 has an integrated I2C
31 * controller (bound to the same lines). It should be
32 * possible to use it and thus save some space in flash.
33 */
34#define SDA_LO (P3 &= ~0x20)
35#define SDA_HI (P3 |= 0x20)
36#define SDA_INPUT (P3CONH &= ~0x0C)
37#define SDA_OUTPUT (P3CONH |= 0x04)
38#define SDA (P3 & 0x20)
39
40#define SCL_LO (P3 &= ~0x10)
41#define SCL_HI (P3 |= 0x10)
42#define SCL_INPUT (P3CONH &= ~0x03)
43#define SCL_OUTPUT (P3CONH |= 0x01)
44#define SCL (P3 & 0x10)
45
46#else /* non Gmini below */
47 27
48/* SDA is PB7 */ 28/* SDA is PB7 */
49#define SDA_LO and_b(~0x80, &PBDRL) 29#define SDA_LO and_b(~0x80, &PBDRL)
@@ -67,7 +47,6 @@
67#define SCL_HI or_b(0x20, &PBDRH) 47#define SCL_HI or_b(0x20, &PBDRH)
68#define SCL (PBDRH & 0x20) 48#define SCL (PBDRH & 0x20)
69#endif 49#endif
70#endif /* ! I2C_GMINI */
71 50
72/* arbitrary delay loop */ 51/* arbitrary delay loop */
73#define DELAY do { int _x; for(_x=0;_x<20;_x++);} while (0) 52#define DELAY do { int _x; for(_x=0;_x<20;_x++);} while (0)
@@ -106,13 +85,10 @@ void i2c_init(void)
106{ 85{
107 int i; 86 int i;
108 87
109#if CONFIG_I2C == I2C_GMINI 88#if CONFIG_I2C == I2C_ONDIO
110 SCL_INPUT;
111 SDA_INPUT;
112#elif CONFIG_I2C == I2C_ONDIO
113 /* make PB6 & PB7 general I/O */ 89 /* make PB6 & PB7 general I/O */
114 PBCR2 &= ~0xf000; 90 PBCR2 &= ~0xf000;
115#else /* not Gmini, not Ondio */ 91#else /* not Ondio */
116 /* make PB7 & PB13 general I/O */ 92 /* make PB7 & PB13 general I/O */
117 PBCR1 &= ~0x0c00; /* PB13 */ 93 PBCR1 &= ~0x0c00; /* PB13 */
118 PBCR2 &= ~0xc000; /* PB7 */ 94 PBCR2 &= ~0xc000; /* PB7 */
diff --git a/firmware/drivers/lcd-recorder.c b/firmware/drivers/lcd-recorder.c
index ceeb413709..5c4a0352a7 100644
--- a/firmware/drivers/lcd-recorder.c
+++ b/firmware/drivers/lcd-recorder.c
@@ -108,35 +108,7 @@ static const char scroll_tick_table[16] = {
108 108
109/* optimised archos recorder code is in lcd.S */ 109/* optimised archos recorder code is in lcd.S */
110 110
111#if CONFIG_CPU == TCC730 111#if CONFIG_CPU == PNX0101
112/* Optimization opportunity:
113 In the following I do exactly as in the archos firmware.
114 There is probably a better way (ie. do only one mask operation)
115*/
116void lcd_write_command(int cmd) {
117 P2 &= 0xF7;
118 P2 &= 0xDF;
119 P2 &= 0xFB;
120 P0 = cmd;
121 P2 |= 0x04;
122 P2 |= 0x08;
123 P2 |= 0x20;
124}
125
126void lcd_write_data( const unsigned char* data, int count ) {
127 int i;
128 for (i=0; i < count; i++) {
129 P2 |= 0x08;
130 P2 &= 0xDF;
131 P2 &= 0xFB;
132 P0 = data[i];
133 P2 |= 0x04;
134 P2 |= 0x08;
135 P2 |= 0x20;
136 }
137}
138
139#elif CONFIG_CPU == PNX0101
140 112
141void lcd_write_command(int cmd) 113void lcd_write_command(int cmd)
142{ 114{
@@ -161,9 +133,7 @@ void lcd_write_data( const unsigned char* data, int count )
161 133
162int lcd_default_contrast(void) 134int lcd_default_contrast(void)
163{ 135{
164#if CONFIG_LCD == LCD_GMINI100 136#if CONFIG_LCD == LCD_IFP7XX
165 return 31;
166#elif CONFIG_LCD == LCD_IFP7XX
167 return 45; 137 return 45;
168#else 138#else
169 return (read_hw_mask() & LCD_CONTRAST_BIAS) ? 31 : 49; 139 return (read_hw_mask() & LCD_CONTRAST_BIAS) ? 31 : 49;
@@ -192,20 +162,6 @@ void lcd_set_flip(bool yesno)
192#else 162#else
193 if (yesno) 163 if (yesno)
194#endif 164#endif
195#if CONFIG_LCD == LCD_GMINI100
196 {
197 lcd_write_command(LCD_SET_SEGMENT_REMAP | 0x01);
198 lcd_write_command(LCD_SET_COM_OUTPUT_SCAN_DIRECTION | 0x08);
199 xoffset = 132 - LCD_WIDTH;
200 }
201 else
202 {
203 lcd_write_command(LCD_SET_SEGMENT_REMAP);
204 lcd_write_command(LCD_SET_COM_OUTPUT_SCAN_DIRECTION | 0x08);
205 xoffset = 0;
206 }
207#else
208
209 { 165 {
210 lcd_write_command(LCD_SET_SEGMENT_REMAP); 166 lcd_write_command(LCD_SET_SEGMENT_REMAP);
211 lcd_write_command(LCD_SET_COM_OUTPUT_SCAN_DIRECTION); 167 lcd_write_command(LCD_SET_COM_OUTPUT_SCAN_DIRECTION);
@@ -221,7 +177,6 @@ void lcd_set_flip(bool yesno)
221 xoffset = 0; 177 xoffset = 0;
222#endif 178#endif
223 } 179 }
224#endif
225} 180}
226 181
227#endif /* !SIMULATOR */ 182#endif /* !SIMULATOR */
@@ -238,15 +193,7 @@ void lcd_init(void)
238 193
239void lcd_init(void) 194void lcd_init(void)
240{ 195{
241#if CONFIG_CPU == TCC730 196#if CONFIG_CPU == PNX0101
242 /* Initialise P0 & some P2 output pins:
243 P0 -> all pins normal cmos output
244 P2 -> pins 1 to 5 normal cmos output. */
245 P0CON = 0xff;
246 P2CONL |= 0x5a;
247 P2CONL &= 0x5b;
248 P2CONH |= 1;
249#elif CONFIG_CPU == PNX0101
250 LCDREG10 = 0xf; 197 LCDREG10 = 0xf;
251 LCDREG04 = 0x4084; 198 LCDREG04 = 0x4084;
252#else 199#else
diff --git a/firmware/drivers/led.c b/firmware/drivers/led.c
index 118911a746..a9be9399c8 100644
--- a/firmware/drivers/led.c
+++ b/firmware/drivers/led.c
@@ -28,11 +28,6 @@
28void led(bool on) 28void led(bool on)
29{ 29{
30 if ( on ) 30 if ( on )
31#ifdef GMINI_ARCH
32 P2 |= 1;
33 else
34 P2 &= ~1;
35#else
36 { 31 {
37 or_b(0x40, &PBDRL); 32 or_b(0x40, &PBDRL);
38 } 33 }
@@ -40,7 +35,6 @@ void led(bool on)
40 { 35 {
41 and_b(~0x40, &PBDRL); 36 and_b(~0x40, &PBDRL);
42 } 37 }
43#endif
44} 38}
45 39
46#elif (CONFIG_LED == LED_VIRTUAL) || defined(HAVE_REMOTE_LCD) 40#elif (CONFIG_LED == LED_VIRTUAL) || defined(HAVE_REMOTE_LCD)
diff --git a/firmware/drivers/power.c b/firmware/drivers/power.c
index e0a5de4bfb..872e8b0657 100644
--- a/firmware/drivers/power.c
+++ b/firmware/drivers/power.c
@@ -86,9 +86,7 @@ void power_init(void)
86#ifdef CONFIG_CHARGING 86#ifdef CONFIG_CHARGING
87bool charger_inserted(void) 87bool charger_inserted(void)
88{ 88{
89#if defined(GMINI_ARCH) 89#if CONFIG_CHARGING == CHARGING_CONTROL
90 return (P7 & 0x80) == 0;
91#elif CONFIG_CHARGING == CHARGING_CONTROL
92 /* Recorder */ 90 /* Recorder */
93 return adc_read(ADC_EXT_POWER) > 0x100; 91 return adc_read(ADC_EXT_POWER) > 0x100;
94#elif defined (HAVE_FMADC) 92#elif defined (HAVE_FMADC)
@@ -139,12 +137,7 @@ void ide_power_enable(bool on)
139{ 137{
140 (void)on; 138 (void)on;
141 139
142#if defined(GMINI_ARCH) 140#if defined(TOSHIBA_GIGABEAT_F)
143 if(on)
144 P1 |= 0x08;
145 else
146 P1 &= ~0x08;
147#elif defined(TOSHIBA_GIGABEAT_F)
148 /* Gigabeat TODO */ 141 /* Gigabeat TODO */
149#else /* SH1 based archos */ 142#else /* SH1 based archos */
150 bool touched = false; 143 bool touched = false;
@@ -189,9 +182,7 @@ void ide_power_enable(bool on)
189 182
190bool ide_powered(void) 183bool ide_powered(void)
191{ 184{
192#if defined(GMINI_ARCH) 185#if defined(TOSHIBA_GIGABEAT_F)
193 return (P1 & 0x08?true:false);
194#elif defined(TOSHIBA_GIGABEAT_F)
195 return false; 186 return false;
196#else /* SH1 based archos */ 187#else /* SH1 based archos */
197#if defined(NEEDS_ATA_POWER_ON) || defined(HAVE_ATA_POWER_OFF) 188#if defined(NEEDS_ATA_POWER_ON) || defined(HAVE_ATA_POWER_OFF)
@@ -220,10 +211,7 @@ bool ide_powered(void)
220void power_off(void) 211void power_off(void)
221{ 212{
222 set_irq_level(HIGHEST_IRQ_LEVEL); 213 set_irq_level(HIGHEST_IRQ_LEVEL);
223#if defined(GMINI_ARCH) 214#if defined(TOSHIBA_GIGABEAT_F)
224 P1 &= ~1;
225 P1CON &= ~1;
226#elif defined(TOSHIBA_GIGABEAT_F)
227 /* FIXME: Can we turn the device off, or only enter sleep mode? */ 215 /* FIXME: Can we turn the device off, or only enter sleep mode? */
228#else 216#else
229#ifdef HAVE_POWEROFF_ON_PBDR 217#ifdef HAVE_POWEROFF_ON_PBDR
diff --git a/firmware/drivers/serial.c b/firmware/drivers/serial.c
index 5120161467..866d7616ed 100644
--- a/firmware/drivers/serial.c
+++ b/firmware/drivers/serial.c
@@ -30,7 +30,7 @@
30 30
31#if CONFIG_CPU == SH7034 31#if CONFIG_CPU == SH7034
32 32
33/* FIX: this doesn't work on iRiver or Gmini or iPod yet */ 33/* FIX: this doesn't work on iRiver or iPod yet */
34/* iFP7xx has no remote */ 34/* iFP7xx has no remote */
35 35
36#ifndef HAVE_MMC /* MMC takes serial port 1, so don't mess with it */ 36#ifndef HAVE_MMC /* MMC takes serial port 1, so don't mess with it */
@@ -172,4 +172,4 @@ void serial_setup (void)
172{ 172{
173 /* a dummy */ 173 /* a dummy */
174} 174}
175#endif /* ! (CONFIG_CPU != MCF5249) && (CONFIG_CPU != TCC730) */ 175#endif
diff --git a/firmware/export/button.h b/firmware/export/button.h
index 240ec08d9b..9c0fe639a6 100644
--- a/firmware/export/button.h
+++ b/firmware/export/button.h
@@ -151,27 +151,6 @@ void wheel_send_events(bool send);
151 151
152#define BUTTON_REMOTE 0 152#define BUTTON_REMOTE 0
153 153
154#elif CONFIG_KEYPAD == GMINI100_PAD
155
156 /* Gmini specific button codes */
157
158#define BUTTON_ON 0x00000001
159#define BUTTON_OFF 0x00000002
160
161#define BUTTON_LEFT 0x00000004
162#define BUTTON_RIGHT 0x00000008
163#define BUTTON_UP 0x00000010
164#define BUTTON_DOWN 0x00000020
165
166#define BUTTON_PLAY 0x00000040
167#define BUTTON_MENU 0x00000080
168
169#define BUTTON_MAIN (BUTTON_ON|BUTTON_OFF|BUTTON_LEFT|BUTTON_RIGHT\
170 |BUTTON_UP|BUTTON_DOWN|BUTTON_PLAY|BUTTON_MENU)
171
172#define BUTTON_REMOTE 0
173
174
175#elif 0 154#elif 0
176 155
177/* 156/*
@@ -186,7 +165,7 @@ void wheel_send_events(bool send);
186 165
187 166
188 167
189#endif /* RECORDER/PLAYER/ONDIO/GMINI KEYPAD */ 168#endif /* RECORDER/PLAYER/ONDIO KEYPAD */
190 169
191#endif /* TARGET_TREE */ 170#endif /* TARGET_TREE */
192 171
diff --git a/firmware/export/config-gmini120.h b/firmware/export/config-gmini120.h
deleted file mode 100644
index a393b17a8a..0000000000
--- a/firmware/export/config-gmini120.h
+++ /dev/null
@@ -1,86 +0,0 @@
1/* Note: this is just a basic early version that needs attention and
2 corrections! */
3
4/* define this if you have recording possibility */
5#define HAVE_RECORDING 1
6
7/* define this if you have a bitmap LCD display */
8#define HAVE_LCD_BITMAP 1
9
10/* define this if you can invert the colours on your LCD */
11#define HAVE_LCD_INVERT
12
13/* define this if you have a real-time clock */
14#define CONFIG_RTC RTC_M41ST84W
15
16/* define this if you have RTC RAM available for settings */
17#define HAVE_RTC_RAM 1
18
19/* define this if you would like tagcache to build on this target */
20#define HAVE_TAGCACHE
21
22/* LCD dimensions */
23#define LCD_WIDTH 128
24#define LCD_HEIGHT 64
25#define LCD_DEPTH 1
26
27#define CONFIG_KEYPAD GMINI100_PAD
28
29/* Define this if you have a software controlled poweroff */
30#define HAVE_SW_POWEROFF
31
32/* The number of bytes reserved for loadable codecs. Although in this case
33 the codec won't be loadable... */
34#define CODEC_SIZE 0x40000
35
36/* The number of bytes reserved for loadable plugins */
37#define PLUGIN_BUFFER_SIZE 0x80000
38
39#define BATTERY_CAPACITY_DEFAULT 2200 /* default battery capacity */
40
41#ifndef SIMULATOR
42
43/* Define this if you have a TCC730 (CalmRISC16) */
44#define CONFIG_CPU TCC730
45
46/* Define this if you have a gmini 100 style LCD */
47#define CONFIG_LCD LCD_GMINI100
48
49#define CONFIG_I2C I2C_GMINI
50
51/* Define this if you do software codec */
52#define CONFIG_CODEC SWCODEC
53
54/* Type of mobile power, FIXME: probably different, make new type */
55#define CONFIG_BATTERY BATT_LIION2200
56#define BATTERY_CAPACITY_MIN 2200 /* min. capacity selectable */
57#define BATTERY_CAPACITY_MAX 3200 /* max. capacity selectable */
58#define BATTERY_CAPACITY_INC 50 /* capacity increment */
59#define BATTERY_TYPES_COUNT 1 /* only one type */
60#define BATTERY_SCALE_FACTOR 6465
61/* chosen values at random -- jyp */
62
63/* Hardware controlled charging? FIXME */
64#define CONFIG_CHARGING CHARGING_SIMPLE
65
66#define CPU_FREQ 30000000
67/* approximate value (and false in general since freq is variable) */
68
69/* Always enable debug till we stabilize */
70#define EMULATOR
71
72#define USB_GMINISTYLE
73
74#define CONFIG_I2C I2C_GMINI
75
76#define CONFIG_BACKLIGHT BL_GMINI
77
78#define GMINI_ARCH
79
80/* Software controlled LED */
81#define CONFIG_LED LED_REAL
82
83/* Define this if you have adjustable CPU frequency */
84#define HAVE_ADJUSTABLE_CPU_FREQ
85
86#endif
diff --git a/firmware/export/config-gminisp.h b/firmware/export/config-gminisp.h
deleted file mode 100644
index 1c1f299afa..0000000000
--- a/firmware/export/config-gminisp.h
+++ /dev/null
@@ -1,77 +0,0 @@
1/* Note: this is just a basic early version that needs attention and
2 corrections! */
3
4/* define this if you have a bitmap LCD display */
5#define HAVE_LCD_BITMAP 1
6
7/* define this if you can invert the colours on your LCD */
8#define HAVE_LCD_INVERT
9
10/* define this if you would like tagcache to build on this target */
11#define HAVE_TAGCACHE
12
13/* LCD dimensions */
14#define LCD_WIDTH 128
15#define LCD_HEIGHT 64
16#define LCD_DEPTH 1
17
18#define CONFIG_KEYPAD GMINI100_PAD
19
20/* Define this if you have a software controlled poweroff */
21#define HAVE_SW_POWEROFF
22
23/* The number of bytes reserved for loadable codecs. Although in this case
24 the codec won't be loadable... */
25#define CODEC_SIZE 0x40000
26
27/* The number of bytes reserved for loadable plugins */
28#define PLUGIN_BUFFER_SIZE 0x80000
29
30#define BATTERY_CAPACITY_DEFAULT 2200 /* default battery capacity */
31
32#ifndef SIMULATOR
33
34/* Define this if you have a TCC730 (CalmRISC16) */
35#define CONFIG_CPU TCC730
36
37/* Define this if you have a gmini 100 style LCD */
38#define CONFIG_LCD LCD_GMINI100
39
40#define CONFIG_I2C I2C_GMINI
41
42/* Define this if you do software codec */
43#define CONFIG_CODEC SWCODEC
44
45/* Type of mobile power, FIXME: probably different, make new type */
46#define CONFIG_BATTERY BATT_LIION2200
47#define BATTERY_CAPACITY_MIN 2200 /* min. capacity selectable */
48#define BATTERY_CAPACITY_MAX 3200 /* max. capacity selectable */
49#define BATTERY_CAPACITY_INC 50 /* capacity increment */
50#define BATTERY_TYPES_COUNT 1 /* only one type */
51#define BATTERY_SCALE_FACTOR 6465
52/* chosen values at random -- jyp */
53
54/* Hardware controlled charging? FIXME */
55#define CONFIG_CHARGING CHARGING_SIMPLE
56
57#define CPU_FREQ 30000000
58/* approximate value (and false in general since freq is variable) */
59
60/* Always enable debug till we stabilize */
61#define EMULATOR
62
63#define USB_GMINISTYLE
64
65#define CONFIG_I2C I2C_GMINI
66
67#define CONFIG_BACKLIGHT BL_GMINI
68
69#define GMINI_ARCH
70
71/* Software controlled LED */
72#define CONFIG_LED LED_REAL
73
74/* Define this if you have adjustable CPU frequency */
75#define HAVE_ADJUSTABLE_CPU_FREQ
76
77#endif
diff --git a/firmware/export/config.h b/firmware/export/config.h
index 45d974a96f..440c0faef3 100644
--- a/firmware/export/config.h
+++ b/firmware/export/config.h
@@ -40,7 +40,6 @@
40#define SH7034 7034 40#define SH7034 7034
41#define MCF5249 5249 41#define MCF5249 5249
42#define MCF5250 5250 42#define MCF5250 5250
43#define TCC730 730 /* lacking a proper abbrivation */
44#define PP5002 5002 43#define PP5002 5002
45#define PP5020 5020 44#define PP5020 5020
46#define PNX0101 101 45#define PNX0101 101
@@ -48,11 +47,10 @@
48#define PP5024 5024 47#define PP5024 5024
49 48
50/* CONFIG_KEYPAD */ 49/* CONFIG_KEYPAD */
51#define PLAYER_PAD 0 50#define PLAYER_PAD 1
52#define RECORDER_PAD 1 51#define RECORDER_PAD 2
53#define ONDIO_PAD 2 52#define ONDIO_PAD 3
54#define IRIVER_H100_PAD 3 53#define IRIVER_H100_PAD 4
55#define GMINI100_PAD 4
56#define IRIVER_H300_PAD 5 54#define IRIVER_H300_PAD 5
57#define IAUDIO_X5_PAD 6 55#define IAUDIO_X5_PAD 6
58#define IPOD_4G_PAD 7 56#define IPOD_4G_PAD 7
@@ -83,7 +81,6 @@
83#define CHARGING_CONTROL 3 /* Software controlled charging */ 81#define CHARGING_CONTROL 3 /* Software controlled charging */
84 82
85/* CONFIG_LCD */ 83/* CONFIG_LCD */
86#define LCD_GMINI100 0
87#define LCD_SSD1815 1 /* as used by Archos Recorders and Ondios */ 84#define LCD_SSD1815 1 /* as used by Archos Recorders and Ondios */
88#define LCD_SSD1801 2 /* as used by Archos Player/Studio */ 85#define LCD_SSD1801 2 /* as used by Archos Player/Studio */
89#define LCD_S1D15E06 3 /* as used by iRiver H100 series */ 86#define LCD_S1D15E06 3 /* as used by iRiver H100 series */
@@ -111,11 +108,10 @@
111#define RGB565SWAPPED 3553 108#define RGB565SWAPPED 3553
112 109
113/* CONFIG_BACKLIGHT */ 110/* CONFIG_BACKLIGHT */
114#define BL_PA14_LO 0 /* Player, PA14 low active */ 111#define BL_PA14_LO 1 /* Player, PA14 low active */
115#define BL_RTC 1 /* Recorder, RTC square wave output */ 112#define BL_RTC 2 /* Recorder, RTC square wave output */
116#define BL_PA14_HI 2 /* Ondio, PA14 high active */ 113#define BL_PA14_HI 3 /* Ondio, PA14 high active */
117#define BL_IRIVER_H100 3 /* IRiver GPIO */ 114#define BL_IRIVER_H100 4 /* IRiver GPIO */
118#define BL_GMINI 4 /* Archos GMini */
119#define BL_IPOD4G 5 /* Apple iPod 4G */ 115#define BL_IPOD4G 5 /* Apple iPod 4G */
120#define BL_IPODNANO 6 /* Apple iPod Nano and iPod Video*/ 116#define BL_IPODNANO 6 /* Apple iPod Nano and iPod Video*/
121#define BL_IPOD3G 7 /* Apple iPod 3g with dock */ 117#define BL_IPOD3G 7 /* Apple iPod 3g with dock */
@@ -129,9 +125,8 @@
129#define BL_TPJ1022 15 /* Tatung Elio TPJ-1022 */ 125#define BL_TPJ1022 15 /* Tatung Elio TPJ-1022 */
130 126
131/* CONFIG_I2C */ 127/* CONFIG_I2C */
132#define I2C_PLAYREC 0 /* Archos Player/Recorder style */ 128#define I2C_PLAYREC 1 /* Archos Player/Recorder style */
133#define I2C_ONDIO 1 /* Ondio style */ 129#define I2C_ONDIO 2 /* Ondio style */
134#define I2C_GMINI 2 /* Gmini style */
135#define I2C_COLDFIRE 3 /* Coldfire style */ 130#define I2C_COLDFIRE 3 /* Coldfire style */
136#define I2C_PP5002 4 /* PP5002 style */ 131#define I2C_PP5002 4 /* PP5002 style */
137#define I2C_PP5020 5 /* PP5020 style */ 132#define I2C_PP5020 5 /* PP5020 style */
@@ -139,7 +134,7 @@
139#define I2C_S3C2440 7 134#define I2C_S3C2440 7
140 135
141/* CONFIG_LED */ 136/* CONFIG_LED */
142#define LED_REAL 1 /* SW controlled LED (Archos recorders, player, Gmini) */ 137#define LED_REAL 1 /* SW controlled LED (Archos recorders, player) */
143#define LED_VIRTUAL 2 /* Virtual LED (icon) (Archos Ondio) */ 138#define LED_VIRTUAL 2 /* Virtual LED (icon) (Archos Ondio) */
144/* else HW controlled LED (iRiver H1x0) */ 139/* else HW controlled LED (iRiver H1x0) */
145 140
@@ -180,10 +175,6 @@
180#include "config-h120.h" 175#include "config-h120.h"
181#elif defined(IRIVER_H300) 176#elif defined(IRIVER_H300)
182#include "config-h300.h" 177#include "config-h300.h"
183#elif defined(ARCHOS_GMINI120)
184#include "config-gmini120.h"
185#elif defined(ARCHOS_GMINISP)
186#include "config-gminisp.h"
187#elif defined(IAUDIO_X5) 178#elif defined(IAUDIO_X5)
188#include "config-iaudiox5.h" 179#include "config-iaudiox5.h"
189#elif defined(IPOD_COLOR) 180#elif defined(IPOD_COLOR)
@@ -286,7 +277,6 @@
286 defined(CPU_COLDFIRE) || /* Coldfire: core, plugins, codecs */ \ 277 defined(CPU_COLDFIRE) || /* Coldfire: core, plugins, codecs */ \
287 (CONFIG_CPU == PP5020) || /* iPod and H10: core, plugins, codecs */ \ 278 (CONFIG_CPU == PP5020) || /* iPod and H10: core, plugins, codecs */ \
288 (CONFIG_CPU == PP5002) || /* iPod: core, plugins, codecs */ \ 279 (CONFIG_CPU == PP5002) || /* iPod: core, plugins, codecs */ \
289 (CONFIG_CPU == TCC730) || /* CalmRISC16: core, (plugins, codecs) */ \
290 (CONFIG_CPU == PNX0101)) 280 (CONFIG_CPU == PNX0101))
291#define ICODE_ATTR __attribute__ ((section(".icode"))) 281#define ICODE_ATTR __attribute__ ((section(".icode")))
292#define ICONST_ATTR __attribute__ ((section(".irodata"))) 282#define ICONST_ATTR __attribute__ ((section(".irodata")))
diff --git a/firmware/export/cpu.h b/firmware/export/cpu.h
index 93b66aac52..6adf52ba5e 100644
--- a/firmware/export/cpu.h
+++ b/firmware/export/cpu.h
@@ -27,9 +27,6 @@
27#if CONFIG_CPU == MCF5250 27#if CONFIG_CPU == MCF5250
28#include "mcf5250.h" 28#include "mcf5250.h"
29#endif 29#endif
30#if CONFIG_CPU == TCC730
31#include "tcc730.h"
32#endif
33#if CONFIG_CPU == PP5020 30#if CONFIG_CPU == PP5020
34#include "pp5020.h" 31#include "pp5020.h"
35#endif 32#endif
diff --git a/firmware/export/system.h b/firmware/export/system.h
index 9b90a6e80c..3ec599d62b 100644
--- a/firmware/export/system.h
+++ b/firmware/export/system.h
@@ -371,72 +371,6 @@ void irq_set_int_handler(int n, interrupt_handler_t handler);
371void irq_enable_int(int n); 371void irq_enable_int(int n);
372#endif 372#endif
373 373
374#elif CONFIG_CPU == TCC730
375
376extern int smsc_version(void);
377
378extern void smsc_delay(void);
379
380extern void set_pll_freq(int pll_index, long freq_out);
381
382
383extern void* volatile interrupt_vector[16] __attribute__ ((section(".idata")));
384
385extern void ddma_transfer(int dir, int mem, void* intAddr, long extAddr,
386 int num);
387
388
389#define HIGHEST_IRQ_LEVEL (1)
390static inline int set_irq_level(int level)
391{
392 int result;
393 __asm__ ("ld %0, 0\n\t"
394 "tstsr ie\n\t"
395 "incc %0" : "=r"(result));
396 if (level > 0)
397 __asm__ volatile ("clrsr ie");
398 else
399 __asm__ volatile ("setsr ie");
400
401 return result;
402}
403
404static inline unsigned short swap16(unsigned short value)
405 /*
406 result[15..8] = value[ 7..0];
407 result[ 7..0] = value[15..8];
408 */
409{
410 return (value >> 8) | (value << 8);
411}
412
413static inline unsigned long swap32(unsigned long value)
414 /*
415 result[31..24] = value[ 7.. 0];
416 result[23..16] = value[15.. 8];
417 result[15.. 8] = value[23..16];
418 result[ 7.. 0] = value[31..24];
419 */
420{
421 unsigned long hi = swap16(value >> 16);
422 unsigned long lo = swap16(value & 0xffff);
423 return (lo << 16) | hi;
424}
425
426/* Archos uses:
427
42822MHz: busy wait on dma
42932MHz: normal
43080Mhz: heavy load
431
432*/
433
434#define CPUFREQ_DEFAULT CPU_FREQ
435#define CPUFREQ_NORMAL (32000000)
436#define CPUFREQ_MAX (80000000)
437
438#define invalidate_icache()
439
440#endif 374#endif
441 375
442#ifndef CPU_COLDFIRE 376#ifndef CPU_COLDFIRE
diff --git a/firmware/export/tcc730.h b/firmware/export/tcc730.h
deleted file mode 100644
index c1208ecc28..0000000000
--- a/firmware/export/tcc730.h
+++ /dev/null
@@ -1,107 +0,0 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2005 by Jean-Philippe Bernardy
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#ifndef TCC730_H
21#define TCC730_H
22
23/* int is 16 bit
24 long is 32 bit */
25
26#define IOBASE (0x3f0000)
27#define MMIO(t, x) (*(volatile t*)(IOBASE+(x)))
28
29#define OSCCON MMIO(unsigned char, 0x01)
30#define WTCON MMIO(unsigned char, 0x02)
31#define BTCON MMIO(unsigned char, 0x04)
32#define BTCNT MMIO(unsigned char, 0x05)
33#define WDTEN MMIO(unsigned char, 0x06)
34#define WDTCON MMIO(unsigned char, 0x07)
35
36#define TACON MMIO(unsigned char, 0x08)
37#define TAPRE MMIO(unsigned char, 0x09)
38#define TADATA MMIO(unsigned int, 0x0A)
39#define TACNT MMIO(unsigned int, 0x0C)
40
41#define IMR0 MMIO(unsigned int, 0x22)
42#define IMR1 MMIO(unsigned int, 0x2A)
43
44#define P0 MMIO(unsigned char, 0x30)
45#define P1 MMIO(unsigned char, 0x31)
46#define P2 MMIO(unsigned char, 0x32)
47#define P3 MMIO(unsigned char, 0x33)
48#define P4 MMIO(unsigned char, 0x34)
49#define P5 MMIO(unsigned char, 0x35)
50#define P6 MMIO(unsigned char, 0x36)
51#define P7 MMIO(unsigned char, 0x37)
52#define P8 MMIO(unsigned char, 0x38)
53#define P9 MMIO(unsigned char, 0x39)
54#define P10 MMIO(unsigned char, 0x3A)
55
56#define P0CON MMIO(unsigned char,0x40)
57#define P1CON MMIO(unsigned char,0x41)
58#define P2CON MMIO(unsigned int,0x42)
59#define P2CONH MMIO(unsigned char,0x42)
60#define P2CONL MMIO(unsigned char,0x43)
61#define P3CON MMIO(unsigned int,0x44)
62#define P3CONH MMIO(unsigned char,0x44)
63#define P3CONL MMIO(unsigned char,0x45)
64#define P3PUR MMIO(unsigned char,0x46)
65#define P5CON MMIO(unsigned char,0x48)
66#define P5PUR MMIO(unsigned char,0x49)
67#define P5INTMOD MMIO(unsigned int,0x4A)
68#define P5INTCON MMIO(unsigned char,0x4C)
69#define P4CON MMIO(unsigned char,0x50)
70#define P4INTCON MMIO(unsigned char,0x51)
71#define P4INTMOD MMIO(unsigned char,0x52)
72#define P6CON MMIO(unsigned char,0x53)
73#define P7CON MMIO(unsigned char,0x54)
74#define P8CON MMIO(unsigned char,0x55)
75#define P9CON MMIO(unsigned char,0x56)
76#define P10CON MMIO(unsigned char,0x57)
77
78#define IISCON0 MMIO(unsigned char, 0x0a0)
79#define IISMODE0 MMIO(unsigned char, 0x0a1)
80#define IISPTR0 MMIO(unsigned char, 0x0a2)
81#define IISCON1 MMIO(unsigned char, 0x0a3)
82#define IISMODE1 MMIO(unsigned char, 0x0a4)
83#define IISPTR1 MMIO(unsigned char, 0x0a5)
84
85#define ADDATA MMIO(unsigned int, 0x74)
86#define ADCON MMIO(unsigned char, 0x76)
87
88#define PLL0DATA MMIO(unsigned int, 0xA8)
89#define PLL0CON MMIO(unsigned char, 0xAA)
90#define PLL1DATA MMIO(unsigned int, 0xAC)
91#define PLL1CON MMIO(unsigned char, 0xAE)
92
93#define IISBUF ((volatile unsigned int*)(IOBASE+(0x0c0)))
94
95#define MIUSCFG MMIO(unsigned char, 0x110)
96#define MIUDCOM MMIO(unsigned char, 0x111)
97#define MIUDCFG MMIO(unsigned int, 0x112)
98#define MIUDCNT MMIO(unsigned int, 0x114)
99
100#define DDMACOM MMIO(unsigned char, 0x120)
101#define DDMACFG MMIO(unsigned char, 0x121)
102#define DDMAIADR MMIO(unsigned long, 0x122)
103#define DDMAEADR MMIO(unsigned long, 0x126)
104#define DDMANUM MMIO(unsigned int, 0x12A)
105#define DDMACNT MMIO(unsigned int, 0x12C)
106
107#endif
diff --git a/firmware/export/thread.h b/firmware/export/thread.h
index 72c692ec3b..8bb9ae2608 100644
--- a/firmware/export/thread.h
+++ b/firmware/export/thread.h
@@ -74,13 +74,6 @@ struct regs
74 unsigned int lr; /* r14 (lr) */ 74 unsigned int lr; /* r14 (lr) */
75 void *start; /* Thread start address, or NULL when started */ 75 void *start; /* Thread start address, or NULL when started */
76}; 76};
77# elif CONFIG_CPU == TCC730
78struct regs
79{
80 void *sp; /* Stack pointer (a15) */
81 void *start; /* Thread start address */
82 int started; /* 0 when not started */
83};
84# endif 77# endif
85 78
86#endif /* !SIMULATOR */ 79#endif /* !SIMULATOR */
diff --git a/firmware/hwcompat.c b/firmware/hwcompat.c
index fc2110d949..756491c79d 100644
--- a/firmware/hwcompat.c
+++ b/firmware/hwcompat.c
@@ -22,18 +22,14 @@
22 22
23int read_rom_version(void) 23int read_rom_version(void)
24{ 24{
25#ifdef GMINI_ARCH
26 int ver = 0;
27#else
28 int ver = *(short *)0x020000fe; 25 int ver = *(short *)0x020000fe;
29#endif
30 26
31 return ver; 27 return ver;
32} 28}
33 29
34int read_hw_mask(void) 30int read_hw_mask(void)
35{ 31{
36#if defined(ARCHOS_PLAYER) || defined(GMINI_ARCH) 32#ifdef ARCHOS_PLAYER
37 int mask = 0; /* Fake value for simplicity */ 33 int mask = 0; /* Fake value for simplicity */
38#else 34#else
39 int mask = *(short *)0x020000fc; 35 int mask = *(short *)0x020000fc;
diff --git a/firmware/kernel.c b/firmware/kernel.c
index b18b92327b..959122ea0a 100644
--- a/firmware/kernel.c
+++ b/firmware/kernel.c
@@ -314,63 +314,6 @@ void TIMER0(void)
314 TER0 = 0xff; /* Clear all events */ 314 TER0 = 0xff; /* Clear all events */
315} 315}
316 316
317#elif CONFIG_CPU == TCC730
318
319void TIMER0(void)
320{
321 int i;
322
323 /* Keep alive (?)
324 * If this is not done, power goes down when DC is unplugged.
325 */
326 if (current_tick % 2 == 0)
327 P8 |= 1;
328 else
329 P8 &= ~1;
330
331 /* Run through the list of tick tasks */
332 for(i = 0;i < MAX_NUM_TICK_TASKS;i++)
333 {
334 if(tick_funcs[i])
335 {
336 tick_funcs[i]();
337 }
338 }
339
340 current_tick++;
341
342 /* re-enable timer by clearing the counter */
343 TACON |= 0x80;
344}
345
346void tick_start(unsigned int interval_in_ms)
347{
348 long count;
349 count = (long)FREQ * (long)interval_in_ms / 1000 / 16;
350
351 if(count > 0xffffL)
352 {
353 panicf("Error! The tick interval is too long (%dms->%lx)\n",
354 interval_in_ms, count);
355 return;
356 }
357
358 /* Use timer A */
359 TAPRE = 0x0;
360 TADATA = count;
361
362 TACON = 0x89;
363 /* counter clear; */
364 /* interval mode; */
365 /* TICS = F(osc) / 16 */
366 /* TCS = internal clock */
367 /* enable */
368
369 /* enable the interrupt */
370 interrupt_vector[2] = TIMER0;
371 IMR0 |= (1<<2);
372}
373
374#elif defined(CPU_PP) 317#elif defined(CPU_PP)
375 318
376#ifndef BOOTLOADER 319#ifndef BOOTLOADER
diff --git a/firmware/rolo.c b/firmware/rolo.c
index e977f7489f..846cebff6f 100644
--- a/firmware/rolo.c
+++ b/firmware/rolo.c
@@ -30,10 +30,10 @@
30#include "string.h" 30#include "string.h"
31#include "buffer.h" 31#include "buffer.h"
32 32
33#if (CONFIG_CPU != TCC730) && !defined(IRIVER_IFP7XX_SERIES) && \ 33#if !defined(IRIVER_IFP7XX_SERIES) && \
34 (CONFIG_CPU != PP5002) && !defined(IRIVER_H10) && \ 34 (CONFIG_CPU != PP5002) && !defined(IRIVER_H10) && \
35 !defined(IRIVER_H10_5GB) && (CONFIG_CPU != S3C2440) 35 !defined(IRIVER_H10_5GB) && (CONFIG_CPU != S3C2440)
36/* FIX: this doesn't work on Gmini, iFP, 3rd Gen ipods, or H10 yet */ 36/* FIX: this doesn't work on iFP, 3rd Gen ipods, or H10 yet */
37 37
38#define IRQ0_EDGE_TRIGGER 0x80 38#define IRQ0_EDGE_TRIGGER 0x80
39 39
@@ -243,7 +243,7 @@ int rolo_load(const char* filename)
243 243
244 return 0; /* this is never reached */ 244 return 0; /* this is never reached */
245} 245}
246#else /* (CONFIG_CPU != TCC730) && !defined(IRIVER_IFP7XX_SERIES) */ 246#else /* !defined(IRIVER_IFP7XX_SERIES) */
247int rolo_load(const char* filename) 247int rolo_load(const char* filename)
248{ 248{
249 /* dummy */ 249 /* dummy */
@@ -251,4 +251,4 @@ int rolo_load(const char* filename)
251 return 0; 251 return 0;
252} 252}
253 253
254#endif /* (CONFIG_CPU != TCC730) && !defined(IRIVER_IFP7XX_SERIES) */ 254#endif /* !defined(IRIVER_IFP7XX_SERIES) */
diff --git a/firmware/system.c b/firmware/system.c
index 207a14727f..102ace6273 100644
--- a/firmware/system.c
+++ b/firmware/system.c
@@ -152,243 +152,7 @@ bool detect_flashed_rockbox(void)
152#endif /* HAVE_FLASHED_ROCKBOX */ 152#endif /* HAVE_FLASHED_ROCKBOX */
153} 153}
154 154
155#if CONFIG_CPU == TCC730 155#if CONFIG_CPU == SH7034
156
157void* volatile interrupt_vector[16] __attribute__ ((section(".idata")));
158
159static void ddma_wait_idle(void) __attribute__ ((section (".icode")));
160static void ddma_wait_idle(void)
161{
162 /* TODO: power saving trick: set the CPU freq to 22MHz
163 while doing the busy wait after a disk dma access.
164 (Used by Archos) */
165 do {
166 } while ((DDMACOM & 3) != 0);
167}
168
169void ddma_transfer(int dir, int mem, void* intAddr, long extAddr, int num)
170 __attribute__ ((section (".icode")));
171void ddma_transfer(int dir, int mem, void* intAddr, long extAddr, int num) {
172 int irq = set_irq_level(1);
173 ddma_wait_idle();
174 long externalAddress = (long) extAddr;
175 long internalAddress = ((long) intAddr) & 0xFFFF;
176 /* HW wants those two in word units. */
177 num /= 2;
178 externalAddress /= 2;
179
180 DDMACFG = (dir << 1) | (mem << 2);
181 DDMAIADR = internalAddress;
182 DDMAEADR = externalAddress;
183 DDMANUM = num;
184 DDMACOM |= 0x4; /* start */
185
186 ddma_wait_idle(); /* wait for completion */
187 set_irq_level(irq);
188}
189
190static void ddma_wait_idle_noicode(void)
191{
192 do {
193 } while ((DDMACOM & 3) != 0);
194}
195
196static void ddma_transfer_noicode(int dir, int mem, long intAddr, long extAddr, int num) {
197 int irq = set_irq_level(1);
198 ddma_wait_idle_noicode();
199 long externalAddress = (long) extAddr;
200 long internalAddress = (long) intAddr;
201 /* HW wants those two in word units. */
202 num /= 2;
203 externalAddress /= 2;
204
205 DDMACFG = (dir << 1) | (mem << 2);
206 DDMAIADR = internalAddress;
207 DDMAEADR = externalAddress;
208 DDMANUM = num;
209 DDMACOM |= 0x4; /* start */
210
211 ddma_wait_idle_noicode(); /* wait for completion */
212 set_irq_level(irq);
213}
214
215/* Some linker-defined symbols */
216extern int icodecopy;
217extern int icodesize;
218extern int icodestart;
219
220/* change the a PLL frequency */
221void set_pll_freq(int pll_index, long freq_out) {
222 volatile unsigned int* plldata;
223 volatile unsigned char* pllcon;
224 if (pll_index == 0) {
225 plldata = &PLL0DATA;
226 pllcon = &PLL0CON;
227 } else {
228 plldata = &PLL1DATA;
229 pllcon = &PLL1CON;
230 }
231 /* VC0 is 32768 Hz */
232#define VC0FREQ (32768L)
233 unsigned m = (freq_out / VC0FREQ) - 2;
234 /* TODO: if m is too small here, use the divider bits [0,1] */
235 *plldata = m << 2;
236 *pllcon |= 0x1; /* activate */
237 do {
238 } while ((*pllcon & 0x2) == 0); /* wait for stabilization */
239}
240
241int smsc_version(void) {
242 int v;
243 int* smsc_ver_addr = (int*)0x4C20;
244 __asm__ ("ldc %0, @%1" : "=r"(v) : "a"(smsc_ver_addr));
245 v &= 0xFF;
246 if (v < 4 || v == 0xFF) {
247 return 3;
248 }
249 return v;
250}
251
252
253
254void smsc_delay() {
255 int i;
256 /* FIXME: tune the delay.
257 Delay doesn't depend on CPU speed in Archos' firmware.
258 */
259 for (i = 0; i < 100; i++) {
260
261 }
262}
263
264static void extra_init(void) {
265 /* Power on stuff */
266 P1 |= 0x07;
267 P1CON |= 0x1f;
268
269 /* P5 conf
270 * lines 0, 1 & 4 are digital, other analog. :
271 */
272 P5CON = 0xec;
273
274 P6CON = 0x19;
275
276 /* P7 conf
277 nothing to do: all are inputs
278 (reset value of the register is good)
279 */
280
281 /* SMSC chip config (?) */
282 P10CON |= 0x20;
283 P6 &= 0xF7;
284 P10 &= 0x20;
285 smsc_delay();
286 if (smsc_version() < 4) {
287 P6 |= 0x08;
288 P10 |= 0x20;
289 }
290}
291
292void set_cpu_frequency(long frequency) {
293 /* Enable SDRAM refresh, at least 15MHz */
294 if (frequency < cpu_frequency)
295 MIUDCNT = 0x800 | (frequency * 15/1000000L - 1);
296
297 set_pll_freq(0, frequency);
298 PLL0CON |= 0x4; /* use as CPU clock */
299
300 cpu_frequency = frequency;
301 /* wait states and such not changed by Archos. (!?) */
302
303 /* Enable SDRAM refresh, 15MHz. */
304 MIUDCNT = 0x800 | (frequency * 15/1000000L - 1);
305
306 tick_start(1000/HZ);
307 /* TODO: when uart is done; sync uart freq */
308}
309
310/* called by crt0 */
311void system_init(void)
312{
313 /* Disable watchdog */
314 WDTEN = 0xA5;
315
316 /****************
317 * GPIO ports
318 */
319
320 /* keep alive (?) -- clear the bit to prevent crash at start (??) */
321 P8 = 0x00;
322 P8CON = 0x01;
323
324 /* smsc chip init (?) */
325 P10 = 0x20;
326 P6 = 0x08;
327
328 P10CON = 0x20;
329 P6CON = 0x08;
330
331 /********
332 * CPU
333 */
334
335
336 /* PLL0 (cpu osc. frequency) */
337 /* set_cpu_frequency(CPU_FREQ); */
338
339
340 /*******************
341 * configure S(D)RAM
342 */
343
344 /************************
345 * Copy .icode section to icram
346 */
347 ddma_transfer_noicode(0, 0, 0x40, (long)&icodecopy, (int)&icodesize);
348
349
350 /***************************
351 * Interrupts
352 */
353
354 /* priorities ? */
355
356 /* mask */
357 IMR0 = 0;
358 IMR1 = 0;
359
360
361/* IRQ0 BT INT */
362/* IRQ1 RTC INT */
363/* IRQ2 TA INT */
364/* IRQ3 TAOV INT */
365/* IRQ4 TB INT */
366/* IRQ5 TBOV INT */
367/* IRQ6 TC INT */
368/* IRQ7 TCOV INT */
369/* IRQ8 USB INT */
370/* IRQ9 PPIC INT */
371/* IRQ10 UART_Rx/UART_Err/ UART_tx INT */
372/* IRQ11 IIC INT */
373/* IRQ12 SIO INT */
374/* IRQ13 IIS0 INT */
375/* IRQ14 IIS1 INT */
376/* IRQ15 */
377
378 extra_init();
379}
380
381void system_reboot (void)
382{
383}
384
385int system_memory_guard(int newmode)
386{
387 (void)newmode;
388 return 0;
389}
390
391#elif CONFIG_CPU == SH7034
392#include "led.h" 156#include "led.h"
393#include "system.h" 157#include "system.h"
394#include "rolo.h" 158#include "rolo.h"
diff --git a/firmware/thread.c b/firmware/thread.c
index 4094877742..20e2a8c9b9 100644
--- a/firmware/thread.c
+++ b/firmware/thread.c
@@ -186,51 +186,6 @@ static inline void load_context(const void* addr)
186 ); 186 );
187} 187}
188 188
189#elif CONFIG_CPU == TCC730
190/*---------------------------------------------------------------------------
191 * Store non-volatile context.
192 *---------------------------------------------------------------------------
193 */
194#define store_context(addr) \
195 __asm__ volatile ( \
196 "push r0,r1\n\t" \
197 "push r2,r3\n\t" \
198 "push r4,r5\n\t" \
199 "push r6,r7\n\t" \
200 "push a8,a9\n\t" \
201 "push a10,a11\n\t" \
202 "push a12,a13\n\t" \
203 "push a14\n\t" \
204 "ldw @[%0+0], a15\n\t" : : "a" (addr) );
205
206/*---------------------------------------------------------------------------
207 * Load non-volatile context.
208 *---------------------------------------------------------------------------
209 */
210#define load_context(addr) \
211 { \
212 if (!(addr)->started) { \
213 (addr)->started = 1; \
214 __asm__ volatile ( \
215 "ldw a15, @[%0+0]\n\t" \
216 "ldw a14, @[%0+4]\n\t" \
217 "jmp a14\n\t" : : "a" (addr) \
218 ); \
219 } else \
220 __asm__ volatile ( \
221 "ldw a15, @[%0+0]\n\t" \
222 "pop a14\n\t" \
223 "pop a13,a12\n\t" \
224 "pop a11,a10\n\t" \
225 "pop a9,a8\n\t" \
226 "pop r7,r6\n\t" \
227 "pop r5,r4\n\t" \
228 "pop r3,r2\n\t" \
229 "pop r1,r0\n\t" : : "a" (addr) \
230 ); \
231 \
232 }
233
234#endif 189#endif
235 190
236static void add_to_list(struct thread_entry **list, 191static void add_to_list(struct thread_entry **list,
@@ -353,13 +308,6 @@ static inline void sleep_core(void)
353 /* This should sleep the CPU. It appears to wake by itself on 308 /* This should sleep the CPU. It appears to wake by itself on
354 interrupts */ 309 interrupts */
355 CPU_CTL = 0x80000000; 310 CPU_CTL = 0x80000000;
356#elif CONFIG_CPU == TCC730
357 /* Sleep mode is triggered by the SYS instr on CalmRisc16.
358 * Unfortunately, the manual doesn't specify which arg to use.
359 __asm__ volatile ("sys #0x0f");
360 0x1f seems to trigger a reset;
361 0x0f is the only one other argument used by Archos.
362 */
363#elif CONFIG_CPU == S3C2440 311#elif CONFIG_CPU == S3C2440
364 CLKCON |= 2; 312 CLKCON |= 2;
365#endif 313#endif
@@ -430,12 +378,10 @@ void switch_thread(bool save_context, struct thread_entry **blocked_list)
430 { 378 {
431 store_context(&cores[CURRENT_CORE].running->context); 379 store_context(&cores[CURRENT_CORE].running->context);
432 380
433# if CONFIG_CPU != TCC730
434 /* Check if the current thread stack is overflown */ 381 /* Check if the current thread stack is overflown */
435 stackptr = cores[CURRENT_CORE].running->stack; 382 stackptr = cores[CURRENT_CORE].running->stack;
436 if(stackptr[0] != DEADBEEF) 383 if(stackptr[0] != DEADBEEF)
437 panicf("Stkov %s", cores[CURRENT_CORE].running->name); 384 panicf("Stkov %s", cores[CURRENT_CORE].running->name);
438# endif
439 385
440 /* Check if a thread state change has been requested. */ 386 /* Check if a thread state change has been requested. */
441 if (cores[CURRENT_CORE].running->statearg) 387 if (cores[CURRENT_CORE].running->statearg)
@@ -644,14 +590,8 @@ struct thread_entry*
644 add_to_list(&cores[core].running, thread); 590 add_to_list(&cores[core].running, thread);
645 591
646 regs = &thread->context; 592 regs = &thread->context;
647#if defined(CPU_COLDFIRE) || (CONFIG_CPU == SH7034) || defined(CPU_ARM)
648 /* Align stack to an even 32 bit boundary */ 593 /* Align stack to an even 32 bit boundary */
649 regs->sp = (void*)(((unsigned int)stack + stack_size) & ~3); 594 regs->sp = (void*)(((unsigned int)stack + stack_size) & ~3);
650#elif CONFIG_CPU == TCC730
651 /* Align stack on word boundary */
652 regs->sp = (void*)(((unsigned long)stack + stack_size - 2) & ~1);
653 regs->started = 0;
654#endif
655 regs->start = (void*)function; 595 regs->start = (void*)function;
656 596
657 return thread; 597 return thread;
@@ -751,11 +691,7 @@ void init_threads(void)
751 cores[COP].threads[0].stack_size = (int)cop_stackend - (int)cop_stackbegin; 691 cores[COP].threads[0].stack_size = (int)cop_stackend - (int)cop_stackbegin;
752#endif 692#endif
753 } 693 }
754#if CONFIG_CPU == TCC730
755 cores[core].threads[0].context.started = 1;
756#else
757 cores[core].threads[0].context.start = 0; /* thread 0 already running */ 694 cores[core].threads[0].context.start = 0; /* thread 0 already running */
758#endif
759} 695}
760 696
761int thread_stack_usage(const struct thread_entry *thread) 697int thread_stack_usage(const struct thread_entry *thread)
diff --git a/firmware/usb.c b/firmware/usb.c
index a0ffef1011..bde9463a7a 100644
--- a/firmware/usb.c
+++ b/firmware/usb.c
@@ -131,30 +131,6 @@ void usb_enable(bool on)
131 or_b(0x08, &PADRL); /* deassert card detect */ 131 or_b(0x08, &PADRL); /* deassert card detect */
132 } 132 }
133 or_b(0x28, &PAIORL); /* output for USB enable and card detect */ 133 or_b(0x28, &PAIORL); /* output for USB enable and card detect */
134#elif defined(USB_GMINISTYLE)
135 {
136 int smsc_ver = smsc_version();
137 if (on) {
138 if (smsc_ver < 4) {
139 P6 &= ~0x04;
140 P10 &= ~0x20;
141
142 smsc_delay();
143
144 P6 |= 0x08;
145 P10 |= 0x20;
146
147 smsc_delay();
148 }
149 P6 |= 0x10;
150 } else {
151 P6 &= ~0x10;
152 if (smsc_ver < 4) {
153 P6 &= ~0x04;
154 P10 &= ~0x20;
155 }
156 }
157 }
158#elif defined(USB_ISP1582) 134#elif defined(USB_ISP1582)
159 /* TODO: Implement USB_ISP1582 */ 135 /* TODO: Implement USB_ISP1582 */
160 (void) on; 136 (void) on;
@@ -371,9 +347,6 @@ bool usb_detect(void)
371#ifdef USB_PLAYERSTYLE 347#ifdef USB_PLAYERSTYLE
372 current_status = (PADR & 0x8000)?false:true; 348 current_status = (PADR & 0x8000)?false:true;
373#endif 349#endif
374#ifdef USB_GMINISTYLE
375 current_status = (P5 & 0x10)?true:false;
376#endif
377#ifdef USB_IPODSTYLE 350#ifdef USB_IPODSTYLE
378 /* The following check is in the ipodlinux source, with the 351 /* The following check is in the ipodlinux source, with the
379 comment "USB2D_IDENT is bad" if USB2D_IDENT != 0x22FA05 */ 352 comment "USB2D_IDENT is bad" if USB2D_IDENT != 0x22FA05 */
@@ -395,18 +368,6 @@ static void usb_tick(void)
395{ 368{
396 bool current_status; 369 bool current_status;
397 370
398#ifdef USB_GMINISTYLE
399 /* Keep usb chip in usb state (?) */
400 if (P5 & 0x10) {
401 if ((P10 & 0x20) == 0 || (P6 & 0x08) == 0) {
402 if (smsc_version() < 4) {
403 P6 |= 0x08;
404 P10 |= 0x20;
405 }
406 }
407 }
408#endif
409
410 if(usb_monitor_enabled) 371 if(usb_monitor_enabled)
411 { 372 {
412 current_status = usb_detect(); 373 current_status = usb_detect();
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-30 07:22:11 +0000