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-rw-r--r--firmware/pcm_playback.c57
1 files changed, 33 insertions, 24 deletions
diff --git a/firmware/pcm_playback.c b/firmware/pcm_playback.c
index a6fa4fb2d8..5e2ba07b18 100644
--- a/firmware/pcm_playback.c
+++ b/firmware/pcm_playback.c
@@ -47,6 +47,10 @@
47 47
48#ifdef HAVE_UDA1380 48#ifdef HAVE_UDA1380
49 49
50#define EBU_DEFPARM ((7 << 12) | (3 << 8) | (1 << 5) | (5 << 2))
51#define IIS_DEFPARM(freq) ((freq << 12) | 0x300 | 4 << 2)
52#define IIS_RESET 0x800
53
50static bool pcm_playing; 54static bool pcm_playing;
51static bool pcm_paused; 55static bool pcm_paused;
52static int pcm_freq = 0x6; /* 44.1 is default */ 56static int pcm_freq = 0x6; /* 44.1 is default */
@@ -63,8 +67,8 @@ static void dma_start(const void *addr, long size)
63 size &= ~3; /* Size must be multiple of 4 */ 67 size &= ~3; /* Size must be multiple of 4 */
64 68
65 /* Reset the audio FIFO */ 69 /* Reset the audio FIFO */
66 IIS2CONFIG = 0x800; 70 //IIS2CONFIG = IIS_RESET;
67 EBU1CONFIG = 0x800; 71 EBU1CONFIG = IIS_RESET;
68 72
69 /* Set up DMA transfer */ 73 /* Set up DMA transfer */
70 SAR0 = ((unsigned long)addr); /* Source address */ 74 SAR0 = ((unsigned long)addr); /* Source address */
@@ -72,9 +76,9 @@ static void dma_start(const void *addr, long size)
72 BCR0 = size; /* Bytes to transfer */ 76 BCR0 = size; /* Bytes to transfer */
73 77
74 /* Enable the FIFO and force one write to it */ 78 /* Enable the FIFO and force one write to it */
75 IIS2CONFIG = (pcm_freq << 12) | 0x300 | 4 << 2; 79 IIS2CONFIG = IIS_DEFPARM(pcm_freq);
76 /* Also send the audio to S/PDIF */ 80 /* Also send the audio to S/PDIF */
77 EBU1CONFIG = (7 << 12) | (3 << 8) | (1 << 5) | (5 << 2); 81 EBU1CONFIG = EBU_DEFPARM;
78 DCR0 = DMA_INT | DMA_EEXT | DMA_CS | DMA_SINC | DMA_START; 82 DCR0 = DMA_INT | DMA_EEXT | DMA_CS | DMA_SINC | DMA_START;
79} 83}
80 84
@@ -85,8 +89,8 @@ static void dma_stop(void)
85 89
86 DCR0 = 0; 90 DCR0 = 0;
87 /* Reset the FIFO */ 91 /* Reset the FIFO */
88 IIS2CONFIG = 0x800; 92 IIS2CONFIG = IIS_RESET | IIS_DEFPARM(pcm_freq);
89 EBU1CONFIG = 0x800; 93 EBU1CONFIG = IIS_RESET;
90 94
91 next_start = NULL; 95 next_start = NULL;
92 next_size = 0; 96 next_size = 0;
@@ -215,8 +219,8 @@ void pcm_play_pause(bool play)
215 //SAR0 = (unsigned long)next_start; 219 //SAR0 = (unsigned long)next_start;
216 //BCR0 = next_size; 220 //BCR0 = next_size;
217 /* Enable the FIFO and force one write to it */ 221 /* Enable the FIFO and force one write to it */
218 IIS2CONFIG = (pcm_freq << 12) | 0x300 | 4 << 2; 222 IIS2CONFIG = IIS_DEFPARM(pcm_freq);
219 EBU1CONFIG = (7 << 12) | (3 << 8) | (1 << 5) | (5 << 2); 223 EBU1CONFIG = EBU_DEFPARM;
220 DCR0 |= DMA_EEXT | DMA_START; 224 DCR0 |= DMA_EEXT | DMA_START;
221 } 225 }
222 else if(!pcm_paused && !play) 226 else if(!pcm_paused && !play)
@@ -225,8 +229,8 @@ void pcm_play_pause(bool play)
225 229
226 /* Disable DMA peripheral request. */ 230 /* Disable DMA peripheral request. */
227 DCR0 &= ~DMA_EEXT; 231 DCR0 &= ~DMA_EEXT;
228 IIS2CONFIG = 0x800; 232 IIS2CONFIG = IIS_RESET | IIS_DEFPARM(pcm_freq);
229 EBU1CONFIG = 0x800; 233 EBU1CONFIG = IIS_RESET;
230 } 234 }
231 pcm_paused = !play; 235 pcm_paused = !play;
232} 236}
@@ -282,19 +286,13 @@ void pcm_init(void)
282 pcm_playing = false; 286 pcm_playing = false;
283 pcm_paused = false; 287 pcm_paused = false;
284 288
285#if defined(HAVE_UDA1380)
286 uda1380_init();
287#elif defined(HAVE_TLV320)
288 tlv320_init();
289#endif
290
291 BUSMASTER_CTRL = 0x81; /* PARK[1,0]=10 + BCR24BIT */ 289 BUSMASTER_CTRL = 0x81; /* PARK[1,0]=10 + BCR24BIT */
292 DIVR0 = 54; /* DMA0 is mapped into vector 54 in system.c */ 290 DIVR0 = 54; /* DMA0 is mapped into vector 54 in system.c */
293 DMAROUTE = (DMAROUTE & 0xffffff00) | DMA0_REQ_AUDIO_1; 291 DMAROUTE = (DMAROUTE & 0xffffff00) | DMA0_REQ_AUDIO_1;
294 DMACONFIG = 1; /* DMA0Req = PDOR3 */ 292 DMACONFIG = 1; /* DMA0Req = PDOR3 */
295 293
296 /* Reset the audio FIFO */ 294 /* Reset the audio FIFO */
297 IIS2CONFIG = 0x800; 295 IIS2CONFIG = IIS_RESET;
298 296
299 /* Enable interrupt at level 7, priority 0 */ 297 /* Enable interrupt at level 7, priority 0 */
300 ICR4 = (ICR4 & 0xffff00ff) | 0x00001c00; 298 ICR4 = (ICR4 & 0xffff00ff) | 0x00001c00;
@@ -302,18 +300,29 @@ void pcm_init(void)
302 300
303 pcm_set_frequency(44100); 301 pcm_set_frequency(44100);
304 302
305 /* Turn on headphone power */ 303 /* Prevent pops (resets DAC to zero point) */
306#if defined(HAVE_UDA1380) 304 IIS2CONFIG = IIS_DEFPARM(pcm_freq) | IIS_RESET;
307 uda1380_mute(false); 305
308#elif defined(HAVE_TLV320)
309 tlv320_mute(false);
310#endif
311 sleep(HZ/4);
312#if defined(HAVE_UDA1380) 306#if defined(HAVE_UDA1380)
307 /* Initialize default register values. */
308 uda1380_init();
309
310 /* Turn on headphone power */
313 uda1380_enable_output(true); 311 uda1380_enable_output(true);
312
313 /* Sleep a little so the power can stabilize. */
314 sleep(HZ/4);
315
316 /* Unmute the master channel (DAC should be at zero point now). */
317 uda1380_mute(false);
314#elif defined(HAVE_TLV320) 318#elif defined(HAVE_TLV320)
319 tlv320_init();
315 tlv320_enable_output(true); 320 tlv320_enable_output(true);
321 sleep(HZ/4);
322 tlv320_mute(false);
316#endif 323#endif
324
325
317 /* Call dma_stop to initialize everything. */ 326 /* Call dma_stop to initialize everything. */
318 dma_stop(); 327 dma_stop();
319} 328}