diff options
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/x1000/cpm.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/x1000/cpm.h b/firmware/target/mips/ingenic_x1000/x1000/cpm.h index 30750195ce..3d59fd6fc7 100644 --- a/firmware/target/mips/ingenic_x1000/x1000/cpm.h +++ b/firmware/target/mips/ingenic_x1000/x1000/cpm.h | |||
@@ -674,6 +674,18 @@ | |||
674 | #define JN_CPM_DRCG CPM_DRCG | 674 | #define JN_CPM_DRCG CPM_DRCG |
675 | #define JI_CPM_DRCG | 675 | #define JI_CPM_DRCG |
676 | 676 | ||
677 | #define REG_CPM_SCRATCH_PROT jz_reg(CPM_SCRATCH_PROT) | ||
678 | #define JA_CPM_SCRATCH_PROT (0xb0000000 + 0x38) | ||
679 | #define JT_CPM_SCRATCH_PROT JIO_32_RW | ||
680 | #define JN_CPM_SCRATCH_PROT CPM_SCRATCH_PROT | ||
681 | #define JI_CPM_SCRATCH_PROT | ||
682 | |||
683 | #define REG_CPM_SCRATCH jz_reg(CPM_SCRATCH) | ||
684 | #define JA_CPM_SCRATCH (0xb0000000 + 0x34) | ||
685 | #define JT_CPM_SCRATCH JIO_32_RW | ||
686 | #define JN_CPM_SCRATCH CPM_SCRATCH | ||
687 | #define JI_CPM_SCRATCH | ||
688 | |||
677 | #define REG_CPM_USBPCR jz_reg(CPM_USBPCR) | 689 | #define REG_CPM_USBPCR jz_reg(CPM_USBPCR) |
678 | #define JA_CPM_USBPCR (0xb0000000 + 0x3c) | 690 | #define JA_CPM_USBPCR (0xb0000000 + 0x3c) |
679 | #define JT_CPM_USBPCR JIO_32_RW | 691 | #define JT_CPM_USBPCR JIO_32_RW |
@@ -1427,4 +1439,34 @@ | |||
1427 | #define BF_CPM_OPCR_BUS_MODE_V(e) BF_CPM_OPCR_BUS_MODE(BV_CPM_OPCR_BUS_MODE__##e) | 1439 | #define BF_CPM_OPCR_BUS_MODE_V(e) BF_CPM_OPCR_BUS_MODE(BV_CPM_OPCR_BUS_MODE__##e) |
1428 | #define BFM_CPM_OPCR_BUS_MODE_V(v) BM_CPM_OPCR_BUS_MODE | 1440 | #define BFM_CPM_OPCR_BUS_MODE_V(v) BM_CPM_OPCR_BUS_MODE |
1429 | 1441 | ||
1442 | #define REG_CPM_RSR jz_reg(CPM_RSR) | ||
1443 | #define JA_CPM_RSR (0xb0000000 + 0x8) | ||
1444 | #define JT_CPM_RSR JIO_32_RW | ||
1445 | #define JN_CPM_RSR CPM_RSR | ||
1446 | #define JI_CPM_RSR | ||
1447 | #define BP_CPM_RSR_HR 3 | ||
1448 | #define BM_CPM_RSR_HR 0x8 | ||
1449 | #define BF_CPM_RSR_HR(v) (((v) & 0x1) << 3) | ||
1450 | #define BFM_CPM_RSR_HR(v) BM_CPM_RSR_HR | ||
1451 | #define BF_CPM_RSR_HR_V(e) BF_CPM_RSR_HR(BV_CPM_RSR_HR__##e) | ||
1452 | #define BFM_CPM_RSR_HR_V(v) BM_CPM_RSR_HR | ||
1453 | #define BP_CPM_RSR_P0R 2 | ||
1454 | #define BM_CPM_RSR_P0R 0x4 | ||
1455 | #define BF_CPM_RSR_P0R(v) (((v) & 0x1) << 2) | ||
1456 | #define BFM_CPM_RSR_P0R(v) BM_CPM_RSR_P0R | ||
1457 | #define BF_CPM_RSR_P0R_V(e) BF_CPM_RSR_P0R(BV_CPM_RSR_P0R__##e) | ||
1458 | #define BFM_CPM_RSR_P0R_V(v) BM_CPM_RSR_P0R | ||
1459 | #define BP_CPM_RSR_WR 1 | ||
1460 | #define BM_CPM_RSR_WR 0x2 | ||
1461 | #define BF_CPM_RSR_WR(v) (((v) & 0x1) << 1) | ||
1462 | #define BFM_CPM_RSR_WR(v) BM_CPM_RSR_WR | ||
1463 | #define BF_CPM_RSR_WR_V(e) BF_CPM_RSR_WR(BV_CPM_RSR_WR__##e) | ||
1464 | #define BFM_CPM_RSR_WR_V(v) BM_CPM_RSR_WR | ||
1465 | #define BP_CPM_RSR_PR 0 | ||
1466 | #define BM_CPM_RSR_PR 0x1 | ||
1467 | #define BF_CPM_RSR_PR(v) (((v) & 0x1) << 0) | ||
1468 | #define BFM_CPM_RSR_PR(v) BM_CPM_RSR_PR | ||
1469 | #define BF_CPM_RSR_PR_V(e) BF_CPM_RSR_PR(BV_CPM_RSR_PR__##e) | ||
1470 | #define BFM_CPM_RSR_PR_V(v) BM_CPM_RSR_PR | ||
1471 | |||
1430 | #endif /* __HEADERGEN_CPM_H__*/ | 1472 | #endif /* __HEADERGEN_CPM_H__*/ |