diff options
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/export/x1000.h | 52 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/spl-x1000.c | 2 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/spl.lds | 6 |
3 files changed, 51 insertions, 9 deletions
diff --git a/firmware/export/x1000.h b/firmware/export/x1000.h index 8384b214ed..b71d37d64d 100644 --- a/firmware/export/x1000.h +++ b/firmware/export/x1000.h | |||
@@ -7,7 +7,7 @@ | |||
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id$ | 8 | * $Id$ |
9 | * | 9 | * |
10 | * Copyright (C) 2021 Aidan MacDonald | 10 | * Copyright (C) 2021-2022 Aidan MacDonald |
11 | * | 11 | * |
12 | * This program is free software; you can redistribute it and/or | 12 | * This program is free software; you can redistribute it and/or |
13 | * modify it under the terms of the GNU General Public License | 13 | * modify it under the terms of the GNU General Public License |
@@ -39,21 +39,65 @@ | |||
39 | # error "Unsupported EXCLK freq" | 39 | # error "Unsupported EXCLK freq" |
40 | #endif | 40 | #endif |
41 | 41 | ||
42 | /* On-chip TCSM (tightly coupled shared memory), aka IRAM */ | 42 | /* On-chip TCSM (tightly coupled shared memory), aka IRAM. The SPL runs from |
43 | * here, but the rest of Rockbox doesn't use it - it is too difficult to use | ||
44 | * as a normal memory region because it's not in KSEG0. */ | ||
43 | #define X1000_TCSM_BASE 0xf4000000 | 45 | #define X1000_TCSM_BASE 0xf4000000 |
44 | #define X1000_TCSM_SIZE (16 * 1024) | 46 | #define X1000_TCSM_SIZE (16 * 1024) |
45 | 47 | ||
46 | /* External SDRAM */ | 48 | /* SPL load and entry point addresses, this is defined by the HW boot ROM. |
49 | * First 4K is used by mask ROM for stack + variables, and the next 2K are | ||
50 | * occupied by SPL header. Usable code+data size is 10K. */ | ||
51 | #define X1000_SPL_LOAD_ADDR (X1000_TCSM_BASE + 0x1000) | ||
52 | #define X1000_SPL_EXEC_ADDR (X1000_TCSM_BASE + 0x1800) | ||
53 | #define X1000_SPL_SIZE (X1000_TCSM_SIZE - 0x1800) | ||
54 | |||
55 | /* External SDRAM - just one big linear mapping in KSEG0. */ | ||
47 | #define X1000_SDRAM_BASE 0x80000000 | 56 | #define X1000_SDRAM_BASE 0x80000000 |
48 | #define X1000_SDRAM_SIZE (MEMORYSIZE * 1024 * 1024) | 57 | #define X1000_SDRAM_SIZE (MEMORYSIZE * 1024 * 1024) |
58 | #define X1000_SDRAM_END (X1000_SDRAM_BASE + X1000_SDRAM_SIZE) | ||
49 | 59 | ||
50 | /* Memory definitions for Rockbox */ | 60 | /* Memory definitions for Rockbox |
61 | * | ||
62 | * IRAM - Contains the exception handlers and acts as a safe stub area | ||
63 | * from which you can overwrite the rest of DRAM (used by RoLo). | ||
64 | * | ||
65 | * DRAM - This is the main RAM area used for code, data, and bss sections. | ||
66 | * The audio, codec, and plugin buffers also reside in here. | ||
67 | * | ||
68 | * X1000_IRAM_BASE is the base of the exception vectors and must be set to | ||
69 | * the base of kseg0 (0x80000000). The X1000 supports the EBase register so | ||
70 | * the vectors can be remapped, allowing IRAM to be moved to any 4K-aligned | ||
71 | * address, but it would introduce more complexity and there's currently no | ||
72 | * good reason to do this. | ||
73 | * | ||
74 | * X1000_DRAM_BASE doubles as the entry point address. There is some legacy | ||
75 | * baggage surrounding this value so be careful when changing it. | ||
76 | * | ||
77 | * - Rockbox's DRAM_BASE should always equal X1000_STANDARD_DRAM_BASE because | ||
78 | * this value is hardcoded by old bootloaders released in 2021. This can be | ||
79 | * changed if truly necessary, but it should be avoided. | ||
80 | * - The bootloader's DRAM_BASE can be changed freely but if it isn't equal | ||
81 | * to X1000_STANDARD_DRAM_BASE, the update package generation *must* be | ||
82 | * updated to use the "bootloader2.ucl" filename to ensure old jztools do | ||
83 | * not try to incorrectly boot the binary at the wrong load address. | ||
84 | * | ||
85 | * The bootloader DRAM_BASE is also hardcoded in the SPL, but the SPL is | ||
86 | * considered as part of the bootloader to avoid introducing unnecessary | ||
87 | * ABI boundaries. Therefore this hardcoded use can safely be ignored. | ||
88 | * | ||
89 | * There is no requirement that IRAM and DRAM are contiguous, but they must | ||
90 | * reside in the same segment (ie. upper 3 address bits must be identical), | ||
91 | * otherwise we need long calls to go between the two. | ||
92 | */ | ||
51 | #define X1000_IRAM_BASE X1000_SDRAM_BASE | 93 | #define X1000_IRAM_BASE X1000_SDRAM_BASE |
52 | #define X1000_IRAM_SIZE (16 * 1024) | 94 | #define X1000_IRAM_SIZE (16 * 1024) |
53 | #define X1000_IRAM_END (X1000_IRAM_BASE + X1000_IRAM_SIZE) | 95 | #define X1000_IRAM_END (X1000_IRAM_BASE + X1000_IRAM_SIZE) |
54 | #define X1000_DRAM_BASE X1000_IRAM_END | 96 | #define X1000_DRAM_BASE X1000_IRAM_END |
55 | #define X1000_DRAM_SIZE (X1000_SDRAM_SIZE - X1000_IRAM_SIZE) | 97 | #define X1000_DRAM_SIZE (X1000_SDRAM_SIZE - X1000_IRAM_SIZE) |
56 | #define X1000_DRAM_END (X1000_DRAM_BASE + X1000_DRAM_SIZE) | 98 | #define X1000_DRAM_END (X1000_DRAM_BASE + X1000_DRAM_SIZE) |
99 | |||
100 | /* Stacks are placed in IRAM to avoid various annoying issues in boot code. */ | ||
57 | #define X1000_STACKSIZE 0x1e00 | 101 | #define X1000_STACKSIZE 0x1e00 |
58 | #define X1000_IRQSTACKSIZE 0x300 | 102 | #define X1000_IRQSTACKSIZE 0x300 |
59 | 103 | ||
diff --git a/firmware/target/mips/ingenic_x1000/spl-x1000.c b/firmware/target/mips/ingenic_x1000/spl-x1000.c index afaf5a7dd6..499b46ce62 100644 --- a/firmware/target/mips/ingenic_x1000/spl-x1000.c +++ b/firmware/target/mips/ingenic_x1000/spl-x1000.c | |||
@@ -432,7 +432,7 @@ void spl_main(void) | |||
432 | /* handle compression */ | 432 | /* handle compression */ |
433 | switch(opt->flags & BOOTFLAG_COMPRESSED) { | 433 | switch(opt->flags & BOOTFLAG_COMPRESSED) { |
434 | case BOOTFLAG_UCLPACK: { | 434 | case BOOTFLAG_UCLPACK: { |
435 | uint32_t out_size = X1000_DRAM_END - opt->load_addr; | 435 | uint32_t out_size = X1000_SDRAM_END - opt->load_addr; |
436 | rc = ucl_unpack((uint8_t*)load_buffer, opt->storage_size, | 436 | rc = ucl_unpack((uint8_t*)load_buffer, opt->storage_size, |
437 | (uint8_t*)opt->load_addr, &out_size); | 437 | (uint8_t*)opt->load_addr, &out_size); |
438 | } break; | 438 | } break; |
diff --git a/firmware/target/mips/ingenic_x1000/spl.lds b/firmware/target/mips/ingenic_x1000/spl.lds index b0169ab1aa..09ab75d520 100644 --- a/firmware/target/mips/ingenic_x1000/spl.lds +++ b/firmware/target/mips/ingenic_x1000/spl.lds | |||
@@ -7,10 +7,8 @@ ENTRY(_spl_start) | |||
7 | STARTUP(target/mips/ingenic_x1000/spl-start.o) | 7 | STARTUP(target/mips/ingenic_x1000/spl-start.o) |
8 | 8 | ||
9 | MEMORY { | 9 | MEMORY { |
10 | /* First 4k of TCSM is used by mask ROM for stack + variables, | 10 | TCSM : ORIGIN = X1000_SPL_EXEC_ADDR, |
11 | * and the next 2k are occupied by SPL header */ | 11 | LENGTH = X1000_SPL_SIZE |
12 | TCSM : ORIGIN = X1000_TCSM_BASE + 0x1800, | ||
13 | LENGTH = X1000_TCSM_SIZE - 0x1800 | ||
14 | } | 12 | } |
15 | 13 | ||
16 | SECTIONS | 14 | SECTIONS |