diff options
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/drivers/audio/cs42l55.c | 490 | ||||
-rw-r--r-- | firmware/drivers/audio/dac3550a.c | 2 | ||||
-rw-r--r-- | firmware/export/ata-defines.h | 116 | ||||
-rw-r--r-- | firmware/export/config/rk27generic.h | 378 | ||||
-rw-r--r-- | firmware/export/dac3550a.h | 2 | ||||
-rw-r--r-- | firmware/export/mascodec.h | 2 | ||||
-rw-r--r-- | firmware/export/s5l8702.h | 1660 | ||||
-rw-r--r-- | firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c | 2 | ||||
-rw-r--r-- | firmware/target/arm/s5l8700/postmortemstub.S | 616 | ||||
-rw-r--r-- | firmware/target/arm/s5l8702/debug-s5l8702.c | 332 | ||||
-rw-r--r-- | firmware/target/arm/s5l8702/debug-target.h | 66 | ||||
-rw-r--r-- | firmware/target/arm/s5l8702/i2c-s5l8702.c | 392 | ||||
-rw-r--r-- | firmware/target/arm/s5l8702/kernel-s5l8702.c | 112 | ||||
-rw-r--r-- | firmware/target/arm/s5l8702/pcm-s5l8702.c | 456 | ||||
-rw-r--r-- | firmware/target/arm/s5l8702/pcm-target.h | 80 | ||||
-rw-r--r-- | firmware/target/arm/s5l8702/system-target.h | 94 | ||||
-rw-r--r-- | firmware/target/arm/s5l8702/timer-s5l8702.c | 188 | ||||
-rw-r--r-- | firmware/target/sh/archos/mascodec-archos.c | 2 |
18 files changed, 2495 insertions, 2495 deletions
diff --git a/firmware/drivers/audio/cs42l55.c b/firmware/drivers/audio/cs42l55.c index c81a3fc012..38380d5a54 100644 --- a/firmware/drivers/audio/cs42l55.c +++ b/firmware/drivers/audio/cs42l55.c | |||
@@ -1,245 +1,245 @@ | |||
1 | /*************************************************************************** | 1 | /*************************************************************************** |
2 | * __________ __ ___. | 2 | * __________ __ ___. |
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ |
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / |
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id: wm8975.c 28572 2010-11-13 11:38:38Z theseven $ | 8 | * $Id: wm8975.c 28572 2010-11-13 11:38:38Z theseven $ |
9 | * | 9 | * |
10 | * Driver for Cirrus Logic CS42L55 audio codec | 10 | * Driver for Cirrus Logic CS42L55 audio codec |
11 | * | 11 | * |
12 | * Copyright (c) 2010 Michael Sparmann | 12 | * Copyright (c) 2010 Michael Sparmann |
13 | * | 13 | * |
14 | * This program is free software; you can redistribute it and/or | 14 | * This program is free software; you can redistribute it and/or |
15 | * modify it under the terms of the GNU General Public License | 15 | * modify it under the terms of the GNU General Public License |
16 | * as published by the Free Software Foundation; either version 2 | 16 | * as published by the Free Software Foundation; either version 2 |
17 | * of the License, or (at your option) any later version. | 17 | * of the License, or (at your option) any later version. |
18 | * | 18 | * |
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY |
20 | * KIND, either express or implied. | 20 | * KIND, either express or implied. |
21 | * | 21 | * |
22 | ****************************************************************************/ | 22 | ****************************************************************************/ |
23 | #include "logf.h" | 23 | #include "logf.h" |
24 | #include "system.h" | 24 | #include "system.h" |
25 | #include "string.h" | 25 | #include "string.h" |
26 | #include "audio.h" | 26 | #include "audio.h" |
27 | #include "sound.h" | 27 | #include "sound.h" |
28 | #include "audiohw.h" | 28 | #include "audiohw.h" |
29 | #include "cscodec.h" | 29 | #include "cscodec.h" |
30 | #include "cs42l55.h" | 30 | #include "cs42l55.h" |
31 | 31 | ||
32 | const struct sound_settings_info audiohw_settings[] = { | 32 | const struct sound_settings_info audiohw_settings[] = { |
33 | [SOUND_VOLUME] = {"dB", 0, 1, -60, 12, -25}, | 33 | [SOUND_VOLUME] = {"dB", 0, 1, -60, 12, -25}, |
34 | [SOUND_BASS] = {"dB", 1, 15,-105, 120, 0}, | 34 | [SOUND_BASS] = {"dB", 1, 15,-105, 120, 0}, |
35 | [SOUND_TREBLE] = {"dB", 1, 15,-105, 120, 0}, | 35 | [SOUND_TREBLE] = {"dB", 1, 15,-105, 120, 0}, |
36 | [SOUND_BALANCE] = {"%", 0, 1,-100, 100, 0}, | 36 | [SOUND_BALANCE] = {"%", 0, 1,-100, 100, 0}, |
37 | [SOUND_CHANNELS] = {"", 0, 1, 0, 5, 0}, | 37 | [SOUND_CHANNELS] = {"", 0, 1, 0, 5, 0}, |
38 | [SOUND_STEREO_WIDTH] = {"%", 0, 5, 0, 250, 100}, | 38 | [SOUND_STEREO_WIDTH] = {"%", 0, 5, 0, 250, 100}, |
39 | [SOUND_BASS_CUTOFF] = {"", 0, 1, 1, 4, 2}, | 39 | [SOUND_BASS_CUTOFF] = {"", 0, 1, 1, 4, 2}, |
40 | [SOUND_TREBLE_CUTOFF] = {"", 0, 1, 1, 4, 1}, | 40 | [SOUND_TREBLE_CUTOFF] = {"", 0, 1, 1, 4, 1}, |
41 | }; | 41 | }; |
42 | 42 | ||
43 | static int bass, treble; | 43 | static int bass, treble; |
44 | 44 | ||
45 | /* convert tenth of dB volume (-600..120) to master volume register value */ | 45 | /* convert tenth of dB volume (-600..120) to master volume register value */ |
46 | int tenthdb2master(int db) | 46 | int tenthdb2master(int db) |
47 | { | 47 | { |
48 | /* -60dB to +12dB in 1dB steps */ | 48 | /* -60dB to +12dB in 1dB steps */ |
49 | /* 0001100 == +12dB (0xc) */ | 49 | /* 0001100 == +12dB (0xc) */ |
50 | /* 0000000 == 0dB (0x0) */ | 50 | /* 0000000 == 0dB (0x0) */ |
51 | /* 1000100 == -60dB (0x44, this is actually -58dB) */ | 51 | /* 1000100 == -60dB (0x44, this is actually -58dB) */ |
52 | 52 | ||
53 | if (db < VOLUME_MIN) return HPACTL_HPAMUTE; | 53 | if (db < VOLUME_MIN) return HPACTL_HPAMUTE; |
54 | return (db / 10) & HPACTL_HPAVOL_MASK; | 54 | return (db / 10) & HPACTL_HPAVOL_MASK; |
55 | } | 55 | } |
56 | 56 | ||
57 | static void cscodec_setbits(int reg, unsigned char off, unsigned char on) | 57 | static void cscodec_setbits(int reg, unsigned char off, unsigned char on) |
58 | { | 58 | { |
59 | unsigned char data = (cscodec_read(reg) & ~off) | on; | 59 | unsigned char data = (cscodec_read(reg) & ~off) | on; |
60 | cscodec_write(reg, data); | 60 | cscodec_write(reg, data); |
61 | } | 61 | } |
62 | 62 | ||
63 | static void audiohw_mute(bool mute) | 63 | static void audiohw_mute(bool mute) |
64 | { | 64 | { |
65 | if (mute) cscodec_setbits(PLAYCTL, 0, PLAYCTL_MSTAMUTE | PLAYCTL_MSTBMUTE); | 65 | if (mute) cscodec_setbits(PLAYCTL, 0, PLAYCTL_MSTAMUTE | PLAYCTL_MSTBMUTE); |
66 | else cscodec_setbits(PLAYCTL, PLAYCTL_MSTAMUTE | PLAYCTL_MSTBMUTE, 0); | 66 | else cscodec_setbits(PLAYCTL, PLAYCTL_MSTAMUTE | PLAYCTL_MSTBMUTE, 0); |
67 | } | 67 | } |
68 | 68 | ||
69 | void audiohw_preinit(void) | 69 | void audiohw_preinit(void) |
70 | { | 70 | { |
71 | cscodec_power(true); | 71 | cscodec_power(true); |
72 | cscodec_clock(true); | 72 | cscodec_clock(true); |
73 | cscodec_reset(true); | 73 | cscodec_reset(true); |
74 | sleep(HZ / 100); | 74 | sleep(HZ / 100); |
75 | cscodec_reset(false); | 75 | cscodec_reset(false); |
76 | 76 | ||
77 | bass = 0; | 77 | bass = 0; |
78 | treble = 0; | 78 | treble = 0; |
79 | 79 | ||
80 | /* Ask Cirrus or maybe Apple what the hell this means */ | 80 | /* Ask Cirrus or maybe Apple what the hell this means */ |
81 | cscodec_write(HIDDENCTL, HIDDENCTL_UNLOCK); | 81 | cscodec_write(HIDDENCTL, HIDDENCTL_UNLOCK); |
82 | cscodec_write(HIDDEN2E, HIDDEN2E_DEFAULT); | 82 | cscodec_write(HIDDEN2E, HIDDEN2E_DEFAULT); |
83 | cscodec_write(HIDDEN32, HIDDEN32_DEFAULT); | 83 | cscodec_write(HIDDEN32, HIDDEN32_DEFAULT); |
84 | cscodec_write(HIDDEN33, HIDDEN33_DEFAULT); | 84 | cscodec_write(HIDDEN33, HIDDEN33_DEFAULT); |
85 | cscodec_write(HIDDEN34, HIDDEN34_DEFAULT); | 85 | cscodec_write(HIDDEN34, HIDDEN34_DEFAULT); |
86 | cscodec_write(HIDDEN35, HIDDEN35_DEFAULT); | 86 | cscodec_write(HIDDEN35, HIDDEN35_DEFAULT); |
87 | cscodec_write(HIDDEN36, HIDDEN36_DEFAULT); | 87 | cscodec_write(HIDDEN36, HIDDEN36_DEFAULT); |
88 | cscodec_write(HIDDEN37, HIDDEN37_DEFAULT); | 88 | cscodec_write(HIDDEN37, HIDDEN37_DEFAULT); |
89 | cscodec_write(HIDDEN3A, HIDDEN3A_DEFAULT); | 89 | cscodec_write(HIDDEN3A, HIDDEN3A_DEFAULT); |
90 | cscodec_write(HIDDEN3C, HIDDEN3C_DEFAULT); | 90 | cscodec_write(HIDDEN3C, HIDDEN3C_DEFAULT); |
91 | cscodec_write(HIDDEN3D, HIDDEN3D_DEFAULT); | 91 | cscodec_write(HIDDEN3D, HIDDEN3D_DEFAULT); |
92 | cscodec_write(HIDDEN3E, HIDDEN3E_DEFAULT); | 92 | cscodec_write(HIDDEN3E, HIDDEN3E_DEFAULT); |
93 | cscodec_write(HIDDEN3F, HIDDEN3F_DEFAULT); | 93 | cscodec_write(HIDDEN3F, HIDDEN3F_DEFAULT); |
94 | cscodec_write(HIDDENCTL, HIDDENCTL_LOCK); | 94 | cscodec_write(HIDDENCTL, HIDDENCTL_LOCK); |
95 | 95 | ||
96 | cscodec_write(PWRCTL2, PWRCTL2_PDN_LINA_ALWAYS | PWRCTL2_PDN_LINB_ALWAYS | 96 | cscodec_write(PWRCTL2, PWRCTL2_PDN_LINA_ALWAYS | PWRCTL2_PDN_LINB_ALWAYS |
97 | | PWRCTL2_PDN_HPA_NEVER | PWRCTL2_PDN_HPB_NEVER); | 97 | | PWRCTL2_PDN_HPA_NEVER | PWRCTL2_PDN_HPB_NEVER); |
98 | cscodec_write(CLKCTL1, CLKCTL1_MASTER | CLKCTL1_SCLKMCLK_BEFORE | 98 | cscodec_write(CLKCTL1, CLKCTL1_MASTER | CLKCTL1_SCLKMCLK_BEFORE |
99 | | CLKCTL1_MCLKDIV2); | 99 | | CLKCTL1_MCLKDIV2); |
100 | cscodec_write(CLKCTL2, CLKCTL2_44100HZ); | 100 | cscodec_write(CLKCTL2, CLKCTL2_44100HZ); |
101 | cscodec_write(MISCCTL, MISCCTL_UNDOC4 | MISCCTL_ANLGZC | MISCCTL_DIGSFT); | 101 | cscodec_write(MISCCTL, MISCCTL_UNDOC4 | MISCCTL_ANLGZC | MISCCTL_DIGSFT); |
102 | cscodec_write(PWRCTL1, PWRCTL1_PDN_CHRG | PWRCTL1_PDN_ADCA | 102 | cscodec_write(PWRCTL1, PWRCTL1_PDN_CHRG | PWRCTL1_PDN_ADCA |
103 | | PWRCTL1_PDN_ADCB | PWRCTL1_PDN_CODEC); | 103 | | PWRCTL1_PDN_ADCB | PWRCTL1_PDN_CODEC); |
104 | cscodec_write(PLAYCTL, PLAYCTL_PDN_DSP | 104 | cscodec_write(PLAYCTL, PLAYCTL_PDN_DSP |
105 | | PLAYCTL_MSTAMUTE | PLAYCTL_MSTBMUTE); | 105 | | PLAYCTL_MSTAMUTE | PLAYCTL_MSTBMUTE); |
106 | cscodec_write(PGAACTL, 0); | 106 | cscodec_write(PGAACTL, 0); |
107 | cscodec_write(PGABCTL, 0); | 107 | cscodec_write(PGABCTL, 0); |
108 | cscodec_write(HPACTL, HPACTL_HPAMUTE); | 108 | cscodec_write(HPACTL, HPACTL_HPAMUTE); |
109 | cscodec_write(HPBCTL, HPBCTL_HPBMUTE); | 109 | cscodec_write(HPBCTL, HPBCTL_HPBMUTE); |
110 | cscodec_write(LINEACTL, LINEACTL_LINEAMUTE); | 110 | cscodec_write(LINEACTL, LINEACTL_LINEAMUTE); |
111 | cscodec_write(LINEBCTL, LINEBCTL_LINEBMUTE); | 111 | cscodec_write(LINEBCTL, LINEBCTL_LINEBMUTE); |
112 | cscodec_write(PWRCTL1, PWRCTL1_PDN_CHRG | PWRCTL1_PDN_ADCA | 112 | cscodec_write(PWRCTL1, PWRCTL1_PDN_CHRG | PWRCTL1_PDN_ADCA |
113 | | PWRCTL1_PDN_ADCB); | 113 | | PWRCTL1_PDN_ADCB); |
114 | } | 114 | } |
115 | 115 | ||
116 | void audiohw_postinit(void) | 116 | void audiohw_postinit(void) |
117 | { | 117 | { |
118 | cscodec_write(HPACTL, 0); | 118 | cscodec_write(HPACTL, 0); |
119 | cscodec_write(HPBCTL, 0); | 119 | cscodec_write(HPBCTL, 0); |
120 | cscodec_write(LINEACTL, 0); | 120 | cscodec_write(LINEACTL, 0); |
121 | cscodec_write(LINEBCTL, 0); | 121 | cscodec_write(LINEBCTL, 0); |
122 | cscodec_write(CLSHCTL, CLSHCTL_ADPTPWR_SIGNAL); | 122 | cscodec_write(CLSHCTL, CLSHCTL_ADPTPWR_SIGNAL); |
123 | audiohw_mute(false); | 123 | audiohw_mute(false); |
124 | } | 124 | } |
125 | 125 | ||
126 | void audiohw_set_master_vol(int vol_l, int vol_r) | 126 | void audiohw_set_master_vol(int vol_l, int vol_r) |
127 | { | 127 | { |
128 | /* -60dB to +12dB in 1dB steps */ | 128 | /* -60dB to +12dB in 1dB steps */ |
129 | /* 0001100 == +12dB (0xc) */ | 129 | /* 0001100 == +12dB (0xc) */ |
130 | /* 0000000 == 0dB (0x0) */ | 130 | /* 0000000 == 0dB (0x0) */ |
131 | /* 1000100 == -60dB (0x44, this is actually -58dB) */ | 131 | /* 1000100 == -60dB (0x44, this is actually -58dB) */ |
132 | 132 | ||
133 | cscodec_setbits(HPACTL, HPACTL_HPAVOL_MASK | HPACTL_HPAMUTE, | 133 | cscodec_setbits(HPACTL, HPACTL_HPAVOL_MASK | HPACTL_HPAMUTE, |
134 | vol_l << HPACTL_HPAVOL_SHIFT); | 134 | vol_l << HPACTL_HPAVOL_SHIFT); |
135 | cscodec_setbits(HPBCTL, HPBCTL_HPBVOL_MASK | HPBCTL_HPBMUTE, | 135 | cscodec_setbits(HPBCTL, HPBCTL_HPBVOL_MASK | HPBCTL_HPBMUTE, |
136 | vol_r << HPBCTL_HPBVOL_SHIFT); | 136 | vol_r << HPBCTL_HPBVOL_SHIFT); |
137 | } | 137 | } |
138 | 138 | ||
139 | void audiohw_set_lineout_vol(int vol_l, int vol_r) | 139 | void audiohw_set_lineout_vol(int vol_l, int vol_r) |
140 | { | 140 | { |
141 | /* -60dB to +12dB in 1dB steps */ | 141 | /* -60dB to +12dB in 1dB steps */ |
142 | /* 0001100 == +12dB (0xc) */ | 142 | /* 0001100 == +12dB (0xc) */ |
143 | /* 0000000 == 0dB (0x0) */ | 143 | /* 0000000 == 0dB (0x0) */ |
144 | /* 1000100 == -60dB (0x44, this is actually -58dB) */ | 144 | /* 1000100 == -60dB (0x44, this is actually -58dB) */ |
145 | 145 | ||
146 | cscodec_setbits(LINEACTL, LINEACTL_LINEAVOL_MASK | LINEACTL_LINEAMUTE, | 146 | cscodec_setbits(LINEACTL, LINEACTL_LINEAVOL_MASK | LINEACTL_LINEAMUTE, |
147 | vol_l << LINEACTL_LINEAVOL_SHIFT); | 147 | vol_l << LINEACTL_LINEAVOL_SHIFT); |
148 | cscodec_setbits(LINEBCTL, LINEBCTL_LINEBVOL_MASK | LINEBCTL_LINEBMUTE, | 148 | cscodec_setbits(LINEBCTL, LINEBCTL_LINEBVOL_MASK | LINEBCTL_LINEBMUTE, |
149 | vol_r << LINEBCTL_LINEBVOL_SHIFT); | 149 | vol_r << LINEBCTL_LINEBVOL_SHIFT); |
150 | } | 150 | } |
151 | 151 | ||
152 | void audiohw_enable_lineout(bool enable) | 152 | void audiohw_enable_lineout(bool enable) |
153 | { | 153 | { |
154 | if (enable) | 154 | if (enable) |
155 | cscodec_setbits(PWRCTL2, PWRCTL2_PDN_LINA_MASK | PWRCTL2_PDN_LINB_MASK, | 155 | cscodec_setbits(PWRCTL2, PWRCTL2_PDN_LINA_MASK | PWRCTL2_PDN_LINB_MASK, |
156 | PWRCTL2_PDN_LINA_NEVER | PWRCTL2_PDN_LINB_NEVER); | 156 | PWRCTL2_PDN_LINA_NEVER | PWRCTL2_PDN_LINB_NEVER); |
157 | else | 157 | else |
158 | cscodec_setbits(PWRCTL2, PWRCTL2_PDN_LINA_MASK | PWRCTL2_PDN_LINB_MASK, | 158 | cscodec_setbits(PWRCTL2, PWRCTL2_PDN_LINA_MASK | PWRCTL2_PDN_LINB_MASK, |
159 | PWRCTL2_PDN_LINA_ALWAYS | PWRCTL2_PDN_LINB_ALWAYS); | 159 | PWRCTL2_PDN_LINA_ALWAYS | PWRCTL2_PDN_LINB_ALWAYS); |
160 | } | 160 | } |
161 | 161 | ||
162 | static void handle_dsp_power(void) | 162 | static void handle_dsp_power(void) |
163 | { | 163 | { |
164 | if (bass || treble) | 164 | if (bass || treble) |
165 | { | 165 | { |
166 | cscodec_setbits(PLAYCTL, PLAYCTL_PDN_DSP, 0); | 166 | cscodec_setbits(PLAYCTL, PLAYCTL_PDN_DSP, 0); |
167 | cscodec_setbits(BTCTL, 0, BTCTL_TCEN); | 167 | cscodec_setbits(BTCTL, 0, BTCTL_TCEN); |
168 | } | 168 | } |
169 | else | 169 | else |
170 | { | 170 | { |
171 | cscodec_setbits(BTCTL, BTCTL_TCEN, 0); | 171 | cscodec_setbits(BTCTL, BTCTL_TCEN, 0); |
172 | cscodec_setbits(PLAYCTL, 0, PLAYCTL_PDN_DSP); | 172 | cscodec_setbits(PLAYCTL, 0, PLAYCTL_PDN_DSP); |
173 | } | 173 | } |
174 | } | 174 | } |
175 | 175 | ||
176 | void audiohw_set_bass(int value) | 176 | void audiohw_set_bass(int value) |
177 | { | 177 | { |
178 | bass = value; | 178 | bass = value; |
179 | handle_dsp_power(); | 179 | handle_dsp_power(); |
180 | if (value >= -105 && value <= 120) | 180 | if (value >= -105 && value <= 120) |
181 | cscodec_setbits(TONECTL, TONECTL_BASS_MASK, | 181 | cscodec_setbits(TONECTL, TONECTL_BASS_MASK, |
182 | (8 - value / 15) << TONECTL_BASS_SHIFT); | 182 | (8 - value / 15) << TONECTL_BASS_SHIFT); |
183 | } | 183 | } |
184 | 184 | ||
185 | void audiohw_set_treble(int value) | 185 | void audiohw_set_treble(int value) |
186 | { | 186 | { |
187 | treble = value; | 187 | treble = value; |
188 | handle_dsp_power(); | 188 | handle_dsp_power(); |
189 | if (value >= -105 && value <= 120) | 189 | if (value >= -105 && value <= 120) |
190 | cscodec_setbits(TONECTL, TONECTL_TREB_MASK, | 190 | cscodec_setbits(TONECTL, TONECTL_TREB_MASK, |
191 | (8 - value / 15) << TONECTL_TREB_SHIFT); | 191 | (8 - value / 15) << TONECTL_TREB_SHIFT); |
192 | } | 192 | } |
193 | 193 | ||
194 | void audiohw_set_bass_cutoff(int value) | 194 | void audiohw_set_bass_cutoff(int value) |
195 | { | 195 | { |
196 | cscodec_setbits(BTCTL, BTCTL_BASSCF_MASK, | 196 | cscodec_setbits(BTCTL, BTCTL_BASSCF_MASK, |
197 | (value - 1) << BTCTL_BASSCF_SHIFT); | 197 | (value - 1) << BTCTL_BASSCF_SHIFT); |
198 | } | 198 | } |
199 | 199 | ||
200 | void audiohw_set_treble_cutoff(int value) | 200 | void audiohw_set_treble_cutoff(int value) |
201 | { | 201 | { |
202 | cscodec_setbits(BTCTL, BTCTL_TREBCF_MASK, | 202 | cscodec_setbits(BTCTL, BTCTL_TREBCF_MASK, |
203 | (value - 1) << BTCTL_TREBCF_SHIFT); | 203 | (value - 1) << BTCTL_TREBCF_SHIFT); |
204 | } | 204 | } |
205 | 205 | ||
206 | void audiohw_set_prescaler(int value) | 206 | void audiohw_set_prescaler(int value) |
207 | { | 207 | { |
208 | cscodec_setbits(MSTAVOL, MSTAVOL_VOLUME_MASK, | 208 | cscodec_setbits(MSTAVOL, MSTAVOL_VOLUME_MASK, |
209 | (-value / 5) << MSTAVOL_VOLUME_SHIFT); | 209 | (-value / 5) << MSTAVOL_VOLUME_SHIFT); |
210 | cscodec_setbits(MSTBVOL, MSTBVOL_VOLUME_MASK, | 210 | cscodec_setbits(MSTBVOL, MSTBVOL_VOLUME_MASK, |
211 | (-value / 5) << MSTBVOL_VOLUME_SHIFT); | 211 | (-value / 5) << MSTBVOL_VOLUME_SHIFT); |
212 | } | 212 | } |
213 | 213 | ||
214 | /* Nice shutdown of CS42L55 codec */ | 214 | /* Nice shutdown of CS42L55 codec */ |
215 | void audiohw_close(void) | 215 | void audiohw_close(void) |
216 | { | 216 | { |
217 | audiohw_mute(true); | 217 | audiohw_mute(true); |
218 | cscodec_write(HPACTL, HPACTL_HPAMUTE); | 218 | cscodec_write(HPACTL, HPACTL_HPAMUTE); |
219 | cscodec_write(HPBCTL, HPBCTL_HPBMUTE); | 219 | cscodec_write(HPBCTL, HPBCTL_HPBMUTE); |
220 | cscodec_write(LINEACTL, LINEACTL_LINEAMUTE); | 220 | cscodec_write(LINEACTL, LINEACTL_LINEAMUTE); |
221 | cscodec_write(LINEBCTL, LINEBCTL_LINEBMUTE); | 221 | cscodec_write(LINEBCTL, LINEBCTL_LINEBMUTE); |
222 | cscodec_write(PWRCTL1, PWRCTL1_PDN_CHRG | PWRCTL1_PDN_ADCA | 222 | cscodec_write(PWRCTL1, PWRCTL1_PDN_CHRG | PWRCTL1_PDN_ADCA |
223 | | PWRCTL1_PDN_ADCB | PWRCTL1_PDN_CODEC); | 223 | | PWRCTL1_PDN_ADCB | PWRCTL1_PDN_CODEC); |
224 | cscodec_reset(true); | 224 | cscodec_reset(true); |
225 | cscodec_clock(false); | 225 | cscodec_clock(false); |
226 | cscodec_power(false); | 226 | cscodec_power(false); |
227 | } | 227 | } |
228 | 228 | ||
229 | /* Note: Disable output before calling this function */ | 229 | /* Note: Disable output before calling this function */ |
230 | void audiohw_set_frequency(int fsel) | 230 | void audiohw_set_frequency(int fsel) |
231 | { | 231 | { |
232 | if (fsel == HW_FREQ_8) cscodec_write(CLKCTL2, CLKCTL2_8000HZ); | 232 | if (fsel == HW_FREQ_8) cscodec_write(CLKCTL2, CLKCTL2_8000HZ); |
233 | else if (fsel == HW_FREQ_11) cscodec_write(CLKCTL2, CLKCTL2_11025HZ); | 233 | else if (fsel == HW_FREQ_11) cscodec_write(CLKCTL2, CLKCTL2_11025HZ); |
234 | else if (fsel == HW_FREQ_12) cscodec_write(CLKCTL2, CLKCTL2_12000HZ); | 234 | else if (fsel == HW_FREQ_12) cscodec_write(CLKCTL2, CLKCTL2_12000HZ); |
235 | else if (fsel == HW_FREQ_16) cscodec_write(CLKCTL2, CLKCTL2_16000HZ); | 235 | else if (fsel == HW_FREQ_16) cscodec_write(CLKCTL2, CLKCTL2_16000HZ); |
236 | else if (fsel == HW_FREQ_22) cscodec_write(CLKCTL2, CLKCTL2_22050HZ); | 236 | else if (fsel == HW_FREQ_22) cscodec_write(CLKCTL2, CLKCTL2_22050HZ); |
237 | else if (fsel == HW_FREQ_24) cscodec_write(CLKCTL2, CLKCTL2_24000HZ); | 237 | else if (fsel == HW_FREQ_24) cscodec_write(CLKCTL2, CLKCTL2_24000HZ); |
238 | else if (fsel == HW_FREQ_32) cscodec_write(CLKCTL2, CLKCTL2_32000HZ); | 238 | else if (fsel == HW_FREQ_32) cscodec_write(CLKCTL2, CLKCTL2_32000HZ); |
239 | else if (fsel == HW_FREQ_44) cscodec_write(CLKCTL2, CLKCTL2_44100HZ); | 239 | else if (fsel == HW_FREQ_44) cscodec_write(CLKCTL2, CLKCTL2_44100HZ); |
240 | else if (fsel == HW_FREQ_48) cscodec_write(CLKCTL2, CLKCTL2_48000HZ); | 240 | else if (fsel == HW_FREQ_48) cscodec_write(CLKCTL2, CLKCTL2_48000HZ); |
241 | } | 241 | } |
242 | 242 | ||
243 | #ifdef HAVE_RECORDING | 243 | #ifdef HAVE_RECORDING |
244 | //TODO: Implement | 244 | //TODO: Implement |
245 | #endif /* HAVE_RECORDING */ | 245 | #endif /* HAVE_RECORDING */ |
diff --git a/firmware/drivers/audio/dac3550a.c b/firmware/drivers/audio/dac3550a.c index e13602e481..9c6dfbb292 100644 --- a/firmware/drivers/audio/dac3550a.c +++ b/firmware/drivers/audio/dac3550a.c | |||
@@ -5,7 +5,7 @@ | |||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id: dac.c 17847 2008-06-28 18:10:04Z bagder $ | 8 | * $Id$ |
9 | * | 9 | * |
10 | * Copyright (C) 2002 by Linus Nielsen Feltzing | 10 | * Copyright (C) 2002 by Linus Nielsen Feltzing |
11 | * | 11 | * |
diff --git a/firmware/export/ata-defines.h b/firmware/export/ata-defines.h index 1650c9fa47..70249ed0a0 100644 --- a/firmware/export/ata-defines.h +++ b/firmware/export/ata-defines.h | |||
@@ -1,58 +1,58 @@ | |||
1 | /*************************************************************************** | 1 | /*************************************************************************** |
2 | * __________ __ ___. | 2 | * __________ __ ___. |
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ |
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / |
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id: ata.h 28951 2011-01-02 23:02:55Z theseven $ | 8 | * $Id: ata.h 28951 2011-01-02 23:02:55Z theseven $ |
9 | * | 9 | * |
10 | * Copyright (C) 2011 by Michael Sparmann | 10 | * Copyright (C) 2011 by Michael Sparmann |
11 | * | 11 | * |
12 | * This program is free software; you can redistribute it and/or | 12 | * This program is free software; you can redistribute it and/or |
13 | * modify it under the terms of the GNU General Public License | 13 | * modify it under the terms of the GNU General Public License |
14 | * as published by the Free Software Foundation; either version 2 | 14 | * as published by the Free Software Foundation; either version 2 |
15 | * of the License, or (at your option) any later version. | 15 | * of the License, or (at your option) any later version. |
16 | * | 16 | * |
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | 17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY |
18 | * KIND, either express or implied. | 18 | * KIND, either express or implied. |
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | #ifndef __ATA_DEFINES_H__ | 21 | #ifndef __ATA_DEFINES_H__ |
22 | #define __ATA_DEFINES_H__ | 22 | #define __ATA_DEFINES_H__ |
23 | 23 | ||
24 | #ifndef ATA_OUT8 | 24 | #ifndef ATA_OUT8 |
25 | #define ATA_OUT8(reg, data) (reg) = (data) | 25 | #define ATA_OUT8(reg, data) (reg) = (data) |
26 | #endif | 26 | #endif |
27 | #ifndef ATA_OUT16 | 27 | #ifndef ATA_OUT16 |
28 | #define ATA_OUT16(reg, data) (reg) = (data) | 28 | #define ATA_OUT16(reg, data) (reg) = (data) |
29 | #endif | 29 | #endif |
30 | #ifndef ATA_IN8 | 30 | #ifndef ATA_IN8 |
31 | #define ATA_IN8(reg) (reg) | 31 | #define ATA_IN8(reg) (reg) |
32 | #endif | 32 | #endif |
33 | #ifndef ATA_IN16 | 33 | #ifndef ATA_IN16 |
34 | #define ATA_IN16(reg) (reg) | 34 | #define ATA_IN16(reg) (reg) |
35 | #endif | 35 | #endif |
36 | #ifndef ATA_SWAP_IDENTIFY | 36 | #ifndef ATA_SWAP_IDENTIFY |
37 | #define ATA_SWAP_IDENTIFY(word) (word) | 37 | #define ATA_SWAP_IDENTIFY(word) (word) |
38 | #endif | 38 | #endif |
39 | 39 | ||
40 | #define STATUS_BSY 0x80 | 40 | #define STATUS_BSY 0x80 |
41 | #define STATUS_RDY 0x40 | 41 | #define STATUS_RDY 0x40 |
42 | #define STATUS_DRQ 0x08 | 42 | #define STATUS_DRQ 0x08 |
43 | #define STATUS_ERR 0x01 | 43 | #define STATUS_ERR 0x01 |
44 | #define STATUS_DF 0x20 | 44 | #define STATUS_DF 0x20 |
45 | #define ERROR_IDNF 0x10 | 45 | #define ERROR_IDNF 0x10 |
46 | #define ERROR_ABRT 0x04 | 46 | #define ERROR_ABRT 0x04 |
47 | 47 | ||
48 | #define TEST_PATTERN1 0xa5 | 48 | #define TEST_PATTERN1 0xa5 |
49 | #define TEST_PATTERN2 0x5a | 49 | #define TEST_PATTERN2 0x5a |
50 | #define TEST_PATTERN3 0xaa | 50 | #define TEST_PATTERN3 0xaa |
51 | #define TEST_PATTERN4 0x55 | 51 | #define TEST_PATTERN4 0x55 |
52 | 52 | ||
53 | #define ATA_FEATURE ATA_ERROR | 53 | #define ATA_FEATURE ATA_ERROR |
54 | 54 | ||
55 | #define ATA_STATUS ATA_COMMAND | 55 | #define ATA_STATUS ATA_COMMAND |
56 | #define ATA_ALT_STATUS ATA_CONTROL | 56 | #define ATA_ALT_STATUS ATA_CONTROL |
57 | 57 | ||
58 | #endif | 58 | #endif |
diff --git a/firmware/export/config/rk27generic.h b/firmware/export/config/rk27generic.h index b2c74bd937..d7b63f0ac2 100644 --- a/firmware/export/config/rk27generic.h +++ b/firmware/export/config/rk27generic.h | |||
@@ -1,189 +1,189 @@ | |||
1 | /* | 1 | /* |
2 | * This config file is for Rockchip rk27xx reference design | 2 | * This config file is for Rockchip rk27xx reference design |
3 | */ | 3 | */ |
4 | #define TARGET_TREE /* this target is using the target tree system */ | 4 | #define TARGET_TREE /* this target is using the target tree system */ |
5 | 5 | ||
6 | /* For Rolo and boot loader */ | 6 | /* For Rolo and boot loader */ |
7 | #define MODEL_NUMBER 78 | 7 | #define MODEL_NUMBER 78 |
8 | 8 | ||
9 | #define MODEL_NAME "Rockchip 27xx generic" | 9 | #define MODEL_NAME "Rockchip 27xx generic" |
10 | 10 | ||
11 | /* define this if you have recording possibility */ | 11 | /* define this if you have recording possibility */ |
12 | /* #define HAVE_RECORDING */ | 12 | /* #define HAVE_RECORDING */ |
13 | 13 | ||
14 | /* Define bitmask of input sources - recordable bitmask can be defined | 14 | /* Define bitmask of input sources - recordable bitmask can be defined |
15 | explicitly if different */ | 15 | explicitly if different */ |
16 | /* #define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_FM) */ | 16 | /* #define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_FM) */ |
17 | 17 | ||
18 | /* define the bitmask of hardware sample rates */ | 18 | /* define the bitmask of hardware sample rates */ |
19 | #define HW_SAMPR_CAPS (SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11 \ | 19 | #define HW_SAMPR_CAPS (SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11 \ |
20 | | SAMPR_CAP_48 | SAMPR_CAP_24 | SAMPR_CAP_12 \ | 20 | | SAMPR_CAP_48 | SAMPR_CAP_24 | SAMPR_CAP_12 \ |
21 | | SAMPR_CAP_32 | SAMPR_CAP_16 | SAMPR_CAP_8) | 21 | | SAMPR_CAP_32 | SAMPR_CAP_16 | SAMPR_CAP_8) |
22 | 22 | ||
23 | /* define the bitmask of recording sample rates */ | 23 | /* define the bitmask of recording sample rates */ |
24 | #define REC_SAMPR_CAPS (SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11 \ | 24 | #define REC_SAMPR_CAPS (SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11 \ |
25 | | SAMPR_CAP_48 | SAMPR_CAP_24 | SAMPR_CAP_12 \ | 25 | | SAMPR_CAP_48 | SAMPR_CAP_24 | SAMPR_CAP_12 \ |
26 | | SAMPR_CAP_32 | SAMPR_CAP_16 | SAMPR_CAP_8) | 26 | | SAMPR_CAP_32 | SAMPR_CAP_16 | SAMPR_CAP_8) |
27 | 27 | ||
28 | /* define this if you have a bitmap LCD display */ | 28 | /* define this if you have a bitmap LCD display */ |
29 | #define HAVE_LCD_BITMAP | 29 | #define HAVE_LCD_BITMAP |
30 | 30 | ||
31 | /* define this if you can flip your LCD */ | 31 | /* define this if you can flip your LCD */ |
32 | /* #define HAVE_LCD_FLIP */ | 32 | /* #define HAVE_LCD_FLIP */ |
33 | 33 | ||
34 | /* define this if you have a colour LCD */ | 34 | /* define this if you have a colour LCD */ |
35 | #define HAVE_LCD_COLOR | 35 | #define HAVE_LCD_COLOR |
36 | 36 | ||
37 | /* define this if you want album art for this target */ | 37 | /* define this if you want album art for this target */ |
38 | #define HAVE_ALBUMART | 38 | #define HAVE_ALBUMART |
39 | 39 | ||
40 | /* define this to enable bitmap scaling */ | 40 | /* define this to enable bitmap scaling */ |
41 | #define HAVE_BMP_SCALING | 41 | #define HAVE_BMP_SCALING |
42 | 42 | ||
43 | /* define this to enable JPEG decoding */ | 43 | /* define this to enable JPEG decoding */ |
44 | #define HAVE_JPEG | 44 | #define HAVE_JPEG |
45 | 45 | ||
46 | /* define this if you can invert the colours on your LCD */ | 46 | /* define this if you can invert the colours on your LCD */ |
47 | /* #define HAVE_LCD_INVERT */ | 47 | /* #define HAVE_LCD_INVERT */ |
48 | 48 | ||
49 | /* define this if you have access to the quickscreen */ | 49 | /* define this if you have access to the quickscreen */ |
50 | #define HAVE_QUICKSCREEN | 50 | #define HAVE_QUICKSCREEN |
51 | 51 | ||
52 | /* define this if you have access to the pitchscreen */ | 52 | /* define this if you have access to the pitchscreen */ |
53 | #define HAVE_PITCHSCREEN | 53 | #define HAVE_PITCHSCREEN |
54 | 54 | ||
55 | /* define this if you would like tagcache to build on this target */ | 55 | /* define this if you would like tagcache to build on this target */ |
56 | #define HAVE_TAGCACHE | 56 | #define HAVE_TAGCACHE |
57 | 57 | ||
58 | /* define this if you have a flash memory storage */ | 58 | /* define this if you have a flash memory storage */ |
59 | #define HAVE_FLASH_STORAGE | 59 | #define HAVE_FLASH_STORAGE |
60 | 60 | ||
61 | #define CONFIG_STORAGE (STORAGE_SD | STORAGE_NAND) | 61 | #define CONFIG_STORAGE (STORAGE_SD | STORAGE_NAND) |
62 | 62 | ||
63 | #define CONFIG_NAND NAND_RK27XX | 63 | #define CONFIG_NAND NAND_RK27XX |
64 | #define HAVE_SW_TONE_CONTROLS | 64 | #define HAVE_SW_TONE_CONTROLS |
65 | 65 | ||
66 | /* commented for now */ | 66 | /* commented for now */ |
67 | /* #define HAVE_HOTSWAP */ | 67 | /* #define HAVE_HOTSWAP */ |
68 | 68 | ||
69 | #define NUM_DRIVES 2 | 69 | #define NUM_DRIVES 2 |
70 | #define SECTOR_SIZE 512 | 70 | #define SECTOR_SIZE 512 |
71 | 71 | ||
72 | /* for small(ish) SD cards */ | 72 | /* for small(ish) SD cards */ |
73 | #define HAVE_FAT16SUPPORT | 73 | #define HAVE_FAT16SUPPORT |
74 | 74 | ||
75 | /* LCD dimensions */ | 75 | /* LCD dimensions */ |
76 | #define LCD_WIDTH 400 | 76 | #define LCD_WIDTH 400 |
77 | #define LCD_HEIGHT 240 | 77 | #define LCD_HEIGHT 240 |
78 | #define LCD_DEPTH 16 /* pseudo 262.144 colors */ | 78 | #define LCD_DEPTH 16 /* pseudo 262.144 colors */ |
79 | #define LCD_PIXELFORMAT RGB565 /* rgb565 */ | 79 | #define LCD_PIXELFORMAT RGB565 /* rgb565 */ |
80 | 80 | ||
81 | /* Define this if the LCD can shut down */ | 81 | /* Define this if the LCD can shut down */ |
82 | /* #define HAVE_LCD_SHUTDOWN */ | 82 | /* #define HAVE_LCD_SHUTDOWN */ |
83 | 83 | ||
84 | /* Define this if your LCD can be enabled/disabled */ | 84 | /* Define this if your LCD can be enabled/disabled */ |
85 | /* #define HAVE_LCD_ENABLE */ | 85 | /* #define HAVE_LCD_ENABLE */ |
86 | 86 | ||
87 | /* Define this if your LCD can be put to sleep. HAVE_LCD_ENABLE | 87 | /* Define this if your LCD can be put to sleep. HAVE_LCD_ENABLE |
88 | should be defined as well. */ | 88 | should be defined as well. */ |
89 | #ifndef BOOTLOADER | 89 | #ifndef BOOTLOADER |
90 | /* TODO: #define HAVE_LCD_SLEEP */ | 90 | /* TODO: #define HAVE_LCD_SLEEP */ |
91 | /* TODO: #define HAVE_LCD_SLEEP_SETTING */ | 91 | /* TODO: #define HAVE_LCD_SLEEP_SETTING */ |
92 | #endif | 92 | #endif |
93 | 93 | ||
94 | #define CONFIG_KEYPAD RK27XX_GENERIC_PAD | 94 | #define CONFIG_KEYPAD RK27XX_GENERIC_PAD |
95 | 95 | ||
96 | /* Define this to enable morse code input */ | 96 | /* Define this to enable morse code input */ |
97 | #define HAVE_MORSE_INPUT | 97 | #define HAVE_MORSE_INPUT |
98 | 98 | ||
99 | /* Define this if you do software codec */ | 99 | /* Define this if you do software codec */ |
100 | #define CONFIG_CODEC SWCODEC | 100 | #define CONFIG_CODEC SWCODEC |
101 | 101 | ||
102 | /* define this if you have a real-time clock */ | 102 | /* define this if you have a real-time clock */ |
103 | /* #define CONFIG_RTC RTC_NANO2G */ | 103 | /* #define CONFIG_RTC RTC_NANO2G */ |
104 | 104 | ||
105 | /* Define if the device can wake from an RTC alarm */ | 105 | /* Define if the device can wake from an RTC alarm */ |
106 | /* #define HAVE_RTC_ALARM */ | 106 | /* #define HAVE_RTC_ALARM */ |
107 | 107 | ||
108 | #define CONFIG_LCD LCD_SPFD5420A | 108 | #define CONFIG_LCD LCD_SPFD5420A |
109 | 109 | ||
110 | /* Define the type of audio codec */ | 110 | /* Define the type of audio codec */ |
111 | #define HAVE_RK27XX_CODEC | 111 | #define HAVE_RK27XX_CODEC |
112 | 112 | ||
113 | /* #define HAVE_PCM_DMA_ADDRESS */ | 113 | /* #define HAVE_PCM_DMA_ADDRESS */ |
114 | 114 | ||
115 | /* Define this for LCD backlight available */ | 115 | /* Define this for LCD backlight available */ |
116 | #define HAVE_BACKLIGHT | 116 | #define HAVE_BACKLIGHT |
117 | #define HAVE_BACKLIGHT_BRIGHTNESS | 117 | #define HAVE_BACKLIGHT_BRIGHTNESS |
118 | #define MIN_BRIGHTNESS_SETTING 0 | 118 | #define MIN_BRIGHTNESS_SETTING 0 |
119 | #define MAX_BRIGHTNESS_SETTING 31 | 119 | #define MAX_BRIGHTNESS_SETTING 31 |
120 | #define DEFAULT_BRIGHTNESS_SETTING 20 | 120 | #define DEFAULT_BRIGHTNESS_SETTING 20 |
121 | #define CONFIG_BACKLIGHT_FADING BACKLIGHT_FADING_SW_HW_REG | 121 | #define CONFIG_BACKLIGHT_FADING BACKLIGHT_FADING_SW_HW_REG |
122 | 122 | ||
123 | /* Define this if you have a software controlled poweroff */ | 123 | /* Define this if you have a software controlled poweroff */ |
124 | #define HAVE_SW_POWEROFF | 124 | #define HAVE_SW_POWEROFF |
125 | 125 | ||
126 | /* The number of bytes reserved for loadable codecs */ | 126 | /* The number of bytes reserved for loadable codecs */ |
127 | #define CODEC_SIZE 0x100000 | 127 | #define CODEC_SIZE 0x100000 |
128 | 128 | ||
129 | /* The number of bytes reserved for loadable plugins */ | 129 | /* The number of bytes reserved for loadable plugins */ |
130 | #define PLUGIN_BUFFER_SIZE 0x80000 | 130 | #define PLUGIN_BUFFER_SIZE 0x80000 |
131 | 131 | ||
132 | /* TODO: Figure out real values */ | 132 | /* TODO: Figure out real values */ |
133 | #define BATTERY_CAPACITY_DEFAULT 400 /* default battery capacity */ | 133 | #define BATTERY_CAPACITY_DEFAULT 400 /* default battery capacity */ |
134 | #define BATTERY_CAPACITY_MIN 300 /* min. capacity selectable */ | 134 | #define BATTERY_CAPACITY_MIN 300 /* min. capacity selectable */ |
135 | #define BATTERY_CAPACITY_MAX 500 /* max. capacity selectable */ | 135 | #define BATTERY_CAPACITY_MAX 500 /* max. capacity selectable */ |
136 | #define BATTERY_CAPACITY_INC 10 /* capacity increment */ | 136 | #define BATTERY_CAPACITY_INC 10 /* capacity increment */ |
137 | #define BATTERY_TYPES_COUNT 1 /* only one type */ | 137 | #define BATTERY_TYPES_COUNT 1 /* only one type */ |
138 | 138 | ||
139 | /* Hardware controlled charging with monitoring */ | 139 | /* Hardware controlled charging with monitoring */ |
140 | #define CONFIG_CHARGING CHARGING_MONITOR | 140 | #define CONFIG_CHARGING CHARGING_MONITOR |
141 | 141 | ||
142 | /* define current usage levels */ | 142 | /* define current usage levels */ |
143 | /* TODO: #define CURRENT_NORMAL | 143 | /* TODO: #define CURRENT_NORMAL |
144 | * TODO: #define CURRENT_BACKLIGHT 23 | 144 | * TODO: #define CURRENT_BACKLIGHT 23 |
145 | */ | 145 | */ |
146 | 146 | ||
147 | /* define this if the unit can be powered or charged via USB */ | 147 | /* define this if the unit can be powered or charged via USB */ |
148 | #define HAVE_USB_POWER | 148 | #define HAVE_USB_POWER |
149 | 149 | ||
150 | /* USB On-the-go */ | 150 | /* USB On-the-go */ |
151 | #define CONFIG_USBOTG USBOTG_RK27XX | 151 | #define CONFIG_USBOTG USBOTG_RK27XX |
152 | 152 | ||
153 | /* enable these for the experimental usb stack */ | 153 | /* enable these for the experimental usb stack */ |
154 | #define HAVE_USBSTACK | 154 | #define HAVE_USBSTACK |
155 | 155 | ||
156 | #define USE_ROCKBOX_USB | 156 | #define USE_ROCKBOX_USB |
157 | #define USB_VENDOR_ID 0x071b | 157 | #define USB_VENDOR_ID 0x071b |
158 | #define USB_PRODUCT_ID 0x3202 | 158 | #define USB_PRODUCT_ID 0x3202 |
159 | #define HAVE_BOOTLOADER_USB_MODE | 159 | #define HAVE_BOOTLOADER_USB_MODE |
160 | 160 | ||
161 | /* Define this if your LCD can set contrast */ | 161 | /* Define this if your LCD can set contrast */ |
162 | /* #define HAVE_LCD_CONTRAST */ | 162 | /* #define HAVE_LCD_CONTRAST */ |
163 | 163 | ||
164 | /* The exact type of CPU */ | 164 | /* The exact type of CPU */ |
165 | #define CONFIG_CPU RK27XX | 165 | #define CONFIG_CPU RK27XX |
166 | 166 | ||
167 | /* I2C interface */ | 167 | /* I2C interface */ |
168 | #define CONFIG_I2C I2C_RK27XX | 168 | #define CONFIG_I2C I2C_RK27XX |
169 | 169 | ||
170 | /* Define this to the CPU frequency */ | 170 | /* Define this to the CPU frequency */ |
171 | #define CPU_FREQ 200000000 | 171 | #define CPU_FREQ 200000000 |
172 | 172 | ||
173 | /* define this if the hardware can be powered off while charging */ | 173 | /* define this if the hardware can be powered off while charging */ |
174 | /* #define HAVE_POWEROFF_WHILE_CHARGING */ | 174 | /* #define HAVE_POWEROFF_WHILE_CHARGING */ |
175 | 175 | ||
176 | /* Offset ( in the firmware file's header ) to the file CRC */ | 176 | /* Offset ( in the firmware file's header ) to the file CRC */ |
177 | #define FIRMWARE_OFFSET_FILE_CRC 0 | 177 | #define FIRMWARE_OFFSET_FILE_CRC 0 |
178 | 178 | ||
179 | /* Offset ( in the firmware file's header ) to the real data */ | 179 | /* Offset ( in the firmware file's header ) to the real data */ |
180 | #define FIRMWARE_OFFSET_FILE_DATA 8 | 180 | #define FIRMWARE_OFFSET_FILE_DATA 8 |
181 | 181 | ||
182 | #define STORAGE_NEEDS_ALIGN | 182 | #define STORAGE_NEEDS_ALIGN |
183 | 183 | ||
184 | /* Define this if you have adjustable CPU frequency */ | 184 | /* Define this if you have adjustable CPU frequency */ |
185 | /* #define HAVE_ADJUSTABLE_CPU_FREQ */ | 185 | /* #define HAVE_ADJUSTABLE_CPU_FREQ */ |
186 | 186 | ||
187 | #define BOOTFILE_EXT "rk27" | 187 | #define BOOTFILE_EXT "rk27" |
188 | #define BOOTFILE "rockbox." BOOTFILE_EXT | 188 | #define BOOTFILE "rockbox." BOOTFILE_EXT |
189 | #define BOOTDIR "/.rockbox" | 189 | #define BOOTDIR "/.rockbox" |
diff --git a/firmware/export/dac3550a.h b/firmware/export/dac3550a.h index 3744b221ed..23c4db9cbc 100644 --- a/firmware/export/dac3550a.h +++ b/firmware/export/dac3550a.h | |||
@@ -5,7 +5,7 @@ | |||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id: dac.h 24158 2010-01-03 11:31:14Z Buschel $ | 8 | * $Id$ |
9 | * | 9 | * |
10 | * Copyright (C) 2002 by Linus Nielsen Feltzing | 10 | * Copyright (C) 2002 by Linus Nielsen Feltzing |
11 | * | 11 | * |
diff --git a/firmware/export/mascodec.h b/firmware/export/mascodec.h index 82a71e30c8..f10dc3f1ca 100644 --- a/firmware/export/mascodec.h +++ b/firmware/export/mascodec.h | |||
@@ -5,7 +5,7 @@ | |||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id: mas.h 24154 2010-01-03 10:27:43Z Buschel $ | 8 | * $Id$ |
9 | * | 9 | * |
10 | * Copyright (C) 2002 by Linus Nielsen Feltzing | 10 | * Copyright (C) 2002 by Linus Nielsen Feltzing |
11 | * | 11 | * |
diff --git a/firmware/export/s5l8702.h b/firmware/export/s5l8702.h index 338d7a5e16..31e6a63dbc 100644 --- a/firmware/export/s5l8702.h +++ b/firmware/export/s5l8702.h | |||
@@ -1,830 +1,830 @@ | |||
1 | /*************************************************************************** | 1 | /*************************************************************************** |
2 | * __________ __ ___. | 2 | * __________ __ ___. |
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ |
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / |
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id: s5l8700.h 28791 2010-12-11 09:39:33Z Buschel $ | 8 | * $Id: s5l8700.h 28791 2010-12-11 09:39:33Z Buschel $ |
9 | * | 9 | * |
10 | * Copyright (C) 2008 by Marcoen Hirschberg, Bart van Adrichem | 10 | * Copyright (C) 2008 by Marcoen Hirschberg, Bart van Adrichem |
11 | * | 11 | * |
12 | * This program is free software; you can redistribute it and/or | 12 | * This program is free software; you can redistribute it and/or |
13 | * modify it under the terms of the GNU General Public License | 13 | * modify it under the terms of the GNU General Public License |
14 | * as published by the Free Software Foundation; either version 2 | 14 | * as published by the Free Software Foundation; either version 2 |
15 | * of the License, or (at your option) any later version. | 15 | * of the License, or (at your option) any later version. |
16 | * | 16 | * |
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | 17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY |
18 | * KIND, either express or implied. | 18 | * KIND, either express or implied. |
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | 21 | ||
22 | #ifndef __S5L8702_H__ | 22 | #ifndef __S5L8702_H__ |
23 | #define __S5L8702_H__ | 23 | #define __S5L8702_H__ |
24 | 24 | ||
25 | #include <inttypes.h> | 25 | #include <inttypes.h> |
26 | 26 | ||
27 | #define REG8_PTR_T volatile uint8_t * | 27 | #define REG8_PTR_T volatile uint8_t * |
28 | #define REG16_PTR_T volatile uint16_t * | 28 | #define REG16_PTR_T volatile uint16_t * |
29 | #define REG32_PTR_T volatile uint32_t * | 29 | #define REG32_PTR_T volatile uint32_t * |
30 | 30 | ||
31 | #define TIMER_FREQ 54000000 | 31 | #define TIMER_FREQ 54000000 |
32 | 32 | ||
33 | #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ | 33 | #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ |
34 | 34 | ||
35 | #define DRAM_ORIG 0x08000000 | 35 | #define DRAM_ORIG 0x08000000 |
36 | #define IRAM_ORIG 0 | 36 | #define IRAM_ORIG 0 |
37 | 37 | ||
38 | #define DRAM_SIZE (MEMORYSIZE * 0x100000) | 38 | #define DRAM_SIZE (MEMORYSIZE * 0x100000) |
39 | #define IRAM_SIZE 0x40000 | 39 | #define IRAM_SIZE 0x40000 |
40 | 40 | ||
41 | #define TTB_SIZE 0x4000 | 41 | #define TTB_SIZE 0x4000 |
42 | #define TTB_BASE_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE) | 42 | #define TTB_BASE_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE) |
43 | 43 | ||
44 | /////SYSTEM CONTROLLER///// | 44 | /////SYSTEM CONTROLLER///// |
45 | #define CLKCON0 (*((volatile uint32_t*)(0x3C500000))) | 45 | #define CLKCON0 (*((volatile uint32_t*)(0x3C500000))) |
46 | #define CLKCON1 (*((volatile uint32_t*)(0x3C500004))) | 46 | #define CLKCON1 (*((volatile uint32_t*)(0x3C500004))) |
47 | #define CLKCON2 (*((volatile uint32_t*)(0x3C500008))) | 47 | #define CLKCON2 (*((volatile uint32_t*)(0x3C500008))) |
48 | #define CLKCON3 (*((volatile uint32_t*)(0x3C50000C))) | 48 | #define CLKCON3 (*((volatile uint32_t*)(0x3C50000C))) |
49 | #define CLKCON4 (*((volatile uint32_t*)(0x3C500010))) | 49 | #define CLKCON4 (*((volatile uint32_t*)(0x3C500010))) |
50 | #define CLKCON5 (*((volatile uint32_t*)(0x3C500014))) | 50 | #define CLKCON5 (*((volatile uint32_t*)(0x3C500014))) |
51 | #define PLL0PMS (*((volatile uint32_t*)(0x3C500020))) | 51 | #define PLL0PMS (*((volatile uint32_t*)(0x3C500020))) |
52 | #define PLL1PMS (*((volatile uint32_t*)(0x3C500024))) | 52 | #define PLL1PMS (*((volatile uint32_t*)(0x3C500024))) |
53 | #define PLL2PMS (*((volatile uint32_t*)(0x3C500028))) | 53 | #define PLL2PMS (*((volatile uint32_t*)(0x3C500028))) |
54 | #define PLL0LCNT (*((volatile uint32_t*)(0x3C500030))) | 54 | #define PLL0LCNT (*((volatile uint32_t*)(0x3C500030))) |
55 | #define PLL1LCNT (*((volatile uint32_t*)(0x3C500034))) | 55 | #define PLL1LCNT (*((volatile uint32_t*)(0x3C500034))) |
56 | #define PLL2LCNT (*((volatile uint32_t*)(0x3C500038))) | 56 | #define PLL2LCNT (*((volatile uint32_t*)(0x3C500038))) |
57 | #define PLLLOCK (*((volatile uint32_t*)(0x3C500040))) | 57 | #define PLLLOCK (*((volatile uint32_t*)(0x3C500040))) |
58 | #define PLLMODE (*((volatile uint32_t*)(0x3C500044))) | 58 | #define PLLMODE (*((volatile uint32_t*)(0x3C500044))) |
59 | #define PWRCON(i) (*((uint32_t volatile*)(0x3C500000 \ | 59 | #define PWRCON(i) (*((uint32_t volatile*)(0x3C500000 \ |
60 | + ((i) == 4 ? 0x6C : \ | 60 | + ((i) == 4 ? 0x6C : \ |
61 | ((i) == 3 ? 0x68 : \ | 61 | ((i) == 3 ? 0x68 : \ |
62 | ((i) == 2 ? 0x58 : \ | 62 | ((i) == 2 ? 0x58 : \ |
63 | ((i) == 1 ? 0x4C : \ | 63 | ((i) == 1 ? 0x4C : \ |
64 | 0x48))))))) | 64 | 0x48))))))) |
65 | 65 | ||
66 | 66 | ||
67 | /////TIMER///// | 67 | /////TIMER///// |
68 | #define TACON (*((uint32_t volatile*)(0x3C700000))) | 68 | #define TACON (*((uint32_t volatile*)(0x3C700000))) |
69 | #define TACMD (*((uint32_t volatile*)(0x3C700004))) | 69 | #define TACMD (*((uint32_t volatile*)(0x3C700004))) |
70 | #define TADATA0 (*((uint32_t volatile*)(0x3C700008))) | 70 | #define TADATA0 (*((uint32_t volatile*)(0x3C700008))) |
71 | #define TADATA1 (*((uint32_t volatile*)(0x3C70000C))) | 71 | #define TADATA1 (*((uint32_t volatile*)(0x3C70000C))) |
72 | #define TAPRE (*((uint32_t volatile*)(0x3C700010))) | 72 | #define TAPRE (*((uint32_t volatile*)(0x3C700010))) |
73 | #define TACNT (*((uint32_t volatile*)(0x3C700014))) | 73 | #define TACNT (*((uint32_t volatile*)(0x3C700014))) |
74 | #define TBCON (*((uint32_t volatile*)(0x3C700020))) | 74 | #define TBCON (*((uint32_t volatile*)(0x3C700020))) |
75 | #define TBCMD (*((uint32_t volatile*)(0x3C700024))) | 75 | #define TBCMD (*((uint32_t volatile*)(0x3C700024))) |
76 | #define TBDATA0 (*((uint32_t volatile*)(0x3C700028))) | 76 | #define TBDATA0 (*((uint32_t volatile*)(0x3C700028))) |
77 | #define TBDATA1 (*((uint32_t volatile*)(0x3C70002C))) | 77 | #define TBDATA1 (*((uint32_t volatile*)(0x3C70002C))) |
78 | #define TBPRE (*((uint32_t volatile*)(0x3C700030))) | 78 | #define TBPRE (*((uint32_t volatile*)(0x3C700030))) |
79 | #define TBCNT (*((uint32_t volatile*)(0x3C700034))) | 79 | #define TBCNT (*((uint32_t volatile*)(0x3C700034))) |
80 | #define TCCON (*((uint32_t volatile*)(0x3C700040))) | 80 | #define TCCON (*((uint32_t volatile*)(0x3C700040))) |
81 | #define TCCMD (*((uint32_t volatile*)(0x3C700044))) | 81 | #define TCCMD (*((uint32_t volatile*)(0x3C700044))) |
82 | #define TCDATA0 (*((uint32_t volatile*)(0x3C700048))) | 82 | #define TCDATA0 (*((uint32_t volatile*)(0x3C700048))) |
83 | #define TCDATA1 (*((uint32_t volatile*)(0x3C70004C))) | 83 | #define TCDATA1 (*((uint32_t volatile*)(0x3C70004C))) |
84 | #define TCPRE (*((uint32_t volatile*)(0x3C700050))) | 84 | #define TCPRE (*((uint32_t volatile*)(0x3C700050))) |
85 | #define TCCNT (*((uint32_t volatile*)(0x3C700054))) | 85 | #define TCCNT (*((uint32_t volatile*)(0x3C700054))) |
86 | #define TDCON (*((uint32_t volatile*)(0x3C700060))) | 86 | #define TDCON (*((uint32_t volatile*)(0x3C700060))) |
87 | #define TDCMD (*((uint32_t volatile*)(0x3C700064))) | 87 | #define TDCMD (*((uint32_t volatile*)(0x3C700064))) |
88 | #define TDDATA0 (*((uint32_t volatile*)(0x3C700068))) | 88 | #define TDDATA0 (*((uint32_t volatile*)(0x3C700068))) |
89 | #define TDDATA1 (*((uint32_t volatile*)(0x3C70006C))) | 89 | #define TDDATA1 (*((uint32_t volatile*)(0x3C70006C))) |
90 | #define TDPRE (*((uint32_t volatile*)(0x3C700070))) | 90 | #define TDPRE (*((uint32_t volatile*)(0x3C700070))) |
91 | #define TDCNT (*((uint32_t volatile*)(0x3C700074))) | 91 | #define TDCNT (*((uint32_t volatile*)(0x3C700074))) |
92 | #define TECON (*((uint32_t volatile*)(0x3C7000A0))) | 92 | #define TECON (*((uint32_t volatile*)(0x3C7000A0))) |
93 | #define TECMD (*((uint32_t volatile*)(0x3C7000A4))) | 93 | #define TECMD (*((uint32_t volatile*)(0x3C7000A4))) |
94 | #define TEDATA0 (*((uint32_t volatile*)(0x3C7000A8))) | 94 | #define TEDATA0 (*((uint32_t volatile*)(0x3C7000A8))) |
95 | #define TEDATA1 (*((uint32_t volatile*)(0x3C7000AC))) | 95 | #define TEDATA1 (*((uint32_t volatile*)(0x3C7000AC))) |
96 | #define TEPRE (*((uint32_t volatile*)(0x3C7000B0))) | 96 | #define TEPRE (*((uint32_t volatile*)(0x3C7000B0))) |
97 | #define TECNT (*((uint32_t volatile*)(0x3C7000B4))) | 97 | #define TECNT (*((uint32_t volatile*)(0x3C7000B4))) |
98 | #define TFCON (*((uint32_t volatile*)(0x3C7000C0))) | 98 | #define TFCON (*((uint32_t volatile*)(0x3C7000C0))) |
99 | #define TFCMD (*((uint32_t volatile*)(0x3C7000C4))) | 99 | #define TFCMD (*((uint32_t volatile*)(0x3C7000C4))) |
100 | #define TFDATA0 (*((uint32_t volatile*)(0x3C7000C8))) | 100 | #define TFDATA0 (*((uint32_t volatile*)(0x3C7000C8))) |
101 | #define TFDATA1 (*((uint32_t volatile*)(0x3C7000CC))) | 101 | #define TFDATA1 (*((uint32_t volatile*)(0x3C7000CC))) |
102 | #define TFPRE (*((uint32_t volatile*)(0x3C7000D0))) | 102 | #define TFPRE (*((uint32_t volatile*)(0x3C7000D0))) |
103 | #define TFCNT (*((uint32_t volatile*)(0x3C7000D4))) | 103 | #define TFCNT (*((uint32_t volatile*)(0x3C7000D4))) |
104 | #define TGCON (*((uint32_t volatile*)(0x3C7000E0))) | 104 | #define TGCON (*((uint32_t volatile*)(0x3C7000E0))) |
105 | #define TGCMD (*((uint32_t volatile*)(0x3C7000E4))) | 105 | #define TGCMD (*((uint32_t volatile*)(0x3C7000E4))) |
106 | #define TGDATA0 (*((uint32_t volatile*)(0x3C7000E8))) | 106 | #define TGDATA0 (*((uint32_t volatile*)(0x3C7000E8))) |
107 | #define TGDATA1 (*((uint32_t volatile*)(0x3C7000EC))) | 107 | #define TGDATA1 (*((uint32_t volatile*)(0x3C7000EC))) |
108 | #define TGPRE (*((uint32_t volatile*)(0x3C7000F0))) | 108 | #define TGPRE (*((uint32_t volatile*)(0x3C7000F0))) |
109 | #define TGCNT (*((uint32_t volatile*)(0x3C7000F4))) | 109 | #define TGCNT (*((uint32_t volatile*)(0x3C7000F4))) |
110 | #define THCON (*((uint32_t volatile*)(0x3C700100))) | 110 | #define THCON (*((uint32_t volatile*)(0x3C700100))) |
111 | #define THCMD (*((uint32_t volatile*)(0x3C700104))) | 111 | #define THCMD (*((uint32_t volatile*)(0x3C700104))) |
112 | #define THDATA0 (*((uint32_t volatile*)(0x3C700108))) | 112 | #define THDATA0 (*((uint32_t volatile*)(0x3C700108))) |
113 | #define THDATA1 (*((uint32_t volatile*)(0x3C70010C))) | 113 | #define THDATA1 (*((uint32_t volatile*)(0x3C70010C))) |
114 | #define THPRE (*((uint32_t volatile*)(0x3C700110))) | 114 | #define THPRE (*((uint32_t volatile*)(0x3C700110))) |
115 | #define THCNT (*((uint32_t volatile*)(0x3C700114))) | 115 | #define THCNT (*((uint32_t volatile*)(0x3C700114))) |
116 | #define USEC_TIMER TECNT | 116 | #define USEC_TIMER TECNT |
117 | 117 | ||
118 | 118 | ||
119 | /////USB///// | 119 | /////USB///// |
120 | #define OTGBASE 0x38400000 | 120 | #define OTGBASE 0x38400000 |
121 | #define PHYBASE 0x3C400000 | 121 | #define PHYBASE 0x3C400000 |
122 | #define SYNOPSYSOTG_CLOCK 0 | 122 | #define SYNOPSYSOTG_CLOCK 0 |
123 | #define SYNOPSYSOTG_AHBCFG 0x2B | 123 | #define SYNOPSYSOTG_AHBCFG 0x2B |
124 | 124 | ||
125 | 125 | ||
126 | /////I2C///// | 126 | /////I2C///// |
127 | #define IICCON(bus) (*((uint32_t volatile*)(0x3C600000 + 0x300000 * (bus)))) | 127 | #define IICCON(bus) (*((uint32_t volatile*)(0x3C600000 + 0x300000 * (bus)))) |
128 | #define IICSTAT(bus) (*((uint32_t volatile*)(0x3C600004 + 0x300000 * (bus)))) | 128 | #define IICSTAT(bus) (*((uint32_t volatile*)(0x3C600004 + 0x300000 * (bus)))) |
129 | #define IICADD(bus) (*((uint32_t volatile*)(0x3C600008 + 0x300000 * (bus)))) | 129 | #define IICADD(bus) (*((uint32_t volatile*)(0x3C600008 + 0x300000 * (bus)))) |
130 | #define IICDS(bus) (*((uint32_t volatile*)(0x3C60000C + 0x300000 * (bus)))) | 130 | #define IICDS(bus) (*((uint32_t volatile*)(0x3C60000C + 0x300000 * (bus)))) |
131 | 131 | ||
132 | 132 | ||
133 | /////INTERRUPT CONTROLLERS///// | 133 | /////INTERRUPT CONTROLLERS///// |
134 | #define VICIRQSTATUS(v) (*((uint32_t volatile*)(0x38E00000 + 0x1000 * (v)))) | 134 | #define VICIRQSTATUS(v) (*((uint32_t volatile*)(0x38E00000 + 0x1000 * (v)))) |
135 | #define VICFIQSTATUS(v) (*((uint32_t volatile*)(0x38E00004 + 0x1000 * (v)))) | 135 | #define VICFIQSTATUS(v) (*((uint32_t volatile*)(0x38E00004 + 0x1000 * (v)))) |
136 | #define VICRAWINTR(v) (*((uint32_t volatile*)(0x38E00008 + 0x1000 * (v)))) | 136 | #define VICRAWINTR(v) (*((uint32_t volatile*)(0x38E00008 + 0x1000 * (v)))) |
137 | #define VICINTSELECT(v) (*((uint32_t volatile*)(0x38E0000C + 0x1000 * (v)))) | 137 | #define VICINTSELECT(v) (*((uint32_t volatile*)(0x38E0000C + 0x1000 * (v)))) |
138 | #define VICINTENABLE(v) (*((uint32_t volatile*)(0x38E00010 + 0x1000 * (v)))) | 138 | #define VICINTENABLE(v) (*((uint32_t volatile*)(0x38E00010 + 0x1000 * (v)))) |
139 | #define VICINTENCLEAR(v) (*((uint32_t volatile*)(0x38E00014 + 0x1000 * (v)))) | 139 | #define VICINTENCLEAR(v) (*((uint32_t volatile*)(0x38E00014 + 0x1000 * (v)))) |
140 | #define VICSOFTINT(v) (*((uint32_t volatile*)(0x38E00018 + 0x1000 * (v)))) | 140 | #define VICSOFTINT(v) (*((uint32_t volatile*)(0x38E00018 + 0x1000 * (v)))) |
141 | #define VICSOFTINTCLEAR(v) (*((uint32_t volatile*)(0x38E0001C + 0x1000 * (v)))) | 141 | #define VICSOFTINTCLEAR(v) (*((uint32_t volatile*)(0x38E0001C + 0x1000 * (v)))) |
142 | #define VICPROTECTION(v) (*((uint32_t volatile*)(0x38E00020 + 0x1000 * (v)))) | 142 | #define VICPROTECTION(v) (*((uint32_t volatile*)(0x38E00020 + 0x1000 * (v)))) |
143 | #define VICSWPRIORITYMASK(v) (*((uint32_t volatile*)(0x38E00024 + 0x1000 * (v)))) | 143 | #define VICSWPRIORITYMASK(v) (*((uint32_t volatile*)(0x38E00024 + 0x1000 * (v)))) |
144 | #define VICPRIORITYDAISY(v) (*((uint32_t volatile*)(0x38E00028 + 0x1000 * (v)))) | 144 | #define VICPRIORITYDAISY(v) (*((uint32_t volatile*)(0x38E00028 + 0x1000 * (v)))) |
145 | #define VICVECTADDR(v, i) (*((uint32_t volatile*)(0x38E00100 + 0x1000 * (v) + 4 * (i)))) | 145 | #define VICVECTADDR(v, i) (*((uint32_t volatile*)(0x38E00100 + 0x1000 * (v) + 4 * (i)))) |
146 | #define VICVECTPRIORITY(v, i) (*((uint32_t volatile*)(0x38E00200 + 0x1000 * (v) + 4 * (i)))) | 146 | #define VICVECTPRIORITY(v, i) (*((uint32_t volatile*)(0x38E00200 + 0x1000 * (v) + 4 * (i)))) |
147 | #define VICADDRESS(v) (*((const void* volatile*)(0x38E00F00 + 0x1000 * (v)))) | 147 | #define VICADDRESS(v) (*((const void* volatile*)(0x38E00F00 + 0x1000 * (v)))) |
148 | #define VIC0IRQSTATUS (*((uint32_t volatile*)(0x38E00000))) | 148 | #define VIC0IRQSTATUS (*((uint32_t volatile*)(0x38E00000))) |
149 | #define VIC0FIQSTATUS (*((uint32_t volatile*)(0x38E00004))) | 149 | #define VIC0FIQSTATUS (*((uint32_t volatile*)(0x38E00004))) |
150 | #define VIC0RAWINTR (*((uint32_t volatile*)(0x38E00008))) | 150 | #define VIC0RAWINTR (*((uint32_t volatile*)(0x38E00008))) |
151 | #define VIC0INTSELECT (*((uint32_t volatile*)(0x38E0000C))) | 151 | #define VIC0INTSELECT (*((uint32_t volatile*)(0x38E0000C))) |
152 | #define VIC0INTENABLE (*((uint32_t volatile*)(0x38E00010))) | 152 | #define VIC0INTENABLE (*((uint32_t volatile*)(0x38E00010))) |
153 | #define VIC0INTENCLEAR (*((uint32_t volatile*)(0x38E00014))) | 153 | #define VIC0INTENCLEAR (*((uint32_t volatile*)(0x38E00014))) |
154 | #define VIC0SOFTINT (*((uint32_t volatile*)(0x38E00018))) | 154 | #define VIC0SOFTINT (*((uint32_t volatile*)(0x38E00018))) |
155 | #define VIC0SOFTINTCLEAR (*((uint32_t volatile*)(0x38E0001C))) | 155 | #define VIC0SOFTINTCLEAR (*((uint32_t volatile*)(0x38E0001C))) |
156 | #define VIC0PROTECTION (*((uint32_t volatile*)(0x38E00020))) | 156 | #define VIC0PROTECTION (*((uint32_t volatile*)(0x38E00020))) |
157 | #define VIC0SWPRIORITYMASK (*((uint32_t volatile*)(0x38E00024))) | 157 | #define VIC0SWPRIORITYMASK (*((uint32_t volatile*)(0x38E00024))) |
158 | #define VIC0PRIORITYDAISY (*((uint32_t volatile*)(0x38E00028))) | 158 | #define VIC0PRIORITYDAISY (*((uint32_t volatile*)(0x38E00028))) |
159 | #define VIC0VECTADDR(i) (*((const void* volatile*)(0x38E00100 + 4 * (i)))) | 159 | #define VIC0VECTADDR(i) (*((const void* volatile*)(0x38E00100 + 4 * (i)))) |
160 | #define VIC0VECTADDR0 (*((const void* volatile*)(0x38E00100))) | 160 | #define VIC0VECTADDR0 (*((const void* volatile*)(0x38E00100))) |
161 | #define VIC0VECTADDR1 (*((const void* volatile*)(0x38E00104))) | 161 | #define VIC0VECTADDR1 (*((const void* volatile*)(0x38E00104))) |
162 | #define VIC0VECTADDR2 (*((const void* volatile*)(0x38E00108))) | 162 | #define VIC0VECTADDR2 (*((const void* volatile*)(0x38E00108))) |
163 | #define VIC0VECTADDR3 (*((const void* volatile*)(0x38E0010C))) | 163 | #define VIC0VECTADDR3 (*((const void* volatile*)(0x38E0010C))) |
164 | #define VIC0VECTADDR4 (*((const void* volatile*)(0x38E00110))) | 164 | #define VIC0VECTADDR4 (*((const void* volatile*)(0x38E00110))) |
165 | #define VIC0VECTADDR5 (*((const void* volatile*)(0x38E00114))) | 165 | #define VIC0VECTADDR5 (*((const void* volatile*)(0x38E00114))) |
166 | #define VIC0VECTADDR6 (*((const void* volatile*)(0x38E00118))) | 166 | #define VIC0VECTADDR6 (*((const void* volatile*)(0x38E00118))) |
167 | #define VIC0VECTADDR7 (*((const void* volatile*)(0x38E0011C))) | 167 | #define VIC0VECTADDR7 (*((const void* volatile*)(0x38E0011C))) |
168 | #define VIC0VECTADDR8 (*((const void* volatile*)(0x38E00120))) | 168 | #define VIC0VECTADDR8 (*((const void* volatile*)(0x38E00120))) |
169 | #define VIC0VECTADDR9 (*((const void* volatile*)(0x38E00124))) | 169 | #define VIC0VECTADDR9 (*((const void* volatile*)(0x38E00124))) |
170 | #define VIC0VECTADDR10 (*((const void* volatile*)(0x38E00128))) | 170 | #define VIC0VECTADDR10 (*((const void* volatile*)(0x38E00128))) |
171 | #define VIC0VECTADDR11 (*((const void* volatile*)(0x38E0012C))) | 171 | #define VIC0VECTADDR11 (*((const void* volatile*)(0x38E0012C))) |
172 | #define VIC0VECTADDR12 (*((const void* volatile*)(0x38E00130))) | 172 | #define VIC0VECTADDR12 (*((const void* volatile*)(0x38E00130))) |
173 | #define VIC0VECTADDR13 (*((const void* volatile*)(0x38E00134))) | 173 | #define VIC0VECTADDR13 (*((const void* volatile*)(0x38E00134))) |
174 | #define VIC0VECTADDR14 (*((const void* volatile*)(0x38E00138))) | 174 | #define VIC0VECTADDR14 (*((const void* volatile*)(0x38E00138))) |
175 | #define VIC0VECTADDR15 (*((const void* volatile*)(0x38E0013C))) | 175 | #define VIC0VECTADDR15 (*((const void* volatile*)(0x38E0013C))) |
176 | #define VIC0VECTADDR16 (*((const void* volatile*)(0x38E00140))) | 176 | #define VIC0VECTADDR16 (*((const void* volatile*)(0x38E00140))) |
177 | #define VIC0VECTADDR17 (*((const void* volatile*)(0x38E00144))) | 177 | #define VIC0VECTADDR17 (*((const void* volatile*)(0x38E00144))) |
178 | #define VIC0VECTADDR18 (*((const void* volatile*)(0x38E00148))) | 178 | #define VIC0VECTADDR18 (*((const void* volatile*)(0x38E00148))) |
179 | #define VIC0VECTADDR19 (*((const void* volatile*)(0x38E0014C))) | 179 | #define VIC0VECTADDR19 (*((const void* volatile*)(0x38E0014C))) |
180 | #define VIC0VECTADDR20 (*((const void* volatile*)(0x38E00150))) | 180 | #define VIC0VECTADDR20 (*((const void* volatile*)(0x38E00150))) |
181 | #define VIC0VECTADDR21 (*((const void* volatile*)(0x38E00154))) | 181 | #define VIC0VECTADDR21 (*((const void* volatile*)(0x38E00154))) |
182 | #define VIC0VECTADDR22 (*((const void* volatile*)(0x38E00158))) | 182 | #define VIC0VECTADDR22 (*((const void* volatile*)(0x38E00158))) |
183 | #define VIC0VECTADDR23 (*((const void* volatile*)(0x38E0015C))) | 183 | #define VIC0VECTADDR23 (*((const void* volatile*)(0x38E0015C))) |
184 | #define VIC0VECTADDR24 (*((const void* volatile*)(0x38E00160))) | 184 | #define VIC0VECTADDR24 (*((const void* volatile*)(0x38E00160))) |
185 | #define VIC0VECTADDR25 (*((const void* volatile*)(0x38E00164))) | 185 | #define VIC0VECTADDR25 (*((const void* volatile*)(0x38E00164))) |
186 | #define VIC0VECTADDR26 (*((const void* volatile*)(0x38E00168))) | 186 | #define VIC0VECTADDR26 (*((const void* volatile*)(0x38E00168))) |
187 | #define VIC0VECTADDR27 (*((const void* volatile*)(0x38E0016C))) | 187 | #define VIC0VECTADDR27 (*((const void* volatile*)(0x38E0016C))) |
188 | #define VIC0VECTADDR28 (*((const void* volatile*)(0x38E00170))) | 188 | #define VIC0VECTADDR28 (*((const void* volatile*)(0x38E00170))) |
189 | #define VIC0VECTADDR29 (*((const void* volatile*)(0x38E00174))) | 189 | #define VIC0VECTADDR29 (*((const void* volatile*)(0x38E00174))) |
190 | #define VIC0VECTADDR30 (*((const void* volatile*)(0x38E00178))) | 190 | #define VIC0VECTADDR30 (*((const void* volatile*)(0x38E00178))) |
191 | #define VIC0VECTADDR31 (*((const void* volatile*)(0x38E0017C))) | 191 | #define VIC0VECTADDR31 (*((const void* volatile*)(0x38E0017C))) |
192 | #define VIC0VECTPRIORITY(i) (*((uint32_t volatile*)(0x38E00200 + 4 * (i)))) | 192 | #define VIC0VECTPRIORITY(i) (*((uint32_t volatile*)(0x38E00200 + 4 * (i)))) |
193 | #define VIC0VECTPRIORITY0 (*((uint32_t volatile*)(0x38E00200))) | 193 | #define VIC0VECTPRIORITY0 (*((uint32_t volatile*)(0x38E00200))) |
194 | #define VIC0VECTPRIORITY1 (*((uint32_t volatile*)(0x38E00204))) | 194 | #define VIC0VECTPRIORITY1 (*((uint32_t volatile*)(0x38E00204))) |
195 | #define VIC0VECTPRIORITY2 (*((uint32_t volatile*)(0x38E00208))) | 195 | #define VIC0VECTPRIORITY2 (*((uint32_t volatile*)(0x38E00208))) |
196 | #define VIC0VECTPRIORITY3 (*((uint32_t volatile*)(0x38E0020C))) | 196 | #define VIC0VECTPRIORITY3 (*((uint32_t volatile*)(0x38E0020C))) |
197 | #define VIC0VECTPRIORITY4 (*((uint32_t volatile*)(0x38E00210))) | 197 | #define VIC0VECTPRIORITY4 (*((uint32_t volatile*)(0x38E00210))) |
198 | #define VIC0VECTPRIORITY5 (*((uint32_t volatile*)(0x38E00214))) | 198 | #define VIC0VECTPRIORITY5 (*((uint32_t volatile*)(0x38E00214))) |
199 | #define VIC0VECTPRIORITY6 (*((uint32_t volatile*)(0x38E00218))) | 199 | #define VIC0VECTPRIORITY6 (*((uint32_t volatile*)(0x38E00218))) |
200 | #define VIC0VECTPRIORITY7 (*((uint32_t volatile*)(0x38E0021C))) | 200 | #define VIC0VECTPRIORITY7 (*((uint32_t volatile*)(0x38E0021C))) |
201 | #define VIC0VECTPRIORITY8 (*((uint32_t volatile*)(0x38E00220))) | 201 | #define VIC0VECTPRIORITY8 (*((uint32_t volatile*)(0x38E00220))) |
202 | #define VIC0VECTPRIORITY9 (*((uint32_t volatile*)(0x38E00224))) | 202 | #define VIC0VECTPRIORITY9 (*((uint32_t volatile*)(0x38E00224))) |
203 | #define VIC0VECTPRIORITY10 (*((uint32_t volatile*)(0x38E00228))) | 203 | #define VIC0VECTPRIORITY10 (*((uint32_t volatile*)(0x38E00228))) |
204 | #define VIC0VECTPRIORITY11 (*((uint32_t volatile*)(0x38E0022C))) | 204 | #define VIC0VECTPRIORITY11 (*((uint32_t volatile*)(0x38E0022C))) |
205 | #define VIC0VECTPRIORITY12 (*((uint32_t volatile*)(0x38E00230))) | 205 | #define VIC0VECTPRIORITY12 (*((uint32_t volatile*)(0x38E00230))) |
206 | #define VIC0VECTPRIORITY13 (*((uint32_t volatile*)(0x38E00234))) | 206 | #define VIC0VECTPRIORITY13 (*((uint32_t volatile*)(0x38E00234))) |
207 | #define VIC0VECTPRIORITY14 (*((uint32_t volatile*)(0x38E00238))) | 207 | #define VIC0VECTPRIORITY14 (*((uint32_t volatile*)(0x38E00238))) |
208 | #define VIC0VECTPRIORITY15 (*((uint32_t volatile*)(0x38E0023C))) | 208 | #define VIC0VECTPRIORITY15 (*((uint32_t volatile*)(0x38E0023C))) |
209 | #define VIC0VECTPRIORITY16 (*((uint32_t volatile*)(0x38E00240))) | 209 | #define VIC0VECTPRIORITY16 (*((uint32_t volatile*)(0x38E00240))) |
210 | #define VIC0VECTPRIORITY17 (*((uint32_t volatile*)(0x38E00244))) | 210 | #define VIC0VECTPRIORITY17 (*((uint32_t volatile*)(0x38E00244))) |
211 | #define VIC0VECTPRIORITY18 (*((uint32_t volatile*)(0x38E00248))) | 211 | #define VIC0VECTPRIORITY18 (*((uint32_t volatile*)(0x38E00248))) |
212 | #define VIC0VECTPRIORITY19 (*((uint32_t volatile*)(0x38E0024C))) | 212 | #define VIC0VECTPRIORITY19 (*((uint32_t volatile*)(0x38E0024C))) |
213 | #define VIC0VECTPRIORITY20 (*((uint32_t volatile*)(0x38E00250))) | 213 | #define VIC0VECTPRIORITY20 (*((uint32_t volatile*)(0x38E00250))) |
214 | #define VIC0VECTPRIORITY21 (*((uint32_t volatile*)(0x38E00254))) | 214 | #define VIC0VECTPRIORITY21 (*((uint32_t volatile*)(0x38E00254))) |
215 | #define VIC0VECTPRIORITY22 (*((uint32_t volatile*)(0x38E00258))) | 215 | #define VIC0VECTPRIORITY22 (*((uint32_t volatile*)(0x38E00258))) |
216 | #define VIC0VECTPRIORITY23 (*((uint32_t volatile*)(0x38E0025C))) | 216 | #define VIC0VECTPRIORITY23 (*((uint32_t volatile*)(0x38E0025C))) |
217 | #define VIC0VECTPRIORITY24 (*((uint32_t volatile*)(0x38E00260))) | 217 | #define VIC0VECTPRIORITY24 (*((uint32_t volatile*)(0x38E00260))) |
218 | #define VIC0VECTPRIORITY25 (*((uint32_t volatile*)(0x38E00264))) | 218 | #define VIC0VECTPRIORITY25 (*((uint32_t volatile*)(0x38E00264))) |
219 | #define VIC0VECTPRIORITY26 (*((uint32_t volatile*)(0x38E00268))) | 219 | #define VIC0VECTPRIORITY26 (*((uint32_t volatile*)(0x38E00268))) |
220 | #define VIC0VECTPRIORITY27 (*((uint32_t volatile*)(0x38E0026C))) | 220 | #define VIC0VECTPRIORITY27 (*((uint32_t volatile*)(0x38E0026C))) |
221 | #define VIC0VECTPRIORITY28 (*((uint32_t volatile*)(0x38E00270))) | 221 | #define VIC0VECTPRIORITY28 (*((uint32_t volatile*)(0x38E00270))) |
222 | #define VIC0VECTPRIORITY29 (*((uint32_t volatile*)(0x38E00274))) | 222 | #define VIC0VECTPRIORITY29 (*((uint32_t volatile*)(0x38E00274))) |
223 | #define VIC0VECTPRIORITY30 (*((uint32_t volatile*)(0x38E00278))) | 223 | #define VIC0VECTPRIORITY30 (*((uint32_t volatile*)(0x38E00278))) |
224 | #define VIC0VECTPRIORITY31 (*((uint32_t volatile*)(0x38E0027C))) | 224 | #define VIC0VECTPRIORITY31 (*((uint32_t volatile*)(0x38E0027C))) |
225 | #define VIC0ADDRESS (*((void* volatile*)(0x38E00F00))) | 225 | #define VIC0ADDRESS (*((void* volatile*)(0x38E00F00))) |
226 | #define VIC1IRQSTATUS (*((uint32_t volatile*)(0x38E01000))) | 226 | #define VIC1IRQSTATUS (*((uint32_t volatile*)(0x38E01000))) |
227 | #define VIC1FIQSTATUS (*((uint32_t volatile*)(0x38E01004))) | 227 | #define VIC1FIQSTATUS (*((uint32_t volatile*)(0x38E01004))) |
228 | #define VIC1RAWINTR (*((uint32_t volatile*)(0x38E01008))) | 228 | #define VIC1RAWINTR (*((uint32_t volatile*)(0x38E01008))) |
229 | #define VIC1INTSELECT (*((uint32_t volatile*)(0x38E0100C))) | 229 | #define VIC1INTSELECT (*((uint32_t volatile*)(0x38E0100C))) |
230 | #define VIC1INTENABLE (*((uint32_t volatile*)(0x38E01010))) | 230 | #define VIC1INTENABLE (*((uint32_t volatile*)(0x38E01010))) |
231 | #define VIC1INTENCLEAR (*((uint32_t volatile*)(0x38E01014))) | 231 | #define VIC1INTENCLEAR (*((uint32_t volatile*)(0x38E01014))) |
232 | #define VIC1SOFTINT (*((uint32_t volatile*)(0x38E01018))) | 232 | #define VIC1SOFTINT (*((uint32_t volatile*)(0x38E01018))) |
233 | #define VIC1SOFTINTCLEAR (*((uint32_t volatile*)(0x38E0101C))) | 233 | #define VIC1SOFTINTCLEAR (*((uint32_t volatile*)(0x38E0101C))) |
234 | #define VIC1PROTECTION (*((uint32_t volatile*)(0x38E01020))) | 234 | #define VIC1PROTECTION (*((uint32_t volatile*)(0x38E01020))) |
235 | #define VIC1SWPRIORITYMASK (*((uint32_t volatile*)(0x38E01024))) | 235 | #define VIC1SWPRIORITYMASK (*((uint32_t volatile*)(0x38E01024))) |
236 | #define VIC1PRIORITYDAISY (*((uint32_t volatile*)(0x38E01028))) | 236 | #define VIC1PRIORITYDAISY (*((uint32_t volatile*)(0x38E01028))) |
237 | #define VIC1VECTADDR(i) (*((const void* volatile*)(0x38E01100 + 4 * (i)))) | 237 | #define VIC1VECTADDR(i) (*((const void* volatile*)(0x38E01100 + 4 * (i)))) |
238 | #define VIC1VECTADDR0 (*((const void* volatile*)(0x38E01100))) | 238 | #define VIC1VECTADDR0 (*((const void* volatile*)(0x38E01100))) |
239 | #define VIC1VECTADDR1 (*((const void* volatile*)(0x38E01104))) | 239 | #define VIC1VECTADDR1 (*((const void* volatile*)(0x38E01104))) |
240 | #define VIC1VECTADDR2 (*((const void* volatile*)(0x38E01108))) | 240 | #define VIC1VECTADDR2 (*((const void* volatile*)(0x38E01108))) |
241 | #define VIC1VECTADDR3 (*((const void* volatile*)(0x38E0110C))) | 241 | #define VIC1VECTADDR3 (*((const void* volatile*)(0x38E0110C))) |
242 | #define VIC1VECTADDR4 (*((const void* volatile*)(0x38E01110))) | 242 | #define VIC1VECTADDR4 (*((const void* volatile*)(0x38E01110))) |
243 | #define VIC1VECTADDR5 (*((const void* volatile*)(0x38E01114))) | 243 | #define VIC1VECTADDR5 (*((const void* volatile*)(0x38E01114))) |
244 | #define VIC1VECTADDR6 (*((const void* volatile*)(0x38E01118))) | 244 | #define VIC1VECTADDR6 (*((const void* volatile*)(0x38E01118))) |
245 | #define VIC1VECTADDR7 (*((const void* volatile*)(0x38E0111C))) | 245 | #define VIC1VECTADDR7 (*((const void* volatile*)(0x38E0111C))) |
246 | #define VIC1VECTADDR8 (*((const void* volatile*)(0x38E01120))) | 246 | #define VIC1VECTADDR8 (*((const void* volatile*)(0x38E01120))) |
247 | #define VIC1VECTADDR9 (*((const void* volatile*)(0x38E01124))) | 247 | #define VIC1VECTADDR9 (*((const void* volatile*)(0x38E01124))) |
248 | #define VIC1VECTADDR10 (*((const void* volatile*)(0x38E01128))) | 248 | #define VIC1VECTADDR10 (*((const void* volatile*)(0x38E01128))) |
249 | #define VIC1VECTADDR11 (*((const void* volatile*)(0x38E0112C))) | 249 | #define VIC1VECTADDR11 (*((const void* volatile*)(0x38E0112C))) |
250 | #define VIC1VECTADDR12 (*((const void* volatile*)(0x38E01130))) | 250 | #define VIC1VECTADDR12 (*((const void* volatile*)(0x38E01130))) |
251 | #define VIC1VECTADDR13 (*((const void* volatile*)(0x38E01134))) | 251 | #define VIC1VECTADDR13 (*((const void* volatile*)(0x38E01134))) |
252 | #define VIC1VECTADDR14 (*((const void* volatile*)(0x38E01138))) | 252 | #define VIC1VECTADDR14 (*((const void* volatile*)(0x38E01138))) |
253 | #define VIC1VECTADDR15 (*((const void* volatile*)(0x38E0113C))) | 253 | #define VIC1VECTADDR15 (*((const void* volatile*)(0x38E0113C))) |
254 | #define VIC1VECTADDR16 (*((const void* volatile*)(0x38E01140))) | 254 | #define VIC1VECTADDR16 (*((const void* volatile*)(0x38E01140))) |
255 | #define VIC1VECTADDR17 (*((const void* volatile*)(0x38E01144))) | 255 | #define VIC1VECTADDR17 (*((const void* volatile*)(0x38E01144))) |
256 | #define VIC1VECTADDR18 (*((const void* volatile*)(0x38E01148))) | 256 | #define VIC1VECTADDR18 (*((const void* volatile*)(0x38E01148))) |
257 | #define VIC1VECTADDR19 (*((const void* volatile*)(0x38E0114C))) | 257 | #define VIC1VECTADDR19 (*((const void* volatile*)(0x38E0114C))) |
258 | #define VIC1VECTADDR20 (*((const void* volatile*)(0x38E01150))) | 258 | #define VIC1VECTADDR20 (*((const void* volatile*)(0x38E01150))) |
259 | #define VIC1VECTADDR21 (*((const void* volatile*)(0x38E01154))) | 259 | #define VIC1VECTADDR21 (*((const void* volatile*)(0x38E01154))) |
260 | #define VIC1VECTADDR22 (*((const void* volatile*)(0x38E01158))) | 260 | #define VIC1VECTADDR22 (*((const void* volatile*)(0x38E01158))) |
261 | #define VIC1VECTADDR23 (*((const void* volatile*)(0x38E0115C))) | 261 | #define VIC1VECTADDR23 (*((const void* volatile*)(0x38E0115C))) |
262 | #define VIC1VECTADDR24 (*((const void* volatile*)(0x38E01160))) | 262 | #define VIC1VECTADDR24 (*((const void* volatile*)(0x38E01160))) |
263 | #define VIC1VECTADDR25 (*((const void* volatile*)(0x38E01164))) | 263 | #define VIC1VECTADDR25 (*((const void* volatile*)(0x38E01164))) |
264 | #define VIC1VECTADDR26 (*((const void* volatile*)(0x38E01168))) | 264 | #define VIC1VECTADDR26 (*((const void* volatile*)(0x38E01168))) |
265 | #define VIC1VECTADDR27 (*((const void* volatile*)(0x38E0116C))) | 265 | #define VIC1VECTADDR27 (*((const void* volatile*)(0x38E0116C))) |
266 | #define VIC1VECTADDR28 (*((const void* volatile*)(0x38E01170))) | 266 | #define VIC1VECTADDR28 (*((const void* volatile*)(0x38E01170))) |
267 | #define VIC1VECTADDR29 (*((const void* volatile*)(0x38E01174))) | 267 | #define VIC1VECTADDR29 (*((const void* volatile*)(0x38E01174))) |
268 | #define VIC1VECTADDR30 (*((const void* volatile*)(0x38E01178))) | 268 | #define VIC1VECTADDR30 (*((const void* volatile*)(0x38E01178))) |
269 | #define VIC1VECTADDR31 (*((const void* volatile*)(0x38E0117C))) | 269 | #define VIC1VECTADDR31 (*((const void* volatile*)(0x38E0117C))) |
270 | #define VIC1VECTPRIORITY(i) (*((uint32_t volatile*)(0x38E01200 + 4 * (i)))) | 270 | #define VIC1VECTPRIORITY(i) (*((uint32_t volatile*)(0x38E01200 + 4 * (i)))) |
271 | #define VIC1VECTPRIORITY0 (*((uint32_t volatile*)(0x38E01200))) | 271 | #define VIC1VECTPRIORITY0 (*((uint32_t volatile*)(0x38E01200))) |
272 | #define VIC1VECTPRIORITY1 (*((uint32_t volatile*)(0x38E01204))) | 272 | #define VIC1VECTPRIORITY1 (*((uint32_t volatile*)(0x38E01204))) |
273 | #define VIC1VECTPRIORITY2 (*((uint32_t volatile*)(0x38E01208))) | 273 | #define VIC1VECTPRIORITY2 (*((uint32_t volatile*)(0x38E01208))) |
274 | #define VIC1VECTPRIORITY3 (*((uint32_t volatile*)(0x38E0120C))) | 274 | #define VIC1VECTPRIORITY3 (*((uint32_t volatile*)(0x38E0120C))) |
275 | #define VIC1VECTPRIORITY4 (*((uint32_t volatile*)(0x38E01210))) | 275 | #define VIC1VECTPRIORITY4 (*((uint32_t volatile*)(0x38E01210))) |
276 | #define VIC1VECTPRIORITY5 (*((uint32_t volatile*)(0x38E01214))) | 276 | #define VIC1VECTPRIORITY5 (*((uint32_t volatile*)(0x38E01214))) |
277 | #define VIC1VECTPRIORITY6 (*((uint32_t volatile*)(0x38E01218))) | 277 | #define VIC1VECTPRIORITY6 (*((uint32_t volatile*)(0x38E01218))) |
278 | #define VIC1VECTPRIORITY7 (*((uint32_t volatile*)(0x38E0121C))) | 278 | #define VIC1VECTPRIORITY7 (*((uint32_t volatile*)(0x38E0121C))) |
279 | #define VIC1VECTPRIORITY8 (*((uint32_t volatile*)(0x38E01220))) | 279 | #define VIC1VECTPRIORITY8 (*((uint32_t volatile*)(0x38E01220))) |
280 | #define VIC1VECTPRIORITY9 (*((uint32_t volatile*)(0x38E01224))) | 280 | #define VIC1VECTPRIORITY9 (*((uint32_t volatile*)(0x38E01224))) |
281 | #define VIC1VECTPRIORITY10 (*((uint32_t volatile*)(0x38E01228))) | 281 | #define VIC1VECTPRIORITY10 (*((uint32_t volatile*)(0x38E01228))) |
282 | #define VIC1VECTPRIORITY11 (*((uint32_t volatile*)(0x38E0122C))) | 282 | #define VIC1VECTPRIORITY11 (*((uint32_t volatile*)(0x38E0122C))) |
283 | #define VIC1VECTPRIORITY12 (*((uint32_t volatile*)(0x38E01230))) | 283 | #define VIC1VECTPRIORITY12 (*((uint32_t volatile*)(0x38E01230))) |
284 | #define VIC1VECTPRIORITY13 (*((uint32_t volatile*)(0x38E01234))) | 284 | #define VIC1VECTPRIORITY13 (*((uint32_t volatile*)(0x38E01234))) |
285 | #define VIC1VECTPRIORITY14 (*((uint32_t volatile*)(0x38E01238))) | 285 | #define VIC1VECTPRIORITY14 (*((uint32_t volatile*)(0x38E01238))) |
286 | #define VIC1VECTPRIORITY15 (*((uint32_t volatile*)(0x38E0123C))) | 286 | #define VIC1VECTPRIORITY15 (*((uint32_t volatile*)(0x38E0123C))) |
287 | #define VIC1VECTPRIORITY16 (*((uint32_t volatile*)(0x38E01240))) | 287 | #define VIC1VECTPRIORITY16 (*((uint32_t volatile*)(0x38E01240))) |
288 | #define VIC1VECTPRIORITY17 (*((uint32_t volatile*)(0x38E01244))) | 288 | #define VIC1VECTPRIORITY17 (*((uint32_t volatile*)(0x38E01244))) |
289 | #define VIC1VECTPRIORITY18 (*((uint32_t volatile*)(0x38E01248))) | 289 | #define VIC1VECTPRIORITY18 (*((uint32_t volatile*)(0x38E01248))) |
290 | #define VIC1VECTPRIORITY19 (*((uint32_t volatile*)(0x38E0124C))) | 290 | #define VIC1VECTPRIORITY19 (*((uint32_t volatile*)(0x38E0124C))) |
291 | #define VIC1VECTPRIORITY20 (*((uint32_t volatile*)(0x38E01250))) | 291 | #define VIC1VECTPRIORITY20 (*((uint32_t volatile*)(0x38E01250))) |
292 | #define VIC1VECTPRIORITY21 (*((uint32_t volatile*)(0x38E01254))) | 292 | #define VIC1VECTPRIORITY21 (*((uint32_t volatile*)(0x38E01254))) |
293 | #define VIC1VECTPRIORITY22 (*((uint32_t volatile*)(0x38E01258))) | 293 | #define VIC1VECTPRIORITY22 (*((uint32_t volatile*)(0x38E01258))) |
294 | #define VIC1VECTPRIORITY23 (*((uint32_t volatile*)(0x38E0125C))) | 294 | #define VIC1VECTPRIORITY23 (*((uint32_t volatile*)(0x38E0125C))) |
295 | #define VIC1VECTPRIORITY24 (*((uint32_t volatile*)(0x38E01260))) | 295 | #define VIC1VECTPRIORITY24 (*((uint32_t volatile*)(0x38E01260))) |
296 | #define VIC1VECTPRIORITY25 (*((uint32_t volatile*)(0x38E01264))) | 296 | #define VIC1VECTPRIORITY25 (*((uint32_t volatile*)(0x38E01264))) |
297 | #define VIC1VECTPRIORITY26 (*((uint32_t volatile*)(0x38E01268))) | 297 | #define VIC1VECTPRIORITY26 (*((uint32_t volatile*)(0x38E01268))) |
298 | #define VIC1VECTPRIORITY27 (*((uint32_t volatile*)(0x38E0126C))) | 298 | #define VIC1VECTPRIORITY27 (*((uint32_t volatile*)(0x38E0126C))) |
299 | #define VIC1VECTPRIORITY28 (*((uint32_t volatile*)(0x38E01270))) | 299 | #define VIC1VECTPRIORITY28 (*((uint32_t volatile*)(0x38E01270))) |
300 | #define VIC1VECTPRIORITY29 (*((uint32_t volatile*)(0x38E01274))) | 300 | #define VIC1VECTPRIORITY29 (*((uint32_t volatile*)(0x38E01274))) |
301 | #define VIC1VECTPRIORITY30 (*((uint32_t volatile*)(0x38E01278))) | 301 | #define VIC1VECTPRIORITY30 (*((uint32_t volatile*)(0x38E01278))) |
302 | #define VIC1VECTPRIORITY31 (*((uint32_t volatile*)(0x38E0127C))) | 302 | #define VIC1VECTPRIORITY31 (*((uint32_t volatile*)(0x38E0127C))) |
303 | #define VIC1ADDRESS (*((void* volatile*)(0x38E01F00))) | 303 | #define VIC1ADDRESS (*((void* volatile*)(0x38E01F00))) |
304 | 304 | ||
305 | 305 | ||
306 | /////GPIO///// | 306 | /////GPIO///// |
307 | #define PCON(i) (*((uint32_t volatile*)(0x3cf00000 + ((i) << 5)))) | 307 | #define PCON(i) (*((uint32_t volatile*)(0x3cf00000 + ((i) << 5)))) |
308 | #define PDAT(i) (*((uint32_t volatile*)(0x3cf00004 + ((i) << 5)))) | 308 | #define PDAT(i) (*((uint32_t volatile*)(0x3cf00004 + ((i) << 5)))) |
309 | #define PUNA(i) (*((uint32_t volatile*)(0x3cf00008 + ((i) << 5)))) | 309 | #define PUNA(i) (*((uint32_t volatile*)(0x3cf00008 + ((i) << 5)))) |
310 | #define PUNB(i) (*((uint32_t volatile*)(0x3cf0000c + ((i) << 5)))) | 310 | #define PUNB(i) (*((uint32_t volatile*)(0x3cf0000c + ((i) << 5)))) |
311 | #define PCON0 (*((uint32_t volatile*)(0x3cf00000))) | 311 | #define PCON0 (*((uint32_t volatile*)(0x3cf00000))) |
312 | #define PDAT0 (*((uint32_t volatile*)(0x3cf00004))) | 312 | #define PDAT0 (*((uint32_t volatile*)(0x3cf00004))) |
313 | #define PCON1 (*((uint32_t volatile*)(0x3cf00020))) | 313 | #define PCON1 (*((uint32_t volatile*)(0x3cf00020))) |
314 | #define PDAT1 (*((uint32_t volatile*)(0x3cf00024))) | 314 | #define PDAT1 (*((uint32_t volatile*)(0x3cf00024))) |
315 | #define PCON2 (*((uint32_t volatile*)(0x3cf00040))) | 315 | #define PCON2 (*((uint32_t volatile*)(0x3cf00040))) |
316 | #define PDAT2 (*((uint32_t volatile*)(0x3cf00044))) | 316 | #define PDAT2 (*((uint32_t volatile*)(0x3cf00044))) |
317 | #define PCON3 (*((uint32_t volatile*)(0x3cf00060))) | 317 | #define PCON3 (*((uint32_t volatile*)(0x3cf00060))) |
318 | #define PDAT3 (*((uint32_t volatile*)(0x3cf00064))) | 318 | #define PDAT3 (*((uint32_t volatile*)(0x3cf00064))) |
319 | #define PCON4 (*((uint32_t volatile*)(0x3cf00080))) | 319 | #define PCON4 (*((uint32_t volatile*)(0x3cf00080))) |
320 | #define PDAT4 (*((uint32_t volatile*)(0x3cf00084))) | 320 | #define PDAT4 (*((uint32_t volatile*)(0x3cf00084))) |
321 | #define PCON5 (*((uint32_t volatile*)(0x3cf000a0))) | 321 | #define PCON5 (*((uint32_t volatile*)(0x3cf000a0))) |
322 | #define PDAT5 (*((uint32_t volatile*)(0x3cf000a4))) | 322 | #define PDAT5 (*((uint32_t volatile*)(0x3cf000a4))) |
323 | #define PCON6 (*((uint32_t volatile*)(0x3cf000c0))) | 323 | #define PCON6 (*((uint32_t volatile*)(0x3cf000c0))) |
324 | #define PDAT6 (*((uint32_t volatile*)(0x3cf000c4))) | 324 | #define PDAT6 (*((uint32_t volatile*)(0x3cf000c4))) |
325 | #define PCON7 (*((uint32_t volatile*)(0x3cf000e0))) | 325 | #define PCON7 (*((uint32_t volatile*)(0x3cf000e0))) |
326 | #define PDAT7 (*((uint32_t volatile*)(0x3cf000e4))) | 326 | #define PDAT7 (*((uint32_t volatile*)(0x3cf000e4))) |
327 | #define PCON8 (*((uint32_t volatile*)(0x3cf00100))) | 327 | #define PCON8 (*((uint32_t volatile*)(0x3cf00100))) |
328 | #define PDAT8 (*((uint32_t volatile*)(0x3cf00104))) | 328 | #define PDAT8 (*((uint32_t volatile*)(0x3cf00104))) |
329 | #define PCON9 (*((uint32_t volatile*)(0x3cf00120))) | 329 | #define PCON9 (*((uint32_t volatile*)(0x3cf00120))) |
330 | #define PDAT9 (*((uint32_t volatile*)(0x3cf00124))) | 330 | #define PDAT9 (*((uint32_t volatile*)(0x3cf00124))) |
331 | #define PCONA (*((uint32_t volatile*)(0x3cf00140))) | 331 | #define PCONA (*((uint32_t volatile*)(0x3cf00140))) |
332 | #define PDATA (*((uint32_t volatile*)(0x3cf00144))) | 332 | #define PDATA (*((uint32_t volatile*)(0x3cf00144))) |
333 | #define PCONB (*((uint32_t volatile*)(0x3cf00160))) | 333 | #define PCONB (*((uint32_t volatile*)(0x3cf00160))) |
334 | #define PDATB (*((uint32_t volatile*)(0x3cf00164))) | 334 | #define PDATB (*((uint32_t volatile*)(0x3cf00164))) |
335 | #define PCONC (*((uint32_t volatile*)(0x3cf00180))) | 335 | #define PCONC (*((uint32_t volatile*)(0x3cf00180))) |
336 | #define PDATC (*((uint32_t volatile*)(0x3cf00184))) | 336 | #define PDATC (*((uint32_t volatile*)(0x3cf00184))) |
337 | #define PCOND (*((uint32_t volatile*)(0x3cf001a0))) | 337 | #define PCOND (*((uint32_t volatile*)(0x3cf001a0))) |
338 | #define PDATD (*((uint32_t volatile*)(0x3cf001a4))) | 338 | #define PDATD (*((uint32_t volatile*)(0x3cf001a4))) |
339 | #define PCONE (*((uint32_t volatile*)(0x3cf001c0))) | 339 | #define PCONE (*((uint32_t volatile*)(0x3cf001c0))) |
340 | #define PDATE (*((uint32_t volatile*)(0x3cf001c4))) | 340 | #define PDATE (*((uint32_t volatile*)(0x3cf001c4))) |
341 | #define PCONF (*((uint32_t volatile*)(0x3cf001e0))) | 341 | #define PCONF (*((uint32_t volatile*)(0x3cf001e0))) |
342 | #define PDATF (*((uint32_t volatile*)(0x3cf001e4))) | 342 | #define PDATF (*((uint32_t volatile*)(0x3cf001e4))) |
343 | #define GPIOCMD (*((uint32_t volatile*)(0x3cf00200))) | 343 | #define GPIOCMD (*((uint32_t volatile*)(0x3cf00200))) |
344 | 344 | ||
345 | 345 | ||
346 | /////SPI///// | 346 | /////SPI///// |
347 | #define SPIBASE(i) ((i) == 2 ? 0x3d200000 : \ | 347 | #define SPIBASE(i) ((i) == 2 ? 0x3d200000 : \ |
348 | (i) == 1 ? 0x3ce00000 : \ | 348 | (i) == 1 ? 0x3ce00000 : \ |
349 | 0x3c300000) | 349 | 0x3c300000) |
350 | #define SPICLKGATE(i) ((i) == 2 ? 0x2f : \ | 350 | #define SPICLKGATE(i) ((i) == 2 ? 0x2f : \ |
351 | (i) == 1 ? 0x2b : \ | 351 | (i) == 1 ? 0x2b : \ |
352 | 0x22) | 352 | 0x22) |
353 | #define SPIDMA(i) ((i) == 2 ? 0xd : \ | 353 | #define SPIDMA(i) ((i) == 2 ? 0xd : \ |
354 | (i) == 1 ? 0xf : \ | 354 | (i) == 1 ? 0xf : \ |
355 | 0x5) | 355 | 0x5) |
356 | #define SPICTRL(i) (*((uint32_t volatile*)(SPIBASE(i)))) | 356 | #define SPICTRL(i) (*((uint32_t volatile*)(SPIBASE(i)))) |
357 | #define SPISETUP(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x4))) | 357 | #define SPISETUP(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x4))) |
358 | #define SPISTATUS(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x8))) | 358 | #define SPISTATUS(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x8))) |
359 | #define SPIUNKREG1(i) (*((uint32_t volatile*)(SPIBASE(i) + 0xc))) | 359 | #define SPIUNKREG1(i) (*((uint32_t volatile*)(SPIBASE(i) + 0xc))) |
360 | #define SPITXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x10))) | 360 | #define SPITXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x10))) |
361 | #define SPIRXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x20))) | 361 | #define SPIRXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x20))) |
362 | #define SPICLKDIV(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x30))) | 362 | #define SPICLKDIV(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x30))) |
363 | #define SPIRXLIMIT(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x34))) | 363 | #define SPIRXLIMIT(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x34))) |
364 | #define SPIUNKREG3(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x38))) | 364 | #define SPIUNKREG3(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x38))) |
365 | 365 | ||
366 | 366 | ||
367 | /////AES///// | 367 | /////AES///// |
368 | #define AESCONTROL (*((uint32_t volatile*)(0x38c00000))) | 368 | #define AESCONTROL (*((uint32_t volatile*)(0x38c00000))) |
369 | #define AESGO (*((uint32_t volatile*)(0x38c00004))) | 369 | #define AESGO (*((uint32_t volatile*)(0x38c00004))) |
370 | #define AESUNKREG0 (*((uint32_t volatile*)(0x38c00008))) | 370 | #define AESUNKREG0 (*((uint32_t volatile*)(0x38c00008))) |
371 | #define AESSTATUS (*((uint32_t volatile*)(0x38c0000c))) | 371 | #define AESSTATUS (*((uint32_t volatile*)(0x38c0000c))) |
372 | #define AESUNKREG1 (*((uint32_t volatile*)(0x38c00010))) | 372 | #define AESUNKREG1 (*((uint32_t volatile*)(0x38c00010))) |
373 | #define AESKEYLEN (*((uint32_t volatile*)(0x38c00014))) | 373 | #define AESKEYLEN (*((uint32_t volatile*)(0x38c00014))) |
374 | #define AESOUTSIZE (*((uint32_t volatile*)(0x38c00018))) | 374 | #define AESOUTSIZE (*((uint32_t volatile*)(0x38c00018))) |
375 | #define AESOUTADDR (*((void* volatile*)(0x38c00020))) | 375 | #define AESOUTADDR (*((void* volatile*)(0x38c00020))) |
376 | #define AESINSIZE (*((uint32_t volatile*)(0x38c00024))) | 376 | #define AESINSIZE (*((uint32_t volatile*)(0x38c00024))) |
377 | #define AESINADDR (*((const void* volatile*)(0x38c00028))) | 377 | #define AESINADDR (*((const void* volatile*)(0x38c00028))) |
378 | #define AESAUXSIZE (*((uint32_t volatile*)(0x38c0002c))) | 378 | #define AESAUXSIZE (*((uint32_t volatile*)(0x38c0002c))) |
379 | #define AESAUXADDR (*((void* volatile*)(0x38c00030))) | 379 | #define AESAUXADDR (*((void* volatile*)(0x38c00030))) |
380 | #define AESSIZE3 (*((uint32_t volatile*)(0x38c00034))) | 380 | #define AESSIZE3 (*((uint32_t volatile*)(0x38c00034))) |
381 | #define AESKEY ((uint32_t volatile*)(0x38c0004c)) | 381 | #define AESKEY ((uint32_t volatile*)(0x38c0004c)) |
382 | #define AESTYPE (*((uint32_t volatile*)(0x38c0006c))) | 382 | #define AESTYPE (*((uint32_t volatile*)(0x38c0006c))) |
383 | #define AESIV ((uint32_t volatile*)(0x38c00074)) | 383 | #define AESIV ((uint32_t volatile*)(0x38c00074)) |
384 | #define AESTYPE2 (*((uint32_t volatile*)(0x38c00088))) | 384 | #define AESTYPE2 (*((uint32_t volatile*)(0x38c00088))) |
385 | #define AESUNKREG2 (*((uint32_t volatile*)(0x38c0008c))) | 385 | #define AESUNKREG2 (*((uint32_t volatile*)(0x38c0008c))) |
386 | 386 | ||
387 | 387 | ||
388 | /////SHA1///// | 388 | /////SHA1///// |
389 | #define SHA1CONFIG (*((uint32_t volatile*)(0x38000000))) | 389 | #define SHA1CONFIG (*((uint32_t volatile*)(0x38000000))) |
390 | #define SHA1RESET (*((uint32_t volatile*)(0x38000004))) | 390 | #define SHA1RESET (*((uint32_t volatile*)(0x38000004))) |
391 | #define SHA1RESULT ((uint32_t volatile*)(0x38000020)) | 391 | #define SHA1RESULT ((uint32_t volatile*)(0x38000020)) |
392 | #define SHA1DATAIN ((uint32_t volatile*)(0x38000040)) | 392 | #define SHA1DATAIN ((uint32_t volatile*)(0x38000040)) |
393 | 393 | ||
394 | 394 | ||
395 | /////DMA///// | 395 | /////DMA///// |
396 | #ifndef ASM | 396 | #ifndef ASM |
397 | struct dma_lli | 397 | struct dma_lli |
398 | { | 398 | { |
399 | const void* srcaddr; | 399 | const void* srcaddr; |
400 | void* dstaddr; | 400 | void* dstaddr; |
401 | const struct dma_lli* nextlli; | 401 | const struct dma_lli* nextlli; |
402 | uint32_t control; | 402 | uint32_t control; |
403 | }; | 403 | }; |
404 | #endif | 404 | #endif |
405 | #define DMACINTSTS(d) (*((uint32_t volatile*)(0x38200000 + 0x1700000 * (d)))) | 405 | #define DMACINTSTS(d) (*((uint32_t volatile*)(0x38200000 + 0x1700000 * (d)))) |
406 | #define DMACINTTCSTS(d) (*((uint32_t volatile*)(0x38200004 + 0x1700000 * (d)))) | 406 | #define DMACINTTCSTS(d) (*((uint32_t volatile*)(0x38200004 + 0x1700000 * (d)))) |
407 | #define DMACINTTCCLR(d) (*((uint32_t volatile*)(0x38200008 + 0x1700000 * (d)))) | 407 | #define DMACINTTCCLR(d) (*((uint32_t volatile*)(0x38200008 + 0x1700000 * (d)))) |
408 | #define DMACINTERRSTS(d) (*((uint32_t volatile*)(0x3820000c + 0x1700000 * (d)))) | 408 | #define DMACINTERRSTS(d) (*((uint32_t volatile*)(0x3820000c + 0x1700000 * (d)))) |
409 | #define DMACINTERRCLR(d) (*((uint32_t volatile*)(0x38200010 + 0x1700000 * (d)))) | 409 | #define DMACINTERRCLR(d) (*((uint32_t volatile*)(0x38200010 + 0x1700000 * (d)))) |
410 | #define DMACRAWINTTCSTS(d) (*((uint32_t volatile*)(0x38200014 + 0x1700000 * (d)))) | 410 | #define DMACRAWINTTCSTS(d) (*((uint32_t volatile*)(0x38200014 + 0x1700000 * (d)))) |
411 | #define DMACRAWINTERRSTS(d) (*((uint32_t volatile*)(0x38200018 + 0x1700000 * (d)))) | 411 | #define DMACRAWINTERRSTS(d) (*((uint32_t volatile*)(0x38200018 + 0x1700000 * (d)))) |
412 | #define DMACENABLEDCHANS(d) (*((uint32_t volatile*)(0x3820001c + 0x1700000 * (d)))) | 412 | #define DMACENABLEDCHANS(d) (*((uint32_t volatile*)(0x3820001c + 0x1700000 * (d)))) |
413 | #define DMACSOFTBREQ(d) (*((uint32_t volatile*)(0x38200020 + 0x1700000 * (d)))) | 413 | #define DMACSOFTBREQ(d) (*((uint32_t volatile*)(0x38200020 + 0x1700000 * (d)))) |
414 | #define DMACSOFTSREQ(d) (*((uint32_t volatile*)(0x38200024 + 0x1700000 * (d)))) | 414 | #define DMACSOFTSREQ(d) (*((uint32_t volatile*)(0x38200024 + 0x1700000 * (d)))) |
415 | #define DMACSOFTLBREQ(d) (*((uint32_t volatile*)(0x38200028 + 0x1700000 * (d)))) | 415 | #define DMACSOFTLBREQ(d) (*((uint32_t volatile*)(0x38200028 + 0x1700000 * (d)))) |
416 | #define DMACSOFTLSREQ(d) (*((uint32_t volatile*)(0x3820002c + 0x1700000 * (d)))) | 416 | #define DMACSOFTLSREQ(d) (*((uint32_t volatile*)(0x3820002c + 0x1700000 * (d)))) |
417 | #define DMACCONFIG(d) (*((uint32_t volatile*)(0x38200030 + 0x1700000 * (d)))) | 417 | #define DMACCONFIG(d) (*((uint32_t volatile*)(0x38200030 + 0x1700000 * (d)))) |
418 | #define DMACSYNC(d) (*((uint32_t volatile*)(0x38200034 + 0x1700000 * (d)))) | 418 | #define DMACSYNC(d) (*((uint32_t volatile*)(0x38200034 + 0x1700000 * (d)))) |
419 | #define DMACCLLI(d, c) (*((struct dma_lli volatile*)(0x38200100 + 0x1700000 * (d) + 0x20 * (c)))) | 419 | #define DMACCLLI(d, c) (*((struct dma_lli volatile*)(0x38200100 + 0x1700000 * (d) + 0x20 * (c)))) |
420 | #define DMACCSRCADDR(d, c) (*((const void* volatile*)(0x38200100 + 0x1700000 * (d) + 0x20 * (c)))) | 420 | #define DMACCSRCADDR(d, c) (*((const void* volatile*)(0x38200100 + 0x1700000 * (d) + 0x20 * (c)))) |
421 | #define DMACCDESTADDR(d, c) (*((void* volatile*)(0x38200104 + 0x1700000 * (d) + 0x20 * (c)))) | 421 | #define DMACCDESTADDR(d, c) (*((void* volatile*)(0x38200104 + 0x1700000 * (d) + 0x20 * (c)))) |
422 | #define DMACCNEXTLLI(d, c) (*((const void* volatile*)(0x38200108 + 0x1700000 * (d) + 0x20 * (c)))) | 422 | #define DMACCNEXTLLI(d, c) (*((const void* volatile*)(0x38200108 + 0x1700000 * (d) + 0x20 * (c)))) |
423 | #define DMACCCONTROL(d, c) (*((uint32_t volatile*)(0x3820010c + 0x1700000 * (d) + 0x20 * (c)))) | 423 | #define DMACCCONTROL(d, c) (*((uint32_t volatile*)(0x3820010c + 0x1700000 * (d) + 0x20 * (c)))) |
424 | #define DMACCCONFIG(d, c) (*((uint32_t volatile*)(0x38200110 + 0x1700000 * (d) + 0x20 * (c)))) | 424 | #define DMACCCONFIG(d, c) (*((uint32_t volatile*)(0x38200110 + 0x1700000 * (d) + 0x20 * (c)))) |
425 | #define DMAC0INTSTS (*((uint32_t volatile*)(0x38200000))) | 425 | #define DMAC0INTSTS (*((uint32_t volatile*)(0x38200000))) |
426 | #define DMAC0INTTCSTS (*((uint32_t volatile*)(0x38200004))) | 426 | #define DMAC0INTTCSTS (*((uint32_t volatile*)(0x38200004))) |
427 | #define DMAC0INTTCCLR (*((uint32_t volatile*)(0x38200008))) | 427 | #define DMAC0INTTCCLR (*((uint32_t volatile*)(0x38200008))) |
428 | #define DMAC0INTERRSTS (*((uint32_t volatile*)(0x3820000c))) | 428 | #define DMAC0INTERRSTS (*((uint32_t volatile*)(0x3820000c))) |
429 | #define DMAC0INTERRCLR (*((uint32_t volatile*)(0x38200010))) | 429 | #define DMAC0INTERRCLR (*((uint32_t volatile*)(0x38200010))) |
430 | #define DMAC0RAWINTTCSTS (*((uint32_t volatile*)(0x38200014))) | 430 | #define DMAC0RAWINTTCSTS (*((uint32_t volatile*)(0x38200014))) |
431 | #define DMAC0RAWINTERRSTS (*((uint32_t volatile*)(0x38200018))) | 431 | #define DMAC0RAWINTERRSTS (*((uint32_t volatile*)(0x38200018))) |
432 | #define DMAC0ENABLEDCHANS (*((uint32_t volatile*)(0x3820001c))) | 432 | #define DMAC0ENABLEDCHANS (*((uint32_t volatile*)(0x3820001c))) |
433 | #define DMAC0SOFTBREQ (*((uint32_t volatile*)(0x38200020))) | 433 | #define DMAC0SOFTBREQ (*((uint32_t volatile*)(0x38200020))) |
434 | #define DMAC0SOFTSREQ (*((uint32_t volatile*)(0x38200024))) | 434 | #define DMAC0SOFTSREQ (*((uint32_t volatile*)(0x38200024))) |
435 | #define DMAC0SOFTLBREQ (*((uint32_t volatile*)(0x38200028))) | 435 | #define DMAC0SOFTLBREQ (*((uint32_t volatile*)(0x38200028))) |
436 | #define DMAC0SOFTLSREQ (*((uint32_t volatile*)(0x3820002c))) | 436 | #define DMAC0SOFTLSREQ (*((uint32_t volatile*)(0x3820002c))) |
437 | #define DMAC0CONFIG (*((uint32_t volatile*)(0x38200030))) | 437 | #define DMAC0CONFIG (*((uint32_t volatile*)(0x38200030))) |
438 | #define DMAC0SYNC (*((uint32_t volatile*)(0x38200034))) | 438 | #define DMAC0SYNC (*((uint32_t volatile*)(0x38200034))) |
439 | #define DMAC0CLLI(c) (*((struct dma_lli volatile*)(0x38200100 + 0x20 * (c)))) | 439 | #define DMAC0CLLI(c) (*((struct dma_lli volatile*)(0x38200100 + 0x20 * (c)))) |
440 | #define DMAC0CSRCADDR(c) (*((const void* volatile*)(0x38200100 + 0x20 * (c)))) | 440 | #define DMAC0CSRCADDR(c) (*((const void* volatile*)(0x38200100 + 0x20 * (c)))) |
441 | #define DMAC0CDESTADDR(c) (*((void* volatile*)(0x38200104 + 0x20 * (c)))) | 441 | #define DMAC0CDESTADDR(c) (*((void* volatile*)(0x38200104 + 0x20 * (c)))) |
442 | #define DMAC0CNEXTLLI(c) (*((const void* volatile*)(0x38200108 + 0x20 * (c)))) | 442 | #define DMAC0CNEXTLLI(c) (*((const void* volatile*)(0x38200108 + 0x20 * (c)))) |
443 | #define DMAC0CCONTROL(c) (*((uint32_t volatile*)(0x3820010c + 0x20 * (c)))) | 443 | #define DMAC0CCONTROL(c) (*((uint32_t volatile*)(0x3820010c + 0x20 * (c)))) |
444 | #define DMAC0CCONFIG(c) (*((uint32_t volatile*)(0x38200110 + 0x20 * (c)))) | 444 | #define DMAC0CCONFIG(c) (*((uint32_t volatile*)(0x38200110 + 0x20 * (c)))) |
445 | #define DMAC0C0LLI (*((struct dma_lli volatile*)(0x38200100))) | 445 | #define DMAC0C0LLI (*((struct dma_lli volatile*)(0x38200100))) |
446 | #define DMAC0C0SRCADDR (*((const void* volatile*)(0x38200100))) | 446 | #define DMAC0C0SRCADDR (*((const void* volatile*)(0x38200100))) |
447 | #define DMAC0C0DESTADDR (*((void* volatile*)(0x38200104))) | 447 | #define DMAC0C0DESTADDR (*((void* volatile*)(0x38200104))) |
448 | #define DMAC0C0NEXTLLI (*((const struct dma_lli* volatile*)(0x38200108))) | 448 | #define DMAC0C0NEXTLLI (*((const struct dma_lli* volatile*)(0x38200108))) |
449 | #define DMAC0C0CONTROL (*((uint32_t volatile*)(0x3820010c))) | 449 | #define DMAC0C0CONTROL (*((uint32_t volatile*)(0x3820010c))) |
450 | #define DMAC0C0CONFIG (*((uint32_t volatile*)(0x38200110))) | 450 | #define DMAC0C0CONFIG (*((uint32_t volatile*)(0x38200110))) |
451 | #define DMAC0C1LLI (*((struct dma_lli volatile*)(0x38200120))) | 451 | #define DMAC0C1LLI (*((struct dma_lli volatile*)(0x38200120))) |
452 | #define DMAC0C1SRCADDR (*((const void* volatile*)(0x38200120))) | 452 | #define DMAC0C1SRCADDR (*((const void* volatile*)(0x38200120))) |
453 | #define DMAC0C1DESTADDR (*((void* volatile*)(0x38200124))) | 453 | #define DMAC0C1DESTADDR (*((void* volatile*)(0x38200124))) |
454 | #define DMAC0C1NEXTLLI (*((const struct dma_lli* volatile*)(0x38200128))) | 454 | #define DMAC0C1NEXTLLI (*((const struct dma_lli* volatile*)(0x38200128))) |
455 | #define DMAC0C1CONTROL (*((uint32_t volatile*)(0x3820012c))) | 455 | #define DMAC0C1CONTROL (*((uint32_t volatile*)(0x3820012c))) |
456 | #define DMAC0C1CONFIG (*((uint32_t volatile*)(0x38200130))) | 456 | #define DMAC0C1CONFIG (*((uint32_t volatile*)(0x38200130))) |
457 | #define DMAC0C2LLI (*((struct dma_lli volatile*)(0x38200140))) | 457 | #define DMAC0C2LLI (*((struct dma_lli volatile*)(0x38200140))) |
458 | #define DMAC0C2SRCADDR (*((const void* volatile*)(0x38200140))) | 458 | #define DMAC0C2SRCADDR (*((const void* volatile*)(0x38200140))) |
459 | #define DMAC0C2DESTADDR (*((void* volatile*)(0x38200144))) | 459 | #define DMAC0C2DESTADDR (*((void* volatile*)(0x38200144))) |
460 | #define DMAC0C2NEXTLLI (*((const struct dma_lli* volatile*)(0x38200148))) | 460 | #define DMAC0C2NEXTLLI (*((const struct dma_lli* volatile*)(0x38200148))) |
461 | #define DMAC0C2CONTROL (*((uint32_t volatile*)(0x3820014c))) | 461 | #define DMAC0C2CONTROL (*((uint32_t volatile*)(0x3820014c))) |
462 | #define DMAC0C2CONFIG (*((uint32_t volatile*)(0x38200150))) | 462 | #define DMAC0C2CONFIG (*((uint32_t volatile*)(0x38200150))) |
463 | #define DMAC0C3LLI (*((struct dma_lli volatile*)(0x38200160))) | 463 | #define DMAC0C3LLI (*((struct dma_lli volatile*)(0x38200160))) |
464 | #define DMAC0C3SRCADDR (*((const void* volatile*)(0x38200160))) | 464 | #define DMAC0C3SRCADDR (*((const void* volatile*)(0x38200160))) |
465 | #define DMAC0C3DESTADDR (*((void* volatile*)(0x38200164))) | 465 | #define DMAC0C3DESTADDR (*((void* volatile*)(0x38200164))) |
466 | #define DMAC0C3NEXTLLI (*((const struct dma_lli* volatile*)(0x38200168))) | 466 | #define DMAC0C3NEXTLLI (*((const struct dma_lli* volatile*)(0x38200168))) |
467 | #define DMAC0C3CONTROL (*((uint32_t volatile*)(0x3820016c))) | 467 | #define DMAC0C3CONTROL (*((uint32_t volatile*)(0x3820016c))) |
468 | #define DMAC0C3CONFIG (*((uint32_t volatile*)(0x38200170))) | 468 | #define DMAC0C3CONFIG (*((uint32_t volatile*)(0x38200170))) |
469 | #define DMAC0C4LLI (*((struct dma_lli volatile*)(0x38200180))) | 469 | #define DMAC0C4LLI (*((struct dma_lli volatile*)(0x38200180))) |
470 | #define DMAC0C4SRCADDR (*((const void* volatile*)(0x38200180))) | 470 | #define DMAC0C4SRCADDR (*((const void* volatile*)(0x38200180))) |
471 | #define DMAC0C4DESTADDR (*((void* volatile*)(0x38200184))) | 471 | #define DMAC0C4DESTADDR (*((void* volatile*)(0x38200184))) |
472 | #define DMAC0C4NEXTLLI (*((const struct dma_lli* volatile*)(0x38200188))) | 472 | #define DMAC0C4NEXTLLI (*((const struct dma_lli* volatile*)(0x38200188))) |
473 | #define DMAC0C4CONTROL (*((uint32_t volatile*)(0x3820018c))) | 473 | #define DMAC0C4CONTROL (*((uint32_t volatile*)(0x3820018c))) |
474 | #define DMAC0C4CONFIG (*((uint32_t volatile*)(0x38200190))) | 474 | #define DMAC0C4CONFIG (*((uint32_t volatile*)(0x38200190))) |
475 | #define DMAC0C5LLI (*((struct dma_lli volatile*)(0x382001a0))) | 475 | #define DMAC0C5LLI (*((struct dma_lli volatile*)(0x382001a0))) |
476 | #define DMAC0C5SRCADDR (*((const void* volatile*)(0x382001a0))) | 476 | #define DMAC0C5SRCADDR (*((const void* volatile*)(0x382001a0))) |
477 | #define DMAC0C5DESTADDR (*((void* volatile*)(0x382001a4))) | 477 | #define DMAC0C5DESTADDR (*((void* volatile*)(0x382001a4))) |
478 | #define DMAC0C5NEXTLLI (*((const struct dma_lli* volatile*)(0x382001a8))) | 478 | #define DMAC0C5NEXTLLI (*((const struct dma_lli* volatile*)(0x382001a8))) |
479 | #define DMAC0C5CONTROL (*((uint32_t volatile*)(0x382001ac))) | 479 | #define DMAC0C5CONTROL (*((uint32_t volatile*)(0x382001ac))) |
480 | #define DMAC0C5CONFIG (*((uint32_t volatile*)(0x382001b0))) | 480 | #define DMAC0C5CONFIG (*((uint32_t volatile*)(0x382001b0))) |
481 | #define DMAC0C6LLI (*((struct dma_lli volatile*)(0x382001c0))) | 481 | #define DMAC0C6LLI (*((struct dma_lli volatile*)(0x382001c0))) |
482 | #define DMAC0C6SRCADDR (*((const void* volatile*)(0x382001c0))) | 482 | #define DMAC0C6SRCADDR (*((const void* volatile*)(0x382001c0))) |
483 | #define DMAC0C6DESTADDR (*((void* volatile*)(0x382001c4))) | 483 | #define DMAC0C6DESTADDR (*((void* volatile*)(0x382001c4))) |
484 | #define DMAC0C6NEXTLLI (*((const struct dma_lli* volatile*)(0x382001c8))) | 484 | #define DMAC0C6NEXTLLI (*((const struct dma_lli* volatile*)(0x382001c8))) |
485 | #define DMAC0C6CONTROL (*((uint32_t volatile*)(0x382001cc))) | 485 | #define DMAC0C6CONTROL (*((uint32_t volatile*)(0x382001cc))) |
486 | #define DMAC0C6CONFIG (*((uint32_t volatile*)(0x382001d0))) | 486 | #define DMAC0C6CONFIG (*((uint32_t volatile*)(0x382001d0))) |
487 | #define DMAC0C7LLI (*((struct dma_lli volatile*)(0x382001e0))) | 487 | #define DMAC0C7LLI (*((struct dma_lli volatile*)(0x382001e0))) |
488 | #define DMAC0C7SRCADDR (*((const void* volatile*)(0x382001e0))) | 488 | #define DMAC0C7SRCADDR (*((const void* volatile*)(0x382001e0))) |
489 | #define DMAC0C7DESTADDR (*((void* volatile*)(0x382001e4))) | 489 | #define DMAC0C7DESTADDR (*((void* volatile*)(0x382001e4))) |
490 | #define DMAC0C7NEXTLLI (*((const struct dma_lli* volatile*)(0x382001e8))) | 490 | #define DMAC0C7NEXTLLI (*((const struct dma_lli* volatile*)(0x382001e8))) |
491 | #define DMAC0C7CONTROL (*((uint32_t volatile*)(0x382001ec))) | 491 | #define DMAC0C7CONTROL (*((uint32_t volatile*)(0x382001ec))) |
492 | #define DMAC0C7CONFIG (*((uint32_t volatile*)(0x382001f0))) | 492 | #define DMAC0C7CONFIG (*((uint32_t volatile*)(0x382001f0))) |
493 | #define DMAC1INTSTS (*((uint32_t volatile*)(0x39900000))) | 493 | #define DMAC1INTSTS (*((uint32_t volatile*)(0x39900000))) |
494 | #define DMAC1INTTCSTS (*((uint32_t volatile*)(0x39900004))) | 494 | #define DMAC1INTTCSTS (*((uint32_t volatile*)(0x39900004))) |
495 | #define DMAC1INTTCCLR (*((uint32_t volatile*)(0x39900008))) | 495 | #define DMAC1INTTCCLR (*((uint32_t volatile*)(0x39900008))) |
496 | #define DMAC1INTERRSTS (*((uint32_t volatile*)(0x3990000c))) | 496 | #define DMAC1INTERRSTS (*((uint32_t volatile*)(0x3990000c))) |
497 | #define DMAC1INTERRCLR (*((uint32_t volatile*)(0x39900010))) | 497 | #define DMAC1INTERRCLR (*((uint32_t volatile*)(0x39900010))) |
498 | #define DMAC1RAWINTTCSTS (*((uint32_t volatile*)(0x39900014))) | 498 | #define DMAC1RAWINTTCSTS (*((uint32_t volatile*)(0x39900014))) |
499 | #define DMAC1RAWINTERRSTS (*((uint32_t volatile*)(0x39900018))) | 499 | #define DMAC1RAWINTERRSTS (*((uint32_t volatile*)(0x39900018))) |
500 | #define DMAC1ENABLEDCHANS (*((uint32_t volatile*)(0x3990001c))) | 500 | #define DMAC1ENABLEDCHANS (*((uint32_t volatile*)(0x3990001c))) |
501 | #define DMAC1SOFTBREQ (*((uint32_t volatile*)(0x39900020))) | 501 | #define DMAC1SOFTBREQ (*((uint32_t volatile*)(0x39900020))) |
502 | #define DMAC1SOFTSREQ (*((uint32_t volatile*)(0x39900024))) | 502 | #define DMAC1SOFTSREQ (*((uint32_t volatile*)(0x39900024))) |
503 | #define DMAC1SOFTLBREQ (*((uint32_t volatile*)(0x39900028))) | 503 | #define DMAC1SOFTLBREQ (*((uint32_t volatile*)(0x39900028))) |
504 | #define DMAC1SOFTLSREQ (*((uint32_t volatile*)(0x3990002c))) | 504 | #define DMAC1SOFTLSREQ (*((uint32_t volatile*)(0x3990002c))) |
505 | #define DMAC1CONFIG (*((uint32_t volatile*)(0x39900030))) | 505 | #define DMAC1CONFIG (*((uint32_t volatile*)(0x39900030))) |
506 | #define DMAC1SYNC (*((uint32_t volatile*)(0x39900034))) | 506 | #define DMAC1SYNC (*((uint32_t volatile*)(0x39900034))) |
507 | #define DMAC1CLLI(c) (*((struct dma_lli volatile*)(0x39900100 + 0x20 * (c)))) | 507 | #define DMAC1CLLI(c) (*((struct dma_lli volatile*)(0x39900100 + 0x20 * (c)))) |
508 | #define DMAC1CSRCADDR(c) (*((const void* volatile*)(0x39900100 + 0x20 * (c)))) | 508 | #define DMAC1CSRCADDR(c) (*((const void* volatile*)(0x39900100 + 0x20 * (c)))) |
509 | #define DMAC1CDESTADDR(c) (*((void* volatile*)(0x39900104 + 0x20 * (c)))) | 509 | #define DMAC1CDESTADDR(c) (*((void* volatile*)(0x39900104 + 0x20 * (c)))) |
510 | #define DMAC1CNEXTLLI(c) (*((const void* volatile*)(0x39900108 + 0x20 * (c)))) | 510 | #define DMAC1CNEXTLLI(c) (*((const void* volatile*)(0x39900108 + 0x20 * (c)))) |
511 | #define DMAC1CCONTROL(c) (*((uint32_t volatile*)(0x3990010c + 0x20 * (c)))) | 511 | #define DMAC1CCONTROL(c) (*((uint32_t volatile*)(0x3990010c + 0x20 * (c)))) |
512 | #define DMAC1CCONFIG(c) (*((uint32_t volatile*)(0x39900110 + 0x20 * (c)))) | 512 | #define DMAC1CCONFIG(c) (*((uint32_t volatile*)(0x39900110 + 0x20 * (c)))) |
513 | #define DMAC1C0LLI (*((struct dma_lli volatile*)(0x39900100))) | 513 | #define DMAC1C0LLI (*((struct dma_lli volatile*)(0x39900100))) |
514 | #define DMAC1C0SRCADDR (*((const void* volatile*)(0x39900100))) | 514 | #define DMAC1C0SRCADDR (*((const void* volatile*)(0x39900100))) |
515 | #define DMAC1C0DESTADDR (*((void* volatile*)(0x39900104))) | 515 | #define DMAC1C0DESTADDR (*((void* volatile*)(0x39900104))) |
516 | #define DMAC1C0NEXTLLI (*((const struct dma_lli* volatile*)(0x39900108))) | 516 | #define DMAC1C0NEXTLLI (*((const struct dma_lli* volatile*)(0x39900108))) |
517 | #define DMAC1C0CONTROL (*((uint32_t volatile*)(0x3990010c))) | 517 | #define DMAC1C0CONTROL (*((uint32_t volatile*)(0x3990010c))) |
518 | #define DMAC1C0CONFIG (*((uint32_t volatile*)(0x39900110))) | 518 | #define DMAC1C0CONFIG (*((uint32_t volatile*)(0x39900110))) |
519 | #define DMAC1C1LLI (*((struct dma_lli volatile*)(0x39900120))) | 519 | #define DMAC1C1LLI (*((struct dma_lli volatile*)(0x39900120))) |
520 | #define DMAC1C1SRCADDR (*((const void* volatile*)(0x39900120))) | 520 | #define DMAC1C1SRCADDR (*((const void* volatile*)(0x39900120))) |
521 | #define DMAC1C1DESTADDR (*((void* volatile*)(0x39900124))) | 521 | #define DMAC1C1DESTADDR (*((void* volatile*)(0x39900124))) |
522 | #define DMAC1C1NEXTLLI (*((const struct dma_lli* volatile*)(0x39900128))) | 522 | #define DMAC1C1NEXTLLI (*((const struct dma_lli* volatile*)(0x39900128))) |
523 | #define DMAC1C1CONTROL (*((uint32_t volatile*)(0x3990012c))) | 523 | #define DMAC1C1CONTROL (*((uint32_t volatile*)(0x3990012c))) |
524 | #define DMAC1C1CONFIG (*((uint32_t volatile*)(0x39900130))) | 524 | #define DMAC1C1CONFIG (*((uint32_t volatile*)(0x39900130))) |
525 | #define DMAC1C2LLI (*((struct dma_lli volatile*)(0x39900140))) | 525 | #define DMAC1C2LLI (*((struct dma_lli volatile*)(0x39900140))) |
526 | #define DMAC1C2SRCADDR (*((const void* volatile*)(0x39900140))) | 526 | #define DMAC1C2SRCADDR (*((const void* volatile*)(0x39900140))) |
527 | #define DMAC1C2DESTADDR (*((void* volatile*)(0x39900144))) | 527 | #define DMAC1C2DESTADDR (*((void* volatile*)(0x39900144))) |
528 | #define DMAC1C2NEXTLLI (*((const struct dma_lli* volatile*)(0x39900148))) | 528 | #define DMAC1C2NEXTLLI (*((const struct dma_lli* volatile*)(0x39900148))) |
529 | #define DMAC1C2CONTROL (*((uint32_t volatile*)(0x3990014c))) | 529 | #define DMAC1C2CONTROL (*((uint32_t volatile*)(0x3990014c))) |
530 | #define DMAC1C2CONFIG (*((uint32_t volatile*)(0x39900150))) | 530 | #define DMAC1C2CONFIG (*((uint32_t volatile*)(0x39900150))) |
531 | #define DMAC1C3LLI (*((struct dma_lli volatile*)(0x39900160))) | 531 | #define DMAC1C3LLI (*((struct dma_lli volatile*)(0x39900160))) |
532 | #define DMAC1C3SRCADDR (*((const void* volatile*)(0x39900160))) | 532 | #define DMAC1C3SRCADDR (*((const void* volatile*)(0x39900160))) |
533 | #define DMAC1C3DESTADDR (*((void* volatile*)(0x39900164))) | 533 | #define DMAC1C3DESTADDR (*((void* volatile*)(0x39900164))) |
534 | #define DMAC1C3NEXTLLI (*((volatile void**)(0x39900168))) | 534 | #define DMAC1C3NEXTLLI (*((volatile void**)(0x39900168))) |
535 | #define DMAC1C3CONTROL (*((uint32_t volatile*)(0x3990016c))) | 535 | #define DMAC1C3CONTROL (*((uint32_t volatile*)(0x3990016c))) |
536 | #define DMAC1C3CONFIG (*((uint32_t volatile*)(0x39900170))) | 536 | #define DMAC1C3CONFIG (*((uint32_t volatile*)(0x39900170))) |
537 | #define DMAC1C4LLI (*((struct dma_lli volatile*)(0x39900180))) | 537 | #define DMAC1C4LLI (*((struct dma_lli volatile*)(0x39900180))) |
538 | #define DMAC1C4SRCADDR (*((const void* volatile*)(0x39900180))) | 538 | #define DMAC1C4SRCADDR (*((const void* volatile*)(0x39900180))) |
539 | #define DMAC1C4DESTADDR (*((void* volatile*)(0x39900184))) | 539 | #define DMAC1C4DESTADDR (*((void* volatile*)(0x39900184))) |
540 | #define DMAC1C4NEXTLLI (*((const struct dma_lli* volatile*)(0x39900188))) | 540 | #define DMAC1C4NEXTLLI (*((const struct dma_lli* volatile*)(0x39900188))) |
541 | #define DMAC1C4CONTROL (*((uint32_t volatile*)(0x3990018c))) | 541 | #define DMAC1C4CONTROL (*((uint32_t volatile*)(0x3990018c))) |
542 | #define DMAC1C4CONFIG (*((uint32_t volatile*)(0x39900190))) | 542 | #define DMAC1C4CONFIG (*((uint32_t volatile*)(0x39900190))) |
543 | #define DMAC1C5LLI (*((struct dma_lli volatile*)(0x399001a0))) | 543 | #define DMAC1C5LLI (*((struct dma_lli volatile*)(0x399001a0))) |
544 | #define DMAC1C5SRCADDR (*((const void* volatile*)(0x399001a0))) | 544 | #define DMAC1C5SRCADDR (*((const void* volatile*)(0x399001a0))) |
545 | #define DMAC1C5DESTADDR (*((void* volatile*)(0x399001a4))) | 545 | #define DMAC1C5DESTADDR (*((void* volatile*)(0x399001a4))) |
546 | #define DMAC1C5NEXTLLI (*((const struct dma_lli* volatile*)(0x399001a8))) | 546 | #define DMAC1C5NEXTLLI (*((const struct dma_lli* volatile*)(0x399001a8))) |
547 | #define DMAC1C5CONTROL (*((uint32_t volatile*)(0x399001ac))) | 547 | #define DMAC1C5CONTROL (*((uint32_t volatile*)(0x399001ac))) |
548 | #define DMAC1C5CONFIG (*((uint32_t volatile*)(0x399001b0))) | 548 | #define DMAC1C5CONFIG (*((uint32_t volatile*)(0x399001b0))) |
549 | #define DMAC1C6LLI (*((struct dma_lli volatile*)(0x399001c0))) | 549 | #define DMAC1C6LLI (*((struct dma_lli volatile*)(0x399001c0))) |
550 | #define DMAC1C6SRCADDR (*((const void* volatile*)(0x399001c0))) | 550 | #define DMAC1C6SRCADDR (*((const void* volatile*)(0x399001c0))) |
551 | #define DMAC1C6DESTADDR (*((void* volatile*)(0x399001c4))) | 551 | #define DMAC1C6DESTADDR (*((void* volatile*)(0x399001c4))) |
552 | #define DMAC1C6NEXTLLI (*((const struct dma_lli* volatile*)(0x399001c8))) | 552 | #define DMAC1C6NEXTLLI (*((const struct dma_lli* volatile*)(0x399001c8))) |
553 | #define DMAC1C6CONTROL (*((uint32_t volatile*)(0x399001cc))) | 553 | #define DMAC1C6CONTROL (*((uint32_t volatile*)(0x399001cc))) |
554 | #define DMAC1C6CONFIG (*((uint32_t volatile*)(0x399001d0))) | 554 | #define DMAC1C6CONFIG (*((uint32_t volatile*)(0x399001d0))) |
555 | #define DMAC1C7LLI (*((struct dma_lli volatile*)(0x399001e0))) | 555 | #define DMAC1C7LLI (*((struct dma_lli volatile*)(0x399001e0))) |
556 | #define DMAC1C7SRCADDR (*((const void* volatile*)(0x399001e0))) | 556 | #define DMAC1C7SRCADDR (*((const void* volatile*)(0x399001e0))) |
557 | #define DMAC1C7DESTADDR (*((void* volatile*)(0x399001e4))) | 557 | #define DMAC1C7DESTADDR (*((void* volatile*)(0x399001e4))) |
558 | #define DMAC1C7NEXTLLI (*((const struct dma_lli* volatile*)(0x399001e8))) | 558 | #define DMAC1C7NEXTLLI (*((const struct dma_lli* volatile*)(0x399001e8))) |
559 | #define DMAC1C7CONTROL (*((uint32_t volatile*)(0x399001ec))) | 559 | #define DMAC1C7CONTROL (*((uint32_t volatile*)(0x399001ec))) |
560 | #define DMAC1C7CONFIG (*((uint32_t volatile*)(0x399001f0))) | 560 | #define DMAC1C7CONFIG (*((uint32_t volatile*)(0x399001f0))) |
561 | 561 | ||
562 | 562 | ||
563 | /////LCD///// | 563 | /////LCD///// |
564 | #define LCD_BASE (0x38300000) | 564 | #define LCD_BASE (0x38300000) |
565 | #define LCD_CONFIG (*((uint32_t volatile*)(0x38300000))) | 565 | #define LCD_CONFIG (*((uint32_t volatile*)(0x38300000))) |
566 | #define LCD_WCMD (*((uint32_t volatile*)(0x38300004))) | 566 | #define LCD_WCMD (*((uint32_t volatile*)(0x38300004))) |
567 | #define LCD_STATUS (*((uint32_t volatile*)(0x3830001c))) | 567 | #define LCD_STATUS (*((uint32_t volatile*)(0x3830001c))) |
568 | #define LCD_WDATA (*((uint32_t volatile*)(0x38300040))) | 568 | #define LCD_WDATA (*((uint32_t volatile*)(0x38300040))) |
569 | 569 | ||
570 | 570 | ||
571 | /////ATA///// | 571 | /////ATA///// |
572 | #define ATA_CONTROL (*((uint32_t volatile*)(0x38700000))) | 572 | #define ATA_CONTROL (*((uint32_t volatile*)(0x38700000))) |
573 | #define ATA_STATUS (*((uint32_t volatile*)(0x38700004))) | 573 | #define ATA_STATUS (*((uint32_t volatile*)(0x38700004))) |
574 | #define ATA_COMMAND (*((uint32_t volatile*)(0x38700008))) | 574 | #define ATA_COMMAND (*((uint32_t volatile*)(0x38700008))) |
575 | #define ATA_SWRST (*((uint32_t volatile*)(0x3870000c))) | 575 | #define ATA_SWRST (*((uint32_t volatile*)(0x3870000c))) |
576 | #define ATA_IRQ (*((uint32_t volatile*)(0x38700010))) | 576 | #define ATA_IRQ (*((uint32_t volatile*)(0x38700010))) |
577 | #define ATA_IRQ_MASK (*((uint32_t volatile*)(0x38700014))) | 577 | #define ATA_IRQ_MASK (*((uint32_t volatile*)(0x38700014))) |
578 | #define ATA_CFG (*((uint32_t volatile*)(0x38700018))) | 578 | #define ATA_CFG (*((uint32_t volatile*)(0x38700018))) |
579 | #define ATA_MDMA_TIME (*((uint32_t volatile*)(0x38700028))) | 579 | #define ATA_MDMA_TIME (*((uint32_t volatile*)(0x38700028))) |
580 | #define ATA_PIO_TIME (*((uint32_t volatile*)(0x3870002c))) | 580 | #define ATA_PIO_TIME (*((uint32_t volatile*)(0x3870002c))) |
581 | #define ATA_UDMA_TIME (*((uint32_t volatile*)(0x38700030))) | 581 | #define ATA_UDMA_TIME (*((uint32_t volatile*)(0x38700030))) |
582 | #define ATA_XFR_NUM (*((uint32_t volatile*)(0x38700034))) | 582 | #define ATA_XFR_NUM (*((uint32_t volatile*)(0x38700034))) |
583 | #define ATA_XFR_CNT (*((uint32_t volatile*)(0x38700038))) | 583 | #define ATA_XFR_CNT (*((uint32_t volatile*)(0x38700038))) |
584 | #define ATA_TBUF_START (*((void* volatile*)(0x3870003c))) | 584 | #define ATA_TBUF_START (*((void* volatile*)(0x3870003c))) |
585 | #define ATA_TBUF_SIZE (*((uint32_t volatile*)(0x38700040))) | 585 | #define ATA_TBUF_SIZE (*((uint32_t volatile*)(0x38700040))) |
586 | #define ATA_SBUF_START (*((void* volatile*)(0x38700044))) | 586 | #define ATA_SBUF_START (*((void* volatile*)(0x38700044))) |
587 | #define ATA_SBUF_SIZE (*((uint32_t volatile*)(0x38700048))) | 587 | #define ATA_SBUF_SIZE (*((uint32_t volatile*)(0x38700048))) |
588 | #define ATA_CADR_TBUF (*((void* volatile*)(0x3870004c))) | 588 | #define ATA_CADR_TBUF (*((void* volatile*)(0x3870004c))) |
589 | #define ATA_CADR_SBUF (*((void* volatile*)(0x38700050))) | 589 | #define ATA_CADR_SBUF (*((void* volatile*)(0x38700050))) |
590 | #define ATA_PIO_DTR (*((uint32_t volatile*)(0x38700054))) | 590 | #define ATA_PIO_DTR (*((uint32_t volatile*)(0x38700054))) |
591 | #define ATA_PIO_FED (*((uint32_t volatile*)(0x38700058))) | 591 | #define ATA_PIO_FED (*((uint32_t volatile*)(0x38700058))) |
592 | #define ATA_PIO_SCR (*((uint32_t volatile*)(0x3870005c))) | 592 | #define ATA_PIO_SCR (*((uint32_t volatile*)(0x3870005c))) |
593 | #define ATA_PIO_LLR (*((uint32_t volatile*)(0x38700060))) | 593 | #define ATA_PIO_LLR (*((uint32_t volatile*)(0x38700060))) |
594 | #define ATA_PIO_LMR (*((uint32_t volatile*)(0x38700064))) | 594 | #define ATA_PIO_LMR (*((uint32_t volatile*)(0x38700064))) |
595 | #define ATA_PIO_LHR (*((uint32_t volatile*)(0x38700068))) | 595 | #define ATA_PIO_LHR (*((uint32_t volatile*)(0x38700068))) |
596 | #define ATA_PIO_DVR (*((uint32_t volatile*)(0x3870006c))) | 596 | #define ATA_PIO_DVR (*((uint32_t volatile*)(0x3870006c))) |
597 | #define ATA_PIO_CSD (*((uint32_t volatile*)(0x38700070))) | 597 | #define ATA_PIO_CSD (*((uint32_t volatile*)(0x38700070))) |
598 | #define ATA_PIO_DAD (*((uint32_t volatile*)(0x38700074))) | 598 | #define ATA_PIO_DAD (*((uint32_t volatile*)(0x38700074))) |
599 | #define ATA_PIO_READY (*((uint32_t volatile*)(0x38700078))) | 599 | #define ATA_PIO_READY (*((uint32_t volatile*)(0x38700078))) |
600 | #define ATA_PIO_RDATA (*((uint32_t volatile*)(0x3870007c))) | 600 | #define ATA_PIO_RDATA (*((uint32_t volatile*)(0x3870007c))) |
601 | #define ATA_BUS_FIFO_STATUS (*((uint32_t volatile*)(0x38700080))) | 601 | #define ATA_BUS_FIFO_STATUS (*((uint32_t volatile*)(0x38700080))) |
602 | #define ATA_FIFO_STATUS (*((uint32_t volatile*)(0x38700084))) | 602 | #define ATA_FIFO_STATUS (*((uint32_t volatile*)(0x38700084))) |
603 | #define ATA_DMA_ADDR (*((void* volatile*)(0x38700088))) | 603 | #define ATA_DMA_ADDR (*((void* volatile*)(0x38700088))) |
604 | 604 | ||
605 | 605 | ||
606 | /////SDCI///// | 606 | /////SDCI///// |
607 | #define SDCI_CTRL (*((uint32_t volatile*)(0x38b00000))) | 607 | #define SDCI_CTRL (*((uint32_t volatile*)(0x38b00000))) |
608 | #define SDCI_DCTRL (*((uint32_t volatile*)(0x38b00004))) | 608 | #define SDCI_DCTRL (*((uint32_t volatile*)(0x38b00004))) |
609 | #define SDCI_CMD (*((uint32_t volatile*)(0x38b00008))) | 609 | #define SDCI_CMD (*((uint32_t volatile*)(0x38b00008))) |
610 | #define SDCI_ARGU (*((uint32_t volatile*)(0x38b0000c))) | 610 | #define SDCI_ARGU (*((uint32_t volatile*)(0x38b0000c))) |
611 | #define SDCI_STATE (*((uint32_t volatile*)(0x38b00010))) | 611 | #define SDCI_STATE (*((uint32_t volatile*)(0x38b00010))) |
612 | #define SDCI_STAC (*((uint32_t volatile*)(0x38b00014))) | 612 | #define SDCI_STAC (*((uint32_t volatile*)(0x38b00014))) |
613 | #define SDCI_DSTA (*((uint32_t volatile*)(0x38b00018))) | 613 | #define SDCI_DSTA (*((uint32_t volatile*)(0x38b00018))) |
614 | #define SDCI_FSTA (*((uint32_t volatile*)(0x38b0001c))) | 614 | #define SDCI_FSTA (*((uint32_t volatile*)(0x38b0001c))) |
615 | #define SDCI_RESP0 (*((uint32_t volatile*)(0x38b00020))) | 615 | #define SDCI_RESP0 (*((uint32_t volatile*)(0x38b00020))) |
616 | #define SDCI_RESP1 (*((uint32_t volatile*)(0x38b00024))) | 616 | #define SDCI_RESP1 (*((uint32_t volatile*)(0x38b00024))) |
617 | #define SDCI_RESP2 (*((uint32_t volatile*)(0x38b00028))) | 617 | #define SDCI_RESP2 (*((uint32_t volatile*)(0x38b00028))) |
618 | #define SDCI_RESP3 (*((uint32_t volatile*)(0x38b0002c))) | 618 | #define SDCI_RESP3 (*((uint32_t volatile*)(0x38b0002c))) |
619 | #define SDCI_CDIV (*((uint32_t volatile*)(0x38b00030))) | 619 | #define SDCI_CDIV (*((uint32_t volatile*)(0x38b00030))) |
620 | #define SDCI_SDIO_CSR (*((uint32_t volatile*)(0x38b00034))) | 620 | #define SDCI_SDIO_CSR (*((uint32_t volatile*)(0x38b00034))) |
621 | #define SDCI_IRQ (*((uint32_t volatile*)(0x38b00038))) | 621 | #define SDCI_IRQ (*((uint32_t volatile*)(0x38b00038))) |
622 | #define SDCI_IRQ_MASK (*((uint32_t volatile*)(0x38b0003c))) | 622 | #define SDCI_IRQ_MASK (*((uint32_t volatile*)(0x38b0003c))) |
623 | #define SDCI_DATA (*((uint32_t volatile*)(0x38b00040))) | 623 | #define SDCI_DATA (*((uint32_t volatile*)(0x38b00040))) |
624 | #define SDCI_DMAADDR (*((void* volatile*)(0x38b00044))) | 624 | #define SDCI_DMAADDR (*((void* volatile*)(0x38b00044))) |
625 | #define SDCI_DMASIZE (*((uint32_t volatile*)(0x38b00048))) | 625 | #define SDCI_DMASIZE (*((uint32_t volatile*)(0x38b00048))) |
626 | #define SDCI_DMACOUNT (*((uint32_t volatile*)(0x38b0004c))) | 626 | #define SDCI_DMACOUNT (*((uint32_t volatile*)(0x38b0004c))) |
627 | #define SDCI_RESET (*((uint32_t volatile*)(0x38b0006c))) | 627 | #define SDCI_RESET (*((uint32_t volatile*)(0x38b0006c))) |
628 | 628 | ||
629 | #define SDCI_CTRL_SDCIEN BIT(0) | 629 | #define SDCI_CTRL_SDCIEN BIT(0) |
630 | #define SDCI_CTRL_CARD_TYPE_MASK BIT(1) | 630 | #define SDCI_CTRL_CARD_TYPE_MASK BIT(1) |
631 | #define SDCI_CTRL_CARD_TYPE_SD 0 | 631 | #define SDCI_CTRL_CARD_TYPE_SD 0 |
632 | #define SDCI_CTRL_CARD_TYPE_MMC BIT(1) | 632 | #define SDCI_CTRL_CARD_TYPE_MMC BIT(1) |
633 | #define SDCI_CTRL_BUS_WIDTH_MASK BITRANGE(2, 3) | 633 | #define SDCI_CTRL_BUS_WIDTH_MASK BITRANGE(2, 3) |
634 | #define SDCI_CTRL_BUS_WIDTH_1BIT 0 | 634 | #define SDCI_CTRL_BUS_WIDTH_1BIT 0 |
635 | #define SDCI_CTRL_BUS_WIDTH_4BIT BIT(2) | 635 | #define SDCI_CTRL_BUS_WIDTH_4BIT BIT(2) |
636 | #define SDCI_CTRL_BUS_WIDTH_8BIT BIT(3) | 636 | #define SDCI_CTRL_BUS_WIDTH_8BIT BIT(3) |
637 | #define SDCI_CTRL_DMA_EN BIT(4) | 637 | #define SDCI_CTRL_DMA_EN BIT(4) |
638 | #define SDCI_CTRL_L_ENDIAN BIT(5) | 638 | #define SDCI_CTRL_L_ENDIAN BIT(5) |
639 | #define SDCI_CTRL_DMA_REQ_CON_MASK BIT(6) | 639 | #define SDCI_CTRL_DMA_REQ_CON_MASK BIT(6) |
640 | #define SDCI_CTRL_DMA_REQ_CON_NEMPTY 0 | 640 | #define SDCI_CTRL_DMA_REQ_CON_NEMPTY 0 |
641 | #define SDCI_CTRL_DMA_REQ_CON_FULL BIT(6) | 641 | #define SDCI_CTRL_DMA_REQ_CON_FULL BIT(6) |
642 | #define SDCI_CTRL_CLK_SEL_MASK BIT(7) | 642 | #define SDCI_CTRL_CLK_SEL_MASK BIT(7) |
643 | #define SDCI_CTRL_CLK_SEL_PCLK 0 | 643 | #define SDCI_CTRL_CLK_SEL_PCLK 0 |
644 | #define SDCI_CTRL_CLK_SEL_SDCLK BIT(7) | 644 | #define SDCI_CTRL_CLK_SEL_SDCLK BIT(7) |
645 | #define SDCI_CTRL_BIT_8 BIT(8) | 645 | #define SDCI_CTRL_BIT_8 BIT(8) |
646 | #define SDCI_CTRL_BIT_14 BIT(14) | 646 | #define SDCI_CTRL_BIT_14 BIT(14) |
647 | 647 | ||
648 | #define SDCI_DCTRL_TXFIFORST BIT(0) | 648 | #define SDCI_DCTRL_TXFIFORST BIT(0) |
649 | #define SDCI_DCTRL_RXFIFORST BIT(1) | 649 | #define SDCI_DCTRL_RXFIFORST BIT(1) |
650 | #define SDCI_DCTRL_TRCONT_MASK BITRANGE(4, 5) | 650 | #define SDCI_DCTRL_TRCONT_MASK BITRANGE(4, 5) |
651 | #define SDCI_DCTRL_TRCONT_TX BIT(4) | 651 | #define SDCI_DCTRL_TRCONT_TX BIT(4) |
652 | #define SDCI_DCTRL_BUS_TEST_MASK BITRANGE(6, 7) | 652 | #define SDCI_DCTRL_BUS_TEST_MASK BITRANGE(6, 7) |
653 | #define SDCI_DCTRL_BUS_TEST_TX BIT(6) | 653 | #define SDCI_DCTRL_BUS_TEST_TX BIT(6) |
654 | #define SDCI_DCTRL_BUS_TEST_RX BIT(7) | 654 | #define SDCI_DCTRL_BUS_TEST_RX BIT(7) |
655 | 655 | ||
656 | #define SDCI_CDIV_CLKDIV_MASK BITRANGE(0, 7) | 656 | #define SDCI_CDIV_CLKDIV_MASK BITRANGE(0, 7) |
657 | #define SDCI_CDIV_CLKDIV(x) ((x) >> 1) | 657 | #define SDCI_CDIV_CLKDIV(x) ((x) >> 1) |
658 | #define SDCI_CDIV_CLKDIV_2 BIT(0) | 658 | #define SDCI_CDIV_CLKDIV_2 BIT(0) |
659 | #define SDCI_CDIV_CLKDIV_4 BIT(1) | 659 | #define SDCI_CDIV_CLKDIV_4 BIT(1) |
660 | #define SDCI_CDIV_CLKDIV_8 BIT(2) | 660 | #define SDCI_CDIV_CLKDIV_8 BIT(2) |
661 | #define SDCI_CDIV_CLKDIV_16 BIT(3) | 661 | #define SDCI_CDIV_CLKDIV_16 BIT(3) |
662 | #define SDCI_CDIV_CLKDIV_32 BIT(4) | 662 | #define SDCI_CDIV_CLKDIV_32 BIT(4) |
663 | #define SDCI_CDIV_CLKDIV_64 BIT(5) | 663 | #define SDCI_CDIV_CLKDIV_64 BIT(5) |
664 | #define SDCI_CDIV_CLKDIV_128 BIT(6) | 664 | #define SDCI_CDIV_CLKDIV_128 BIT(6) |
665 | #define SDCI_CDIV_CLKDIV_256 BIT(7) | 665 | #define SDCI_CDIV_CLKDIV_256 BIT(7) |
666 | 666 | ||
667 | #define SDCI_CMD_CMD_NUM_MASK BITRANGE(0, 5) | 667 | #define SDCI_CMD_CMD_NUM_MASK BITRANGE(0, 5) |
668 | #define SDCI_CMD_CMD_NUM_SHIFT 0 | 668 | #define SDCI_CMD_CMD_NUM_SHIFT 0 |
669 | #define SDCI_CMD_CMD_NUM(x) (x) | 669 | #define SDCI_CMD_CMD_NUM(x) (x) |
670 | #define SDCI_CMD_CMD_TYPE_MASK BITRANGE(6, 7) | 670 | #define SDCI_CMD_CMD_TYPE_MASK BITRANGE(6, 7) |
671 | #define SDCI_CMD_CMD_TYPE_BC 0 | 671 | #define SDCI_CMD_CMD_TYPE_BC 0 |
672 | #define SDCI_CMD_CMD_TYPE_BCR BIT(6) | 672 | #define SDCI_CMD_CMD_TYPE_BCR BIT(6) |
673 | #define SDCI_CMD_CMD_TYPE_AC BIT(7) | 673 | #define SDCI_CMD_CMD_TYPE_AC BIT(7) |
674 | #define SDCI_CMD_CMD_TYPE_ADTC (BIT(6) | BIT(7)) | 674 | #define SDCI_CMD_CMD_TYPE_ADTC (BIT(6) | BIT(7)) |
675 | #define SDCI_CMD_CMD_RD_WR BIT(8) | 675 | #define SDCI_CMD_CMD_RD_WR BIT(8) |
676 | #define SDCI_CMD_RES_TYPE_MASK BITRANGE(16, 18) | 676 | #define SDCI_CMD_RES_TYPE_MASK BITRANGE(16, 18) |
677 | #define SDCI_CMD_RES_TYPE_NONE 0 | 677 | #define SDCI_CMD_RES_TYPE_NONE 0 |
678 | #define SDCI_CMD_RES_TYPE_R1 BIT(16) | 678 | #define SDCI_CMD_RES_TYPE_R1 BIT(16) |
679 | #define SDCI_CMD_RES_TYPE_R2 BIT(17) | 679 | #define SDCI_CMD_RES_TYPE_R2 BIT(17) |
680 | #define SDCI_CMD_RES_TYPE_R3 (BIT(16) | BIT(17)) | 680 | #define SDCI_CMD_RES_TYPE_R3 (BIT(16) | BIT(17)) |
681 | #define SDCI_CMD_RES_TYPE_R4 BIT(18) | 681 | #define SDCI_CMD_RES_TYPE_R4 BIT(18) |
682 | #define SDCI_CMD_RES_TYPE_R5 (BIT(16) | BIT(18)) | 682 | #define SDCI_CMD_RES_TYPE_R5 (BIT(16) | BIT(18)) |
683 | #define SDCI_CMD_RES_TYPE_R6 (BIT(17) | BIT(18)) | 683 | #define SDCI_CMD_RES_TYPE_R6 (BIT(17) | BIT(18)) |
684 | #define SDCI_CMD_RES_BUSY BIT(19) | 684 | #define SDCI_CMD_RES_BUSY BIT(19) |
685 | #define SDCI_CMD_RES_SIZE_MASK BIT(20) | 685 | #define SDCI_CMD_RES_SIZE_MASK BIT(20) |
686 | #define SDCI_CMD_RES_SIZE_48 0 | 686 | #define SDCI_CMD_RES_SIZE_48 0 |
687 | #define SDCI_CMD_RES_SIZE_136 BIT(20) | 687 | #define SDCI_CMD_RES_SIZE_136 BIT(20) |
688 | #define SDCI_CMD_NCR_NID_MASK BIT(21) | 688 | #define SDCI_CMD_NCR_NID_MASK BIT(21) |
689 | #define SDCI_CMD_NCR_NID_NCR 0 | 689 | #define SDCI_CMD_NCR_NID_NCR 0 |
690 | #define SDCI_CMD_NCR_NID_NID BIT(21) | 690 | #define SDCI_CMD_NCR_NID_NID BIT(21) |
691 | #define SDCI_CMD_CMDSTR BIT(31) | 691 | #define SDCI_CMD_CMDSTR BIT(31) |
692 | 692 | ||
693 | #define SDCI_STATE_DAT_STATE_MASK BITRANGE(0, 3) | 693 | #define SDCI_STATE_DAT_STATE_MASK BITRANGE(0, 3) |
694 | #define SDCI_STATE_DAT_STATE_IDLE 0 | 694 | #define SDCI_STATE_DAT_STATE_IDLE 0 |
695 | #define SDCI_STATE_DAT_STATE_DAT_RCV BIT(0) | 695 | #define SDCI_STATE_DAT_STATE_DAT_RCV BIT(0) |
696 | #define SDCI_STATE_DAT_STATE_CRC_RCV BIT(1) | 696 | #define SDCI_STATE_DAT_STATE_CRC_RCV BIT(1) |
697 | #define SDCI_STATE_DAT_STATE_DAT_END (BIT(0) | BIT(1)) | 697 | #define SDCI_STATE_DAT_STATE_DAT_END (BIT(0) | BIT(1)) |
698 | #define SDCI_STATE_DAT_STATE_DAT_SET BIT(2) | 698 | #define SDCI_STATE_DAT_STATE_DAT_SET BIT(2) |
699 | #define SDCI_STATE_DAT_STATE_DAT_OUT (BIT(0) | BIT(2)) | 699 | #define SDCI_STATE_DAT_STATE_DAT_OUT (BIT(0) | BIT(2)) |
700 | #define SDCI_STATE_DAT_STATE_CRC_TIME (BIT(1) | BIT(2)) | 700 | #define SDCI_STATE_DAT_STATE_CRC_TIME (BIT(1) | BIT(2)) |
701 | #define SDCI_STATE_DAT_STATE_CRC_OUT (BIT(0) | BIT(1) | BIT(2)) | 701 | #define SDCI_STATE_DAT_STATE_CRC_OUT (BIT(0) | BIT(1) | BIT(2)) |
702 | #define SDCI_STATE_DAT_STATE_ENDB_OUT BIT(3) | 702 | #define SDCI_STATE_DAT_STATE_ENDB_OUT BIT(3) |
703 | #define SDCI_STATE_DAT_STATE_ENDB_STOD (BIT(0) | BIT(3)) | 703 | #define SDCI_STATE_DAT_STATE_ENDB_STOD (BIT(0) | BIT(3)) |
704 | #define SDCI_STATE_DAT_STATE_DAT_CRCR (BIT(1) | BIT(3)) | 704 | #define SDCI_STATE_DAT_STATE_DAT_CRCR (BIT(1) | BIT(3)) |
705 | #define SDCI_STATE_DAT_STATE_CARD_PRG (BIT(0) | BIT(1) | BIT(3)) | 705 | #define SDCI_STATE_DAT_STATE_CARD_PRG (BIT(0) | BIT(1) | BIT(3)) |
706 | #define SDCI_STATE_DAT_STATE_DAT_BUSY (BIT(2) | BIT(3)) | 706 | #define SDCI_STATE_DAT_STATE_DAT_BUSY (BIT(2) | BIT(3)) |
707 | #define SDCI_STATE_CMD_STATE_MASK (BIT(4) | BIT(5) | BIT(6)) | 707 | #define SDCI_STATE_CMD_STATE_MASK (BIT(4) | BIT(5) | BIT(6)) |
708 | #define SDCI_STATE_CMD_STATE_CMD_IDLE 0 | 708 | #define SDCI_STATE_CMD_STATE_CMD_IDLE 0 |
709 | #define SDCI_STATE_CMD_STATE_CMD_CMDO BIT(4) | 709 | #define SDCI_STATE_CMD_STATE_CMD_CMDO BIT(4) |
710 | #define SDCI_STATE_CMD_STATE_CMD_CRCO BIT(5) | 710 | #define SDCI_STATE_CMD_STATE_CMD_CRCO BIT(5) |
711 | #define SDCI_STATE_CMD_STATE_CMD_TOUT (BIT(4) | BIT(5)) | 711 | #define SDCI_STATE_CMD_STATE_CMD_TOUT (BIT(4) | BIT(5)) |
712 | #define SDCI_STATE_CMD_STATE_CMD_RESR BIT(6) | 712 | #define SDCI_STATE_CMD_STATE_CMD_RESR BIT(6) |
713 | #define SDCI_STATE_CMD_STATE_CMD_INTV (BIT(4) | BIT(6)) | 713 | #define SDCI_STATE_CMD_STATE_CMD_INTV (BIT(4) | BIT(6)) |
714 | 714 | ||
715 | #define SDCI_STAC_CLR_CMDEND BIT(2) | 715 | #define SDCI_STAC_CLR_CMDEND BIT(2) |
716 | #define SDCI_STAC_CLR_BIT_3 BIT(3) | 716 | #define SDCI_STAC_CLR_BIT_3 BIT(3) |
717 | #define SDCI_STAC_CLR_RESEND BIT(4) | 717 | #define SDCI_STAC_CLR_RESEND BIT(4) |
718 | #define SDCI_STAC_CLR_DATEND BIT(6) | 718 | #define SDCI_STAC_CLR_DATEND BIT(6) |
719 | #define SDCI_STAC_CLR_DAT_CRCEND BIT(7) | 719 | #define SDCI_STAC_CLR_DAT_CRCEND BIT(7) |
720 | #define SDCI_STAC_CLR_CRC_STAEND BIT(8) | 720 | #define SDCI_STAC_CLR_CRC_STAEND BIT(8) |
721 | #define SDCI_STAC_CLR_RESTOUTE BIT(15) | 721 | #define SDCI_STAC_CLR_RESTOUTE BIT(15) |
722 | #define SDCI_STAC_CLR_RESENDE BIT(16) | 722 | #define SDCI_STAC_CLR_RESENDE BIT(16) |
723 | #define SDCI_STAC_CLR_RESINDE BIT(17) | 723 | #define SDCI_STAC_CLR_RESINDE BIT(17) |
724 | #define SDCI_STAC_CLR_RESCRCE BIT(18) | 724 | #define SDCI_STAC_CLR_RESCRCE BIT(18) |
725 | #define SDCI_STAC_CLR_WR_DATCRCE BIT(22) | 725 | #define SDCI_STAC_CLR_WR_DATCRCE BIT(22) |
726 | #define SDCI_STAC_CLR_RD_DATCRCE BIT(23) | 726 | #define SDCI_STAC_CLR_RD_DATCRCE BIT(23) |
727 | #define SDCI_STAC_CLR_RD_DATENDE0 BIT(24) | 727 | #define SDCI_STAC_CLR_RD_DATENDE0 BIT(24) |
728 | #define SDCI_STAC_CLR_RD_DATENDE1 BIT(25) | 728 | #define SDCI_STAC_CLR_RD_DATENDE1 BIT(25) |
729 | #define SDCI_STAC_CLR_RD_DATENDE2 BIT(26) | 729 | #define SDCI_STAC_CLR_RD_DATENDE2 BIT(26) |
730 | #define SDCI_STAC_CLR_RD_DATENDE3 BIT(27) | 730 | #define SDCI_STAC_CLR_RD_DATENDE3 BIT(27) |
731 | #define SDCI_STAC_CLR_RD_DATENDE4 BIT(28) | 731 | #define SDCI_STAC_CLR_RD_DATENDE4 BIT(28) |
732 | #define SDCI_STAC_CLR_RD_DATENDE5 BIT(29) | 732 | #define SDCI_STAC_CLR_RD_DATENDE5 BIT(29) |
733 | #define SDCI_STAC_CLR_RD_DATENDE6 BIT(30) | 733 | #define SDCI_STAC_CLR_RD_DATENDE6 BIT(30) |
734 | #define SDCI_STAC_CLR_RD_DATENDE7 BIT(31) | 734 | #define SDCI_STAC_CLR_RD_DATENDE7 BIT(31) |
735 | 735 | ||
736 | #define SDCI_DSTA_CMDRDY BIT(0) | 736 | #define SDCI_DSTA_CMDRDY BIT(0) |
737 | #define SDCI_DSTA_CMDPRO BIT(1) | 737 | #define SDCI_DSTA_CMDPRO BIT(1) |
738 | #define SDCI_DSTA_CMDEND BIT(2) | 738 | #define SDCI_DSTA_CMDEND BIT(2) |
739 | #define SDCI_DSTA_RESPRO BIT(3) | 739 | #define SDCI_DSTA_RESPRO BIT(3) |
740 | #define SDCI_DSTA_RESEND BIT(4) | 740 | #define SDCI_DSTA_RESEND BIT(4) |
741 | #define SDCI_DSTA_DATPRO BIT(5) | 741 | #define SDCI_DSTA_DATPRO BIT(5) |
742 | #define SDCI_DSTA_DATEND BIT(6) | 742 | #define SDCI_DSTA_DATEND BIT(6) |
743 | #define SDCI_DSTA_DAT_CRCEND BIT(7) | 743 | #define SDCI_DSTA_DAT_CRCEND BIT(7) |
744 | #define SDCI_DSTA_CRC_STAEND BIT(8) | 744 | #define SDCI_DSTA_CRC_STAEND BIT(8) |
745 | #define SDCI_DSTA_DAT_BUSY BIT(9) | 745 | #define SDCI_DSTA_DAT_BUSY BIT(9) |
746 | #define SDCI_DSTA_SDCLK_HOLD BIT(12) | 746 | #define SDCI_DSTA_SDCLK_HOLD BIT(12) |
747 | #define SDCI_DSTA_DAT0_STATUS BIT(13) | 747 | #define SDCI_DSTA_DAT0_STATUS BIT(13) |
748 | #define SDCI_DSTA_WP_DECT_INPUT BIT(14) | 748 | #define SDCI_DSTA_WP_DECT_INPUT BIT(14) |
749 | #define SDCI_DSTA_RESTOUTE BIT(15) | 749 | #define SDCI_DSTA_RESTOUTE BIT(15) |
750 | #define SDCI_DSTA_RESENDE BIT(16) | 750 | #define SDCI_DSTA_RESENDE BIT(16) |
751 | #define SDCI_DSTA_RESINDE BIT(17) | 751 | #define SDCI_DSTA_RESINDE BIT(17) |
752 | #define SDCI_DSTA_RESCRCE BIT(18) | 752 | #define SDCI_DSTA_RESCRCE BIT(18) |
753 | #define SDCI_DSTA_WR_CRC_STATUS_MASK BITRANGE(19, 21) | 753 | #define SDCI_DSTA_WR_CRC_STATUS_MASK BITRANGE(19, 21) |
754 | #define SDCI_DSTA_WR_CRC_STATUS_OK BIT(20) | 754 | #define SDCI_DSTA_WR_CRC_STATUS_OK BIT(20) |
755 | #define SDCI_DSTA_WR_CRC_STATUS_TXERR (BIT(19) | BIT(21)) | 755 | #define SDCI_DSTA_WR_CRC_STATUS_TXERR (BIT(19) | BIT(21)) |
756 | #define SDCI_DSTA_WR_CRC_STATUS_CARDERR (BIT(19) | BIT(20) | BIT(21)) | 756 | #define SDCI_DSTA_WR_CRC_STATUS_CARDERR (BIT(19) | BIT(20) | BIT(21)) |
757 | #define SDCI_DSTA_WR_DATCRCE BIT(22) | 757 | #define SDCI_DSTA_WR_DATCRCE BIT(22) |
758 | #define SDCI_DSTA_RD_DATCRCE BIT(23) | 758 | #define SDCI_DSTA_RD_DATCRCE BIT(23) |
759 | #define SDCI_DSTA_RD_DATENDE0 BIT(24) | 759 | #define SDCI_DSTA_RD_DATENDE0 BIT(24) |
760 | #define SDCI_DSTA_RD_DATENDE1 BIT(25) | 760 | #define SDCI_DSTA_RD_DATENDE1 BIT(25) |
761 | #define SDCI_DSTA_RD_DATENDE2 BIT(26) | 761 | #define SDCI_DSTA_RD_DATENDE2 BIT(26) |
762 | #define SDCI_DSTA_RD_DATENDE3 BIT(27) | 762 | #define SDCI_DSTA_RD_DATENDE3 BIT(27) |
763 | #define SDCI_DSTA_RD_DATENDE4 BIT(28) | 763 | #define SDCI_DSTA_RD_DATENDE4 BIT(28) |
764 | #define SDCI_DSTA_RD_DATENDE5 BIT(29) | 764 | #define SDCI_DSTA_RD_DATENDE5 BIT(29) |
765 | #define SDCI_DSTA_RD_DATENDE6 BIT(30) | 765 | #define SDCI_DSTA_RD_DATENDE6 BIT(30) |
766 | #define SDCI_DSTA_RD_DATENDE7 BIT(31) | 766 | #define SDCI_DSTA_RD_DATENDE7 BIT(31) |
767 | 767 | ||
768 | #define SDCI_FSTA_RX_FIFO_EMPTY BIT(0) | 768 | #define SDCI_FSTA_RX_FIFO_EMPTY BIT(0) |
769 | #define SDCI_FSTA_RX_FIFO_FULL BIT(1) | 769 | #define SDCI_FSTA_RX_FIFO_FULL BIT(1) |
770 | #define SDCI_FSTA_TX_FIFO_EMPTY BIT(2) | 770 | #define SDCI_FSTA_TX_FIFO_EMPTY BIT(2) |
771 | #define SDCI_FSTA_TX_FIFO_FULL BIT(3) | 771 | #define SDCI_FSTA_TX_FIFO_FULL BIT(3) |
772 | 772 | ||
773 | #define SDCI_SDIO_CSR_SDIO_RW_EN BIT(0) | 773 | #define SDCI_SDIO_CSR_SDIO_RW_EN BIT(0) |
774 | #define SDCI_SDIO_CSR_SDIO_INT_EN BIT(1) | 774 | #define SDCI_SDIO_CSR_SDIO_INT_EN BIT(1) |
775 | #define SDCI_SDIO_CSR_SDIO_RW_REQ BIT(2) | 775 | #define SDCI_SDIO_CSR_SDIO_RW_REQ BIT(2) |
776 | #define SDCI_SDIO_CSR_SDIO_RW_STOP BIT(3) | 776 | #define SDCI_SDIO_CSR_SDIO_RW_STOP BIT(3) |
777 | #define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MASK BIT(4) | 777 | #define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MASK BIT(4) |
778 | #define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MORE 0 | 778 | #define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MORE 0 |
779 | #define SDCI_SDIO_CSR_SDIO_INT_PERIOD_XACT BIT(4) | 779 | #define SDCI_SDIO_CSR_SDIO_INT_PERIOD_XACT BIT(4) |
780 | 780 | ||
781 | #define SDCI_IRQ_DAT_DONE_INT BIT(0) | 781 | #define SDCI_IRQ_DAT_DONE_INT BIT(0) |
782 | #define SDCI_IRQ_IOCARD_IRQ_INT BIT(1) | 782 | #define SDCI_IRQ_IOCARD_IRQ_INT BIT(1) |
783 | #define SDCI_IRQ_READ_WAIT_INT BIT(2) | 783 | #define SDCI_IRQ_READ_WAIT_INT BIT(2) |
784 | 784 | ||
785 | #define SDCI_IRQ_MASK_MASK_DAT_DONE_INT BIT(0) | 785 | #define SDCI_IRQ_MASK_MASK_DAT_DONE_INT BIT(0) |
786 | #define SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT BIT(1) | 786 | #define SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT BIT(1) |
787 | #define SDCI_IRQ_MASK_MASK_READ_WAIT_INT BIT(2) | 787 | #define SDCI_IRQ_MASK_MASK_READ_WAIT_INT BIT(2) |
788 | 788 | ||
789 | 789 | ||
790 | /////CLICKWHEEL///// | 790 | /////CLICKWHEEL///// |
791 | #define WHEEL00 (*((uint32_t volatile*)(0x3C200000))) | 791 | #define WHEEL00 (*((uint32_t volatile*)(0x3C200000))) |
792 | #define WHEEL04 (*((uint32_t volatile*)(0x3C200004))) | 792 | #define WHEEL04 (*((uint32_t volatile*)(0x3C200004))) |
793 | #define WHEEL08 (*((uint32_t volatile*)(0x3C200008))) | 793 | #define WHEEL08 (*((uint32_t volatile*)(0x3C200008))) |
794 | #define WHEEL0C (*((uint32_t volatile*)(0x3C20000C))) | 794 | #define WHEEL0C (*((uint32_t volatile*)(0x3C20000C))) |
795 | #define WHEEL10 (*((uint32_t volatile*)(0x3C200010))) | 795 | #define WHEEL10 (*((uint32_t volatile*)(0x3C200010))) |
796 | #define WHEELINT (*((uint32_t volatile*)(0x3C200014))) | 796 | #define WHEELINT (*((uint32_t volatile*)(0x3C200014))) |
797 | #define WHEELRX (*((uint32_t volatile*)(0x3C200018))) | 797 | #define WHEELRX (*((uint32_t volatile*)(0x3C200018))) |
798 | #define WHEELTX (*((uint32_t volatile*)(0x3C20001C))) | 798 | #define WHEELTX (*((uint32_t volatile*)(0x3C20001C))) |
799 | 799 | ||
800 | 800 | ||
801 | /////I2S///// | 801 | /////I2S///// |
802 | #define I2SCLKCON (*((volatile uint32_t*)(0x3CA00000))) | 802 | #define I2SCLKCON (*((volatile uint32_t*)(0x3CA00000))) |
803 | #define I2STXCON (*((volatile uint32_t*)(0x3CA00004))) | 803 | #define I2STXCON (*((volatile uint32_t*)(0x3CA00004))) |
804 | #define I2STXCOM (*((volatile uint32_t*)(0x3CA00008))) | 804 | #define I2STXCOM (*((volatile uint32_t*)(0x3CA00008))) |
805 | #define I2STXDB0 (*((volatile uint32_t*)(0x3CA00010))) | 805 | #define I2STXDB0 (*((volatile uint32_t*)(0x3CA00010))) |
806 | #define I2SRXCON (*((volatile uint32_t*)(0x3CA00030))) | 806 | #define I2SRXCON (*((volatile uint32_t*)(0x3CA00030))) |
807 | #define I2SRXCOM (*((volatile uint32_t*)(0x3CA00034))) | 807 | #define I2SRXCOM (*((volatile uint32_t*)(0x3CA00034))) |
808 | #define I2SRXDB (*((volatile uint32_t*)(0x3CA00038))) | 808 | #define I2SRXDB (*((volatile uint32_t*)(0x3CA00038))) |
809 | #define I2SSTATUS (*((volatile uint32_t*)(0x3CA0003C))) | 809 | #define I2SSTATUS (*((volatile uint32_t*)(0x3CA0003C))) |
810 | #define I2S40 (*((volatile uint32_t*)(0x3CA00040))) | 810 | #define I2S40 (*((volatile uint32_t*)(0x3CA00040))) |
811 | 811 | ||
812 | 812 | ||
813 | /////CLOCK GATES///// | 813 | /////CLOCK GATES///// |
814 | #define CLOCKGATE_USB_1 2 | 814 | #define CLOCKGATE_USB_1 2 |
815 | #define CLOCKGATE_USB_2 35 | 815 | #define CLOCKGATE_USB_2 35 |
816 | 816 | ||
817 | 817 | ||
818 | /////INTERRUPTS///// | 818 | /////INTERRUPTS///// |
819 | #define IRQ_TIMER 8 | 819 | #define IRQ_TIMER 8 |
820 | #define IRQ_USB_FUNC 19 | 820 | #define IRQ_USB_FUNC 19 |
821 | #define IRQ_DMAC(d) 16 + d | 821 | #define IRQ_DMAC(d) 16 + d |
822 | #define IRQ_DMAC0 16 | 822 | #define IRQ_DMAC0 16 |
823 | #define IRQ_DMAC1 17 | 823 | #define IRQ_DMAC1 17 |
824 | #define IRQ_WHEEL 23 | 824 | #define IRQ_WHEEL 23 |
825 | #define IRQ_ATA 29 | 825 | #define IRQ_ATA 29 |
826 | #define IRQ_MMC 44 | 826 | #define IRQ_MMC 44 |
827 | 827 | ||
828 | 828 | ||
829 | #endif | 829 | #endif |
830 | 830 | ||
diff --git a/firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c b/firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c index 4650913ce3..2d8d25cf31 100644 --- a/firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c +++ b/firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c | |||
@@ -5,7 +5,7 @@ | |||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id: lcd-clipzip.c 30465 2011-09-06 16:55:52Z bertrik $ | 8 | * $Id$ |
9 | * | 9 | * |
10 | * Copyright (C) 2011 Bertrik Sikken | 10 | * Copyright (C) 2011 Bertrik Sikken |
11 | * | 11 | * |
diff --git a/firmware/target/arm/s5l8700/postmortemstub.S b/firmware/target/arm/s5l8700/postmortemstub.S index 73f192a553..d0874c418b 100644 --- a/firmware/target/arm/s5l8700/postmortemstub.S +++ b/firmware/target/arm/s5l8700/postmortemstub.S | |||
@@ -1,308 +1,308 @@ | |||
1 | .section .text.post_mortem_stub, "ax", %progbits | 1 | .section .text.post_mortem_stub, "ax", %progbits |
2 | .align 4 | 2 | .align 4 |
3 | .global post_mortem_stub | 3 | .global post_mortem_stub |
4 | .type post_mortem_stub, %function | 4 | .type post_mortem_stub, %function |
5 | post_mortem_stub: | 5 | post_mortem_stub: |
6 | MSR CPSR_c, #0xD3 @ Supervisor mode, no IRQs, no FIQs | 6 | MSR CPSR_c, #0xD3 @ Supervisor mode, no IRQs, no FIQs |
7 | MRC p15, 0, R0,c1,c0 | 7 | MRC p15, 0, R0,c1,c0 |
8 | BIC R0, R0, #5 | 8 | BIC R0, R0, #5 |
9 | MCR p15, 0, R0,c1,c0 @ Disable the Protection Unit and DCache | 9 | MCR p15, 0, R0,c1,c0 @ Disable the Protection Unit and DCache |
10 | MOV R13, #0 | 10 | MOV R13, #0 |
11 | pms_flushcache_loop: | 11 | pms_flushcache_loop: |
12 | MCR p15, 0, R13,c7,c14,2 | 12 | MCR p15, 0, R13,c7,c14,2 |
13 | ADD R0, R13, #0x10 | 13 | ADD R0, R13, #0x10 |
14 | MCR p15, 0, R0,c7,c14,2 | 14 | MCR p15, 0, R0,c7,c14,2 |
15 | ADD R0, R0, #0x10 | 15 | ADD R0, R0, #0x10 |
16 | MCR p15, 0, R0,c7,c14,2 | 16 | MCR p15, 0, R0,c7,c14,2 |
17 | ADD R0, R0, #0x10 | 17 | ADD R0, R0, #0x10 |
18 | MCR p15, 0, R0,c7,c14,2 | 18 | MCR p15, 0, R0,c7,c14,2 |
19 | ADDS R13, R13, #0x04000000 | 19 | ADDS R13, R13, #0x04000000 |
20 | BNE pms_flushcache_loop | 20 | BNE pms_flushcache_loop |
21 | MCR p15, 0, R13,c7,c10,4 | 21 | MCR p15, 0, R13,c7,c10,4 |
22 | 22 | ||
23 | LDR R7, pms_00080200 | 23 | LDR R7, pms_00080200 |
24 | ORR R8, R7, #0x8000 | 24 | ORR R8, R7, #0x8000 |
25 | ADR R9, pms_recvbuf | 25 | ADR R9, pms_recvbuf |
26 | LDR R10, pms_20080040 | 26 | LDR R10, pms_20080040 |
27 | MOV R11, #0x38800000 | 27 | MOV R11, #0x38800000 |
28 | MOV R12, #1 | 28 | MOV R12, #1 |
29 | 29 | ||
30 | MOV R2, #0x3C400000 | 30 | MOV R2, #0x3C400000 |
31 | ADD R1, R2, #0x00100000 @ Enable USB clocks | 31 | ADD R1, R2, #0x00100000 @ Enable USB clocks |
32 | LDR R0, [R1,#0x28] | 32 | LDR R0, [R1,#0x28] |
33 | BIC R0, R0, #0x4000 | 33 | BIC R0, R0, #0x4000 |
34 | STR R0, [R1,#0x28] | 34 | STR R0, [R1,#0x28] |
35 | LDR R0, [R1,#0x40] | 35 | LDR R0, [R1,#0x40] |
36 | BIC R0, R0, #0x800 | 36 | BIC R0, R0, #0x800 |
37 | STR R0, [R1,#0x40] | 37 | STR R0, [R1,#0x40] |
38 | LDR R0, pms_20803180 @ Clocking config | 38 | LDR R0, pms_20803180 @ Clocking config |
39 | STR R0, [R1] | 39 | STR R0, [R1] |
40 | MOV R0, #0x280 | 40 | MOV R0, #0x280 |
41 | STR R0, [R1,#0x3C] | 41 | STR R0, [R1,#0x3C] |
42 | MRC p15, 0, R0,c1,c0 | 42 | MRC p15, 0, R0,c1,c0 |
43 | ORR R0, R0, #0xc0000000 | 43 | ORR R0, R0, #0xc0000000 |
44 | MCR p15, 0, R0,c1,c0 @ Asynchronous mode | 44 | MCR p15, 0, R0,c1,c0 @ Asynchronous mode |
45 | 45 | ||
46 | STR R13, [R11,#0xE00] @ PHY clock enable | 46 | STR R13, [R11,#0xE00] @ PHY clock enable |
47 | 47 | ||
48 | MOV R1, #0x800 | 48 | MOV R1, #0x800 |
49 | ORR R0, R2, #2 | 49 | ORR R0, R2, #2 |
50 | STR R0, [R11,#0x804] @ USB2 Gadget: Soft disconnect | 50 | STR R0, [R11,#0x804] @ USB2 Gadget: Soft disconnect |
51 | 51 | ||
52 | STR R13, [R2] @ USB2 PHY: Power on | 52 | STR R13, [R2] @ USB2 PHY: Power on |
53 | STR R12, [R2,#0x08] @ USB2 PHY: Assert Software Reset | 53 | STR R12, [R2,#0x08] @ USB2 PHY: Assert Software Reset |
54 | MOV R0, #0x10000 | 54 | MOV R0, #0x10000 |
55 | pms_wait: | 55 | pms_wait: |
56 | SUBS R0, R0, #1 | 56 | SUBS R0, R0, #1 |
57 | BNE pms_wait | 57 | BNE pms_wait |
58 | STR R13, [R2,#0x08] @ USB2 PHY: Deassert Software Reset | 58 | STR R13, [R2,#0x08] @ USB2 PHY: Deassert Software Reset |
59 | STR R13, [R2,#0x04] @ USB2 PHY: Clock is 48MHz | 59 | STR R13, [R2,#0x04] @ USB2 PHY: Clock is 48MHz |
60 | 60 | ||
61 | STR R12, [R11,#0x10] @ USB2 Gadget: Assert Core Software Reset | 61 | STR R12, [R11,#0x10] @ USB2 Gadget: Assert Core Software Reset |
62 | pms_waitcorereset: | 62 | pms_waitcorereset: |
63 | LDR R0, [R11,#0x10] @ USB2 Gadget: Wait for Core to reset | 63 | LDR R0, [R11,#0x10] @ USB2 Gadget: Wait for Core to reset |
64 | TST R0, #1 | 64 | TST R0, #1 |
65 | BNE pms_waitcorereset | 65 | BNE pms_waitcorereset |
66 | TST R0, #0x80000000 @ USB2 Gadget: Wait for AHB IDLE | 66 | TST R0, #0x80000000 @ USB2 Gadget: Wait for AHB IDLE |
67 | BEQ pms_waitcorereset | 67 | BEQ pms_waitcorereset |
68 | 68 | ||
69 | MOV R0, #0x200 | 69 | MOV R0, #0x200 |
70 | STR R0, [R11,#0x24] @ USB2 Gadget: RX FIFO size: 512 bytes | 70 | STR R0, [R11,#0x24] @ USB2 Gadget: RX FIFO size: 512 bytes |
71 | ORR R0, R0, #0x2000000 | 71 | ORR R0, R0, #0x2000000 |
72 | STR R0, [R11,#0x28] @ USB2 Gadget: Non-periodic TX FIFO size: 512 bytes | 72 | STR R0, [R11,#0x28] @ USB2 Gadget: Non-periodic TX FIFO size: 512 bytes |
73 | MOV R0, #0x26 | 73 | MOV R0, #0x26 |
74 | STR R0, [R11,#0x08] @ USB2 Gadget: DMA Enable, Burst Length: 4, Mask Interrupts | 74 | STR R0, [R11,#0x08] @ USB2 Gadget: DMA Enable, Burst Length: 4, Mask Interrupts |
75 | MOV R0, #0x1400 | 75 | MOV R0, #0x1400 |
76 | ADD R0, R0, #8 | 76 | ADD R0, R0, #8 |
77 | STR R0, [R11,#0x0C] @ USB2 Gadget: PHY IF is 16bit, Turnaround 5 | 77 | STR R0, [R11,#0x0C] @ USB2 Gadget: PHY IF is 16bit, Turnaround 5 |
78 | STR R1, [R11,#0x804] @ USB2 Gadget: Soft reconnect | 78 | STR R1, [R11,#0x804] @ USB2 Gadget: Soft reconnect |
79 | 79 | ||
80 | ADR R14, pms_ctrlbuf | 80 | ADR R14, pms_ctrlbuf |
81 | ORR R5, R8, #0x84000000 | 81 | ORR R5, R8, #0x84000000 |
82 | @ fallthrough | 82 | @ fallthrough |
83 | 83 | ||
84 | pms_mainloop: | 84 | pms_mainloop: |
85 | LDR R3, [R11,#0x14] @ Global USB interrupts | 85 | LDR R3, [R11,#0x14] @ Global USB interrupts |
86 | TST R3, #0x00001000 @ BUS reset | 86 | TST R3, #0x00001000 @ BUS reset |
87 | BEQ pms_noreset | 87 | BEQ pms_noreset |
88 | MOV R0, #0x500 | 88 | MOV R0, #0x500 |
89 | STR R0, [R11,#0x804] | 89 | STR R0, [R11,#0x804] |
90 | MOV R0, #4 | 90 | MOV R0, #4 |
91 | STR R0, [R11,#0x800] @ USB2 Gadget: Device Address 0, STALL on non-zero length status stage | 91 | STR R0, [R11,#0x800] @ USB2 Gadget: Device Address 0, STALL on non-zero length status stage |
92 | MOV R0, #0x8000 | 92 | MOV R0, #0x8000 |
93 | STR R0, [R11,#0x900] @ USB2 Gadget: Endpoint 0 IN Control: ACTIVE | 93 | STR R0, [R11,#0x900] @ USB2 Gadget: Endpoint 0 IN Control: ACTIVE |
94 | STR R10, [R11,#0xB10] @ USB2 Gadget: Endpoint 0 OUT Transfer Size: 64 Bytes, 1 Packet, 1 Setup Packet | 94 | STR R10, [R11,#0xB10] @ USB2 Gadget: Endpoint 0 OUT Transfer Size: 64 Bytes, 1 Packet, 1 Setup Packet |
95 | STR R14, [R11,#0xB14] @ USB2 Gadget: Endpoint 0 OUT DMA Address: pms_ctrlbuf | 95 | STR R14, [R11,#0xB14] @ USB2 Gadget: Endpoint 0 OUT DMA Address: pms_ctrlbuf |
96 | ORR R6, R0, #0x84000000 | 96 | ORR R6, R0, #0x84000000 |
97 | STR R6, [R11,#0xB00] @ USB2 Gadget: Endpoint 0 OUT Control: ENABLE CLEARNAK | 97 | STR R6, [R11,#0xB00] @ USB2 Gadget: Endpoint 0 OUT Control: ENABLE CLEARNAK |
98 | STR R8, [R11,#0x960] @ USB2 Gadget: Endpoint 3 IN Control: ACTIVE BULK, 512 byte packets | 98 | STR R8, [R11,#0x960] @ USB2 Gadget: Endpoint 3 IN Control: ACTIVE BULK, 512 byte packets |
99 | STR R8, [R11,#0xB80] @ USB2 Gadget: Endpoint 4 OUT Control: ACTIVE BULK, 512 byte packets | 99 | STR R8, [R11,#0xB80] @ USB2 Gadget: Endpoint 4 OUT Control: ACTIVE BULK, 512 byte packets |
100 | STR R7, [R11,#0xB90] @ USB2 Gadget: Endpoint 4 OUT Transfer Size: 512 Bytes, 1 Packet | 100 | STR R7, [R11,#0xB90] @ USB2 Gadget: Endpoint 4 OUT Transfer Size: 512 Bytes, 1 Packet |
101 | STR R9, [R11,#0xB94] @ USB2 Gadget: Endpoint 4 OUT DMA Address: pms_recvbuf | 101 | STR R9, [R11,#0xB94] @ USB2 Gadget: Endpoint 4 OUT DMA Address: pms_recvbuf |
102 | ORR R4, R5, #0x10000000 | 102 | ORR R4, R5, #0x10000000 |
103 | STR R4, [R11,#0xB80] @ USB2 Gadget: Endpoint 4 OUT Control: ENABLE CLEARNAK DATA0 | 103 | STR R4, [R11,#0xB80] @ USB2 Gadget: Endpoint 4 OUT Control: ENABLE CLEARNAK DATA0 |
104 | pms_noreset: | 104 | pms_noreset: |
105 | LDR R0, [R11,#0x908] @ Just ACK all IN events... | 105 | LDR R0, [R11,#0x908] @ Just ACK all IN events... |
106 | STR R0, [R11,#0x908] | 106 | STR R0, [R11,#0x908] |
107 | LDR R0, [R11,#0x968] | 107 | LDR R0, [R11,#0x968] |
108 | STR R0, [R11,#0x968] | 108 | STR R0, [R11,#0x968] |
109 | LDR R2, [R11,#0xB08] | 109 | LDR R2, [R11,#0xB08] |
110 | MOVS R2, R2 @ Event on OUT EP0 | 110 | MOVS R2, R2 @ Event on OUT EP0 |
111 | BEQ pms_noep0out | 111 | BEQ pms_noep0out |
112 | TST R2, #8 @ SETUP phase done | 112 | TST R2, #8 @ SETUP phase done |
113 | BEQ pms_controldone | 113 | BEQ pms_controldone |
114 | LDRB R0, [R14,#1] @ Get request type | 114 | LDRB R0, [R14,#1] @ Get request type |
115 | CMP R0, #0 | 115 | CMP R0, #0 |
116 | BEQ pms_GET_STATUS | 116 | BEQ pms_GET_STATUS |
117 | CMP R0, #1 | 117 | CMP R0, #1 |
118 | BEQ pms_CLEAR_FEATURE | 118 | BEQ pms_CLEAR_FEATURE |
119 | CMP R0, #3 | 119 | CMP R0, #3 |
120 | BEQ pms_SET_FEATURE | 120 | BEQ pms_SET_FEATURE |
121 | CMP R0, #5 | 121 | CMP R0, #5 |
122 | BEQ pms_SET_ADDRESS | 122 | BEQ pms_SET_ADDRESS |
123 | CMP R0, #6 | 123 | CMP R0, #6 |
124 | BEQ pms_GET_DESCRIPTOR | 124 | BEQ pms_GET_DESCRIPTOR |
125 | CMP R0, #8 | 125 | CMP R0, #8 |
126 | BEQ pms_GET_CONFIGURATION | 126 | BEQ pms_GET_CONFIGURATION |
127 | CMP R0, #9 | 127 | CMP R0, #9 |
128 | BEQ pms_SET_CONFIGURATION | 128 | BEQ pms_SET_CONFIGURATION |
129 | pms_ctrlstall: | 129 | pms_ctrlstall: |
130 | LDR R0, [R11,#0x900] | 130 | LDR R0, [R11,#0x900] |
131 | ORR R0, R0, #0x00200000 | 131 | ORR R0, R0, #0x00200000 |
132 | STR R0, [R11,#0x900] @ Stall IN EP0 | 132 | STR R0, [R11,#0x900] @ Stall IN EP0 |
133 | LDR R0, [R11,#0xB00] | 133 | LDR R0, [R11,#0xB00] |
134 | ORR R0, R0, #0x00200000 | 134 | ORR R0, R0, #0x00200000 |
135 | STR R0, [R11,#0xB00] @ Stall OUT EP0 | 135 | STR R0, [R11,#0xB00] @ Stall OUT EP0 |
136 | pms_controldone: | 136 | pms_controldone: |
137 | STR R10, [R11,#0xB10] @ OUT EP0: 64 Bytes, 1 Packet, 1 Setup Packet | 137 | STR R10, [R11,#0xB10] @ OUT EP0: 64 Bytes, 1 Packet, 1 Setup Packet |
138 | STR R14, [R11,#0xB14] @ OUT EP0: DMA address | 138 | STR R14, [R11,#0xB14] @ OUT EP0: DMA address |
139 | STR R6, [R11,#0xB00] @ OUT EP0: Enable ClearNAK | 139 | STR R6, [R11,#0xB00] @ OUT EP0: Enable ClearNAK |
140 | pms_noep0out: | 140 | pms_noep0out: |
141 | STR R2, [R11,#0xB08] @ ACK it, whatever it was... | 141 | STR R2, [R11,#0xB08] @ ACK it, whatever it was... |
142 | LDR R2, [R11,#0xB88] | 142 | LDR R2, [R11,#0xB88] |
143 | MOVS R2, R2 @ Event on OUT EP4 | 143 | MOVS R2, R2 @ Event on OUT EP4 |
144 | BEQ pms_noep1out | 144 | BEQ pms_noep1out |
145 | TST R2, #1 @ XFER complete | 145 | TST R2, #1 @ XFER complete |
146 | BEQ pms_datadone | 146 | BEQ pms_datadone |
147 | LDR R0, pms_000001FF | 147 | LDR R0, pms_000001FF |
148 | LDR R1, pms_recvbuf+4 | 148 | LDR R1, pms_recvbuf+4 |
149 | ADD R0, R0, R1 | 149 | ADD R0, R0, R1 |
150 | MOV R0, R0,LSR#9 | 150 | MOV R0, R0,LSR#9 |
151 | ORR R1, R1, R0,LSL#19 @ Number of packets | 151 | ORR R1, R1, R0,LSL#19 @ Number of packets |
152 | LDR R0, pms_recvbuf | 152 | LDR R0, pms_recvbuf |
153 | STR R1, [R11,#0x970] @ EP3 IN: Number of packets, size | 153 | STR R1, [R11,#0x970] @ EP3 IN: Number of packets, size |
154 | STR R0, [R11,#0x974] @ EP3 IN: DMA address | 154 | STR R0, [R11,#0x974] @ EP3 IN: DMA address |
155 | STR R5, [R11,#0x960] @ EP3 IN: Enable ClearNAK | 155 | STR R5, [R11,#0x960] @ EP3 IN: Enable ClearNAK |
156 | pms_datadone: | 156 | pms_datadone: |
157 | STR R7, [R11,#0xB90] @ OUT EP4: 512 Bytes, 1 Packet | 157 | STR R7, [R11,#0xB90] @ OUT EP4: 512 Bytes, 1 Packet |
158 | STR R9, [R11,#0xB94] @ Out EP4: DMA address | 158 | STR R9, [R11,#0xB94] @ Out EP4: DMA address |
159 | STR R5, [R11,#0xB80] @ Out EP4: Enable ClearNAK | 159 | STR R5, [R11,#0xB80] @ Out EP4: Enable ClearNAK |
160 | pms_noep1out: | 160 | pms_noep1out: |
161 | STR R2, [R11,#0xB88] @ ACK it, whatever it was... | 161 | STR R2, [R11,#0xB88] @ ACK it, whatever it was... |
162 | STR R3, [R11,#0x14] @ ACK global ints | 162 | STR R3, [R11,#0x14] @ ACK global ints |
163 | B pms_mainloop | 163 | B pms_mainloop |
164 | 164 | ||
165 | pms_CLEAR_FEATURE: | 165 | pms_CLEAR_FEATURE: |
166 | LDRB R0, [R14] | 166 | LDRB R0, [R14] |
167 | CMP R0, #2 | 167 | CMP R0, #2 |
168 | LDREQ R0, [R14,#2] | 168 | LDREQ R0, [R14,#2] |
169 | BICEQ R0, R0, #0x00800000 | 169 | BICEQ R0, R0, #0x00800000 |
170 | CMPEQ R0, #0x00010000 | 170 | CMPEQ R0, #0x00010000 |
171 | @ fallthrough | 171 | @ fallthrough |
172 | 172 | ||
173 | pms_SET_CONFIGURATION: | 173 | pms_SET_CONFIGURATION: |
174 | ORREQ R0, R8, #0x10000000 | 174 | ORREQ R0, R8, #0x10000000 |
175 | STREQ R0, [R11,#0x960] @ EP3 IN: Set DATA0 PID | 175 | STREQ R0, [R11,#0x960] @ EP3 IN: Set DATA0 PID |
176 | STREQ R4, [R11,#0xB80] @ EP4 OUT: Set DATA0 PID | 176 | STREQ R4, [R11,#0xB80] @ EP4 OUT: Set DATA0 PID |
177 | B pms_SET_FEATURE @ zero-length ACK | 177 | B pms_SET_FEATURE @ zero-length ACK |
178 | 178 | ||
179 | pms_GET_CONFIGURATION: | 179 | pms_GET_CONFIGURATION: |
180 | MOV R1, #1 | 180 | MOV R1, #1 |
181 | STR R1, [R14] | 181 | STR R1, [R14] |
182 | @ fallthrough | 182 | @ fallthrough |
183 | 183 | ||
184 | pms_ctrlsend: | 184 | pms_ctrlsend: |
185 | ORR R0, R1, #0x00080000 @ 1 Packet | 185 | ORR R0, R1, #0x00080000 @ 1 Packet |
186 | STR R0, [R11,#0x910] @ EP0 IN: 1 Packet, Size as in R1 | 186 | STR R0, [R11,#0x910] @ EP0 IN: 1 Packet, Size as in R1 |
187 | STR R14, [R11,#0x914] @ EP0 IN: DMA address | 187 | STR R14, [R11,#0x914] @ EP0 IN: DMA address |
188 | ORR R0, R6, #0x1800 | 188 | ORR R0, R6, #0x1800 |
189 | STR R0, [R11,#0x900] @ EP0 IN: Enable ClearNAK | 189 | STR R0, [R11,#0x900] @ EP0 IN: Enable ClearNAK |
190 | ADR R14, pms_ctrlbuf | 190 | ADR R14, pms_ctrlbuf |
191 | B pms_controldone | 191 | B pms_controldone |
192 | 192 | ||
193 | pms_GET_DESCRIPTOR: | 193 | pms_GET_DESCRIPTOR: |
194 | LDRB R0, [R14,#3] @ Descriptor type | 194 | LDRB R0, [R14,#3] @ Descriptor type |
195 | CMP R0, #1 | 195 | CMP R0, #1 |
196 | ADREQ R14, pms_devicedescriptor | 196 | ADREQ R14, pms_devicedescriptor |
197 | BEQ pms_senddescriptor | 197 | BEQ pms_senddescriptor |
198 | CMP R0, #2 | 198 | CMP R0, #2 |
199 | ADREQ R14, pms_configurationdescriptor | 199 | ADREQ R14, pms_configurationdescriptor |
200 | MOVEQ R1, #0x20 | 200 | MOVEQ R1, #0x20 |
201 | BEQ pms_senddescriptorcustomsize | 201 | BEQ pms_senddescriptorcustomsize |
202 | CMP R0, #3 | 202 | CMP R0, #3 |
203 | BNE pms_ctrlstall | 203 | BNE pms_ctrlstall |
204 | LDRB R0, [R14,#2] @ String descriptor index | 204 | LDRB R0, [R14,#2] @ String descriptor index |
205 | CMP R0, #0 | 205 | CMP R0, #0 |
206 | LDREQ R0, pms_langstringdescriptor | 206 | LDREQ R0, pms_langstringdescriptor |
207 | STREQ R0, [R14] | 207 | STREQ R0, [R14] |
208 | BEQ pms_senddescriptor | 208 | BEQ pms_senddescriptor |
209 | CMP R0, #1 | 209 | CMP R0, #1 |
210 | CMPNE R0, #2 | 210 | CMPNE R0, #2 |
211 | ADREQ R14, pms_devnamestringdescriptor | 211 | ADREQ R14, pms_devnamestringdescriptor |
212 | BNE pms_ctrlstall | 212 | BNE pms_ctrlstall |
213 | @ fallthrough | 213 | @ fallthrough |
214 | 214 | ||
215 | pms_senddescriptor: | 215 | pms_senddescriptor: |
216 | LDRB R1, [R14] @ Descriptor length | 216 | LDRB R1, [R14] @ Descriptor length |
217 | @ fallthrough | 217 | @ fallthrough |
218 | 218 | ||
219 | pms_senddescriptorcustomsize: | 219 | pms_senddescriptorcustomsize: |
220 | LDRH R0, pms_ctrlbuf+6 @ Requested length | 220 | LDRH R0, pms_ctrlbuf+6 @ Requested length |
221 | CMP R0, R1 | 221 | CMP R0, R1 |
222 | MOVLO R1, R0 | 222 | MOVLO R1, R0 |
223 | B pms_ctrlsend | 223 | B pms_ctrlsend |
224 | 224 | ||
225 | pms_SET_ADDRESS: | 225 | pms_SET_ADDRESS: |
226 | LDRH R1, [R14,#2] @ new address | 226 | LDRH R1, [R14,#2] @ new address |
227 | LDR R0, [R11,#0x800] | 227 | LDR R0, [R11,#0x800] |
228 | BIC R0, R0, #0x000007F0 | 228 | BIC R0, R0, #0x000007F0 |
229 | ORR R0, R0, R1,LSL#4 | 229 | ORR R0, R0, R1,LSL#4 |
230 | STR R0, [R11,#0x800] @ set new address | 230 | STR R0, [R11,#0x800] @ set new address |
231 | @ fallthrough | 231 | @ fallthrough |
232 | 232 | ||
233 | pms_SET_FEATURE: | 233 | pms_SET_FEATURE: |
234 | MOV R1, #0 @ zero-length ACK | 234 | MOV R1, #0 @ zero-length ACK |
235 | B pms_ctrlsend | 235 | B pms_ctrlsend |
236 | 236 | ||
237 | pms_20803180: | 237 | pms_20803180: |
238 | .word 0x20803180 | 238 | .word 0x20803180 |
239 | 239 | ||
240 | .ltorg | 240 | .ltorg |
241 | 241 | ||
242 | .align 4 | 242 | .align 4 |
243 | 243 | ||
244 | pms_configurationdescriptor: | 244 | pms_configurationdescriptor: |
245 | .word 0x00200209 | 245 | .word 0x00200209 |
246 | .word 0xC0000101 | 246 | .word 0xC0000101 |
247 | .word 0x00040932 | 247 | .word 0x00040932 |
248 | .word 0xFFFF0200 | 248 | .word 0xFFFF0200 |
249 | .word 0x050700FF | 249 | .word 0x050700FF |
250 | .word 0x02000204 | 250 | .word 0x02000204 |
251 | .word 0x83050701 | 251 | .word 0x83050701 |
252 | .word 0x01020002 | 252 | .word 0x01020002 |
253 | 253 | ||
254 | pms_devicedescriptor: | 254 | pms_devicedescriptor: |
255 | .word 0x02000112 | 255 | .word 0x02000112 |
256 | .word 0x40FFFFFF | 256 | .word 0x40FFFFFF |
257 | .word 0xA112FFFF | 257 | .word 0xA112FFFF |
258 | .word 0x02010001 | 258 | .word 0x02010001 |
259 | .word 0x00010100 | 259 | .word 0x00010100 |
260 | 260 | ||
261 | pms_00080200: | 261 | pms_00080200: |
262 | .word 0x00080200 | 262 | .word 0x00080200 |
263 | 263 | ||
264 | pms_20080040: | 264 | pms_20080040: |
265 | .word 0x20080040 | 265 | .word 0x20080040 |
266 | 266 | ||
267 | pms_000001FF: | 267 | pms_000001FF: |
268 | .word 0x000001FF | 268 | .word 0x000001FF |
269 | 269 | ||
270 | pms_devnamestringdescriptor: | 270 | pms_devnamestringdescriptor: |
271 | .word 0x0052030C | 271 | .word 0x0052030C |
272 | .word 0x00500042 | 272 | .word 0x00500042 |
273 | .word 0x0053004D | 273 | .word 0x0053004D |
274 | 274 | ||
275 | pms_langstringdescriptor: | 275 | pms_langstringdescriptor: |
276 | .word 0x04090304 | 276 | .word 0x04090304 |
277 | 277 | ||
278 | pms_ctrlbuf: | 278 | pms_ctrlbuf: |
279 | .word 0 | 279 | .word 0 |
280 | .word 0 | 280 | .word 0 |
281 | .word 0 | 281 | .word 0 |
282 | .word 0 | 282 | .word 0 |
283 | .word 0 | 283 | .word 0 |
284 | .word 0 | 284 | .word 0 |
285 | .word 0 | 285 | .word 0 |
286 | .word 0 | 286 | .word 0 |
287 | .word 0 | 287 | .word 0 |
288 | .word 0 | 288 | .word 0 |
289 | .word 0 | 289 | .word 0 |
290 | .word 0 | 290 | .word 0 |
291 | .word 0 | 291 | .word 0 |
292 | .word 0 | 292 | .word 0 |
293 | .word 0 | 293 | .word 0 |
294 | .word 0 | 294 | .word 0 |
295 | 295 | ||
296 | pms_recvbuf: | 296 | pms_recvbuf: |
297 | .word 0 | 297 | .word 0 |
298 | .word 0 | 298 | .word 0 |
299 | 299 | ||
300 | pms_GET_STATUS: | 300 | pms_GET_STATUS: |
301 | LDRB R0, [R14] | 301 | LDRB R0, [R14] |
302 | CMP R0, #0x80 | 302 | CMP R0, #0x80 |
303 | STREQ R12, [R14] | 303 | STREQ R12, [R14] |
304 | STRNE R13, [R14] | 304 | STRNE R13, [R14] |
305 | MOV R1, #2 | 305 | MOV R1, #2 |
306 | B pms_ctrlsend | 306 | B pms_ctrlsend |
307 | 307 | ||
308 | .size post_mortem_stub, .-post_mortem_stub | 308 | .size post_mortem_stub, .-post_mortem_stub |
diff --git a/firmware/target/arm/s5l8702/debug-s5l8702.c b/firmware/target/arm/s5l8702/debug-s5l8702.c index 5001d61f70..f49595aa00 100644 --- a/firmware/target/arm/s5l8702/debug-s5l8702.c +++ b/firmware/target/arm/s5l8702/debug-s5l8702.c | |||
@@ -1,166 +1,166 @@ | |||
1 | /*************************************************************************** | 1 | /*************************************************************************** |
2 | * __________ __ ___. | 2 | * __________ __ ___. |
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ |
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / |
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id: debug-s5l8700.c 28719 2010-12-01 18:35:01Z Buschel $ | 8 | * $Id: debug-s5l8700.c 28719 2010-12-01 18:35:01Z Buschel $ |
9 | * | 9 | * |
10 | * Copyright © 2008 Rafaël Carré | 10 | * Copyright © 2008 Rafaël Carré |
11 | * | 11 | * |
12 | * This program is free software; you can redistribute it and/or | 12 | * This program is free software; you can redistribute it and/or |
13 | * modify it under the terms of the GNU General Public License | 13 | * modify it under the terms of the GNU General Public License |
14 | * as published by the Free Software Foundation; either version 2 | 14 | * as published by the Free Software Foundation; either version 2 |
15 | * of the License, or (at your option) any later version. | 15 | * of the License, or (at your option) any later version. |
16 | * | 16 | * |
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | 17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY |
18 | * KIND, either express or implied. | 18 | * KIND, either express or implied. |
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | 21 | ||
22 | #include <stdbool.h> | 22 | #include <stdbool.h> |
23 | #include "config.h" | 23 | #include "config.h" |
24 | #include "kernel.h" | 24 | #include "kernel.h" |
25 | #include "debug-target.h" | 25 | #include "debug-target.h" |
26 | #include "button.h" | 26 | #include "button.h" |
27 | #include "lcd.h" | 27 | #include "lcd.h" |
28 | #include "font.h" | 28 | #include "font.h" |
29 | #include "storage.h" | 29 | #include "storage.h" |
30 | #include "power.h" | 30 | #include "power.h" |
31 | #include "pmu-target.h" | 31 | #include "pmu-target.h" |
32 | #include "pcm-target.h" | 32 | #include "pcm-target.h" |
33 | 33 | ||
34 | /* Skeleton for adding target specific debug info to the debug menu | 34 | /* Skeleton for adding target specific debug info to the debug menu |
35 | */ | 35 | */ |
36 | 36 | ||
37 | #define _DEBUG_PRINTF(a, varargs...) lcd_putsf(0, line++, (a), ##varargs); | 37 | #define _DEBUG_PRINTF(a, varargs...) lcd_putsf(0, line++, (a), ##varargs); |
38 | 38 | ||
39 | extern int lcd_type; | 39 | extern int lcd_type; |
40 | bool dbg_hw_info(void) | 40 | bool dbg_hw_info(void) |
41 | { | 41 | { |
42 | int line; | 42 | int line; |
43 | int i; | 43 | int i; |
44 | unsigned int state = 0; | 44 | unsigned int state = 0; |
45 | const unsigned int max_states=3; | 45 | const unsigned int max_states=3; |
46 | 46 | ||
47 | lcd_clear_display(); | 47 | lcd_clear_display(); |
48 | lcd_setfont(FONT_SYSFIXED); | 48 | lcd_setfont(FONT_SYSFIXED); |
49 | 49 | ||
50 | state=0; | 50 | state=0; |
51 | while(1) | 51 | while(1) |
52 | { | 52 | { |
53 | lcd_clear_display(); | 53 | lcd_clear_display(); |
54 | line = 0; | 54 | line = 0; |
55 | 55 | ||
56 | if(state == 0) | 56 | if(state == 0) |
57 | { | 57 | { |
58 | _DEBUG_PRINTF("CPU:"); | 58 | _DEBUG_PRINTF("CPU:"); |
59 | _DEBUG_PRINTF("current_tick: %d", (unsigned int)current_tick); | 59 | _DEBUG_PRINTF("current_tick: %d", (unsigned int)current_tick); |
60 | line++; | 60 | line++; |
61 | 61 | ||
62 | _DEBUG_PRINTF("LCD type: %d", lcd_type); | 62 | _DEBUG_PRINTF("LCD type: %d", lcd_type); |
63 | line++; | 63 | line++; |
64 | } | 64 | } |
65 | else if(state==1) | 65 | else if(state==1) |
66 | { | 66 | { |
67 | _DEBUG_PRINTF("PMU:"); | 67 | _DEBUG_PRINTF("PMU:"); |
68 | for(i=0;i<7;i++) | 68 | for(i=0;i<7;i++) |
69 | { | 69 | { |
70 | char *device[] = {"(unknown)", | 70 | char *device[] = {"(unknown)", |
71 | "(unknown)", | 71 | "(unknown)", |
72 | "(unknown)", | 72 | "(unknown)", |
73 | "(unknown)", | 73 | "(unknown)", |
74 | "(unknown)", | 74 | "(unknown)", |
75 | "(unknown)", | 75 | "(unknown)", |
76 | "(unknown)"}; | 76 | "(unknown)"}; |
77 | _DEBUG_PRINTF("ldo%d %s: %dmV %s",i, | 77 | _DEBUG_PRINTF("ldo%d %s: %dmV %s",i, |
78 | pmu_read(0x2e + (i << 1))?" on":"off", | 78 | pmu_read(0x2e + (i << 1))?" on":"off", |
79 | 900 + pmu_read(0x2d + (i << 1))*100, | 79 | 900 + pmu_read(0x2d + (i << 1))*100, |
80 | device[i]); | 80 | device[i]); |
81 | } | 81 | } |
82 | _DEBUG_PRINTF("cpu voltage: %dmV",625 + pmu_read(0x1e)*25); | 82 | _DEBUG_PRINTF("cpu voltage: %dmV",625 + pmu_read(0x1e)*25); |
83 | _DEBUG_PRINTF("memory voltage: %dmV",625 + pmu_read(0x22)*25); | 83 | _DEBUG_PRINTF("memory voltage: %dmV",625 + pmu_read(0x22)*25); |
84 | line++; | 84 | line++; |
85 | _DEBUG_PRINTF("charging: %s", charging_state() ? "true" : "false"); | 85 | _DEBUG_PRINTF("charging: %s", charging_state() ? "true" : "false"); |
86 | _DEBUG_PRINTF("backlight: %s", pmu_read(0x29) ? "on" : "off"); | 86 | _DEBUG_PRINTF("backlight: %s", pmu_read(0x29) ? "on" : "off"); |
87 | _DEBUG_PRINTF("brightness value: %d", pmu_read(0x28)); | 87 | _DEBUG_PRINTF("brightness value: %d", pmu_read(0x28)); |
88 | } | 88 | } |
89 | else if(state==2) | 89 | else if(state==2) |
90 | { | 90 | { |
91 | _DEBUG_PRINTF("Audio DMA:"); | 91 | _DEBUG_PRINTF("Audio DMA:"); |
92 | _DEBUG_PRINTF(">%08X %08X %08X %08X %08X", DMAC0C0CONFIG, DMAC0C0SRCADDR, | 92 | _DEBUG_PRINTF(">%08X %08X %08X %08X %08X", DMAC0C0CONFIG, DMAC0C0SRCADDR, |
93 | DMAC0C0DESTADDR, DMAC0C0NEXTLLI, DMAC0C0CONTROL); | 93 | DMAC0C0DESTADDR, DMAC0C0NEXTLLI, DMAC0C0CONTROL); |
94 | for(i = 0; i < PCM_LLICOUNT; i++) | 94 | for(i = 0; i < PCM_LLICOUNT; i++) |
95 | _DEBUG_PRINTF("%08X: %08X %08X %08X %08X", &pcm_lli[i], pcm_lli[i].srcaddr, | 95 | _DEBUG_PRINTF("%08X: %08X %08X %08X %08X", &pcm_lli[i], pcm_lli[i].srcaddr, |
96 | pcm_lli[i].dstaddr, pcm_lli[i].nextlli, pcm_lli[i].control); | 96 | pcm_lli[i].dstaddr, pcm_lli[i].nextlli, pcm_lli[i].control); |
97 | _DEBUG_PRINTF("chunk: %08X %08X", pcm_chunksize, pcm_remaining); | 97 | _DEBUG_PRINTF("chunk: %08X %08X", pcm_chunksize, pcm_remaining); |
98 | } | 98 | } |
99 | else | 99 | else |
100 | { | 100 | { |
101 | state=0; | 101 | state=0; |
102 | } | 102 | } |
103 | 103 | ||
104 | 104 | ||
105 | lcd_update(); | 105 | lcd_update(); |
106 | switch(button_get_w_tmo(HZ/20)) | 106 | switch(button_get_w_tmo(HZ/20)) |
107 | { | 107 | { |
108 | case BUTTON_SCROLL_BACK: | 108 | case BUTTON_SCROLL_BACK: |
109 | if(state!=0) state--; | 109 | if(state!=0) state--; |
110 | break; | 110 | break; |
111 | 111 | ||
112 | case BUTTON_SCROLL_FWD: | 112 | case BUTTON_SCROLL_FWD: |
113 | if(state!=max_states-1) | 113 | if(state!=max_states-1) |
114 | { | 114 | { |
115 | state++; | 115 | state++; |
116 | } | 116 | } |
117 | break; | 117 | break; |
118 | 118 | ||
119 | case DEBUG_CANCEL: | 119 | case DEBUG_CANCEL: |
120 | case BUTTON_REL: | 120 | case BUTTON_REL: |
121 | lcd_setfont(FONT_UI); | 121 | lcd_setfont(FONT_UI); |
122 | return false; | 122 | return false; |
123 | } | 123 | } |
124 | } | 124 | } |
125 | 125 | ||
126 | lcd_setfont(FONT_UI); | 126 | lcd_setfont(FONT_UI); |
127 | return false; | 127 | return false; |
128 | } | 128 | } |
129 | 129 | ||
130 | bool dbg_ports(void) | 130 | bool dbg_ports(void) |
131 | { | 131 | { |
132 | int line; | 132 | int line; |
133 | 133 | ||
134 | lcd_setfont(FONT_SYSFIXED); | 134 | lcd_setfont(FONT_SYSFIXED); |
135 | 135 | ||
136 | while(1) | 136 | while(1) |
137 | { | 137 | { |
138 | lcd_clear_display(); | 138 | lcd_clear_display(); |
139 | line = 0; | 139 | line = 0; |
140 | 140 | ||
141 | _DEBUG_PRINTF("GPIO 0: %08x",(unsigned int)PDAT(0)); | 141 | _DEBUG_PRINTF("GPIO 0: %08x",(unsigned int)PDAT(0)); |
142 | _DEBUG_PRINTF("GPIO 1: %08x",(unsigned int)PDAT(1)); | 142 | _DEBUG_PRINTF("GPIO 1: %08x",(unsigned int)PDAT(1)); |
143 | _DEBUG_PRINTF("GPIO 2: %08x",(unsigned int)PDAT(2)); | 143 | _DEBUG_PRINTF("GPIO 2: %08x",(unsigned int)PDAT(2)); |
144 | _DEBUG_PRINTF("GPIO 3: %08x",(unsigned int)PDAT(3)); | 144 | _DEBUG_PRINTF("GPIO 3: %08x",(unsigned int)PDAT(3)); |
145 | _DEBUG_PRINTF("GPIO 4: %08x",(unsigned int)PDAT(4)); | 145 | _DEBUG_PRINTF("GPIO 4: %08x",(unsigned int)PDAT(4)); |
146 | _DEBUG_PRINTF("GPIO 5: %08x",(unsigned int)PDAT(5)); | 146 | _DEBUG_PRINTF("GPIO 5: %08x",(unsigned int)PDAT(5)); |
147 | _DEBUG_PRINTF("GPIO 6: %08x",(unsigned int)PDAT(6)); | 147 | _DEBUG_PRINTF("GPIO 6: %08x",(unsigned int)PDAT(6)); |
148 | _DEBUG_PRINTF("GPIO 7: %08x",(unsigned int)PDAT(7)); | 148 | _DEBUG_PRINTF("GPIO 7: %08x",(unsigned int)PDAT(7)); |
149 | _DEBUG_PRINTF("GPIO 8: %08x",(unsigned int)PDAT(8)); | 149 | _DEBUG_PRINTF("GPIO 8: %08x",(unsigned int)PDAT(8)); |
150 | _DEBUG_PRINTF("GPIO 9: %08x",(unsigned int)PDAT(9)); | 150 | _DEBUG_PRINTF("GPIO 9: %08x",(unsigned int)PDAT(9)); |
151 | _DEBUG_PRINTF("GPIO 10: %08x",(unsigned int)PDAT(10)); | 151 | _DEBUG_PRINTF("GPIO 10: %08x",(unsigned int)PDAT(10)); |
152 | _DEBUG_PRINTF("GPIO 11: %08x",(unsigned int)PDAT(11)); | 152 | _DEBUG_PRINTF("GPIO 11: %08x",(unsigned int)PDAT(11)); |
153 | _DEBUG_PRINTF("GPIO 12: %08x",(unsigned int)PDAT(12)); | 153 | _DEBUG_PRINTF("GPIO 12: %08x",(unsigned int)PDAT(12)); |
154 | _DEBUG_PRINTF("GPIO 13: %08x",(unsigned int)PDAT(13)); | 154 | _DEBUG_PRINTF("GPIO 13: %08x",(unsigned int)PDAT(13)); |
155 | _DEBUG_PRINTF("GPIO 14: %08x",(unsigned int)PDAT(14)); | 155 | _DEBUG_PRINTF("GPIO 14: %08x",(unsigned int)PDAT(14)); |
156 | _DEBUG_PRINTF("GPIO 15: %08x",(unsigned int)PDAT(15)); | 156 | _DEBUG_PRINTF("GPIO 15: %08x",(unsigned int)PDAT(15)); |
157 | _DEBUG_PRINTF("USEC : %08x",(unsigned int)USEC_TIMER); | 157 | _DEBUG_PRINTF("USEC : %08x",(unsigned int)USEC_TIMER); |
158 | 158 | ||
159 | lcd_update(); | 159 | lcd_update(); |
160 | if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL)) | 160 | if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL)) |
161 | break; | 161 | break; |
162 | } | 162 | } |
163 | lcd_setfont(FONT_UI); | 163 | lcd_setfont(FONT_UI); |
164 | return false; | 164 | return false; |
165 | } | 165 | } |
166 | 166 | ||
diff --git a/firmware/target/arm/s5l8702/debug-target.h b/firmware/target/arm/s5l8702/debug-target.h index 55ea497f00..a493c0e3dd 100644 --- a/firmware/target/arm/s5l8702/debug-target.h +++ b/firmware/target/arm/s5l8702/debug-target.h | |||
@@ -1,33 +1,33 @@ | |||
1 | /*************************************************************************** | 1 | /*************************************************************************** |
2 | * __________ __ ___. | 2 | * __________ __ ___. |
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ |
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / |
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id: debug-target.h 28522 2010-11-06 14:24:25Z wodz $ | 8 | * $Id: debug-target.h 28522 2010-11-06 14:24:25Z wodz $ |
9 | * | 9 | * |
10 | * Copyright (C) 2007 by Karl Kurbjun | 10 | * Copyright (C) 2007 by Karl Kurbjun |
11 | * | 11 | * |
12 | * This program is free software; you can redistribute it and/or | 12 | * This program is free software; you can redistribute it and/or |
13 | * modify it under the terms of the GNU General Public License | 13 | * modify it under the terms of the GNU General Public License |
14 | * as published by the Free Software Foundation; either version 2 | 14 | * as published by the Free Software Foundation; either version 2 |
15 | * of the License, or (at your option) any later version. | 15 | * of the License, or (at your option) any later version. |
16 | * | 16 | * |
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | 17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY |
18 | * KIND, either express or implied. | 18 | * KIND, either express or implied. |
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | 21 | ||
22 | #ifndef _DEBUG_TARGET_H_ | 22 | #ifndef _DEBUG_TARGET_H_ |
23 | #define _DEBUG_TARGET_H_ | 23 | #define _DEBUG_TARGET_H_ |
24 | 24 | ||
25 | #include <stdbool.h> | 25 | #include <stdbool.h> |
26 | 26 | ||
27 | #define DEBUG_CANCEL BUTTON_MENU | 27 | #define DEBUG_CANCEL BUTTON_MENU |
28 | 28 | ||
29 | bool dbg_hw_info(void); | 29 | bool dbg_hw_info(void); |
30 | bool dbg_ports(void); | 30 | bool dbg_ports(void); |
31 | 31 | ||
32 | #endif /* _DEBUG_TARGET_H_ */ | 32 | #endif /* _DEBUG_TARGET_H_ */ |
33 | 33 | ||
diff --git a/firmware/target/arm/s5l8702/i2c-s5l8702.c b/firmware/target/arm/s5l8702/i2c-s5l8702.c index 294e5b58ce..4d0e4188ab 100644 --- a/firmware/target/arm/s5l8702/i2c-s5l8702.c +++ b/firmware/target/arm/s5l8702/i2c-s5l8702.c | |||
@@ -1,196 +1,196 @@ | |||
1 | /*************************************************************************** | 1 | /*************************************************************************** |
2 | * __________ __ ___. | 2 | * __________ __ ___. |
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ |
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / |
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id: i2c-s5l8700.c 28589 2010-11-14 15:19:30Z theseven $ | 8 | * $Id: i2c-s5l8700.c 28589 2010-11-14 15:19:30Z theseven $ |
9 | * | 9 | * |
10 | * Copyright (C) 2009 by Bertrik Sikken | 10 | * Copyright (C) 2009 by Bertrik Sikken |
11 | * | 11 | * |
12 | * This program is free software; you can redistribute it and/or | 12 | * This program is free software; you can redistribute it and/or |
13 | * modify it under the terms of the GNU General Public License | 13 | * modify it under the terms of the GNU General Public License |
14 | * as published by the Free Software Foundation; either version 2 | 14 | * as published by the Free Software Foundation; either version 2 |
15 | * of the License, or (at your option) any later version. | 15 | * of the License, or (at your option) any later version. |
16 | * | 16 | * |
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | 17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY |
18 | * KIND, either express or implied. | 18 | * KIND, either express or implied. |
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | 21 | ||
22 | #include "config.h" | 22 | #include "config.h" |
23 | #include "system.h" | 23 | #include "system.h" |
24 | #include "kernel.h" | 24 | #include "kernel.h" |
25 | #include "i2c-s5l8702.h" | 25 | #include "i2c-s5l8702.h" |
26 | 26 | ||
27 | /* Driver for the s5l8700 built-in I2C controller in master mode | 27 | /* Driver for the s5l8700 built-in I2C controller in master mode |
28 | 28 | ||
29 | Both the i2c_read and i2c_write function take the following arguments: | 29 | Both the i2c_read and i2c_write function take the following arguments: |
30 | * slave, the address of the i2c slave device to read from / write to | 30 | * slave, the address of the i2c slave device to read from / write to |
31 | * address, optional sub-address in the i2c slave (unused if -1) | 31 | * address, optional sub-address in the i2c slave (unused if -1) |
32 | * len, number of bytes to be transfered | 32 | * len, number of bytes to be transfered |
33 | * data, pointer to data to be transfered | 33 | * data, pointer to data to be transfered |
34 | A return value < 0 indicates an error. | 34 | A return value < 0 indicates an error. |
35 | 35 | ||
36 | Note: | 36 | Note: |
37 | * blocks the calling thread for the entire duraton of the i2c transfer but | 37 | * blocks the calling thread for the entire duraton of the i2c transfer but |
38 | uses wakeup_wait/wakeup_signal to allow other threads to run. | 38 | uses wakeup_wait/wakeup_signal to allow other threads to run. |
39 | * ACK from slave is not checked, so functions never return an error | 39 | * ACK from slave is not checked, so functions never return an error |
40 | */ | 40 | */ |
41 | 41 | ||
42 | static struct mutex i2c_mtx[2]; | 42 | static struct mutex i2c_mtx[2]; |
43 | 43 | ||
44 | static void i2c_on(int bus) | 44 | static void i2c_on(int bus) |
45 | { | 45 | { |
46 | /* enable I2C clock */ | 46 | /* enable I2C clock */ |
47 | PWRCON(1) &= ~(1 << 4); | 47 | PWRCON(1) &= ~(1 << 4); |
48 | 48 | ||
49 | IICCON(bus) = (1 << 7) | /* ACK_GEN */ | 49 | IICCON(bus) = (1 << 7) | /* ACK_GEN */ |
50 | (0 << 6) | /* CLKSEL = PCLK/16 */ | 50 | (0 << 6) | /* CLKSEL = PCLK/16 */ |
51 | (1 << 5) | /* INT_EN */ | 51 | (1 << 5) | /* INT_EN */ |
52 | (1 << 4) | /* IRQ clear */ | 52 | (1 << 4) | /* IRQ clear */ |
53 | (7 << 0); /* CK_REG */ | 53 | (7 << 0); /* CK_REG */ |
54 | 54 | ||
55 | /* serial output on */ | 55 | /* serial output on */ |
56 | IICSTAT(bus) = (1 << 4); | 56 | IICSTAT(bus) = (1 << 4); |
57 | } | 57 | } |
58 | 58 | ||
59 | static void i2c_off(int bus) | 59 | static void i2c_off(int bus) |
60 | { | 60 | { |
61 | /* serial output off */ | 61 | /* serial output off */ |
62 | IICSTAT(bus) = 0; | 62 | IICSTAT(bus) = 0; |
63 | 63 | ||
64 | /* disable I2C clock */ | 64 | /* disable I2C clock */ |
65 | PWRCON(1) |= (1 << 4); | 65 | PWRCON(1) |= (1 << 4); |
66 | } | 66 | } |
67 | 67 | ||
68 | void i2c_init() | 68 | void i2c_init() |
69 | { | 69 | { |
70 | mutex_init(&i2c_mtx[0]); | 70 | mutex_init(&i2c_mtx[0]); |
71 | mutex_init(&i2c_mtx[1]); | 71 | mutex_init(&i2c_mtx[1]); |
72 | } | 72 | } |
73 | 73 | ||
74 | int i2c_write(int bus, unsigned char slave, int address, int len, const unsigned char *data) | 74 | int i2c_write(int bus, unsigned char slave, int address, int len, const unsigned char *data) |
75 | { | 75 | { |
76 | mutex_lock(&i2c_mtx[bus]); | 76 | mutex_lock(&i2c_mtx[bus]); |
77 | i2c_on(bus); | 77 | i2c_on(bus); |
78 | long timeout = current_tick + HZ / 50; | 78 | long timeout = current_tick + HZ / 50; |
79 | 79 | ||
80 | /* START */ | 80 | /* START */ |
81 | IICDS(bus) = slave & ~1; | 81 | IICDS(bus) = slave & ~1; |
82 | IICSTAT(bus) = 0xF0; | 82 | IICSTAT(bus) = 0xF0; |
83 | IICCON(bus) = 0xB3; | 83 | IICCON(bus) = 0xB3; |
84 | while ((IICCON(bus) & 0x10) == 0) | 84 | while ((IICCON(bus) & 0x10) == 0) |
85 | if (TIME_AFTER(current_tick, timeout)) | 85 | if (TIME_AFTER(current_tick, timeout)) |
86 | { | 86 | { |
87 | mutex_unlock(&i2c_mtx[bus]); | 87 | mutex_unlock(&i2c_mtx[bus]); |
88 | return 1; | 88 | return 1; |
89 | } | 89 | } |
90 | 90 | ||
91 | 91 | ||
92 | if (address >= 0) { | 92 | if (address >= 0) { |
93 | /* write address */ | 93 | /* write address */ |
94 | IICDS(bus) = address; | 94 | IICDS(bus) = address; |
95 | IICCON(bus) = 0xB3; | 95 | IICCON(bus) = 0xB3; |
96 | while ((IICCON(bus) & 0x10) == 0) | 96 | while ((IICCON(bus) & 0x10) == 0) |
97 | if (TIME_AFTER(current_tick, timeout)) | 97 | if (TIME_AFTER(current_tick, timeout)) |
98 | { | 98 | { |
99 | mutex_unlock(&i2c_mtx[bus]); | 99 | mutex_unlock(&i2c_mtx[bus]); |
100 | return 2; | 100 | return 2; |
101 | } | 101 | } |
102 | } | 102 | } |
103 | 103 | ||
104 | /* write data */ | 104 | /* write data */ |
105 | while (len--) { | 105 | while (len--) { |
106 | IICDS(bus) = *data++; | 106 | IICDS(bus) = *data++; |
107 | IICCON(bus) = 0xB3; | 107 | IICCON(bus) = 0xB3; |
108 | while ((IICCON(bus) & 0x10) == 0) | 108 | while ((IICCON(bus) & 0x10) == 0) |
109 | if (TIME_AFTER(current_tick, timeout)) | 109 | if (TIME_AFTER(current_tick, timeout)) |
110 | { | 110 | { |
111 | mutex_unlock(&i2c_mtx[bus]); | 111 | mutex_unlock(&i2c_mtx[bus]); |
112 | return 4; | 112 | return 4; |
113 | } | 113 | } |
114 | } | 114 | } |
115 | 115 | ||
116 | /* STOP */ | 116 | /* STOP */ |
117 | IICSTAT(bus) = 0xD0; | 117 | IICSTAT(bus) = 0xD0; |
118 | IICCON(bus) = 0xB3; | 118 | IICCON(bus) = 0xB3; |
119 | while ((IICSTAT(bus) & (1 << 5)) != 0) | 119 | while ((IICSTAT(bus) & (1 << 5)) != 0) |
120 | if (TIME_AFTER(current_tick, timeout)) | 120 | if (TIME_AFTER(current_tick, timeout)) |
121 | { | 121 | { |
122 | mutex_unlock(&i2c_mtx[bus]); | 122 | mutex_unlock(&i2c_mtx[bus]); |
123 | return 5; | 123 | return 5; |
124 | } | 124 | } |
125 | 125 | ||
126 | i2c_off(bus); | 126 | i2c_off(bus); |
127 | mutex_unlock(&i2c_mtx[bus]); | 127 | mutex_unlock(&i2c_mtx[bus]); |
128 | return 0; | 128 | return 0; |
129 | } | 129 | } |
130 | 130 | ||
131 | int i2c_read(int bus, unsigned char slave, int address, int len, unsigned char *data) | 131 | int i2c_read(int bus, unsigned char slave, int address, int len, unsigned char *data) |
132 | { | 132 | { |
133 | mutex_lock(&i2c_mtx[bus]); | 133 | mutex_lock(&i2c_mtx[bus]); |
134 | i2c_on(bus); | 134 | i2c_on(bus); |
135 | long timeout = current_tick + HZ / 50; | 135 | long timeout = current_tick + HZ / 50; |
136 | 136 | ||
137 | if (address >= 0) { | 137 | if (address >= 0) { |
138 | /* START */ | 138 | /* START */ |
139 | IICDS(bus) = slave & ~1; | 139 | IICDS(bus) = slave & ~1; |
140 | IICSTAT(bus) = 0xF0; | 140 | IICSTAT(bus) = 0xF0; |
141 | IICCON(bus) = 0xB3; | 141 | IICCON(bus) = 0xB3; |
142 | while ((IICCON(bus) & 0x10) == 0) | 142 | while ((IICCON(bus) & 0x10) == 0) |
143 | if (TIME_AFTER(current_tick, timeout)) | 143 | if (TIME_AFTER(current_tick, timeout)) |
144 | { | 144 | { |
145 | mutex_unlock(&i2c_mtx[bus]); | 145 | mutex_unlock(&i2c_mtx[bus]); |
146 | return 1; | 146 | return 1; |
147 | } | 147 | } |
148 | 148 | ||
149 | /* write address */ | 149 | /* write address */ |
150 | IICDS(bus) = address; | 150 | IICDS(bus) = address; |
151 | IICCON(bus) = 0xB3; | 151 | IICCON(bus) = 0xB3; |
152 | while ((IICCON(bus) & 0x10) == 0) | 152 | while ((IICCON(bus) & 0x10) == 0) |
153 | if (TIME_AFTER(current_tick, timeout)) | 153 | if (TIME_AFTER(current_tick, timeout)) |
154 | { | 154 | { |
155 | mutex_unlock(&i2c_mtx[bus]); | 155 | mutex_unlock(&i2c_mtx[bus]); |
156 | return 2; | 156 | return 2; |
157 | } | 157 | } |
158 | } | 158 | } |
159 | 159 | ||
160 | /* (repeated) START */ | 160 | /* (repeated) START */ |
161 | IICDS(bus) = slave | 1; | 161 | IICDS(bus) = slave | 1; |
162 | IICSTAT(bus) = 0xB0; | 162 | IICSTAT(bus) = 0xB0; |
163 | IICCON(bus) = 0xB3; | 163 | IICCON(bus) = 0xB3; |
164 | while ((IICCON(bus) & 0x10) == 0) | 164 | while ((IICCON(bus) & 0x10) == 0) |
165 | if (TIME_AFTER(current_tick, timeout)) | 165 | if (TIME_AFTER(current_tick, timeout)) |
166 | { | 166 | { |
167 | mutex_unlock(&i2c_mtx[bus]); | 167 | mutex_unlock(&i2c_mtx[bus]); |
168 | return 3; | 168 | return 3; |
169 | } | 169 | } |
170 | 170 | ||
171 | while (len--) { | 171 | while (len--) { |
172 | IICCON(bus) = (len == 0) ? 0x33 : 0xB3; /* NAK or ACK */ | 172 | IICCON(bus) = (len == 0) ? 0x33 : 0xB3; /* NAK or ACK */ |
173 | while ((IICCON(bus) & 0x10) == 0) | 173 | while ((IICCON(bus) & 0x10) == 0) |
174 | if (TIME_AFTER(current_tick, timeout)) | 174 | if (TIME_AFTER(current_tick, timeout)) |
175 | { | 175 | { |
176 | mutex_unlock(&i2c_mtx[bus]); | 176 | mutex_unlock(&i2c_mtx[bus]); |
177 | return 4; | 177 | return 4; |
178 | } | 178 | } |
179 | *data++ = IICDS(bus); | 179 | *data++ = IICDS(bus); |
180 | } | 180 | } |
181 | 181 | ||
182 | /* STOP */ | 182 | /* STOP */ |
183 | IICSTAT(bus) = 0x90; | 183 | IICSTAT(bus) = 0x90; |
184 | IICCON(bus) = 0xB3; | 184 | IICCON(bus) = 0xB3; |
185 | while ((IICSTAT(bus) & (1 << 5)) != 0) | 185 | while ((IICSTAT(bus) & (1 << 5)) != 0) |
186 | if (TIME_AFTER(current_tick, timeout)) | 186 | if (TIME_AFTER(current_tick, timeout)) |
187 | { | 187 | { |
188 | mutex_unlock(&i2c_mtx[bus]); | 188 | mutex_unlock(&i2c_mtx[bus]); |
189 | return 5; | 189 | return 5; |
190 | } | 190 | } |
191 | 191 | ||
192 | i2c_off(bus); | 192 | i2c_off(bus); |
193 | mutex_unlock(&i2c_mtx[bus]); | 193 | mutex_unlock(&i2c_mtx[bus]); |
194 | return 0; | 194 | return 0; |
195 | } | 195 | } |
196 | 196 | ||
diff --git a/firmware/target/arm/s5l8702/kernel-s5l8702.c b/firmware/target/arm/s5l8702/kernel-s5l8702.c index 7c5a697043..af54e4dca4 100644 --- a/firmware/target/arm/s5l8702/kernel-s5l8702.c +++ b/firmware/target/arm/s5l8702/kernel-s5l8702.c | |||
@@ -1,56 +1,56 @@ | |||
1 | /*************************************************************************** | 1 | /*************************************************************************** |
2 | * __________ __ ___. | 2 | * __________ __ ___. |
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ |
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / |
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id: kernel-s5l8700.c 28795 2010-12-11 17:52:52Z Buschel $ | 8 | * $Id: kernel-s5l8700.c 28795 2010-12-11 17:52:52Z Buschel $ |
9 | * | 9 | * |
10 | * Copyright © 2009 Bertrik Sikken | 10 | * Copyright © 2009 Bertrik Sikken |
11 | * | 11 | * |
12 | * This program is free software; you can redistribute it and/or | 12 | * This program is free software; you can redistribute it and/or |
13 | * modify it under the terms of the GNU General Public License | 13 | * modify it under the terms of the GNU General Public License |
14 | * as published by the Free Software Foundation; either version 2 | 14 | * as published by the Free Software Foundation; either version 2 |
15 | * of the License, or (at your option) any later version. | 15 | * of the License, or (at your option) any later version. |
16 | * | 16 | * |
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | 17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY |
18 | * KIND, either express or implied. | 18 | * KIND, either express or implied. |
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | #include "config.h" | 21 | #include "config.h" |
22 | #include "system.h" | 22 | #include "system.h" |
23 | #include "kernel.h" | 23 | #include "kernel.h" |
24 | 24 | ||
25 | /* S5L8702 driver for the kernel timer | 25 | /* S5L8702 driver for the kernel timer |
26 | 26 | ||
27 | Timer B is configured as a 10 kHz timer | 27 | Timer B is configured as a 10 kHz timer |
28 | */ | 28 | */ |
29 | 29 | ||
30 | void INT_TIMERB(void) | 30 | void INT_TIMERB(void) |
31 | { | 31 | { |
32 | /* clear interrupt */ | 32 | /* clear interrupt */ |
33 | TBCON = TBCON; | 33 | TBCON = TBCON; |
34 | 34 | ||
35 | call_tick_tasks(); /* Run through the list of tick tasks */ | 35 | call_tick_tasks(); /* Run through the list of tick tasks */ |
36 | } | 36 | } |
37 | 37 | ||
38 | void tick_start(unsigned int interval_in_ms) | 38 | void tick_start(unsigned int interval_in_ms) |
39 | { | 39 | { |
40 | int cycles = 10 * interval_in_ms; | 40 | int cycles = 10 * interval_in_ms; |
41 | 41 | ||
42 | /* configure timer for 10 kHz */ | 42 | /* configure timer for 10 kHz */ |
43 | TBCMD = (1 << 1); /* TB_CLR */ | 43 | TBCMD = (1 << 1); /* TB_CLR */ |
44 | TBPRE = 337 - 1; /* prescaler */ | 44 | TBPRE = 337 - 1; /* prescaler */ |
45 | TBCON = (0 << 13) | /* TB_INT1_EN */ | 45 | TBCON = (0 << 13) | /* TB_INT1_EN */ |
46 | (1 << 12) | /* TB_INT0_EN */ | 46 | (1 << 12) | /* TB_INT0_EN */ |
47 | (0 << 11) | /* TB_START */ | 47 | (0 << 11) | /* TB_START */ |
48 | (2 << 8) | /* TB_CS = PCLK / 16 */ | 48 | (2 << 8) | /* TB_CS = PCLK / 16 */ |
49 | (0 << 4); /* TB_MODE_SEL = interval mode */ | 49 | (0 << 4); /* TB_MODE_SEL = interval mode */ |
50 | TBDATA0 = cycles; /* set interval period */ | 50 | TBDATA0 = cycles; /* set interval period */ |
51 | TBCMD = (1 << 0); /* TB_EN */ | 51 | TBCMD = (1 << 0); /* TB_EN */ |
52 | 52 | ||
53 | /* enable timer interrupt */ | 53 | /* enable timer interrupt */ |
54 | VIC0INTENABLE = 1 << IRQ_TIMER; | 54 | VIC0INTENABLE = 1 << IRQ_TIMER; |
55 | } | 55 | } |
56 | 56 | ||
diff --git a/firmware/target/arm/s5l8702/pcm-s5l8702.c b/firmware/target/arm/s5l8702/pcm-s5l8702.c index c3df77f14f..6461418744 100644 --- a/firmware/target/arm/s5l8702/pcm-s5l8702.c +++ b/firmware/target/arm/s5l8702/pcm-s5l8702.c | |||
@@ -1,228 +1,228 @@ | |||
1 | /*************************************************************************** | 1 | /*************************************************************************** |
2 | * __________ __ ___. | 2 | * __________ __ ___. |
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ |
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / |
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id: pcm-s5l8700.c 28600 2010-11-14 19:49:20Z Buschel $ | 8 | * $Id: pcm-s5l8700.c 28600 2010-11-14 19:49:20Z Buschel $ |
9 | * | 9 | * |
10 | * Copyright © 2011 Michael Sparmann | 10 | * Copyright © 2011 Michael Sparmann |
11 | * | 11 | * |
12 | * This program is free software; you can redistribute it and/or | 12 | * This program is free software; you can redistribute it and/or |
13 | * modify it under the terms of the GNU General Public License | 13 | * modify it under the terms of the GNU General Public License |
14 | * as published by the Free Software Foundation; either version 2 | 14 | * as published by the Free Software Foundation; either version 2 |
15 | * of the License, or (at your option) any later version. | 15 | * of the License, or (at your option) any later version. |
16 | * | 16 | * |
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | 17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY |
18 | * KIND, either express or implied. | 18 | * KIND, either express or implied. |
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | #include <string.h> | 21 | #include <string.h> |
22 | 22 | ||
23 | #include "config.h" | 23 | #include "config.h" |
24 | #include "system.h" | 24 | #include "system.h" |
25 | #include "audio.h" | 25 | #include "audio.h" |
26 | #include "s5l8702.h" | 26 | #include "s5l8702.h" |
27 | #include "panic.h" | 27 | #include "panic.h" |
28 | #include "audiohw.h" | 28 | #include "audiohw.h" |
29 | #include "pcm.h" | 29 | #include "pcm.h" |
30 | #include "pcm-internal.h" | 30 | #include "pcm-internal.h" |
31 | #include "pcm_sampr.h" | 31 | #include "pcm_sampr.h" |
32 | #include "mmu-arm.h" | 32 | #include "mmu-arm.h" |
33 | #include "pcm-target.h" | 33 | #include "pcm-target.h" |
34 | 34 | ||
35 | static volatile int locked = 0; | 35 | static volatile int locked = 0; |
36 | static const int zerosample = 0; | 36 | static const int zerosample = 0; |
37 | static unsigned char dblbuf[2][PCM_WATERMARK * 4]; | 37 | static unsigned char dblbuf[2][PCM_WATERMARK * 4]; |
38 | static int active_dblbuf; | 38 | static int active_dblbuf; |
39 | struct dma_lli pcm_lli[PCM_LLICOUNT] __attribute__((aligned(16))); | 39 | struct dma_lli pcm_lli[PCM_LLICOUNT] __attribute__((aligned(16))); |
40 | static struct dma_lli* lastlli; | 40 | static struct dma_lli* lastlli; |
41 | static const unsigned char* dataptr; | 41 | static const unsigned char* dataptr; |
42 | size_t pcm_remaining; | 42 | size_t pcm_remaining; |
43 | size_t pcm_chunksize; | 43 | size_t pcm_chunksize; |
44 | 44 | ||
45 | /* Mask the DMA interrupt */ | 45 | /* Mask the DMA interrupt */ |
46 | void pcm_play_lock(void) | 46 | void pcm_play_lock(void) |
47 | { | 47 | { |
48 | if (locked++ == 0) { | 48 | if (locked++ == 0) { |
49 | //TODO: Urgh, I don't like that at all... | 49 | //TODO: Urgh, I don't like that at all... |
50 | VIC0INTENCLEAR = 1 << IRQ_DMAC0; | 50 | VIC0INTENCLEAR = 1 << IRQ_DMAC0; |
51 | } | 51 | } |
52 | } | 52 | } |
53 | 53 | ||
54 | /* Unmask the DMA interrupt if enabled */ | 54 | /* Unmask the DMA interrupt if enabled */ |
55 | void pcm_play_unlock(void) | 55 | void pcm_play_unlock(void) |
56 | { | 56 | { |
57 | if (--locked == 0) { | 57 | if (--locked == 0) { |
58 | VIC0INTENABLE = 1 << IRQ_DMAC0; | 58 | VIC0INTENABLE = 1 << IRQ_DMAC0; |
59 | } | 59 | } |
60 | } | 60 | } |
61 | 61 | ||
62 | void INT_DMAC0C0(void) ICODE_ATTR; | 62 | void INT_DMAC0C0(void) ICODE_ATTR; |
63 | void INT_DMAC0C0(void) | 63 | void INT_DMAC0C0(void) |
64 | { | 64 | { |
65 | DMAC0INTTCCLR = 1; | 65 | DMAC0INTTCCLR = 1; |
66 | if (!pcm_remaining) | 66 | if (!pcm_remaining) |
67 | { | 67 | { |
68 | pcm_play_get_more_callback((void**)&dataptr, &pcm_remaining); | 68 | pcm_play_get_more_callback((void**)&dataptr, &pcm_remaining); |
69 | pcm_chunksize = pcm_remaining; | 69 | pcm_chunksize = pcm_remaining; |
70 | } | 70 | } |
71 | if (!pcm_remaining) | 71 | if (!pcm_remaining) |
72 | { | 72 | { |
73 | pcm_lli->nextlli = NULL; | 73 | pcm_lli->nextlli = NULL; |
74 | pcm_lli->control = 0x75249000; | 74 | pcm_lli->control = 0x75249000; |
75 | clean_dcache(); | 75 | clean_dcache(); |
76 | return; | 76 | return; |
77 | } | 77 | } |
78 | uint32_t lastsize = MIN(PCM_WATERMARK * 4, pcm_remaining / 2 + 1) & ~1; | 78 | uint32_t lastsize = MIN(PCM_WATERMARK * 4, pcm_remaining / 2 + 1) & ~1; |
79 | pcm_remaining -= lastsize; | 79 | pcm_remaining -= lastsize; |
80 | if (pcm_remaining) lastlli = &pcm_lli[ARRAYLEN(pcm_lli) - 1]; | 80 | if (pcm_remaining) lastlli = &pcm_lli[ARRAYLEN(pcm_lli) - 1]; |
81 | else lastlli = pcm_lli; | 81 | else lastlli = pcm_lli; |
82 | uint32_t chunksize = MIN(PCM_CHUNKSIZE * 4 - lastsize, pcm_remaining); | 82 | uint32_t chunksize = MIN(PCM_CHUNKSIZE * 4 - lastsize, pcm_remaining); |
83 | if (pcm_remaining > chunksize && chunksize > pcm_remaining - PCM_WATERMARK * 8) | 83 | if (pcm_remaining > chunksize && chunksize > pcm_remaining - PCM_WATERMARK * 8) |
84 | chunksize = pcm_remaining - PCM_WATERMARK * 8; | 84 | chunksize = pcm_remaining - PCM_WATERMARK * 8; |
85 | pcm_remaining -= chunksize; | 85 | pcm_remaining -= chunksize; |
86 | bool last = !chunksize; | 86 | bool last = !chunksize; |
87 | int i = 0; | 87 | int i = 0; |
88 | while (chunksize) | 88 | while (chunksize) |
89 | { | 89 | { |
90 | uint32_t thislli = MIN(PCM_LLIMAX * 4, chunksize); | 90 | uint32_t thislli = MIN(PCM_LLIMAX * 4, chunksize); |
91 | chunksize -= thislli; | 91 | chunksize -= thislli; |
92 | pcm_lli[i].srcaddr = (void*)dataptr; | 92 | pcm_lli[i].srcaddr = (void*)dataptr; |
93 | pcm_lli[i].dstaddr = (void*)((int)&I2STXDB0); | 93 | pcm_lli[i].dstaddr = (void*)((int)&I2STXDB0); |
94 | pcm_lli[i].nextlli = chunksize ? &pcm_lli[i + 1] : lastlli; | 94 | pcm_lli[i].nextlli = chunksize ? &pcm_lli[i + 1] : lastlli; |
95 | pcm_lli[i].control = (chunksize ? 0x75249000 : 0xf5249000) | (thislli / 2); | 95 | pcm_lli[i].control = (chunksize ? 0x75249000 : 0xf5249000) | (thislli / 2); |
96 | dataptr += thislli; | 96 | dataptr += thislli; |
97 | i++; | 97 | i++; |
98 | } | 98 | } |
99 | if (!pcm_remaining) | 99 | if (!pcm_remaining) |
100 | { | 100 | { |
101 | memcpy(dblbuf[active_dblbuf], dataptr, lastsize); | 101 | memcpy(dblbuf[active_dblbuf], dataptr, lastsize); |
102 | lastlli->srcaddr = dblbuf[active_dblbuf]; | 102 | lastlli->srcaddr = dblbuf[active_dblbuf]; |
103 | active_dblbuf ^= 1; | 103 | active_dblbuf ^= 1; |
104 | } | 104 | } |
105 | else lastlli->srcaddr = dataptr; | 105 | else lastlli->srcaddr = dataptr; |
106 | lastlli->dstaddr = (void*)((int)&I2STXDB0); | 106 | lastlli->dstaddr = (void*)((int)&I2STXDB0); |
107 | lastlli->nextlli = last ? NULL : pcm_lli; | 107 | lastlli->nextlli = last ? NULL : pcm_lli; |
108 | lastlli->control = (last ? 0xf5249000 : 0x75249000) | (lastsize / 2); | 108 | lastlli->control = (last ? 0xf5249000 : 0x75249000) | (lastsize / 2); |
109 | dataptr += lastsize; | 109 | dataptr += lastsize; |
110 | clean_dcache(); | 110 | clean_dcache(); |
111 | if (!(DMAC0C0CONFIG & 1) && (pcm_lli[0].control & 0xfff)) | 111 | if (!(DMAC0C0CONFIG & 1) && (pcm_lli[0].control & 0xfff)) |
112 | { | 112 | { |
113 | DMAC0C0LLI = pcm_lli[0]; | 113 | DMAC0C0LLI = pcm_lli[0]; |
114 | DMAC0C0CONFIG = 0x8a81; | 114 | DMAC0C0CONFIG = 0x8a81; |
115 | } | 115 | } |
116 | else DMAC0C0NEXTLLI = pcm_lli; | 116 | else DMAC0C0NEXTLLI = pcm_lli; |
117 | 117 | ||
118 | pcm_play_dma_started_callback(); | 118 | pcm_play_dma_started_callback(); |
119 | } | 119 | } |
120 | 120 | ||
121 | void pcm_play_dma_start(const void* addr, size_t size) | 121 | void pcm_play_dma_start(const void* addr, size_t size) |
122 | { | 122 | { |
123 | dataptr = (const unsigned char*)addr; | 123 | dataptr = (const unsigned char*)addr; |
124 | pcm_remaining = size; | 124 | pcm_remaining = size; |
125 | I2STXCOM = 0xe; | 125 | I2STXCOM = 0xe; |
126 | DMAC0CONFIG |= 4; | 126 | DMAC0CONFIG |= 4; |
127 | INT_DMAC0C0(); | 127 | INT_DMAC0C0(); |
128 | } | 128 | } |
129 | 129 | ||
130 | void pcm_play_dma_stop(void) | 130 | void pcm_play_dma_stop(void) |
131 | { | 131 | { |
132 | DMAC0C0CONFIG = 0x8a80; | 132 | DMAC0C0CONFIG = 0x8a80; |
133 | I2STXCOM = 0xa; | 133 | I2STXCOM = 0xa; |
134 | } | 134 | } |
135 | 135 | ||
136 | /* pause playback by disabling LRCK */ | 136 | /* pause playback by disabling LRCK */ |
137 | void pcm_play_dma_pause(bool pause) | 137 | void pcm_play_dma_pause(bool pause) |
138 | { | 138 | { |
139 | if (pause) I2STXCOM |= 1; | 139 | if (pause) I2STXCOM |= 1; |
140 | else I2STXCOM &= ~1; | 140 | else I2STXCOM &= ~1; |
141 | } | 141 | } |
142 | 142 | ||
143 | void pcm_play_dma_init(void) | 143 | void pcm_play_dma_init(void) |
144 | { | 144 | { |
145 | PWRCON(0) &= ~(1 << 4); | 145 | PWRCON(0) &= ~(1 << 4); |
146 | PWRCON(1) &= ~(1 << 7); | 146 | PWRCON(1) &= ~(1 << 7); |
147 | I2S40 = 0x110; | 147 | I2S40 = 0x110; |
148 | I2STXCON = 0xb100059; | 148 | I2STXCON = 0xb100059; |
149 | I2SCLKCON = 1; | 149 | I2SCLKCON = 1; |
150 | VIC0INTENABLE = 1 << IRQ_DMAC0; | 150 | VIC0INTENABLE = 1 << IRQ_DMAC0; |
151 | 151 | ||
152 | audiohw_preinit(); | 152 | audiohw_preinit(); |
153 | } | 153 | } |
154 | 154 | ||
155 | void pcm_play_dma_postinit(void) | 155 | void pcm_play_dma_postinit(void) |
156 | { | 156 | { |
157 | audiohw_postinit(); | 157 | audiohw_postinit(); |
158 | } | 158 | } |
159 | 159 | ||
160 | void pcm_dma_apply_settings(void) | 160 | void pcm_dma_apply_settings(void) |
161 | { | 161 | { |
162 | } | 162 | } |
163 | 163 | ||
164 | size_t pcm_get_bytes_waiting(void) | 164 | size_t pcm_get_bytes_waiting(void) |
165 | { | 165 | { |
166 | int bytes = pcm_remaining; | 166 | int bytes = pcm_remaining; |
167 | const struct dma_lli* lli = (const struct dma_lli*)((int)&DMAC0C0LLI); | 167 | const struct dma_lli* lli = (const struct dma_lli*)((int)&DMAC0C0LLI); |
168 | while (lli) | 168 | while (lli) |
169 | { | 169 | { |
170 | bytes += (lli->control & 0xfff) * 2; | 170 | bytes += (lli->control & 0xfff) * 2; |
171 | if (lli == lastlli) break; | 171 | if (lli == lastlli) break; |
172 | lli = lli->nextlli; | 172 | lli = lli->nextlli; |
173 | } | 173 | } |
174 | return bytes; | 174 | return bytes; |
175 | } | 175 | } |
176 | 176 | ||
177 | const void* pcm_play_dma_get_peak_buffer(int *count) | 177 | const void* pcm_play_dma_get_peak_buffer(int *count) |
178 | { | 178 | { |
179 | *count = (DMAC0C0LLI.control & 0xfff) * 2; | 179 | *count = (DMAC0C0LLI.control & 0xfff) * 2; |
180 | return (void*)(((uint32_t)DMAC0C0LLI.srcaddr) & ~3); | 180 | return (void*)(((uint32_t)DMAC0C0LLI.srcaddr) & ~3); |
181 | } | 181 | } |
182 | 182 | ||
183 | #ifdef HAVE_PCM_DMA_ADDRESS | 183 | #ifdef HAVE_PCM_DMA_ADDRESS |
184 | void * pcm_dma_addr(void *addr) | 184 | void * pcm_dma_addr(void *addr) |
185 | { | 185 | { |
186 | return addr; | 186 | return addr; |
187 | } | 187 | } |
188 | #endif | 188 | #endif |
189 | 189 | ||
190 | 190 | ||
191 | /**************************************************************************** | 191 | /**************************************************************************** |
192 | ** Recording DMA transfer | 192 | ** Recording DMA transfer |
193 | **/ | 193 | **/ |
194 | #ifdef HAVE_RECORDING | 194 | #ifdef HAVE_RECORDING |
195 | void pcm_rec_lock(void) | 195 | void pcm_rec_lock(void) |
196 | { | 196 | { |
197 | } | 197 | } |
198 | 198 | ||
199 | void pcm_rec_unlock(void) | 199 | void pcm_rec_unlock(void) |
200 | { | 200 | { |
201 | } | 201 | } |
202 | 202 | ||
203 | void pcm_rec_dma_stop(void) | 203 | void pcm_rec_dma_stop(void) |
204 | { | 204 | { |
205 | } | 205 | } |
206 | 206 | ||
207 | void pcm_rec_dma_start(void *addr, size_t size) | 207 | void pcm_rec_dma_start(void *addr, size_t size) |
208 | { | 208 | { |
209 | (void)addr; | 209 | (void)addr; |
210 | (void)size; | 210 | (void)size; |
211 | } | 211 | } |
212 | 212 | ||
213 | void pcm_rec_dma_close(void) | 213 | void pcm_rec_dma_close(void) |
214 | { | 214 | { |
215 | } | 215 | } |
216 | 216 | ||
217 | 217 | ||
218 | void pcm_rec_dma_init(void) | 218 | void pcm_rec_dma_init(void) |
219 | { | 219 | { |
220 | } | 220 | } |
221 | 221 | ||
222 | 222 | ||
223 | const void * pcm_rec_dma_get_peak_buffer(void) | 223 | const void * pcm_rec_dma_get_peak_buffer(void) |
224 | { | 224 | { |
225 | return NULL; | 225 | return NULL; |
226 | } | 226 | } |
227 | 227 | ||
228 | #endif /* HAVE_RECORDING */ | 228 | #endif /* HAVE_RECORDING */ |
diff --git a/firmware/target/arm/s5l8702/pcm-target.h b/firmware/target/arm/s5l8702/pcm-target.h index 1b149a6e0b..aefb64e328 100644 --- a/firmware/target/arm/s5l8702/pcm-target.h +++ b/firmware/target/arm/s5l8702/pcm-target.h | |||
@@ -1,40 +1,40 @@ | |||
1 | /*************************************************************************** | 1 | /*************************************************************************** |
2 | * __________ __ ___. | 2 | * __________ __ ___. |
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ |
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / |
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id: system-target.h 28791 2010-12-11 09:39:33Z Buschel $ | 8 | * $Id: system-target.h 28791 2010-12-11 09:39:33Z Buschel $ |
9 | * | 9 | * |
10 | * Copyright (C) 2010 by Michael Sparmann | 10 | * Copyright (C) 2010 by Michael Sparmann |
11 | * | 11 | * |
12 | * This program is free software; you can redistribute it and/or | 12 | * This program is free software; you can redistribute it and/or |
13 | * modify it under the terms of the GNU General Public License | 13 | * modify it under the terms of the GNU General Public License |
14 | * as published by the Free Software Foundation; either version 2 | 14 | * as published by the Free Software Foundation; either version 2 |
15 | * of the License, or (at your option) any later version. | 15 | * of the License, or (at your option) any later version. |
16 | * | 16 | * |
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | 17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY |
18 | * KIND, either express or implied. | 18 | * KIND, either express or implied. |
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | #ifndef __PCM_TARGET_H__ | 21 | #ifndef __PCM_TARGET_H__ |
22 | #define __PCM_TARGET_H__ | 22 | #define __PCM_TARGET_H__ |
23 | 23 | ||
24 | 24 | ||
25 | /* S5L8702 PCM driver tunables: */ | 25 | /* S5L8702 PCM driver tunables: */ |
26 | #define PCM_LLIMAX (2047) /* Maximum number of samples per LLI */ | 26 | #define PCM_LLIMAX (2047) /* Maximum number of samples per LLI */ |
27 | #define PCM_CHUNKSIZE (10747) /* Maximum number of samples to handle with one IRQ */ | 27 | #define PCM_CHUNKSIZE (10747) /* Maximum number of samples to handle with one IRQ */ |
28 | /* (bigger chunks will be segmented internally) */ | 28 | /* (bigger chunks will be segmented internally) */ |
29 | #define PCM_WATERMARK (512) /* Number of remaining samples to schedule IRQ at */ | 29 | #define PCM_WATERMARK (512) /* Number of remaining samples to schedule IRQ at */ |
30 | 30 | ||
31 | 31 | ||
32 | #define PCM_LLICOUNT ((PCM_CHUNKSIZE - PCM_WATERMARK + PCM_LLIMAX - 1) / PCM_LLIMAX + 1) | 32 | #define PCM_LLICOUNT ((PCM_CHUNKSIZE - PCM_WATERMARK + PCM_LLIMAX - 1) / PCM_LLIMAX + 1) |
33 | 33 | ||
34 | 34 | ||
35 | extern struct dma_lli pcm_lli[PCM_LLICOUNT]; | 35 | extern struct dma_lli pcm_lli[PCM_LLICOUNT]; |
36 | extern size_t pcm_remaining; | 36 | extern size_t pcm_remaining; |
37 | extern size_t pcm_chunksize; | 37 | extern size_t pcm_chunksize; |
38 | 38 | ||
39 | 39 | ||
40 | #endif /* __PCM_TARGET_H__ */ | 40 | #endif /* __PCM_TARGET_H__ */ |
diff --git a/firmware/target/arm/s5l8702/system-target.h b/firmware/target/arm/s5l8702/system-target.h index 30e53ad6ea..799efb7006 100644 --- a/firmware/target/arm/s5l8702/system-target.h +++ b/firmware/target/arm/s5l8702/system-target.h | |||
@@ -1,47 +1,47 @@ | |||
1 | /*************************************************************************** | 1 | /*************************************************************************** |
2 | * __________ __ ___. | 2 | * __________ __ ___. |
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ |
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / |
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id: system-target.h 28791 2010-12-11 09:39:33Z Buschel $ | 8 | * $Id: system-target.h 28791 2010-12-11 09:39:33Z Buschel $ |
9 | * | 9 | * |
10 | * Copyright (C) 2007 by Dave Chapman | 10 | * Copyright (C) 2007 by Dave Chapman |
11 | * | 11 | * |
12 | * This program is free software; you can redistribute it and/or | 12 | * This program is free software; you can redistribute it and/or |
13 | * modify it under the terms of the GNU General Public License | 13 | * modify it under the terms of the GNU General Public License |
14 | * as published by the Free Software Foundation; either version 2 | 14 | * as published by the Free Software Foundation; either version 2 |
15 | * of the License, or (at your option) any later version. | 15 | * of the License, or (at your option) any later version. |
16 | * | 16 | * |
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | 17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY |
18 | * KIND, either express or implied. | 18 | * KIND, either express or implied. |
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | #ifndef SYSTEM_TARGET_H | 21 | #ifndef SYSTEM_TARGET_H |
22 | #define SYSTEM_TARGET_H | 22 | #define SYSTEM_TARGET_H |
23 | 23 | ||
24 | #include "system-arm.h" | 24 | #include "system-arm.h" |
25 | #include "mmu-arm.h" | 25 | #include "mmu-arm.h" |
26 | 26 | ||
27 | #define CPUFREQ_SLEEP 32768 | 27 | #define CPUFREQ_SLEEP 32768 |
28 | #define CPUFREQ_MAX 216000000 | 28 | #define CPUFREQ_MAX 216000000 |
29 | #define CPUFREQ_DEFAULT 108000000 | 29 | #define CPUFREQ_DEFAULT 108000000 |
30 | #define CPUFREQ_NORMAL 108000000 | 30 | #define CPUFREQ_NORMAL 108000000 |
31 | 31 | ||
32 | #define STORAGE_WANTS_ALIGN | 32 | #define STORAGE_WANTS_ALIGN |
33 | 33 | ||
34 | #define inl(a) (*(volatile unsigned long *) (a)) | 34 | #define inl(a) (*(volatile unsigned long *) (a)) |
35 | #define outl(a,b) (*(volatile unsigned long *) (b) = (a)) | 35 | #define outl(a,b) (*(volatile unsigned long *) (b) = (a)) |
36 | #define inb(a) (*(volatile unsigned char *) (a)) | 36 | #define inb(a) (*(volatile unsigned char *) (a)) |
37 | #define outb(a,b) (*(volatile unsigned char *) (b) = (a)) | 37 | #define outb(a,b) (*(volatile unsigned char *) (b) = (a)) |
38 | #define inw(a) (*(volatile unsigned short*) (a)) | 38 | #define inw(a) (*(volatile unsigned short*) (a)) |
39 | #define outw(a,b) (*(volatile unsigned short*) (b) = (a)) | 39 | #define outw(a,b) (*(volatile unsigned short*) (b) = (a)) |
40 | 40 | ||
41 | static inline void udelay(unsigned usecs) | 41 | static inline void udelay(unsigned usecs) |
42 | { | 42 | { |
43 | unsigned stop = USEC_TIMER + usecs; | 43 | unsigned stop = USEC_TIMER + usecs; |
44 | while (TIME_BEFORE(USEC_TIMER, stop)); | 44 | while (TIME_BEFORE(USEC_TIMER, stop)); |
45 | } | 45 | } |
46 | 46 | ||
47 | #endif /* SYSTEM_TARGET_H */ | 47 | #endif /* SYSTEM_TARGET_H */ |
diff --git a/firmware/target/arm/s5l8702/timer-s5l8702.c b/firmware/target/arm/s5l8702/timer-s5l8702.c index fb56a9ffcf..61d4d590e4 100644 --- a/firmware/target/arm/s5l8702/timer-s5l8702.c +++ b/firmware/target/arm/s5l8702/timer-s5l8702.c | |||
@@ -1,94 +1,94 @@ | |||
1 | /*************************************************************************** | 1 | /*************************************************************************** |
2 | * __________ __ ___. | 2 | * __________ __ ___. |
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ |
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / |
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id: timer-s5l8700.c 23103 2009-10-11 11:35:14Z theseven $ | 8 | * $Id: timer-s5l8700.c 23103 2009-10-11 11:35:14Z theseven $ |
9 | * | 9 | * |
10 | * Copyright (C) 2009 Bertrik Sikken | 10 | * Copyright (C) 2009 Bertrik Sikken |
11 | * | 11 | * |
12 | * This program is free software; you can redistribute it and/or | 12 | * This program is free software; you can redistribute it and/or |
13 | * modify it under the terms of the GNU General Public License | 13 | * modify it under the terms of the GNU General Public License |
14 | * as published by the Free Software Foundation; either version 2 | 14 | * as published by the Free Software Foundation; either version 2 |
15 | * of the License, or (at your option) any later version. | 15 | * of the License, or (at your option) any later version. |
16 | * | 16 | * |
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | 17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY |
18 | * KIND, either express or implied. | 18 | * KIND, either express or implied. |
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | 21 | ||
22 | #include "config.h" | 22 | #include "config.h" |
23 | 23 | ||
24 | #include "inttypes.h" | 24 | #include "inttypes.h" |
25 | #include "s5l8702.h" | 25 | #include "s5l8702.h" |
26 | #include "system.h" | 26 | #include "system.h" |
27 | #include "timer.h" | 27 | #include "timer.h" |
28 | 28 | ||
29 | //TODO: This needs calibration once we figure out the clocking | 29 | //TODO: This needs calibration once we figure out the clocking |
30 | 30 | ||
31 | void INT_TIMERC(void) | 31 | void INT_TIMERC(void) |
32 | { | 32 | { |
33 | /* clear interrupt */ | 33 | /* clear interrupt */ |
34 | TCCON = TCCON; | 34 | TCCON = TCCON; |
35 | 35 | ||
36 | if (pfn_timer != NULL) { | 36 | if (pfn_timer != NULL) { |
37 | pfn_timer(); | 37 | pfn_timer(); |
38 | } | 38 | } |
39 | } | 39 | } |
40 | 40 | ||
41 | bool timer_set(long cycles, bool start) | 41 | bool timer_set(long cycles, bool start) |
42 | { | 42 | { |
43 | static const int cs_table[] = {1, 2, 4, 6}; | 43 | static const int cs_table[] = {1, 2, 4, 6}; |
44 | int prescale, cs; | 44 | int prescale, cs; |
45 | long count; | 45 | long count; |
46 | 46 | ||
47 | /* stop and clear timer */ | 47 | /* stop and clear timer */ |
48 | TCCMD = (1 << 1); /* TD_CLR */ | 48 | TCCMD = (1 << 1); /* TD_CLR */ |
49 | 49 | ||
50 | /* optionally unregister any previously registered timer user */ | 50 | /* optionally unregister any previously registered timer user */ |
51 | if (start) { | 51 | if (start) { |
52 | if (pfn_unregister != NULL) { | 52 | if (pfn_unregister != NULL) { |
53 | pfn_unregister(); | 53 | pfn_unregister(); |
54 | pfn_unregister = NULL; | 54 | pfn_unregister = NULL; |
55 | } | 55 | } |
56 | } | 56 | } |
57 | 57 | ||
58 | /* scale the count down with the clock select */ | 58 | /* scale the count down with the clock select */ |
59 | for (cs = 0; cs < 4; cs++) { | 59 | for (cs = 0; cs < 4; cs++) { |
60 | count = cycles >> cs_table[cs]; | 60 | count = cycles >> cs_table[cs]; |
61 | if ((count < 65536) || (cs == 3)) { | 61 | if ((count < 65536) || (cs == 3)) { |
62 | break; | 62 | break; |
63 | } | 63 | } |
64 | } | 64 | } |
65 | 65 | ||
66 | /* scale the count down with the prescaler */ | 66 | /* scale the count down with the prescaler */ |
67 | prescale = 1; | 67 | prescale = 1; |
68 | while (count >= 65536) { | 68 | while (count >= 65536) { |
69 | count >>= 1; | 69 | count >>= 1; |
70 | prescale <<= 1; | 70 | prescale <<= 1; |
71 | } | 71 | } |
72 | 72 | ||
73 | /* configure timer */ | 73 | /* configure timer */ |
74 | TCCON = (1 << 12) | /* TD_INT0_EN */ | 74 | TCCON = (1 << 12) | /* TD_INT0_EN */ |
75 | (cs << 8) | /* TS_CS */ | 75 | (cs << 8) | /* TS_CS */ |
76 | (0 << 4); /* TD_MODE_SEL, 0 = interval mode */ | 76 | (0 << 4); /* TD_MODE_SEL, 0 = interval mode */ |
77 | TCPRE = prescale - 1; | 77 | TCPRE = prescale - 1; |
78 | TCDATA0 = count; | 78 | TCDATA0 = count; |
79 | TCCMD = (1 << 0); /* TD_ENABLE */ | 79 | TCCMD = (1 << 0); /* TD_ENABLE */ |
80 | 80 | ||
81 | return true; | 81 | return true; |
82 | } | 82 | } |
83 | 83 | ||
84 | bool timer_start(void) | 84 | bool timer_start(void) |
85 | { | 85 | { |
86 | TCCMD = (1 << 0); /* TD_ENABLE */ | 86 | TCCMD = (1 << 0); /* TD_ENABLE */ |
87 | return true; | 87 | return true; |
88 | } | 88 | } |
89 | 89 | ||
90 | void timer_stop(void) | 90 | void timer_stop(void) |
91 | { | 91 | { |
92 | TCCMD = (0 << 0); /* TD_ENABLE */ | 92 | TCCMD = (0 << 0); /* TD_ENABLE */ |
93 | } | 93 | } |
94 | 94 | ||
diff --git a/firmware/target/sh/archos/mascodec-archos.c b/firmware/target/sh/archos/mascodec-archos.c index 3f932166eb..1eb6e1044d 100644 --- a/firmware/target/sh/archos/mascodec-archos.c +++ b/firmware/target/sh/archos/mascodec-archos.c | |||
@@ -5,7 +5,7 @@ | |||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id: mas.c 18807 2008-10-14 11:12:20Z zagor $ | 8 | * $Id$ |
9 | * | 9 | * |
10 | * Copyright (C) 2002 by Linus Nielsen Feltzing | 10 | * Copyright (C) 2002 by Linus Nielsen Feltzing |
11 | * | 11 | * |