diff options
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/crt0.S | 848 |
1 files changed, 5 insertions, 843 deletions
diff --git a/firmware/crt0.S b/firmware/crt0.S index 96e08be9f1..61a2d63f1e 100644 --- a/firmware/crt0.S +++ b/firmware/crt0.S | |||
@@ -16,432 +16,21 @@ | |||
16 | * KIND, either express or implied. | 16 | * KIND, either express or implied. |
17 | * | 17 | * |
18 | ****************************************************************************/ | 18 | ****************************************************************************/ |
19 | |||
20 | /* Most of the code from this file has now been moved into the target trees */ | ||
21 | |||
19 | #include "config.h" | 22 | #include "config.h" |
20 | #include "cpu.h" | 23 | #include "cpu.h" |
21 | 24 | ||
22 | #if defined(CPU_ARM) | ||
23 | .section .init.text,"ax",%progbits | ||
24 | #else | ||
25 | .section .init.text,"ax",@progbits | 25 | .section .init.text,"ax",@progbits |
26 | #endif | ||
27 | 26 | ||
28 | .global start | 27 | .global start |
29 | start: | 28 | start: |
30 | 29 | ||
31 | #if defined(CPU_ARM) | 30 | #if CONFIG_CPU == TCC730 |
32 | |||
33 | /* iPod bootloader and startup code based on startup.s from the iPodLinux loader | ||
34 | * | ||
35 | * Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org) | ||
36 | * Copyright (c) 2005, Bernard Leach <leachbj@bouncycastle.org> | ||
37 | * | ||
38 | */ | ||
39 | .equ PP5002_PROC_ID, 0xc4000000 | ||
40 | .equ PP5002_COP_CTRL, 0xcf004058 | ||
41 | .equ PP5020_PROC_ID, 0x60000000 | ||
42 | .equ PP5020_COP_CTRL, 0x60007004 | ||
43 | |||
44 | msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ */ | ||
45 | |||
46 | #ifndef BOOTLOADER | ||
47 | #ifdef CPU_PP | ||
48 | b pad_skip | ||
49 | .space 50*4 /* (more than enough) space for exception vectors */ | ||
50 | pad_skip: | ||
51 | /* We need to remap memory from wherever SDRAM is mapped natively, to | ||
52 | base address 0, so we can put our exception vectors there. We don't | ||
53 | want to do this remapping while executing from SDRAM, so we copy the | ||
54 | remapping code to IRAM, then execute from there. Hence, the following | ||
55 | code is compiled for address 0, but is currently executing at either | ||
56 | 0x28000000 or 0x10000000, depending on chipset version. Do not use any | ||
57 | absolute addresses until remapping has been done. */ | ||
58 | ldr r1, =0x40000000 | ||
59 | ldr r2, =remap_start | ||
60 | ldr r3, =remap_end | ||
61 | |||
62 | and r5, pc, #0xff000000 /* adjust for execute address */ | ||
63 | orr r2, r2, r5 | ||
64 | orr r3, r3, r5 | ||
65 | |||
66 | /* copy the code to 0x40000000 */ | ||
67 | 1: | ||
68 | ldr r4, [r2], #4 | ||
69 | str r4, [r1], #4 | ||
70 | cmp r2, r3 | ||
71 | ble 1b | ||
72 | |||
73 | ldr r3, =0x3f84 /* r3 and r1 values here are magic, don't touch */ | ||
74 | orr r3, r3, r5 /* adjust for execute address */ | ||
75 | ldr r2, =0xf000f014 | ||
76 | mov r1, #0x3a00 | ||
77 | ldr r0, =0xf000f010 | ||
78 | mov pc, #0x40000000 | ||
79 | |||
80 | remap_start: | ||
81 | str r1, [r0] | ||
82 | str r3, [r2] | ||
83 | ldr r0, L_post_remap | ||
84 | mov pc, r0 | ||
85 | L_post_remap: .word remap_end | ||
86 | remap_end: | ||
87 | |||
88 | /* After doing the remapping, send the COP to sleep. | ||
89 | On wakeup it will go to cop_init */ | ||
90 | #if CONFIG_CPU == PP5002 | ||
91 | ldr r0, =PP5002_PROC_ID | ||
92 | #else | ||
93 | ldr r0, =PP5020_PROC_ID | ||
94 | #endif | ||
95 | ldr r0, [r0] | ||
96 | and r0, r0, #0xff | ||
97 | cmp r0, #0x55 | ||
98 | beq 1f | ||
99 | |||
100 | /* put us (co-processor) to sleep */ | ||
101 | #if CONFIG_CPU == PP5002 | ||
102 | ldr r4, =PP5002_COP_CTRL | ||
103 | mov r3, #0xca | ||
104 | #else | ||
105 | ldr r4, =PP5020_COP_CTRL | ||
106 | mov r3, #0x80000000 | ||
107 | #endif | ||
108 | str r3, [r4] | ||
109 | |||
110 | ldr pc, =cop_init | ||
111 | |||
112 | 1: | ||
113 | |||
114 | #elif CONFIG_CPU == PNX0101 | ||
115 | |||
116 | #ifndef DEBUG | ||
117 | ldr r0, =0x80105000 | ||
118 | mov r1, #1 | ||
119 | str r1, [r0, #4] | ||
120 | mov r1, #0 | ||
121 | str r1, [r0, #4] | ||
122 | 1: ldr r1, [r0] | ||
123 | cmp r1, #0 | ||
124 | bne 1b | ||
125 | mov r1, #0x74 | ||
126 | str r1, [r0, #8] | ||
127 | mov r1, #2 | ||
128 | str r1, [r0, #0x18] | ||
129 | mov r1, #0x120 | ||
130 | str r1, [r0, #0x30] | ||
131 | mov r1, #6 | ||
132 | str r1, [r0, #4] | ||
133 | ldr r0, =1f | ||
134 | mov r15, r0 | ||
135 | 1: | ||
136 | #endif /* !DEBUG */ | ||
137 | #endif /* chipset specific */ | ||
138 | |||
139 | #ifndef DEBUG | ||
140 | /* Copy exception handler code to address 0 */ | ||
141 | ldr r2, =_vectorsstart | ||
142 | ldr r3, =_vectorsend | ||
143 | ldr r4, =_vectorscopy | ||
144 | 1: | ||
145 | cmp r3, r2 | ||
146 | ldrhi r5, [r4], #4 | ||
147 | strhi r5, [r2], #4 | ||
148 | bhi 1b | ||
149 | #else | ||
150 | ldr r1, =vectors | ||
151 | ldr r0, =irq_handler | ||
152 | str r0, [r1, #24] | ||
153 | ldr r0, =fiq_handler | ||
154 | str r0, [r1, #28] | ||
155 | #endif | ||
156 | |||
157 | #ifndef STUB | ||
158 | /* Zero out IBSS */ | ||
159 | ldr r2, =_iedata | ||
160 | ldr r3, =_iend | ||
161 | mov r4, #0 | ||
162 | 1: | ||
163 | cmp r3, r2 | ||
164 | strhi r4, [r2], #4 | ||
165 | bhi 1b | ||
166 | |||
167 | /* Copy the IRAM */ | ||
168 | ldr r2, =_iramcopy | ||
169 | ldr r3, =_iramstart | ||
170 | ldr r4, =_iramend | ||
171 | 1: | ||
172 | cmp r4, r3 | ||
173 | ldrhi r5, [r2], #4 | ||
174 | strhi r5, [r3], #4 | ||
175 | bhi 1b | ||
176 | #endif /* !STUB */ | ||
177 | #endif /* !BOOTLOADER */ | ||
178 | |||
179 | /* Initialise bss section to zero */ | ||
180 | ldr r2, =_edata | ||
181 | ldr r3, =_end | ||
182 | mov r4, #0 | ||
183 | 1: | ||
184 | cmp r3, r2 | ||
185 | strhi r4, [r2], #4 | ||
186 | bhi 1b | ||
187 | |||
188 | /* Set up some stack and munge it with 0xdeadbeef */ | ||
189 | ldr sp, =stackend | ||
190 | mov r3, sp | ||
191 | ldr r2, =stackbegin | ||
192 | ldr r4, =0xdeadbeef | ||
193 | 1: | ||
194 | cmp r3, r2 | ||
195 | strhi r4, [r2], #4 | ||
196 | bhi 1b | ||
197 | |||
198 | #ifdef BOOTLOADER | ||
199 | #ifdef CPU_PP | ||
200 | /* TODO: the high part of the address is probably dependent on CONFIG_CPU. | ||
201 | Since we tend to use ifdefs for each chipset target | ||
202 | anyway, we might as well just hardcode it here. | ||
203 | */ | ||
204 | |||
205 | /* get the high part of our execute address */ | ||
206 | ldr r0, =0xff000000 | ||
207 | and r8, pc, r0 @ r8 is used later | ||
208 | |||
209 | #if CONFIG_CPU==PP5002 | ||
210 | mov r0, #PP5002_PROC_ID | ||
211 | #else | ||
212 | mov r0, #PP5020_PROC_ID | ||
213 | #endif | ||
214 | ldr r0, [r0] | ||
215 | and r0, r0, #0xff | ||
216 | cmp r0, #0x55 | ||
217 | beq 1f | ||
218 | |||
219 | /* put us (co-processor) to sleep */ | ||
220 | #if CONFIG_CPU==PP5002 | ||
221 | ldr r4, =PP5002_COP_CTRL | ||
222 | mov r3, #0xca | ||
223 | #else | ||
224 | ldr r4, =PP5020_COP_CTRL | ||
225 | mov r3, #0x80000000 | ||
226 | #endif | ||
227 | str r3, [r4] | ||
228 | |||
229 | |||
230 | ldr pc, =cop_wake_start | ||
231 | |||
232 | cop_wake_start: | ||
233 | /* jump the COP to startup */ | ||
234 | ldr r0, =startup_loc | ||
235 | ldr pc, [r0] | ||
236 | |||
237 | 1: | ||
238 | |||
239 | /* get the high part of our execute address */ | ||
240 | ldr r2, =0xffffff00 | ||
241 | and r4, pc, r2 | ||
242 | |||
243 | /* Copy bootloader to safe area - 0x40000000 */ | ||
244 | mov r5, #0x40000000 | ||
245 | ldr r6, = _dataend | ||
246 | sub r0, r6, r5 /* length of loader */ | ||
247 | add r0, r4, r0 /* r0 points to start of loader */ | ||
248 | 1: | ||
249 | cmp r5, r6 | ||
250 | ldrcc r2, [r4], #4 | ||
251 | strcc r2, [r5], #4 | ||
252 | bcc 1b | ||
253 | |||
254 | ldr pc, =start_loc /* jump to the relocated start_loc: */ | ||
255 | |||
256 | start_loc: | ||
257 | |||
258 | /* execute the loader - this will load an image to 0x10000000 */ | ||
259 | bl main | ||
260 | |||
261 | /* The loader only returns if it is loading the Apple firmware or Linux - | ||
262 | the following code isn't executed when starting Rockbox */ | ||
263 | |||
264 | /* save the startup address for the COP */ | ||
265 | ldr r1, =startup_loc | ||
266 | str r0, [r1] | ||
267 | |||
268 | #if CONFIG_CPU==PP5002 | ||
269 | /* make sure COP is sleeping */ | ||
270 | ldr r4, =0xcf004050 | ||
271 | 1: | ||
272 | ldr r3, [r4] | ||
273 | ands r3, r3, #0x4000 | ||
274 | beq 1b | ||
275 | |||
276 | /* wake up COP */ | ||
277 | ldr r4, =PP5002_COP_CTRL | ||
278 | mov r3, #0xce | ||
279 | strh r3, [r4] | ||
280 | #else | ||
281 | /* make sure COP is sleeping */ | ||
282 | ldr r4, =PP5020_COP_CTRL | ||
283 | 1: | ||
284 | ldr r3, [r4] | ||
285 | ands r3, r3, #0x80000000 | ||
286 | beq 1b | ||
287 | |||
288 | /* wake up COP */ | ||
289 | @ldr r4, =PP5020_COP_CTRL | ||
290 | mov r3, #0x0 | ||
291 | str r3, [r4] | ||
292 | #endif | ||
293 | /* jump to start location */ | ||
294 | mov pc, r0 | ||
295 | |||
296 | startup_loc: | ||
297 | .word 0x0 | ||
298 | |||
299 | .align 8 /* starts at 0x100 */ | ||
300 | .global boot_table | ||
301 | boot_table: | ||
302 | /* here comes the boot table, don't move its offset */ | ||
303 | .space 400 | ||
304 | #endif /* PP specific */ | ||
305 | /* Code for ARM bootloader targets other than iPod go here */ | ||
306 | |||
307 | #if CONFIG_CPU == S3C2440 | ||
308 | bl main | ||
309 | #endif | ||
310 | |||
311 | #else /* BOOTLOADER */ | ||
312 | |||
313 | /* Set up stack for IRQ mode */ | ||
314 | msr cpsr_c, #0xd2 | ||
315 | ldr sp, =irq_stack | ||
316 | /* Set up stack for FIQ mode */ | ||
317 | msr cpsr_c, #0xd1 | ||
318 | ldr sp, =fiq_stack | ||
319 | #ifdef CPU_PP | ||
320 | /* We'll load the banked FIQ mode registers with useful values here. | ||
321 | These values will be used in the FIQ handler in pcm_playback.c */ | ||
322 | #if CONFIG_CPU == PP5002 | ||
323 | ldr r12, =0xc0002500 /* PP5002 IISCONFIG */ | ||
324 | #else | ||
325 | ldr r12, =0x70002800 /* PP502x IISCONFIG */ | ||
326 | #endif | ||
327 | ldr r11, =p | ||
328 | #endif | ||
329 | /* Let abort and undefined modes use IRQ stack */ | ||
330 | msr cpsr_c, #0xd7 | ||
331 | ldr sp, =irq_stack | ||
332 | msr cpsr_c, #0xdb | ||
333 | ldr sp, =irq_stack | ||
334 | /* Switch to supervisor mode */ | ||
335 | msr cpsr_c, #0xd3 | ||
336 | ldr sp, =stackend | ||
337 | bl main | ||
338 | /* main() should never return */ | ||
339 | |||
340 | #ifdef CPU_PP | ||
341 | cop_init: | ||
342 | ldr sp, =cop_stackend | ||
343 | mov r3, sp | ||
344 | ldr r2, =cop_stackbegin | ||
345 | ldr r4, =0xdeadbeef | ||
346 | 2: | ||
347 | cmp r3, r2 | ||
348 | strhi r4, [r2], #4 | ||
349 | bhi 2b | ||
350 | |||
351 | ldr sp, =cop_stackend | ||
352 | bl cop_main | ||
353 | #endif /* PP specific */ | ||
354 | |||
355 | /* Exception handlers. Will be copied to address 0 after memory remapping */ | ||
356 | .section .vectors,"aw" | ||
357 | ldr pc, [pc, #24] | ||
358 | ldr pc, [pc, #24] | ||
359 | ldr pc, [pc, #24] | ||
360 | ldr pc, [pc, #24] | ||
361 | ldr pc, [pc, #24] | ||
362 | ldr pc, [pc, #24] | ||
363 | ldr pc, [pc, #24] | ||
364 | ldr pc, [pc, #24] | ||
365 | |||
366 | /* Exception vectors */ | ||
367 | .global vectors | ||
368 | vectors: | ||
369 | .word start | ||
370 | .word undef_instr_handler | ||
371 | .word software_int_handler | ||
372 | .word prefetch_abort_handler | ||
373 | .word data_abort_handler | ||
374 | .word reserved_handler | ||
375 | .word irq_handler | ||
376 | .word fiq_handler | ||
377 | |||
378 | .text | ||
379 | |||
380 | #ifndef STUB | ||
381 | .global irq | ||
382 | .global fiq | ||
383 | .global UIE | ||
384 | #endif | ||
385 | |||
386 | /* All illegal exceptions call into UIE with exception address as first | ||
387 | parameter. This is calculated differently depending on which exception | ||
388 | we're in. Second parameter is exception number, used for a string lookup | ||
389 | in UIE. | ||
390 | */ | ||
391 | undef_instr_handler: | ||
392 | mov r0, lr | ||
393 | mov r1, #0 | ||
394 | b UIE | ||
395 | |||
396 | /* We run supervisor mode most of the time, and should never see a software | ||
397 | exception being thrown. Perhaps make it illegal and call UIE? | ||
398 | */ | ||
399 | software_int_handler: | ||
400 | reserved_handler: | ||
401 | movs pc, lr | ||
402 | |||
403 | prefetch_abort_handler: | ||
404 | sub r0, lr, #4 | ||
405 | mov r1, #1 | ||
406 | b UIE | ||
407 | |||
408 | fiq_handler: | ||
409 | @ Branch straight to FIQ handler in pcm_playback.c. This also handles the | ||
410 | @ the correct return sequence. | ||
411 | ldr pc, =fiq | ||
412 | |||
413 | data_abort_handler: | ||
414 | sub r0, lr, #8 | ||
415 | mov r1, #2 | ||
416 | b UIE | ||
417 | |||
418 | irq_handler: | ||
419 | #ifndef STUB | ||
420 | stmfd sp!, {r0-r3, r12, lr} | ||
421 | bl irq | ||
422 | ldmfd sp!, {r0-r3, r12, lr} | ||
423 | #endif | ||
424 | subs pc, lr, #4 | ||
425 | |||
426 | #ifdef STUB | ||
427 | UIE: | ||
428 | b UIE | ||
429 | #endif | ||
430 | |||
431 | /* 256 words of IRQ stack */ | ||
432 | .space 256*4 | ||
433 | irq_stack: | ||
434 | |||
435 | /* 256 words of FIQ stack */ | ||
436 | .space 256*4 | ||
437 | fiq_stack: | ||
438 | |||
439 | #endif /* BOOTLOADER */ | ||
440 | |||
441 | #elif CONFIG_CPU == TCC730 | ||
442 | /* Platform: Gmini 120/SP */ | 31 | /* Platform: Gmini 120/SP */ |
443 | ;; disable all interrupts | 32 | ;; disable all interrupts |
444 | clrsr fe | 33 | clrsr fe |
445 | clrsr ie | 34 | clrsr ie |
446 | clrsr te | 35 | clrsr te |
447 | ld a14, #0x3F0000 | 36 | ld a14, #0x3F0000 |
@@ -531,431 +120,4 @@ irq_handler: | |||
531 | pop r3, r2 | 120 | pop r3, r2 |
532 | pop r1, r0 | 121 | pop r1, r0 |
533 | ret_irq | 122 | ret_irq |
534 | |||
535 | #elif defined(CPU_COLDFIRE) | ||
536 | move.w #0x2700,%sr | ||
537 | |||
538 | move.l #vectors,%d0 | ||
539 | movec.l %d0,%vbr | ||
540 | |||
541 | move.l #MBAR+1,%d0 | ||
542 | movec.l %d0,%mbar | ||
543 | |||
544 | move.l #MBAR2+1,%d0 | ||
545 | movec.l %d0,%mbar2 | ||
546 | |||
547 | lea MBAR,%a0 | ||
548 | lea MBAR2,%a1 | ||
549 | |||
550 | clr.l (0x180,%a1) /* PLLCR = 0 */ | ||
551 | |||
552 | /* 64K DMA-capable SRAM at 0x10000000 | ||
553 | DMA is enabled and has priority in both banks | ||
554 | All types of accesses are allowed | ||
555 | (We might want to restrict that to save power) */ | ||
556 | move.l #0x10000e01,%d0 | ||
557 | movec.l %d0,%rambar1 | ||
558 | |||
559 | /* 32K Non-DMA SRAM at 0x10010000 | ||
560 | All types of accesses are allowed | ||
561 | (We might want to restrict that to save power) */ | ||
562 | move.l #0x10010001,%d0 | ||
563 | movec.l %d0,%rambar0 | ||
564 | |||
565 | /* Chip select 0 - Flash ROM */ | ||
566 | moveq.l #0x00,%d0 /* CSAR0 - Base = 0x00000000 */ | ||
567 | move.l %d0,(0x080,%a0) | ||
568 | move.l #FLASH_SIZE-0x10000+1,%d0 /* CSMR0 - All access */ | ||
569 | move.l %d0,(0x084,%a0) | ||
570 | move.l #0x00000180,%d0 /* CSCR0 - no wait states, 16 bits, no bursts */ | ||
571 | move.l %d0,(0x088,%a0) | ||
572 | |||
573 | /* Chip select 1 - LCD controller */ | ||
574 | move.l #0xf0000000,%d0 /* CSAR1 - Base = 0xf0000000 */ | ||
575 | move.l %d0,(0x08c,%a0) | ||
576 | moveq.l #0x1,%d0 /* CSMR1 - 64K */ | ||
577 | move.l %d0,(0x090,%a0) | ||
578 | move.l #0x00000180,%d0 /* CSCR1 - no wait states, 16 bits, no bursts */ | ||
579 | move.l %d0,(0x094,%a0) | ||
580 | |||
581 | /* Chip select 2 - ATA controller */ | ||
582 | move.l #0x20000000,%d0 /* CSAR2 - Base = 0x20000000 */ | ||
583 | move.l %d0,(0x098,%a0) | ||
584 | move.l #0x000f0001,%d0 /* CSMR2 - 64K, Only data access */ | ||
585 | move.l %d0,(0x09c,%a0) | ||
586 | move.l #0x00000080,%d0 /* CSCR2 - no wait states, 16 bits, no bursts */ | ||
587 | move.l %d0,(0x0a0,%a0) /* NOTE: I'm not sure about the wait states. | ||
588 | We have to be careful with the access times, | ||
589 | since IORDY isn't connected to the HDD. */ | ||
590 | |||
591 | #if CONFIG_USBOTG == USBOTG_ISP1362 | ||
592 | /* Chip select 3 - USBOTG controller */ | ||
593 | move.l #0xc0000000,%d0 /* CSAR3 - Base = 0xc0000000 */ | ||
594 | move.l %d0,(0x0a4,%a0) | ||
595 | moveq.l #0x1,%d0 /* CSMR3 - 64K */ | ||
596 | move.l %d0,(0x0a8,%a0) | ||
597 | move.l #0x00000180,%d0 /* CSCR3 - no wait states, 16 bits, no bursts */ | ||
598 | move.l %d0,(0x0ac,%a0) | ||
599 | #endif | ||
600 | |||
601 | #ifdef BOOTLOADER | ||
602 | /* Check if original firmware is still present */ | ||
603 | lea 0x00001000,%a2 | ||
604 | move.l (%a2),%d0 | ||
605 | move.l #0xfbfbfbf1,%d1 | ||
606 | cmp.l %d0,%d1 | ||
607 | beq.b .ignorecookie | ||
608 | |||
609 | /* The cookie is not reset. This must mean that the boot loader | ||
610 | has crashed. Let's start the original firmware immediately. */ | ||
611 | lea 0x10017ffc,%a2 | ||
612 | move.l (%a2),%d0 | ||
613 | move.l #0xc0015a17,%d1 | ||
614 | cmp.l %d0,%d1 | ||
615 | bne.b .nocookie | ||
616 | /* Clear the cookie again */ | ||
617 | clr.l (%a2) | ||
618 | jmp 8 | ||
619 | |||
620 | .nocookie: | ||
621 | /* Set the cookie */ | ||
622 | move.l %d1,(%a2) | ||
623 | .ignorecookie: | ||
624 | |||
625 | /* Set up the DRAM controller. The refresh is based on the 11.2896MHz | ||
626 | clock (5.6448MHz bus frequency). We haven't yet started the PLL */ | ||
627 | #if MEM < 32 | ||
628 | move.w #0x8004,%d0 /* DCR - Synchronous, 80 cycle refresh */ | ||
629 | #else | ||
630 | move.w #0x8001,%d0 /* DCR - Synchronous, 32 cycle refresh */ | ||
631 | #endif | ||
632 | move.w %d0,(0x100,%a0) | ||
633 | |||
634 | /* Note on 32Mbyte models: | ||
635 | We place the SDRAM on an 0x1000000 (16M) offset because | ||
636 | the 5249 BGA chip has a fault which disables the use of A24. The | ||
637 | suggested workaround by FreeScale is to offset the base address by | ||
638 | half the DRAM size and increase the mask to the double. | ||
639 | In our case this means that we set the base address 16M ahead and | ||
640 | use a 64M mask. | ||
641 | */ | ||
642 | #if MEM < 32 | ||
643 | move.l #0x31002324,%d0 /* DACR0 - Base 0x31000000, Banks on 21 and up, | ||
644 | CAS latency 1, Page mode, No refresh yet */ | ||
645 | move.l %d0,(0x108,%a0) | ||
646 | move.l #0x00fc0001,%d0 /* Size: 16M */ | ||
647 | move.l %d0,(0x10c,%a0) /* DMR0 - 32Mb */ | ||
648 | #else | ||
649 | move.l #0x31002524,%d0 /* DACR0 - Base 0x31000000, Banks on 23 and up, | ||
650 | CAS latency 1, Page mode, No refresh yet */ | ||
651 | move.l %d0,(0x108,%a0) | ||
652 | move.l #0x03fc0001,%d0 /* Size: 64M because of workaround above */ | ||
653 | move.l %d0,(0x10c,%a0) /* DMR0 - 32Mb */ | ||
654 | #endif | ||
655 | |||
656 | /* Precharge */ | ||
657 | moveq.l #8,%d0 | ||
658 | or.l %d0,(0x108,%a0) /* DACR0[IP] = 1, next access will issue a | ||
659 | Precharge command */ | ||
660 | move.l #0xabcd1234,%d0 | ||
661 | move.l %d0,0x31000000 /* Issue precharge command */ | ||
662 | |||
663 | move.l #0x8000,%d0 | ||
664 | or.l %d0,(0x108,%a0) /* Enable refresh */ | ||
665 | |||
666 | /* Let it refresh */ | ||
667 | move.l #500,%d0 | ||
668 | .delayloop: | ||
669 | subq.l #1,%d0 | ||
670 | bne.b .delayloop | ||
671 | |||
672 | /* Mode Register init */ | ||
673 | moveq.l #0x40,%d0 /* DACR0[IMRS] = 1, next access will set the | ||
674 | Mode Register */ | ||
675 | or.l %d0,(0x108,%a0) | ||
676 | |||
677 | move.l #0xabcd1234,%d0 | ||
678 | move.l %d0,0x31000800 /* A12=1 means CASL=1 (a0 is not connected) */ | ||
679 | |||
680 | /* DACR0[IMRS] gets deactivated by the SDRAM controller */ | ||
681 | #endif /* BOOTLOADER */ | ||
682 | |||
683 | /* Invalicate cache */ | ||
684 | move.l #0x01000000,%d0 | ||
685 | movec.l %d0,%cacr | ||
686 | |||
687 | /* Enable cache, default=non-cacheable,no buffered writes */ | ||
688 | move.l #0x80000000,%d0 | ||
689 | movec.l %d0,%cacr | ||
690 | |||
691 | /* Cache enabled in SDRAM only, buffered writes enabled */ | ||
692 | move.l #0x3103c020,%d0 | ||
693 | movec.l %d0,%acr0 | ||
694 | moveq.l #0,%d0 | ||
695 | movec.l %d0,%acr1 | ||
696 | |||
697 | #ifndef BOOTLOADER | ||
698 | /* zero out .ibss */ | ||
699 | lea _iedata,%a2 | ||
700 | lea _iend,%a4 | ||
701 | bra.b .iedatastart | ||
702 | .iedataloop: | ||
703 | clr.l (%a2)+ | ||
704 | .iedatastart: | ||
705 | cmp.l %a2,%a4 | ||
706 | bhi.b .iedataloop | ||
707 | |||
708 | /* copy the .iram section */ | ||
709 | lea _iramcopy,%a2 | ||
710 | lea _iramstart,%a3 | ||
711 | lea _iramend,%a4 | ||
712 | bra.b .iramstart | ||
713 | .iramloop: | ||
714 | move.l (%a2)+,(%a3)+ | ||
715 | .iramstart: | ||
716 | cmp.l %a3,%a4 | ||
717 | bhi.b .iramloop | ||
718 | #endif /* !BOOTLOADER */ | ||
719 | |||
720 | #ifdef IRIVER_H300_SERIES | ||
721 | /* Set KEEP_ACT before doing the lengthy copy and zero-fill operations */ | ||
722 | move.l #0x00080000,%d0 | ||
723 | or.l %d0,(0xb4,%a1) | ||
724 | or.l %d0,(0xb8,%a1) | ||
725 | or.l %d0,(0xbc,%a1) | ||
726 | #endif | ||
727 | |||
728 | /* zero out bss */ | ||
729 | lea _edata,%a2 | ||
730 | lea _end,%a4 | ||
731 | bra.b .edatastart | ||
732 | .edataloop: | ||
733 | clr.l (%a2)+ | ||
734 | .edatastart: | ||
735 | cmp.l %a2,%a4 | ||
736 | bhi.b .edataloop | ||
737 | |||
738 | /* copy the .data section */ | ||
739 | lea _datacopy,%a2 | ||
740 | lea _datastart,%a3 | ||
741 | cmp.l %a2,%a3 | ||
742 | beq.b .nodatacopy /* Don't copy if src and dest are equal */ | ||
743 | lea _dataend,%a4 | ||
744 | bra.b .datastart | ||
745 | .dataloop: | ||
746 | move.l (%a2)+,(%a3)+ | ||
747 | .datastart: | ||
748 | cmp.l %a3,%a4 | ||
749 | bhi.b .dataloop | ||
750 | .nodatacopy: | ||
751 | |||
752 | /* Munge the main stack */ | ||
753 | lea stackbegin,%a2 | ||
754 | lea stackend,%a4 | ||
755 | move.l %a4,%sp | ||
756 | move.l #0xdeadbeef,%d0 | ||
757 | .mungeloop: | ||
758 | move.l %d0,(%a2)+ | ||
759 | cmp.l %a2,%a4 | ||
760 | bhi.b .mungeloop | ||
761 | |||
762 | jsr main | ||
763 | .hoo: | ||
764 | bra.b .hoo | ||
765 | |||
766 | .section .resetvectors | ||
767 | vectors: | ||
768 | .long stackend | ||
769 | .long start | ||
770 | #else | ||
771 | /* Platform: Archos Jukebox */ | ||
772 | |||
773 | mov.l .vbr_k,r1 | ||
774 | #ifdef DEBUG | ||
775 | /* If we have built our code to be loaded via the standalone GDB | ||
776 | * stub, we will have out VBR at some other location than 0x9000000. | ||
777 | * We must copy the trap vectors for the GDB stub to our vector table. */ | ||
778 | mov.l .orig_vbr_k,r2 | ||
779 | |||
780 | /* Move the invalid instruction vector (4) */ | ||
781 | mov #4,r0 | ||
782 | shll2 r0 | ||
783 | mov.l @(r0,r2),r3 | ||
784 | mov.l r3,@(r0,r1) | ||
785 | |||
786 | /* Move the invalid slot vector (6) */ | ||
787 | mov #6,r0 | ||
788 | shll2 r0 | ||
789 | mov.l @(r0,r2),r3 | ||
790 | mov.l r3,@(r0,r1) | ||
791 | |||
792 | /* Move the bus error vector (9) */ | ||
793 | mov #9,r0 | ||
794 | shll2 r0 | ||
795 | mov.l @(r0,r2),r3 | ||
796 | mov.l r3,@(r0,r1) | ||
797 | |||
798 | /* Move the DMA bus error vector (10) */ | ||
799 | mov #10,r0 | ||
800 | shll2 r0 | ||
801 | mov.l @(r0,r2),r3 | ||
802 | mov.l r3,@(r0,r1) | ||
803 | |||
804 | /* Move the NMI vector as well (11) */ | ||
805 | mov #11,r0 | ||
806 | shll2 r0 | ||
807 | mov.l @(r0,r2),r3 | ||
808 | mov.l r3,@(r0,r1) | ||
809 | |||
810 | /* Move the UserBreak vector as well (12) */ | ||
811 | mov #12,r0 | ||
812 | shll2 r0 | ||
813 | mov.l @(r0,r2),r3 | ||
814 | mov.l r3,@(r0,r1) | ||
815 | |||
816 | /* Move the breakpoint trap vector (32) */ | ||
817 | mov #32,r0 | ||
818 | shll2 r0 | ||
819 | mov.l @(r0,r2),r3 | ||
820 | mov.l r3,@(r0,r1) | ||
821 | |||
822 | /* Move the IO trap vector (33) */ | ||
823 | mov #33,r0 | ||
824 | shll2 r0 | ||
825 | mov.l @(r0,r2),r3 | ||
826 | mov.l r3,@(r0,r1) | ||
827 | |||
828 | /* Move the serial Rx interrupt vector (105) */ | ||
829 | mov #105,r0 | ||
830 | shll2 r0 | ||
831 | mov.l @(r0,r2),r3 | ||
832 | mov.l r3,@(r0,r1) | ||
833 | |||
834 | /* Move the single step trap vector (127) */ | ||
835 | mov #127,r0 | ||
836 | shll2 r0 | ||
837 | mov.l @(r0,r2),r3 | ||
838 | mov.l r3,@(r0,r1) | ||
839 | #endif /* DEBUG */ | ||
840 | ldc r1,vbr | ||
841 | |||
842 | mov #0,r0 | ||
843 | ldc r0,gbr | ||
844 | |||
845 | /* zero out .ibss */ | ||
846 | mov.l .iedata_k,r0 | ||
847 | mov.l .iend_k,r1 | ||
848 | bra .iedatastart | ||
849 | mov #0,r2 | ||
850 | .iedataloop: /* backwards is faster and shorter */ | ||
851 | mov.l r2,@-r1 | ||
852 | .iedatastart: | ||
853 | cmp/hi r0,r1 | ||
854 | bt .iedataloop | ||
855 | |||
856 | /* copy the .iram section */ | ||
857 | mov.l .iramcopy_k,r0 | ||
858 | mov.l .iram_k,r1 | ||
859 | mov.l .iramend_k,r2 | ||
860 | /* Note: We cannot put a PC relative load into the delay slot of a 'bra' | ||
861 | instruction (the offset would be wrong), but there is nothing else to | ||
862 | do before the loop, so the delay slot would be 'nop'. The cmp / bf | ||
863 | sequence is the same length, but more efficient. */ | ||
864 | cmp/hi r1,r2 | ||
865 | bf .noiramcopy | ||
866 | .iramloop: | ||
867 | mov.l @r0+,r3 | ||
868 | mov.l r3,@r1 | ||
869 | add #4,r1 | ||
870 | cmp/hi r1,r2 | ||
871 | bt .iramloop | ||
872 | .noiramcopy: | ||
873 | |||
874 | /* zero out bss */ | ||
875 | mov.l .edata_k,r0 | ||
876 | mov.l .end_k,r1 | ||
877 | bra .edatastart | ||
878 | mov #0,r2 | ||
879 | .edataloop: /* backwards is faster and shorter */ | ||
880 | mov.l r2,@-r1 | ||
881 | .edatastart: | ||
882 | cmp/hi r0,r1 | ||
883 | bt .edataloop | ||
884 | |||
885 | /* copy the .data section, for rombased execution */ | ||
886 | mov.l .datacopy_k,r0 | ||
887 | mov.l .data_k,r1 | ||
888 | cmp/eq r0,r1 | ||
889 | bt .nodatacopy /* Don't copy if src and dest are equal */ | ||
890 | mov.l .dataend_k,r2 | ||
891 | cmp/hi r1,r2 | ||
892 | bf .nodatacopy | ||
893 | .dataloop: | ||
894 | mov.l @r0+,r3 | ||
895 | mov.l r3,@r1 | ||
896 | add #4,r1 | ||
897 | cmp/hi r1,r2 | ||
898 | bt .dataloop | ||
899 | .nodatacopy: | ||
900 | |||
901 | /* Munge the main thread stack */ | ||
902 | mov.l .stackbegin_k,r0 | ||
903 | mov.l .stackend_k,r1 | ||
904 | mov r1,r15 | ||
905 | mov.l .deadbeef_k,r2 | ||
906 | .mungeloop: /* backwards is faster and shorter */ | ||
907 | mov.l r2,@-r1 | ||
908 | cmp/hi r0,r1 | ||
909 | bt .mungeloop | ||
910 | |||
911 | /* call the mainline */ | ||
912 | mov.l .main_k,r0 | ||
913 | jsr @r0 | ||
914 | nop | ||
915 | .hoo: | ||
916 | bra .hoo | ||
917 | nop | ||
918 | |||
919 | .align 2 | ||
920 | .vbr_k: | ||
921 | .long vectors | ||
922 | #ifdef DEBUG | ||
923 | .orig_vbr_k: | ||
924 | .long 0x09000000 | ||
925 | #endif | ||
926 | .iedata_k: | ||
927 | .long _iedata | ||
928 | .iend_k: | ||
929 | .long _iend | ||
930 | .iramcopy_k: | ||
931 | .long _iramcopy | ||
932 | .iram_k: | ||
933 | .long _iramstart | ||
934 | .iramend_k: | ||
935 | .long _iramend | ||
936 | .edata_k: | ||
937 | .long _edata | ||
938 | .end_k: | ||
939 | .long _end | ||
940 | .datacopy_k: | ||
941 | .long _datacopy | ||
942 | .data_k: | ||
943 | .long _datastart | ||
944 | .dataend_k: | ||
945 | .long _dataend | ||
946 | .stackbegin_k: | ||
947 | .long _stackbegin | ||
948 | .stackend_k: | ||
949 | .long _stackend | ||
950 | .deadbeef_k: | ||
951 | .long 0xdeadbeef | ||
952 | .main_k: | ||
953 | .long _main | ||
954 | |||
955 | .section .resetvectors | ||
956 | vectors: | ||
957 | .long start | ||
958 | .long _stackend | ||
959 | .long start | ||
960 | .long _stackend | ||
961 | #endif | 123 | #endif |