diff options
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/target/arm/imx233/sansa-fuzeplus/lcd-fuzeplus.c | 69 |
1 files changed, 35 insertions, 34 deletions
diff --git a/firmware/target/arm/imx233/sansa-fuzeplus/lcd-fuzeplus.c b/firmware/target/arm/imx233/sansa-fuzeplus/lcd-fuzeplus.c index d6f8f5323b..74cfa08712 100644 --- a/firmware/target/arm/imx233/sansa-fuzeplus/lcd-fuzeplus.c +++ b/firmware/target/arm/imx233/sansa-fuzeplus/lcd-fuzeplus.c | |||
@@ -152,40 +152,41 @@ static void setup_lcdif_clock(void) | |||
152 | imx233_enable_clock(CLK_PIX, true); | 152 | imx233_enable_clock(CLK_PIX, true); |
153 | } | 153 | } |
154 | 154 | ||
155 | static uint32_t i80_write_read_single(uint32_t data_out) | 155 | static uint32_t i80_read_register(uint32_t data_out) |
156 | { | 156 | { |
157 | /* lcd_enable is mapped to the RD pin of the controller */ | ||
157 | imx233_set_gpio_output(1, 21, true); /* lcd_cs */ | 158 | imx233_set_gpio_output(1, 21, true); /* lcd_cs */ |
158 | imx233_set_gpio_output(1, 19, true); /* lcd_rs */ | 159 | imx233_set_gpio_output(1, 19, true); /* lcd_rs */ |
159 | imx233_set_gpio_output(1, 23, true); /* lcd_enable */ | 160 | imx233_set_gpio_output(1, 23, true); /* lcd_enable */ |
160 | imx233_set_gpio_output(1, 20, true); /* lcd_wr */ | 161 | imx233_set_gpio_output(1, 20, true); /* lcd_wr */ |
161 | imx233_enable_gpio_output_mask(1, 0x3ffff, true); /* lcd_d{0-17} */ | 162 | imx233_enable_gpio_output_mask(1, 0x3ffff, true); /* lcd_d{0-17} */ |
162 | udelay(2); | 163 | mdelay(2); |
163 | imx233_set_gpio_output(1, 19, false); /* lcd_rs */ | 164 | imx233_set_gpio_output(1, 19, false); /* lcd_rs */ |
164 | udelay(1); | 165 | mdelay(1); |
165 | imx233_set_gpio_output(1, 21, false); /* lcd_cs */ | 166 | imx233_set_gpio_output(1, 21, false); /* lcd_cs */ |
166 | udelay(1); | 167 | mdelay(1); |
167 | imx233_set_gpio_output(1, 20, false); /* lcd_wr */ | 168 | imx233_set_gpio_output(1, 20, false); /* lcd_wr */ |
168 | udelay(1); | 169 | mdelay(1); |
169 | imx233_set_gpio_output_mask(1, data_out & 0x3ffff, true); /* lcd_d{0-17} */ | 170 | imx233_set_gpio_output_mask(1, data_out & 0x3ffff, true); /* lcd_d{0-17} */ |
170 | udelay(1); | 171 | mdelay(1); |
171 | imx233_set_gpio_output(1, 20, true); /* lcd_wr */ | 172 | imx233_set_gpio_output(1, 20, true); /* lcd_wr */ |
172 | udelay(3); | 173 | mdelay(3); |
173 | imx233_enable_gpio_output_mask(1, 0x3ffff, false); /* lcd_d{0-17} */ | 174 | imx233_enable_gpio_output_mask(1, 0x3ffff, false); /* lcd_d{0-17} */ |
174 | udelay(2); | 175 | mdelay(2); |
175 | imx233_set_gpio_output(1, 23, false); /* lcd_enable */ | 176 | imx233_set_gpio_output(1, 23, false); /* lcd_enable */ |
176 | udelay(1); | 177 | mdelay(1); |
177 | imx233_set_gpio_output(1, 19, true); /* lcd_rs */ | 178 | imx233_set_gpio_output(1, 19, true); /* lcd_rs */ |
178 | udelay(1); | 179 | mdelay(1); |
179 | imx233_set_gpio_output(1, 23, true); /* lcd_enable */ | 180 | imx233_set_gpio_output(1, 23, true); /* lcd_enable */ |
180 | udelay(3); | 181 | mdelay(3); |
181 | imx233_set_gpio_output(1, 23, false); /* lcd_enable */ | 182 | imx233_set_gpio_output(1, 23, false); /* lcd_enable */ |
182 | udelay(2); | 183 | mdelay(2); |
183 | uint32_t data_in = imx233_get_gpio_input_mask(1, 0x3ffff); /* lcd_d{0-17} */ | 184 | uint32_t data_in = imx233_get_gpio_input_mask(1, 0x3ffff); /* lcd_d{0-17} */ |
184 | udelay(1); | 185 | mdelay(1); |
185 | imx233_set_gpio_output(1, 23, true); /* lcd_enable */ | 186 | imx233_set_gpio_output(1, 23, true); /* lcd_enable */ |
186 | udelay(1); | 187 | mdelay(1); |
187 | imx233_set_gpio_output(1, 21, true); /* lcd_cs */ | 188 | imx233_set_gpio_output(1, 21, true); /* lcd_cs */ |
188 | udelay(1); | 189 | mdelay(1); |
189 | return data_in; | 190 | return data_in; |
190 | } | 191 | } |
191 | 192 | ||
@@ -205,7 +206,7 @@ static void lcd_write_reg(uint32_t reg, uint32_t data) | |||
205 | static uint32_t lcd_read_reg(uint32_t reg) | 206 | static uint32_t lcd_read_reg(uint32_t reg) |
206 | { | 207 | { |
207 | setup_lcd_pins_i80(true); | 208 | setup_lcd_pins_i80(true); |
208 | uint32_t data_in = i80_write_read_single(encode_16_to_18(reg)); | 209 | uint32_t data_in = i80_read_register(encode_16_to_18(reg)); |
209 | setup_lcd_pins_i80(false); | 210 | setup_lcd_pins_i80(false); |
210 | lcd_write_reg(0x22, 0); | 211 | lcd_write_reg(0x22, 0); |
211 | return decode_18_to_16(data_in); | 212 | return decode_18_to_16(data_in); |
@@ -214,11 +215,11 @@ static uint32_t lcd_read_reg(uint32_t reg) | |||
214 | static void lcd_init_seq_7783(void) | 215 | static void lcd_init_seq_7783(void) |
215 | { | 216 | { |
216 | __REG_SET(HW_LCDIF_CTRL1) = HW_LCDIF_CTRL1__RESET; | 217 | __REG_SET(HW_LCDIF_CTRL1) = HW_LCDIF_CTRL1__RESET; |
217 | udelay(50); | 218 | mdelay(50); |
218 | __REG_CLR(HW_LCDIF_CTRL1) = HW_LCDIF_CTRL1__RESET; | 219 | __REG_CLR(HW_LCDIF_CTRL1) = HW_LCDIF_CTRL1__RESET; |
219 | udelay(10); | 220 | mdelay(10); |
220 | __REG_SET(HW_LCDIF_CTRL1) = HW_LCDIF_CTRL1__RESET; | 221 | __REG_SET(HW_LCDIF_CTRL1) = HW_LCDIF_CTRL1__RESET; |
221 | udelay(200); | 222 | mdelay(200); |
222 | lcd_write_reg(1, 0x100); | 223 | lcd_write_reg(1, 0x100); |
223 | lcd_write_reg(2, 0x700); | 224 | lcd_write_reg(2, 0x700); |
224 | lcd_write_reg(3, 0x1030); | 225 | lcd_write_reg(3, 0x1030); |
@@ -230,15 +231,15 @@ static void lcd_init_seq_7783(void) | |||
230 | lcd_write_reg(0x11, 5); | 231 | lcd_write_reg(0x11, 5); |
231 | lcd_write_reg(0x12, 0); | 232 | lcd_write_reg(0x12, 0); |
232 | lcd_write_reg(0x13, 0); | 233 | lcd_write_reg(0x13, 0); |
233 | udelay(100); | 234 | mdelay(100); |
234 | lcd_write_reg(0x10, 0x12b0); | 235 | lcd_write_reg(0x10, 0x12b0); |
235 | udelay(100); | 236 | mdelay(100); |
236 | lcd_write_reg(0x11, 7); | 237 | lcd_write_reg(0x11, 7); |
237 | udelay(100); | 238 | mdelay(100); |
238 | lcd_write_reg(0x12, 0x89); | 239 | lcd_write_reg(0x12, 0x89); |
239 | lcd_write_reg(0x13, 0x1d00); | 240 | lcd_write_reg(0x13, 0x1d00); |
240 | lcd_write_reg(0x29, 0x2f); | 241 | lcd_write_reg(0x29, 0x2f); |
241 | udelay(50); | 242 | mdelay(50); |
242 | lcd_write_reg(0x30, 0); | 243 | lcd_write_reg(0x30, 0); |
243 | lcd_write_reg(0x31, 0x505); | 244 | lcd_write_reg(0x31, 0x505); |
244 | lcd_write_reg(0x32, 0x205); | 245 | lcd_write_reg(0x32, 0x205); |
@@ -261,7 +262,7 @@ static void lcd_init_seq_7783(void) | |||
261 | lcd_write_reg(0x2b, 0xa); | 262 | lcd_write_reg(0x2b, 0xa); |
262 | lcd_write_reg(9, 0); | 263 | lcd_write_reg(9, 0); |
263 | lcd_write_reg(7, 0x133); | 264 | lcd_write_reg(7, 0x133); |
264 | udelay(50); | 265 | mdelay(50); |
265 | lcd_write_reg(0x22, 0); | 266 | lcd_write_reg(0x22, 0); |
266 | } | 267 | } |
267 | 268 | ||
@@ -288,7 +289,7 @@ void lcd_init_device(void) | |||
288 | lcd_kind = LCD_KIND_OTHER; | 289 | lcd_kind = LCD_KIND_OTHER; |
289 | } | 290 | } |
290 | } | 291 | } |
291 | udelay(5); | 292 | mdelay(5); |
292 | switch(lcd_kind) | 293 | switch(lcd_kind) |
293 | { | 294 | { |
294 | case LCD_KIND_7783: lcd_init_seq_7783(); break; | 295 | case LCD_KIND_7783: lcd_init_seq_7783(); break; |
@@ -304,28 +305,28 @@ static void lcd_enable_7783(bool enable) | |||
304 | if(!enable) | 305 | if(!enable) |
305 | { | 306 | { |
306 | lcd_write_reg(7, 0x131); | 307 | lcd_write_reg(7, 0x131); |
307 | udelay(50); | 308 | mdelay(50); |
308 | lcd_write_reg(7, 0x20); | 309 | lcd_write_reg(7, 0x20); |
309 | udelay(50); | 310 | mdelay(50); |
310 | lcd_write_reg(0x10, 0x82); | 311 | lcd_write_reg(0x10, 0x82); |
311 | udelay(50); | 312 | mdelay(50); |
312 | } | 313 | } |
313 | else | 314 | else |
314 | { | 315 | { |
315 | lcd_write_reg(0x11, 5); | 316 | lcd_write_reg(0x11, 5); |
316 | lcd_write_reg(0x10, 0x12b0); | 317 | lcd_write_reg(0x10, 0x12b0); |
317 | udelay(50); | 318 | mdelay(50); |
318 | lcd_write_reg(7, 0x11); | 319 | lcd_write_reg(7, 0x11); |
319 | udelay(50); | 320 | mdelay(50); |
320 | lcd_write_reg(0x12, 0x89); | 321 | lcd_write_reg(0x12, 0x89); |
321 | udelay(50); | 322 | mdelay(50); |
322 | lcd_write_reg(0x13, 0x1d00); | 323 | lcd_write_reg(0x13, 0x1d00); |
323 | udelay(50); | 324 | mdelay(50); |
324 | lcd_write_reg(0x29, 0x2f); | 325 | lcd_write_reg(0x29, 0x2f); |
325 | udelay(50); | 326 | mdelay(50); |
326 | lcd_write_reg(0x2b, 0xa); | 327 | lcd_write_reg(0x2b, 0xa); |
327 | lcd_write_reg(7, 0x133); | 328 | lcd_write_reg(7, 0x133); |
328 | udelay(50); | 329 | mdelay(50); |
329 | lcd_write_reg(0x22, 0); | 330 | lcd_write_reg(0x22, 0); |
330 | } | 331 | } |
331 | } | 332 | } |