diff options
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/export/cpu.h | 3 | ||||
-rw-r--r-- | firmware/export/x1000.h | 72 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/app.lds | 35 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c | 4 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/spl.lds | 23 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/system-target.h | 16 |
6 files changed, 100 insertions, 53 deletions
diff --git a/firmware/export/cpu.h b/firmware/export/cpu.h index e862cedb74..67509141aa 100644 --- a/firmware/export/cpu.h +++ b/firmware/export/cpu.h | |||
@@ -77,3 +77,6 @@ | |||
77 | #if CONFIG_CPU == RK27XX | 77 | #if CONFIG_CPU == RK27XX |
78 | #include "rk27xx.h" | 78 | #include "rk27xx.h" |
79 | #endif | 79 | #endif |
80 | #if CONFIG_CPU == X1000 | ||
81 | #include "x1000.h" | ||
82 | #endif | ||
diff --git a/firmware/export/x1000.h b/firmware/export/x1000.h new file mode 100644 index 0000000000..102d4ec978 --- /dev/null +++ b/firmware/export/x1000.h | |||
@@ -0,0 +1,72 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #ifndef __X1000_H__ | ||
23 | #define __X1000_H__ | ||
24 | |||
25 | #include "config.h" | ||
26 | |||
27 | /* Frequency of external oscillator EXCLK */ | ||
28 | //#define X1000_EXCLK_FREQ 24000000 | ||
29 | |||
30 | /* Maximum CPU frequency that can be achieved on the target */ | ||
31 | //#define CPU_FREQ 1008000000 | ||
32 | |||
33 | /* Only 24 MHz and 26 MHz external oscillators are supported by the X1000 */ | ||
34 | #if X1000_EXCLK_FREQ == 24000000 | ||
35 | # define X1000_EXCLK_24MHZ | ||
36 | #elif X1000_EXCLK_FREQ == 26000000 | ||
37 | # define X1000_EXCLK_26MHZ | ||
38 | #else | ||
39 | # error "Unsupported EXCLK freq" | ||
40 | #endif | ||
41 | |||
42 | /* On-chip TCSM (tightly coupled shared memory), aka IRAM */ | ||
43 | #define X1000_TCSM_BASE 0xf4000000 | ||
44 | #define X1000_TCSM_SIZE (16 * 1024) | ||
45 | |||
46 | /* External SDRAM */ | ||
47 | #define X1000_SDRAM_BASE 0x80000000 | ||
48 | #define X1000_SDRAM_SIZE (MEMORYSIZE * 1024 * 1024) | ||
49 | |||
50 | /* Memory definitions for Rockbox */ | ||
51 | #define X1000_IRAM_BASE X1000_SDRAM_BASE | ||
52 | #define X1000_IRAM_SIZE (16 * 1024) | ||
53 | #define X1000_IRAM_END (X1000_IRAM_BASE + X1000_IRAM_SIZE) | ||
54 | #define X1000_DRAM_BASE X1000_IRAM_END | ||
55 | #define X1000_DRAM_SIZE (X1000_SDRAM_SIZE - X1000_IRAM_SIZE) | ||
56 | #define X1000_DRAM_END (X1000_DRAM_BASE + X1000_DRAM_SIZE) | ||
57 | #define X1000_STACKSIZE 0x1e00 | ||
58 | #define X1000_IRQSTACKSIZE 0x300 | ||
59 | |||
60 | /* Convert kseg0 address to physical address or uncached address */ | ||
61 | #define PHYSADDR(x) ((unsigned long)(x) & 0x1fffffff) | ||
62 | #define UNCACHEDADDR(x) (PHYSADDR(x) | 0xa0000000) | ||
63 | |||
64 | /* Defines for usb-designware driver */ | ||
65 | #define OTGBASE 0xb3500000 | ||
66 | #define USB_NUM_ENDPOINTS 9 | ||
67 | |||
68 | /* CPU cache parameters */ | ||
69 | #define CACHEALIGN_BITS 5 | ||
70 | #define CACHE_SIZE (16 * 1024) | ||
71 | |||
72 | #endif /* __X1000_H__ */ | ||
diff --git a/firmware/target/mips/ingenic_x1000/app.lds b/firmware/target/mips/ingenic_x1000/app.lds index 48a2d8d3c5..26b2854728 100644 --- a/firmware/target/mips/ingenic_x1000/app.lds +++ b/firmware/target/mips/ingenic_x1000/app.lds | |||
@@ -1,30 +1,21 @@ | |||
1 | #include "config.h" | 1 | #include "config.h" |
2 | #include "cpu.h" | ||
2 | 3 | ||
3 | OUTPUT_FORMAT("elf32-littlemips") | 4 | OUTPUT_FORMAT("elf32-littlemips") |
4 | OUTPUT_ARCH(MIPS) | 5 | OUTPUT_ARCH(MIPS) |
5 | ENTRY(_start) | 6 | ENTRY(_start) |
6 | STARTUP(target/mips/ingenic_x1000/crt0.o) | 7 | STARTUP(target/mips/ingenic_x1000/crt0.o) |
7 | 8 | ||
8 | /* Stub area is used for loading new firmware via RoLo */ | ||
9 | #define STUBSIZE 0x4000 | ||
10 | #define SDRAM_ORIG 0x80000000 | ||
11 | |||
12 | /* IRAM contains stub, DRAM contains main app */ | ||
13 | #define IRAMORIG SDRAM_ORIG | ||
14 | #define IRAMSIZE STUBSIZE | ||
15 | #define DRAMORIG (SDRAM_ORIG + STUBSIZE) | ||
16 | #define DRAMSIZE (MEMORYSIZE * 0x100000 - STUBSIZE) | ||
17 | |||
18 | /* End of the audio buffer, where the codec buffer starts */ | 9 | /* End of the audio buffer, where the codec buffer starts */ |
19 | #define ENDAUDIOADDR (DRAMORIG + DRAMSIZE - PLUGIN_BUFFER_SIZE - CODEC_SIZE) | 10 | #define ENDAUDIOADDR (X1000_DRAM_END - PLUGIN_BUFFER_SIZE - CODEC_SIZE) |
20 | 11 | ||
21 | /* Where the codec buffer ends, and the plugin buffer starts */ | 12 | /* Where the codec buffer ends, and the plugin buffer starts */ |
22 | #define ENDCODECADDR (ENDAUDIOADDR + CODEC_SIZE) | 13 | #define ENDCODECADDR (ENDAUDIOADDR + CODEC_SIZE) |
23 | 14 | ||
24 | MEMORY | 15 | MEMORY |
25 | { | 16 | { |
26 | IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE | 17 | IRAM : ORIGIN = X1000_IRAM_BASE, LENGTH = X1000_IRAM_SIZE |
27 | DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE | 18 | DRAM : ORIGIN = X1000_DRAM_BASE, LENGTH = X1000_DRAM_SIZE |
28 | } | 19 | } |
29 | 20 | ||
30 | SECTIONS | 21 | SECTIONS |
@@ -50,7 +41,7 @@ SECTIONS | |||
50 | *(.sdata*); | 41 | *(.sdata*); |
51 | } > DRAM | 42 | } > DRAM |
52 | 43 | ||
53 | .iram IRAMORIG: AT (_bssbegin) | 44 | .iram X1000_IRAM_BASE: AT (_bssbegin) |
54 | { | 45 | { |
55 | _iramstart = .; | 46 | _iramstart = .; |
56 | . = 0x000; /* TLB refill */ | 47 | . = 0x000; /* TLB refill */ |
@@ -75,10 +66,10 @@ SECTIONS | |||
75 | { | 66 | { |
76 | *(.stack); | 67 | *(.stack); |
77 | stackbegin = .; | 68 | stackbegin = .; |
78 | . += 0x1E00; | 69 | . += X1000_STACKSIZE; |
79 | stackend = .; | 70 | stackend = .; |
80 | _irqstackbegin = .; | 71 | _irqstackbegin = .; |
81 | . += 0x300; | 72 | . += X1000_IRQSTACKSIZE; |
82 | _irqstackend = .; | 73 | _irqstackend = .; |
83 | } > IRAM | 74 | } > IRAM |
84 | 75 | ||
@@ -93,23 +84,17 @@ SECTIONS | |||
93 | _end = .; | 84 | _end = .; |
94 | } > DRAM | 85 | } > DRAM |
95 | 86 | ||
96 | #ifdef BOOTLOADER | ||
97 | . = ALIGN(4); | ||
98 | loadbuffer = .; | ||
99 | . += 0x100000 * 4; /* Allow 4 MiB for the rockbox binary */ | ||
100 | loadbufferend = .; | ||
101 | #else | ||
102 | |||
103 | .audiobuf : | 87 | .audiobuf : |
104 | { | 88 | { |
105 | . = ALIGN(4); /* XXX might need more alignment here */ | 89 | . = ALIGN(4); |
106 | audiobuffer = .; | 90 | audiobuffer = .; |
91 | loadbuffer = .; | ||
107 | } > DRAM | 92 | } > DRAM |
108 | 93 | ||
94 | loadbufferend = ENDAUDIOADDR; | ||
109 | audiobufend = ENDAUDIOADDR; | 95 | audiobufend = ENDAUDIOADDR; |
110 | codecbuf = ENDAUDIOADDR; | 96 | codecbuf = ENDAUDIOADDR; |
111 | pluginbuf = ENDCODECADDR; | 97 | pluginbuf = ENDCODECADDR; |
112 | #endif | ||
113 | 98 | ||
114 | /DISCARD/ : | 99 | /DISCARD/ : |
115 | { | 100 | { |
diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c b/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c index 7f4441c109..bdd0ffc2e0 100644 --- a/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c +++ b/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c | |||
@@ -56,8 +56,8 @@ const struct spl_boot_option spl_boot_options[] = { | |||
56 | */ | 56 | */ |
57 | .nand_addr = 0x6800, | 57 | .nand_addr = 0x6800, |
58 | .nand_size = 0x19800, | 58 | .nand_size = 0x19800, |
59 | .load_addr = 0x80003ff8, /* first 8 bytes are bootloader ID */ | 59 | .load_addr = X1000_DRAM_BASE - 8, /* first 8 bytes are bootloader ID */ |
60 | .exec_addr = 0x80004000, | 60 | .exec_addr = X1000_DRAM_BASE, |
61 | .cmdline = NULL, | 61 | .cmdline = NULL, |
62 | }, | 62 | }, |
63 | { | 63 | { |
diff --git a/firmware/target/mips/ingenic_x1000/spl.lds b/firmware/target/mips/ingenic_x1000/spl.lds index 39b5939a6a..e8bf9d4700 100644 --- a/firmware/target/mips/ingenic_x1000/spl.lds +++ b/firmware/target/mips/ingenic_x1000/spl.lds | |||
@@ -1,23 +1,22 @@ | |||
1 | #include "config.h" | 1 | #include "config.h" |
2 | #include "cpu.h" | ||
2 | 3 | ||
3 | OUTPUT_FORMAT("elf32-littlemips") | 4 | OUTPUT_FORMAT("elf32-littlemips") |
4 | OUTPUT_ARCH(MIPS) | 5 | OUTPUT_ARCH(MIPS) |
5 | ENTRY(_start) | 6 | ENTRY(_start) |
6 | STARTUP(target/mips/ingenic_x1000/crt0.o) | 7 | STARTUP(target/mips/ingenic_x1000/crt0.o) |
7 | 8 | ||
8 | #define DRAMORIG 0x80000000 | ||
9 | #define DRAMSIZE (MEMORYSIZE * 0x100000) | ||
10 | #define USED_DRAM 16K | ||
11 | |||
12 | /* TCSM is 16 KiB and is mapped starting at address 0xf4000000. | ||
13 | * | ||
14 | * The SPL is loaded to TCSM + 0x1000. The area below that is stack space. | ||
15 | * The first 2 KiB of SPL is just headers. The code begins at TCSM + 0x1800. | ||
16 | * The maskrom will jump to that address (via jalr) after loading the SPL. | ||
17 | */ | ||
18 | MEMORY { | 9 | MEMORY { |
19 | TCSM : ORIGIN = 0xf4001800, LENGTH = 0x2800 | 10 | /* First 4k of TCSM is used by mask ROM for stack + variables, |
20 | DRAM : ORIGIN = DRAMORIG + DRAMSIZE - USED_DRAM, LENGTH = USED_DRAM | 11 | * and the next 2k are occupied by SPL header */ |
12 | TCSM : ORIGIN = X1000_TCSM_BASE + 0x1800, | ||
13 | LENGTH = X1000_TCSM_SIZE - 0x1800 | ||
14 | |||
15 | /* Small area of DRAM is required for NAND bounce buffers, | ||
16 | * though not strictly necessary as ECC isn't really practical | ||
17 | * this early in the boot */ | ||
18 | DRAM : ORIGIN = X1000_DRAM_END - 16K, | ||
19 | LENGTH = 16K | ||
21 | } | 20 | } |
22 | 21 | ||
23 | SECTIONS | 22 | SECTIONS |
diff --git a/firmware/target/mips/ingenic_x1000/system-target.h b/firmware/target/mips/ingenic_x1000/system-target.h index 13024584d3..1390faf43a 100644 --- a/firmware/target/mips/ingenic_x1000/system-target.h +++ b/firmware/target/mips/ingenic_x1000/system-target.h | |||
@@ -22,35 +22,23 @@ | |||
22 | #ifndef __SYSTEM_TARGET_H__ | 22 | #ifndef __SYSTEM_TARGET_H__ |
23 | #define __SYSTEM_TARGET_H__ | 23 | #define __SYSTEM_TARGET_H__ |
24 | 24 | ||
25 | /* For the sake of system.h CACHEALIGN macros. | ||
26 | * We need this to align DMA buffers, etc. | ||
27 | */ | ||
28 | #define CACHEALIGN_BITS 5 | ||
29 | #define CACHE_SIZE (16*1024) | ||
30 | |||
31 | #ifdef DEBUG | 25 | #ifdef DEBUG |
32 | /* Define this to get CPU idle stats, visible in the debug menu. */ | 26 | /* Define this to get CPU idle stats, visible in the debug menu. */ |
33 | # define X1000_CPUIDLE_STATS | 27 | # define X1000_CPUIDLE_STATS |
34 | #endif | 28 | #endif |
35 | 29 | ||
36 | #define OTGBASE 0xb3500000 | 30 | #include "cpu.h" |
37 | #define USB_NUM_ENDPOINTS 9 | ||
38 | |||
39 | #include "mmu-mips.h" | 31 | #include "mmu-mips.h" |
40 | #include "mipsregs.h" | 32 | #include "mipsregs.h" |
41 | #include "mipsr2-endian.h" | 33 | #include "mipsr2-endian.h" |
42 | #include <stdint.h> | 34 | #include <stdint.h> |
43 | 35 | ||
44 | /* Get physical address for DMA */ | ||
45 | #define PHYSADDR(addr) (((unsigned long)(addr)) & 0x1fffffff) | ||
46 | |||
47 | #define HIGHEST_IRQ_LEVEL 0 | ||
48 | |||
49 | /* Rockbox API */ | 36 | /* Rockbox API */ |
50 | #define enable_irq() set_c0_status(ST0_IE) | 37 | #define enable_irq() set_c0_status(ST0_IE) |
51 | #define disable_irq() clear_c0_status(ST0_IE) | 38 | #define disable_irq() clear_c0_status(ST0_IE) |
52 | #define disable_irq_save() set_irq_level(0) | 39 | #define disable_irq_save() set_irq_level(0) |
53 | #define restore_irq(arg) write_c0_status(arg) | 40 | #define restore_irq(arg) write_c0_status(arg) |
41 | #define HIGHEST_IRQ_LEVEL 0 | ||
54 | 42 | ||
55 | static inline int set_irq_level(int lev) | 43 | static inline int set_irq_level(int lev) |
56 | { | 44 | { |