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-rw-r--r--firmware/target/arm/rk27xx/app.lds35
-rw-r--r--firmware/target/arm/rk27xx/boot.lds43
-rw-r--r--firmware/target/arm/rk27xx/crt0.S81
3 files changed, 77 insertions, 82 deletions
diff --git a/firmware/target/arm/rk27xx/app.lds b/firmware/target/arm/rk27xx/app.lds
index 080c74fc7c..1675da491c 100644
--- a/firmware/target/arm/rk27xx/app.lds
+++ b/firmware/target/arm/rk27xx/app.lds
@@ -37,42 +37,28 @@ SECTIONS
37 37
38 .intvect : { 38 .intvect : {
39 _intvectstart = . ; 39 _intvectstart = . ;
40 *(.intvect) 40 KEEP(*(.intvect))
41 _intvectend = _newstart ; 41 _intvectend = . ;
42 } > IRAM AT > DRAM 42 } > IRAM AT > DRAM
43 _intvectcopy = LOADADDR(.intvect) ; 43 _intvectcopy = LOADADDR(.intvect);
44 44
45 .text : { 45 .text : {
46 *(.init.text) 46 *(.init.text)
47 *(.text*) 47 *(.text*)
48 *(.icode*)
48 *(.glue_7*) 49 *(.glue_7*)
49 } > DRAM 50 } > DRAM
50 51
51 .data : { 52 .rodata : {
52 *(.rodata*) 53 *(.rodata*)
53 *(.data*) 54 *(.irodata*)
54 *(.ncdata*);
55 . = ALIGN(0x4); 55 . = ALIGN(0x4);
56 } > DRAM 56 } > DRAM
57 57
58 .iram : 58 .data : {
59 { 59 *(.data*)
60 _iramstart = .; 60 *(.idata*)
61 *(.icode) 61 . = ALIGN(0x4);
62 *(.irodata)
63 *(.idata)
64 . = ALIGN(0x4);
65 _iramend = .;
66 } > DRAM
67 _iramcopy = LOADADDR(.iram) ;
68
69 .ibss (NOLOAD) :
70 {
71 _iedata = .;
72 *(.qharray)
73 *(.ibss)
74 . = ALIGN(0x4);
75 _iend = .;
76 } > DRAM 62 } > DRAM
77 63
78 .stack (NOLOAD) : 64 .stack (NOLOAD) :
@@ -95,7 +81,6 @@ SECTIONS
95 _edata = .; 81 _edata = .;
96 *(.bss*); 82 *(.bss*);
97 *(.ibss); 83 *(.ibss);
98 *(.ncbss*);
99 *(COMMON); 84 *(COMMON);
100 . = ALIGN(0x4); 85 . = ALIGN(0x4);
101 _end = .; 86 _end = .;
diff --git a/firmware/target/arm/rk27xx/boot.lds b/firmware/target/arm/rk27xx/boot.lds
index b7bc9beac0..5e25d12dab 100644
--- a/firmware/target/arm/rk27xx/boot.lds
+++ b/firmware/target/arm/rk27xx/boot.lds
@@ -9,8 +9,8 @@ OUTPUT_FORMAT(elf32-bigarm)
9OUTPUT_ARCH(arm) 9OUTPUT_ARCH(arm)
10STARTUP(target/arm/rk27xx/crt0.o) 10STARTUP(target/arm/rk27xx/crt0.o)
11 11
12#define DRAMORIG 0x60000000 12#define DRAMORIG 0x60700000
13#define DRAMSIZE (MEMORYSIZE * 0x100000) 13#define DRAMSIZE (MEMORYSIZE * 0x100000 - 0x700000)
14 14
15#define IRAMORIG 0x00000000 15#define IRAMORIG 0x00000000
16#define IRAMSIZE 4K 16#define IRAMSIZE 4K
@@ -23,35 +23,39 @@ MEMORY
23 23
24SECTIONS 24SECTIONS
25{ 25{
26 .intvect : { 26 .relocstart (NOLOAD) : {
27 _intvectstart = . ; 27 _relocstart = .;
28 *(.intvect) 28 } > DRAM
29 _intvectend = _newstart ;
30 } > IRAM AT > DRAM
31 _intvectcopy = LOADADDR(.intvect) ;
32 29
33 .text : { 30 .text : {
34 *(.init.text) 31 *(.init.text)
35 *(.text*) 32 *(.text*)
33 *(.icode*)
36 *(.glue_7*) 34 *(.glue_7*)
35 } > DRAM
36
37 .intvect : {
38 _intvectstart = . ;
39 KEEP(*(.intvect))
40 _intvectend = . ;
41 } > IRAM AT > DRAM
42 _intvectcopy = LOADADDR(.intvect) ;
43
44 .rodata : {
45 *(.rodata*)
46 *(.irodata*)
47 . = ALIGN(0x4);
37 } > DRAM 48 } > DRAM
38 49
39 .data : { 50 .data : {
40 *(.rodata*)
41 *(.data*) 51 *(.data*)
42 *(.ncdata*); 52 *(.idata*)
43 . = ALIGN(0x4); 53 . = ALIGN(0x4);
44 } > DRAM 54 } > DRAM
45 55
46 .idata : { 56 .relocend (NOLOAD) : {
47 _datastart = . ; 57 _relocend = .;
48 *(.irodata) 58 } > DRAM
49 *(.icode)
50 *(.idata)
51 . = ALIGN(0x4);
52 _dataend = . ;
53 } > DRAM
54 _datacopy = LOADADDR(.idata) ;
55 59
56 .stack (NOLOAD) : 60 .stack (NOLOAD) :
57 { 61 {
@@ -73,7 +77,6 @@ SECTIONS
73 _edata = .; 77 _edata = .;
74 *(.bss*); 78 *(.bss*);
75 *(.ibss); 79 *(.ibss);
76 *(.ncbss*);
77 *(COMMON); 80 *(COMMON);
78 . = ALIGN(0x4); 81 . = ALIGN(0x4);
79 _end = .; 82 _end = .;
diff --git a/firmware/target/arm/rk27xx/crt0.S b/firmware/target/arm/rk27xx/crt0.S
index 23f3fcf2c9..1bbd46a12c 100644
--- a/firmware/target/arm/rk27xx/crt0.S
+++ b/firmware/target/arm/rk27xx/crt0.S
@@ -5,7 +5,6 @@
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < 5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ 6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/ 7 * \/ \/ \/ \/ \/
8 * $Id: crt0.S 18776 2008-10-11 18:32:17Z gevaerts $
9 * 8 *
10 * Copyright (C) 2008 by Marcoen Hirschberg 9 * Copyright (C) 2008 by Marcoen Hirschberg
11 * Copyright (C) 2008 by Denes Balatoni 10 * Copyright (C) 2008 by Denes Balatoni
@@ -24,26 +23,50 @@
24#include "config.h" 23#include "config.h"
25#include "cpu.h" 24#include "cpu.h"
26 25
27 .section .intvect,"ax",%progbits 26 .global start
28 .global start 27 .global entry_point
29 .global _newstart 28
30 /* Exception vectors */ 29 /* Exception vectors */
31start: 30 .section .intvect,"ax",%progbits
32 b _newstart 31 ldr pc, =start
33 ldr pc, =undef_instr_handler 32 ldr pc, =undef_instr_handler
34 ldr pc, =software_int_handler 33 ldr pc, =software_int_handler
35 ldr pc, =prefetch_abort_handler 34 ldr pc, =prefetch_abort_handler
36 ldr pc, =data_abort_handler 35 ldr pc, =data_abort_handler
37 ldr pc, =reserved_handler 36 ldr pc, =reserved_handler
38 ldr pc, =irq_handler 37 ldr pc, =irq_handler
39 ldr pc, =fiq_handler 38 ldr pc, =fiq_handler
40 .ltorg 39 .ltorg
41_newstart:
42 ldr pc, =newstart2
43 .section .init.text,"ax",%progbits
44newstart2:
45 msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
46 40
41 .text
42start:
43 msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
44
45#ifdef BOOTLOADER
46 sub r4, pc, #12 /* copy running address, accomodate
47 * for prefetch (-8) and msr instr (-4)
48 */
49
50 ldr r0, =0xefff0000 /* cache controler base address */
51 ldrh r1, [r0]
52 strh r1, [r0] /* global cache disable */
53
54 ldr r2, =_relocstart
55 ldr r3, =_relocend
56
57 cmp r2, r4
58 beq entry_point /* skip copying if we are in place already */
591:
60 cmp r3, r2
61 ldrhi r1, [r4], #4
62 strhi r1, [r2], #4
63 bhi 1b
64
65entry_point_jmp:
66 ldr pc, =entry_point
67#endif
68
69entry_point:
47 mov r0, #0x18000000 70 mov r0, #0x18000000
48 add r0, r0, #0x1c000 71 add r0, r0, #0x1c000
49 72
@@ -135,26 +158,14 @@ newstart2:
135 strhi r4, [r2], #4 158 strhi r4, [r2], #4
136 bhi 1b 159 bhi 1b
137 160
138#ifndef BOOTLOADER 161 /* Initialise bss, ibss section to zero */
139 /* Copy icode and data to ram */ 162 ldr r2, =_edata
140 ldr r2, =_iramstart 163 ldr r3, =_end
141 ldr r3, =_iramend
142 ldr r4, =_iramcopy
1431:
144 cmp r3, r2
145 ldrhi r1, [r4], #4
146 strhi r1, [r2], #4
147 bhi 1b
148
149 /* Initialise ibss section to zero */
150 ldr r2, =_iedata
151 ldr r3, =_iend
152 mov r4, #0 164 mov r4, #0
1531: 1651:
154 cmp r3, r2 166 cmp r3, r2
155 strhi r4, [r2], #4 167 strhi r4, [r2], #4
156 bhi 1b 168 bhi 1b
157#endif
158 169
159 /* Set up stack for IRQ mode */ 170 /* Set up stack for IRQ mode */
160 msr cpsr_c, #0xd2 171 msr cpsr_c, #0xd2
@@ -184,12 +195,8 @@ newstart2:
184 strhi r3, [r2], #4 195 strhi r3, [r2], #4
185 bhi 1b 196 bhi 1b
186 197
187
188 bl main 198 bl main
189 199
190 .text
191/* .global UIE*/
192
193/* All illegal exceptions call into UIE with exception address as first 200/* All illegal exceptions call into UIE with exception address as first
194 * parameter. This is calculated differently depending on which exception 201 * parameter. This is calculated differently depending on which exception
195 * we're in. Second parameter is exception number, used for a string lookup 202 * we're in. Second parameter is exception number, used for a string lookup